RISC-V: Enable and adjust the testsuite for XTheadVector.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/rvv.exp: Enable testsuite of
	XTheadVector.
	* gcc.target/riscv/rvv/xtheadvector/pr114194.c: Adjust correctly.
	* gcc.target/riscv/rvv/xtheadvector/prefix.c: Likewise.
	* gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c: Likewise.
	* gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c: Likewise.
	* gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c: Likewise.
	* gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c: Likewise.
	* gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c: Likewise.
	* gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c: Likewise.

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
index d82710e9c416d821684c603805906306301af596..3824997c90825b3096a0e07e4ba296dde1a1a2d4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
@@ -41,6 +41,8 @@ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \
        "" $CFLAGS
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/xsfvector/*.\[cS\]]] \
        "" $CFLAGS
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/xtheadvector/*.\[cS\]]] \
+       "" $CFLAGS
 gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \
        "" $CFLAGS
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c
index a82e2d3fbfe6c9843f21e166ed3aa2326b4fd255..5c9777b071b516071305d09e6e3366fb201a33da 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c
@@ -1,11 +1,11 @@
 /* { dg-do compile { target { ! riscv_abi_e } } } */
-/* { dg-options "-march=rv32gc_xtheadvector" { target { rv32 } } } */
-/* { dg-options "-march=rv64gc_xtheadvector" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_xtheadvector -O2" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadvector -O2" { target { rv64 } } } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 /*
 ** foo0_1:
-**     sb\tzero,0([a-x0-9]+)
+**     sb\tzero,0\([a-x0-9]+\)
 **     ret
 */
 void foo0_1 (void *p)
@@ -15,13 +15,13 @@ void foo0_1 (void *p)
 
 /*
 ** foo0_7:
-**     sb\tzero,0([a-x0-9]+)
-**     sb\tzero,1([a-x0-9]+)
-**     sb\tzero,2([a-x0-9]+)
-**     sb\tzero,3([a-x0-9]+)
-**     sb\tzero,4([a-x0-9]+)
-**     sb\tzero,5([a-x0-9]+)
-**     sb\tzero,6([a-x0-9]+)
+**     sb\tzero,0\([a-x0-9]+\)
+**     sb\tzero,1\([a-x0-9]+\)
+**     sb\tzero,2\([a-x0-9]+\)
+**     sb\tzero,3\([a-x0-9]+\)
+**     sb\tzero,4\([a-x0-9]+\)
+**     sb\tzero,5\([a-x0-9]+\)
+**     sb\tzero,6\([a-x0-9]+\)
 **     ret
 */
 void foo0_7 (void *p)
@@ -32,7 +32,7 @@ void foo0_7 (void *p)
 /*
 ** foo1_1:
 **     li\t[a-x0-9]+,1
-**     sb\t[a-x0-9]+,0([a-x0-9]+)
+**     sb\t[a-x0-9]+,0\([a-x0-9]+\)
 **     ret
 */
 void foo1_1 (void *p)
@@ -43,11 +43,11 @@ void foo1_1 (void *p)
 /*
 ** foo1_5:
 **     li\t[a-x0-9]+,1
-**     sb\t[a-x0-9]+,0([a-x0-9]+)
-**     sb\t[a-x0-9]+,1([a-x0-9]+)
-**     sb\t[a-x0-9]+,2([a-x0-9]+)
-**     sb\t[a-x0-9]+,3([a-x0-9]+)
-**     sb\t[a-x0-9]+,4([a-x0-9]+)
+**     sb\t[a-x0-9]+,0\([a-x0-9]+\)
+**     sb\t[a-x0-9]+,1\([a-x0-9]+\)
+**     sb\t[a-x0-9]+,2\([a-x0-9]+\)
+**     sb\t[a-x0-9]+,3\([a-x0-9]+\)
+**     sb\t[a-x0-9]+,4\([a-x0-9]+\)
 **     ret
 */
 void foo1_5 (void *p)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
index eee727ef6b42d2b0c25a219d9b8a658dee592bd0..0a18e697830caeaf00f97b4d0f61437c7cca2f2d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
@@ -9,4 +9,4 @@ prefix (vint32m1_t vx, vint32m1_t vy, size_t vl)
   return __riscv_vadd_vv_i32m1 (vx, vy, vl);
 }
 
-/* { dg-final { scan-assembler {\mth\.v\M} } } */
+/* { dg-final { scan-assembler {\mth\.vadd\.vv\M} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
index 3c12c12459747a2bc513a4af9741f833d38d6622..16073ccb236678ab185c7921b49e53c82daeb7cb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
@@ -5,7 +5,8 @@
 
 /*
 ** f1:
-**     th.vsetivli\tzero,4,e32,m1,tu,ma
+**     li\t[a-x0-9]+,4
+**     th.vsetvli\tzero,[a-x0-9]+,e32,m1
 **     th.vlb\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     th.vlb\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     th.vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -24,9 +25,10 @@ void f1 (void * in, void *out)
 
 /*
 ** f2:
-**     th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**     th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     th.vsetivli\tzero,4,e32,m1,ta,ma
+**     th.vsetvli\tzero,zero,e8,m1
+**     th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+**     li\t[a-x0-9]+,4
+**     th.vsetvli\tzero,[a-x0-9]+,e32,m1
 **     th.vlb.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     th.vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 **     th.vadd\.vv\tv[1-9][0-9]?,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t
@@ -46,9 +48,10 @@ void f2 (void * in, void *out)
 
 /*
 ** f3:
-**     th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**     th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     th.vsetivli\tzero,4,e32,m1,tu,mu
+**     th.vsetvli\tzero,zero,e8,m1
+**     th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+**     li\t[a-x0-9]+,4
+**     th.vsetvli\tzero,[a-x0-9]+,e32,m1
 **     th.vlb\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     th.vlb.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     th.vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
index 30bef369375f5b05ac7fea10515314212dea1cd3..f60f125c0e56e9878d37df599d506f38a62c6ce4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
@@ -5,7 +5,8 @@
 
 /*
 ** f1:
-**     th.vsetivli\tzero,4,e32,m1,tu,ma
+**     li\t[a-x0-9]+,4
+**     th.vsetvli\tzero,[a-x0-9]+,e32,m1
 **     th.vlbu\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     th.vlbu\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -24,9 +25,10 @@ void f1 (void * in, void *out, uint32_t x)
 
 /*
 ** f2:
-**     th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**     th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     th.vsetivli\tzero,4,e32,m1,ta,ma
+**     th.vsetvli\tzero,zero,e8,m1
+**     th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+**     li\t[a-x0-9]+,4
+**     th.vsetvli\tzero,[a-x0-9]+,e32,m1
 **     th.vlbu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -46,9 +48,10 @@ void f2 (void * in, void *out, uint32_t x)
 
 /*
 ** f3:
-**     th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**     th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     th.vsetivli\tzero,4,e32,m1,tu,mu
+**     th.vsetvli\tzero,zero,e8,m1
+**     th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+**     li\t[a-x0-9]+,4
+**     th.vsetvli\tzero,[a-x0-9]+,e32,m1
 **     th.vlbu\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     th.vlbu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
index 3c8b5ccc16ba0746760b2ab64bad3fdb92fd0463..ec1a18f33cd370d3a0e29274246039b5b08dc717 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
@@ -5,7 +5,8 @@
 
 /*
 ** f1:
-**     th.vsetivli\tzero,4,e32,m1,tu,ma
+**     li\t[a-x0-9]+,4
+**     th.vsetvli\tzero,[a-x0-9]+,e32,m1
 **     th.vlh\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     th.vlh\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -24,9 +25,10 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**     th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     th.vsetivli\tzero,4,e32,m1,ta,ma
+**     th.vsetvli\tzero,zero,e8,m1
+**     th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+**     li\t[a-x0-9]+,4
+**     th.vsetvli\tzero,[a-x0-9]+,e32,m1
 **     th.vlh.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -46,9 +48,10 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**     th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     th.vsetivli\tzero,4,e32,m1,tu,mu
+**     th.vsetvli\tzero,zero,e8,m1
+**     th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+**     li\t[a-x0-9]+,4
+**     th.vsetvli\tzero,[a-x0-9]+,e32,m1
 **     th.vlh\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     th.vlh.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
index b7c00404f181ba4b510167d52c3194dd705014fe..6cdd2dd8eb0c99559065a0424e331a664b84aac2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
@@ -5,7 +5,8 @@
 
 /*
 ** f1:
-**     th.vsetivli\tzero,4,e32,m1,tu,ma
+**     li\t[a-x0-9]+,4
+**     th.vsetvli\tzero,[a-x0-9]+,e32,m1
 **     th.vlhu\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     th.vlhu\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -24,9 +25,10 @@ void f1 (void * in, void *out, uint32_t x)
 
 /*
 ** f2:
-**     th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**     th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     th.vsetivli\tzero,4,e32,m1,ta,ma
+**     th.vsetvli\tzero,zero,e8,m1
+**     th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+**     li\t[a-x0-9]+,4
+**     th.vsetvli\tzero,[a-x0-9]+,e32,m1
 **     th.vlhu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -46,9 +48,10 @@ void f2 (void * in, void *out, uint32_t x)
 
 /*
 ** f3:
-**     th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**     th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     th.vsetivli\tzero,4,e32,m1,tu,mu
+**     th.vsetvli\tzero,zero,e8,m1
+**     th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+**     li\t[a-x0-9]+,4
+**     th.vsetvli\tzero,[a-x0-9]+,e32,m1
 **     th.vlhu\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     th.vlhu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
index 17a53012acf73e9500d2b1b6ada38184db8a09dc..74a2369f1353e58696c513eaea9fcf50b63e548e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
@@ -5,7 +5,8 @@
 
 /*
 ** f1:
-**     th.vsetivli\tzero,4,e32,m1,tu,ma
+**     li\t[a-x0-9]+,4
+**     th.vsetvli\tzero,[a-x0-9]+,e32,m1
 **     th.vlw\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     th.vlw\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +25,10 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**     th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     th.vsetivli\tzero,4,e32,m1,ta,ma
+**     th.vsetvli\tzero,zero,e8,m1
+**     th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+**     li\t[a-x0-9]+,4
+**     th.vsetvli\tzero,[a-x0-9]+,e32,m1
 **     th.vlw.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     th.vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +48,10 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**     th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     th.vsetivli\tzero,4,e32,m1,tu,mu
+**     th.vsetvli\tzero,zero,e8,m1
+**     th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+**     li\t[a-x0-9]+,4
+**     th.vsetvli\tzero,[a-x0-9]+,e32,m1
 **     th.vlw\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     th.vlw.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c
index b187cfc852b9a58dda4ddd693719a394a82fee8e..0ddc3e8808b054a51035ab5c84d54ffeb3e0ba81 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c
@@ -5,7 +5,8 @@
 
 /*
 ** f1:
-**     th.vsetivli\tzero,4,e32,m1,tu,ma
+**     li\t[a-x0-9]+,4
+**     th.vsetvli\tzero,[a-x0-9]+,e32,m1
 **     th.vlwu\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     th.vlwu\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -24,9 +25,10 @@ void f1 (void * in, void *out, uint32_t x)
 
 /*
 ** f2:
-**     th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**     th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     th.vsetivli\tzero,4,e32,m1,ta,ma
+**     th.vsetvli\tzero,zero,e8,m1
+**     th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+**     li\t[a-x0-9]+,4
+**     th.vsetvli\tzero,[a-x0-9]+,e32,m1
 **     th.vlwu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -46,9 +48,10 @@ void f2 (void * in, void *out, uint32_t x)
 
 /*
 ** f3:
-**     th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**     th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     th.vsetivli\tzero,4,e32,m1,tu,mu
+**     th.vsetvli\tzero,zero,e8,m1
+**     th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+**     li\t[a-x0-9]+,4
+**     th.vsetvli\tzero,[a-x0-9]+,e32,m1
 **     th.vlwu\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     th.vlwu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16