]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
[testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
authorAlexandre Oliva <oliva@adacore.com>
Wed, 29 May 2024 05:52:18 +0000 (02:52 -0300)
committerAlexandre Oliva <oliva@gnu.org>
Thu, 30 May 2024 07:08:31 +0000 (04:08 -0300)
Codegen changes caused add instruction count mismatches on
ppc-*-linux-gnu and other 32-bit ppc targets.  At some point the
expected counts were adjusted for lp64, but ilp32 differences
remained, and published test results confirm it.

for  gcc/testsuite/ChangeLog

PR testsuite/101169
* gcc.target/powerpc/fold-vec-extract-double.p7.c: Adjust addi
counts for ilp32.
* gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise.

gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c

index 3cae644b90b71feb250a96481a2fe389db193a7f..e69d9253e2d287b3496e2f57f32209d74f2aa200 100644 (file)
 /* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */
 /* { dg-final { scan-assembler-times {\mli\M} 1 } } */
 /* -m32 target has an 'add' in place of one of the 'addi'. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi?\M} 2 } } */
 /* -m32 target has a rlwinm in place of a rldic .  */
 /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
 /* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlfdx\M|\mlfd\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlfdx?\M} 1 } } */
 
 #include <altivec.h>
 
index f7c06e961091416d0014125471ec5cab57a0d699..ab03cd8adb00e5932643ec144e3167548860614e 100644 (file)
 /* { dg-final { scan-assembler-times {\mxscvspdp\M} 1 } } */
 /* { dg-final { scan-assembler-times {\mli\M} 1 } } */
 /* -m32 as an add in place of an addi. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi?\M} 2 } } */
 /* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */
 /* -m32 uses rlwinm in place of rldic */
 /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
 /* -m32 has lfs in place of lfsx */
-/* { dg-final { scan-assembler-times {\mlfsx\M|\mlfs\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlfsx?\M} 1 } } */
 
 #include <altivec.h>
 
index 6819d271c539d8373f40e1c924d1648c54d5652d..ce435d82c164521f4f80a88f680c66b502b9fa11 100644 (file)
@@ -24,9 +24,8 @@
 /* { dg-final { scan-assembler-times {\mli\M} 1 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times {\mrlwinm\M} 1 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi?\M} 2 { target ilp32 } } } */
 
 
 #include <altivec.h>
index 51636926953398313b33a6dd53b2b12452d5f2a0..20e3d25348952645561aab9f6b049c739c7e76bc 100644 (file)
@@ -10,8 +10,7 @@
 // P7 variables:  li, addi, stxvw4x, lwa/lwz
 
 /* { dg-final { scan-assembler-times {\mli\M} 6 } } */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi?\M} 9 } } */
 /* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */
 /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 3 } } */
 /* { dg-final { scan-assembler-times {\mlwz\M|\mlwa\M|\mlwzx\M|\mlwax\M} 6 } } */
index 67fa89d9e02e6526c57c805c590dd7f998c62ca0..81d95e456bf01dad40a35385cb96abd7d4d6750a 100644 (file)
@@ -28,9 +28,8 @@
 /* { dg-final { scan-assembler-times {\mli\M} 6 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times {\mrlwinm\M} 3 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times {\mstxvw4x\M} 6 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\madd\M} 3 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times {\mlwz\M} 6 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 9 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi?\M} 9 { target ilp32 } } } */
 
 
 
index 5f3b11fc5c10e8ed2b1c3f9f3db96439b70b5abc..d8ed54703c9ea08c04ff0d8f1feb689ca26218a0 100644 (file)
@@ -10,8 +10,7 @@
 // P7 (be) constants:            li, addi,              stxvw4x, lha/lhz
 
 /* { dg-final { scan-assembler-times {\mli\M} 6 } } */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi?\M} 9 } } */
 /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 3 } } */
 /* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M} 6 } } */
 /* { dg-final { scan-assembler-times "lhz|lha|lhzx|lhax" 6 } } */
index 0db99933871ff195d0d099420ab25950e181f4bc..af741c1a7ab83934bc78a2d84180201e691dd8b9 100644 (file)
@@ -30,9 +30,8 @@
 /* { dg-final { scan-assembler-times {\mli\M} 6 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times "stxvw4x" 6 { target ilp32 } } } */
 /* add and rlwinm instructions only on the variable tests. */
-/* { dg-final { scan-assembler-times {\madd\M} 3 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times "rlwinm" 3 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 9 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi?\M} 9 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times {\mlha\M|\mlhz\M} 6 { target ilp32 } } } */