arm64: dts: ti: k3-am62p-j722s-common-main: Add HSM M4F node

The TI K3 AM62P and J722S SoCs have a HSM (High Security Module) M4F
core in the MAIN Voltage Domain which could be used to run secure
services like Authentication. Add Device Tree Node definitions for the
HSM core in the respective SoC common main dtsi file.

The HSM node is reserved to be loaded and booted by the early-stage
bootloader. The firmware-name property is defined at the SoC level
since the HSM is not a general-purpose remote core and boards are
unlikely to use separate firmware. If needed in exceptional cases,
board-specific device trees can override this property.

The corresponding reg ranges of HSM node has also been added to its
parent node's (cbass_main bus) ranges property.

Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://patch.msgid.link/20260114173551.2545088-3-b-padhi@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
index 3cf7c2b3ce2ddd1516e67578043a9ff102a4a169..0e1af2a69ca2ed608b2547e77572e0f96be5e17f 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
@@ -1117,4 +1117,21 @@
                clocks = <&k3_clks 204 2>;
                power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>;
        };
+
+       hsm: remoteproc@43c00000 {
+               compatible = "ti,hsm-m4fss";
+               /* contiguous regions but instantiated separately in HW */
+               reg = <0x00 0x43c00000 0x00 0x20000>,
+                     <0x00 0x43c20000 0x00 0x10000>,
+                     <0x00 0x43c30000 0x00 0x10000>;
+               reg-names = "sram0_0", "sram0_1", "sram1";
+               resets = <&k3_reset 225 1>;
+               firmware-name = "am62p-hsm-m4f-fw";
+               bootph-pre-ram;
+               ti,sci = <&dmsc>;
+               ti,sci-dev-id = <225>;
+               ti,sci-proc-ids = <0x80 0xff>;
+               /* reserved for early-stage bootloader */
+               status = "reserved";
+       };
 };

diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p.dtsi
index e2c01328eb2986312c280d585bf763c51ec61488..9d6266d6ddb82554577f9bf0dfa59a09cdef7b8c 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi
@@ -96,6 +96,7 @@
                         <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
                         <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
                         <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
+                        <0x00 0x43c00000 0x00 0x43c00000 0x00 0x00040000>, /* HSM SRAM ranges */
                         <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
                         <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
                         <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */

diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
index 873415ec4fa37c8fed0342376fad8d91f0b8f431..9ee5d0c8ffd1ef9be023a2739708b1718fbf0539 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -429,6 +429,11 @@
        firmware-name = "j722s-wkup-r5f0_0-fw";
 };
 
+/* MAIN domain overrides */
+&hsm {
+       firmware-name = "j722s-hsm-m4f-fw";
+};
+
 &main_conf {
        serdes_ln_ctrl: mux-controller@4080 {
                compatible = "reg-mux";

diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
index c8b634c346779039bb625016c080f09ae1f8cf1a..059c65ece183f60b9b1c6e5447579cee1524f0b3 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
@@ -173,6 +173,7 @@
                         <0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core window */
                         <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
                         <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
+                        <0x00 0x43c00000 0x00 0x43c00000 0x00 0x00040000>, /* HSM SRAM ranges */
                         <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
                         <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
                         <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */