clk: qcom: rpmh: Add support for Kaanapali rpmh clocks

Add the RPMH clocks present in Kaanapali SoC.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251209-gcc_kaanapali-v3-v5-2-3af118262289@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index a2185a6f321fb60ddc9272582ed67fa9ada6535e..10e84ada48eed0a0ed6d93d9c2232ac67f6784ca 100644 (file)
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -390,11 +390,22 @@ DEFINE_CLK_RPMH_VRM(clk7, _a4, "clka7", 4);
 
 DEFINE_CLK_RPMH_VRM(div_clk1, _div2, "divclka1", 2);
 
+DEFINE_CLK_RPMH_VRM(clk1, _a1_e0, "C1A_E0", 1);
+DEFINE_CLK_RPMH_VRM(clk2, _a1_e0, "C2A_E0", 1);
 DEFINE_CLK_RPMH_VRM(clk3, _a1_e0, "C3A_E0", 1);
 DEFINE_CLK_RPMH_VRM(clk4, _a1_e0, "C4A_E0", 1);
 DEFINE_CLK_RPMH_VRM(clk5, _a1_e0, "C5A_E0", 1);
 DEFINE_CLK_RPMH_VRM(clk8, _a1_e0, "C8A_E0", 1);
 
+DEFINE_CLK_RPMH_VRM(clk3, _a2_e0, "C3A_E0", 2);
+DEFINE_CLK_RPMH_VRM(clk4, _a2_e0, "C4A_E0", 2);
+DEFINE_CLK_RPMH_VRM(clk5, _a2_e0, "C5A_E0", 2);
+DEFINE_CLK_RPMH_VRM(clk6, _a2_e0, "C6A_E0", 2);
+DEFINE_CLK_RPMH_VRM(clk7, _a2_e0, "C7A_E0", 2);
+DEFINE_CLK_RPMH_VRM(clk8, _a2_e0, "C8A_E0", 2);
+
+DEFINE_CLK_RPMH_VRM(clk11, _a4_e0, "C11A_E0", 4);
+
 DEFINE_CLK_RPMH_BCM(ce, "CE0");
 DEFINE_CLK_RPMH_BCM(hwkm, "HK0");
 DEFINE_CLK_RPMH_BCM(ipa, "IP0");
@@ -901,6 +912,34 @@ static const struct clk_rpmh_desc clk_rpmh_glymur = {
        .num_clks = ARRAY_SIZE(glymur_rpmh_clocks),
 };
 
+static struct clk_hw *kaanapali_rpmh_clocks[] = {
+       [RPMH_CXO_CLK]          = &clk_rpmh_bi_tcxo_div2.hw,
+       [RPMH_CXO_CLK_A]        = &clk_rpmh_bi_tcxo_div2_ao.hw,
+       [RPMH_DIV_CLK1]         = &clk_rpmh_clk11_a4_e0.hw,
+       [RPMH_LN_BB_CLK1]       = &clk_rpmh_clk6_a2_e0.hw,
+       [RPMH_LN_BB_CLK1_A]     = &clk_rpmh_clk6_a2_e0_ao.hw,
+       [RPMH_LN_BB_CLK2]       = &clk_rpmh_clk7_a2_e0.hw,
+       [RPMH_LN_BB_CLK2_A]     = &clk_rpmh_clk7_a2_e0_ao.hw,
+       [RPMH_LN_BB_CLK3]       = &clk_rpmh_clk8_a2_e0.hw,
+       [RPMH_LN_BB_CLK3_A]     = &clk_rpmh_clk8_a2_e0_ao.hw,
+       [RPMH_RF_CLK1]          = &clk_rpmh_clk1_a1_e0.hw,
+       [RPMH_RF_CLK1_A]        = &clk_rpmh_clk1_a1_e0_ao.hw,
+       [RPMH_RF_CLK2]          = &clk_rpmh_clk2_a1_e0.hw,
+       [RPMH_RF_CLK2_A]        = &clk_rpmh_clk2_a1_e0_ao.hw,
+       [RPMH_RF_CLK3]          = &clk_rpmh_clk3_a2_e0.hw,
+       [RPMH_RF_CLK3_A]        = &clk_rpmh_clk3_a2_e0_ao.hw,
+       [RPMH_RF_CLK4]          = &clk_rpmh_clk4_a2_e0.hw,
+       [RPMH_RF_CLK4]          = &clk_rpmh_clk4_a2_e0_ao.hw,
+       [RPMH_RF_CLK5_A]        = &clk_rpmh_clk5_a2_e0.hw,
+       [RPMH_RF_CLK5_A]        = &clk_rpmh_clk5_a2_e0_ao.hw,
+       [RPMH_IPA_CLK]          = &clk_rpmh_ipa.hw,
+};
+
+static const struct clk_rpmh_desc clk_rpmh_kaanapali = {
+       .clks = kaanapali_rpmh_clocks,
+       .num_clks = ARRAY_SIZE(kaanapali_rpmh_clocks),
+};
+
 static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
                                         void *data)
 {
@@ -991,6 +1030,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
 
 static const struct of_device_id clk_rpmh_match_table[] = {
        { .compatible = "qcom,glymur-rpmh-clk", .data = &clk_rpmh_glymur},
+       { .compatible = "qcom,kaanapali-rpmh-clk", .data = &clk_rpmh_kaanapali},
        { .compatible = "qcom,milos-rpmh-clk", .data = &clk_rpmh_milos},
        { .compatible = "qcom,qcs615-rpmh-clk", .data = &clk_rpmh_qcs615},
        { .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000},