]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
wifi: ath12k: Refactor idle ring descriptor setup
authorKarthikeyan Periyasamy <quic_periyasa@quicinc.com>
Fri, 3 May 2024 10:34:38 +0000 (13:34 +0300)
committerKalle Valo <quic_kvalo@quicinc.com>
Fri, 3 May 2024 13:19:23 +0000 (16:19 +0300)
Currently, the WBM idle ring descriptor setup uses implicit value
HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST for the return buffer manager
parameter. To support inter-device MLO (Multi-link operation), this
parameter needs to be configure dynamically based on the device identifier
within the MLO group. Therefore, introduce a new argument to the helper
function ath12k_hal_set_link_desc_addr().

Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.0.1-00029-QCAHKSWPL_SILICONZ-1

Signed-off-by: Karthikeyan Periyasamy <quic_periyasa@quicinc.com>
Acked-by: Jeff Johnson <quic_jjohnson@quicinc.com>
Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
Link: https://msgid.link/20240430165811.1377182-3-quic_periyasa@quicinc.com
drivers/net/wireless/ath/ath12k/dp.c
drivers/net/wireless/ath/ath12k/dp.h
drivers/net/wireless/ath/ath12k/dp_rx.c
drivers/net/wireless/ath/ath12k/hal.c
drivers/net/wireless/ath/ath12k/hal.h

index 7843c76a82c17f8dac490e33b9809a5a477c6678..f41b3f9dac3d5b6e176ac85f27a72e513f461fb3 100644 (file)
@@ -616,6 +616,7 @@ static int ath12k_dp_scatter_idle_link_desc_setup(struct ath12k_base *ab,
        int i;
        int ret = 0;
        u32 end_offset, cookie;
+       enum hal_rx_buf_return_buf_manager rbm = dp->idle_link_rbm;
 
        n_entries_per_buf = HAL_WBM_IDLE_SCATTER_BUF_SIZE /
                ath12k_hal_srng_get_entrysize(ab, HAL_WBM_IDLE_LINK);
@@ -646,7 +647,8 @@ static int ath12k_dp_scatter_idle_link_desc_setup(struct ath12k_base *ab,
                paddr = link_desc_banks[i].paddr;
                while (n_entries) {
                        cookie = DP_LINK_DESC_COOKIE_SET(n_entries, i);
-                       ath12k_hal_set_link_desc_addr(scatter_buf, cookie, paddr);
+                       ath12k_hal_set_link_desc_addr(scatter_buf, cookie,
+                                                     paddr, rbm);
                        n_entries--;
                        paddr += HAL_LINK_DESC_SIZE;
                        if (rem_entries) {
@@ -790,6 +792,7 @@ int ath12k_dp_link_desc_setup(struct ath12k_base *ab,
        u32 paddr;
        int i, ret;
        u32 cookie;
+       enum hal_rx_buf_return_buf_manager rbm = ab->dp.idle_link_rbm;
 
        tot_mem_sz = n_link_desc * HAL_LINK_DESC_SIZE;
        tot_mem_sz += HAL_LINK_DESC_ALIGN;
@@ -850,8 +853,7 @@ int ath12k_dp_link_desc_setup(struct ath12k_base *ab,
                while (n_entries &&
                       (desc = ath12k_hal_srng_src_get_next_entry(ab, srng))) {
                        cookie = DP_LINK_DESC_COOKIE_SET(n_entries, i);
-                       ath12k_hal_set_link_desc_addr(desc,
-                                                     cookie, paddr);
+                       ath12k_hal_set_link_desc_addr(desc, cookie, paddr, rbm);
                        n_entries--;
                        paddr += HAL_LINK_DESC_SIZE;
                }
@@ -1603,6 +1605,7 @@ int ath12k_dp_alloc(struct ath12k_base *ab)
        spin_lock_init(&dp->reo_cmd_lock);
 
        dp->reo_cmd_cache_flush_count = 0;
+       dp->idle_link_rbm = HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST;
 
        ret = ath12k_wbm_idle_ring_setup(ab, &n_link_desc);
        if (ret) {
index 5cf0d21ef184b6f2ed60105fe8759dd37e98fcc4..e9880b34a7abeeb5ebc182698b2fa82b63b08e46 100644 (file)
@@ -325,6 +325,7 @@ struct ath12k_dp {
        u8 htt_tgt_ver_major;
        u8 htt_tgt_ver_minor;
        struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
+       enum hal_rx_buf_return_buf_manager idle_link_rbm;
        struct dp_srng wbm_idle_ring;
        struct dp_srng wbm_desc_rel_ring;
        struct dp_srng tcl_cmd_ring;
index fc4b953249552aad4ae4a96dc441ee65621a6e2b..18030c9e735d4b80fb474ab39a1ea9ba41eb5a61 100644 (file)
@@ -2994,6 +2994,7 @@ static int ath12k_dp_rx_h_defrag_reo_reinject(struct ath12k *ar,
        u32 cookie, hal_rx_desc_sz, dest_ring_info0;
        int ret;
        struct ath12k_rx_desc_info *desc_info;
+       enum hal_rx_buf_return_buf_manager idle_link_rbm = dp->idle_link_rbm;
        u8 dst_ind;
 
        hal_rx_desc_sz = ab->hal.hal_desc_sz;
@@ -3071,7 +3072,7 @@ static int ath12k_dp_rx_h_defrag_reo_reinject(struct ath12k *ar,
 
        ath12k_hal_rx_buf_addr_info_set(&reo_ent_ring->buf_addr_info, link_paddr,
                                        cookie,
-                                       HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST);
+                                       idle_link_rbm);
 
        mpdu_info = u32_encode_bits(1, RX_MPDU_DESC_INFO0_MSDU_COUNT) |
                    u32_encode_bits(0, RX_MPDU_DESC_INFO0_FRAG_FLAG) |
@@ -3451,7 +3452,7 @@ int ath12k_dp_rx_process_err(struct ath12k_base *ab, struct napi_struct *napi,
                               (paddr - link_desc_banks[desc_bank].paddr);
                ath12k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
                                                 &rbm);
-               if (rbm != HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST &&
+               if (rbm != dp->idle_link_rbm &&
                    rbm != HAL_RX_BUF_RBM_SW3_BM &&
                    rbm != ab->hw_params->hal_params->rx_buf_rbm) {
                        ab->soc_stats.invalid_rbm++;
index 78310da8cfe8e87d33d5307a66dbeb32cdd88fae..ca04bfae8bdccc578005d7c4c45a0d1de7a5f923 100644 (file)
@@ -1969,14 +1969,15 @@ u32 ath12k_hal_ce_dst_status_get_length(struct hal_ce_srng_dst_status_desc *desc
 }
 
 void ath12k_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, u32 cookie,
-                                  dma_addr_t paddr)
+                                  dma_addr_t paddr,
+                                  enum hal_rx_buf_return_buf_manager rbm)
 {
        desc->buf_addr_info.info0 = le32_encode_bits((paddr & HAL_ADDR_LSB_REG_MASK),
                                                     BUFFER_ADDR_INFO0_ADDR);
        desc->buf_addr_info.info1 =
                        le32_encode_bits(((u64)paddr >> HAL_ADDR_MSB_REG_SHIFT),
                                         BUFFER_ADDR_INFO1_ADDR) |
-                       le32_encode_bits(1, BUFFER_ADDR_INFO1_RET_BUF_MGR) |
+                       le32_encode_bits(rbm, BUFFER_ADDR_INFO1_RET_BUF_MGR) |
                        le32_encode_bits(cookie, BUFFER_ADDR_INFO1_SW_COOKIE);
 }
 
index f364b2938ef850c8383968e3020fab4a82d02726..8a78bb9a10bc15a3c715c2c2b03ed18e21b5816e 100644 (file)
@@ -1113,7 +1113,8 @@ dma_addr_t ath12k_hal_srng_get_tp_addr(struct ath12k_base *ab,
 dma_addr_t ath12k_hal_srng_get_hp_addr(struct ath12k_base *ab,
                                       struct hal_srng *srng);
 void ath12k_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, u32 cookie,
-                                  dma_addr_t paddr);
+                                  dma_addr_t paddr,
+                                  enum hal_rx_buf_return_buf_manager rbm);
 u32 ath12k_hal_ce_get_desc_size(enum hal_ce_desc type);
 void ath12k_hal_ce_src_set_desc(struct hal_ce_srng_src_desc *desc, dma_addr_t paddr,
                                u32 len, u32 id, u8 byte_swap_data);