]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
wifi: rtw89: phy: abstract BB wrap registers to share initial flow
authorPing-Ke Shih <pkshih@realtek.com>
Wed, 14 Jan 2026 01:39:44 +0000 (09:39 +0800)
committerPing-Ke Shih <pkshih@realtek.com>
Thu, 22 Jan 2026 01:38:18 +0000 (09:38 +0800)
BB wrap registers are to configure TX power in MAC register domain, but
they are controlled and designed by BB layer. Since coming chips use
different register address, add a struct to define them.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20260114013950.19704-7-pkshih@realtek.com
drivers/net/wireless/realtek/rtw89/phy.c
drivers/net/wireless/realtek/rtw89/phy.h
drivers/net/wireless/realtek/rtw89/phy_be.c
drivers/net/wireless/realtek/rtw89/reg.h

index 77481695cd2ece0d06fa4317f389e27220b1e127..d311de093425a9af932bcace7d9d6d8216680c17 100644 (file)
@@ -8237,6 +8237,7 @@ const struct rtw89_phy_gen_def rtw89_phy_gen_ax = {
        .ccx = &rtw89_ccx_regs_ax,
        .physts = &rtw89_physts_regs_ax,
        .cfo = &rtw89_cfo_regs_ax,
+       .bb_wrap = NULL,
        .phy0_phy1_offset = rtw89_phy0_phy1_offset_ax,
        .config_bb_gain = rtw89_phy_config_bb_gain_ax,
        .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_ax,
index f285806896268a234e7766b4e78a107cc268a693..0834569278cd0eed7ce027859ae4f88ad5fb471c 100644 (file)
@@ -460,6 +460,11 @@ struct rtw89_cfo_regs {
        u32 valid_0_mask;
 };
 
+struct rtw89_bb_wrap_regs {
+       u32 pwr_macid_lmt;
+       u32 pwr_macid_path;
+};
+
 enum rtw89_bandwidth_section_num_ax {
        RTW89_BW20_SEC_NUM_AX = 8,
        RTW89_BW40_SEC_NUM_AX = 4,
@@ -537,6 +542,7 @@ struct rtw89_phy_gen_def {
        const struct rtw89_ccx_regs *ccx;
        const struct rtw89_physts_regs *physts;
        const struct rtw89_cfo_regs *cfo;
+       const struct rtw89_bb_wrap_regs *bb_wrap;
        u32 (*phy0_phy1_offset)(struct rtw89_dev *rtwdev, u32 addr);
        void (*config_bb_gain)(struct rtw89_dev *rtwdev,
                               const struct rtw89_reg2_def *reg,
index 33c28a1666d4a0191f49c969f06be42b9e47ed9f..e333c3eb1e9bbd2effe2ddb58d377feb37dd7d7d 100644 (file)
@@ -160,6 +160,16 @@ static const struct rtw89_cfo_regs rtw89_cfo_regs_be_v1 = {
        .valid_0_mask = B_DCFO_OPT_EN_BE,
 };
 
+static const struct rtw89_bb_wrap_regs rtw89_bb_wrap_regs_be = {
+       .pwr_macid_lmt = R_BE_PWR_MACID_LMT_BASE,
+       .pwr_macid_path = R_BE_PWR_MACID_PATH_BASE,
+};
+
+static const struct rtw89_bb_wrap_regs rtw89_bb_wrap_regs_be_v1 = {
+       .pwr_macid_lmt = R_BE_PWR_MACID_LMT_BASE_V1,
+       .pwr_macid_path = R_BE_PWR_MACID_PATH_BASE_V1,
+};
+
 static u32 rtw89_phy0_phy1_offset_be(struct rtw89_dev *rtwdev, u32 addr)
 {
        u32 phy_page = addr >> 8;
@@ -406,9 +416,11 @@ static void rtw89_phy_preinit_rf_nctl_be_v1(struct rtw89_dev *rtwdev)
 static
 void rtw89_phy_bb_wrap_pwr_by_macid_init(struct rtw89_dev *rtwdev)
 {
+       const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
+       const struct rtw89_bb_wrap_regs *bb_wrap = phy->bb_wrap;
        u32 macid_idx, cr, base_macid_lmt, max_macid = 32;
 
-       base_macid_lmt = R_BE_PWR_MACID_LMT_BASE;
+       base_macid_lmt = bb_wrap->pwr_macid_lmt;
 
        for (macid_idx = 0; macid_idx < 4 * max_macid; macid_idx += 4) {
                cr = base_macid_lmt + macid_idx;
@@ -419,8 +431,10 @@ void rtw89_phy_bb_wrap_pwr_by_macid_init(struct rtw89_dev *rtwdev)
 static
 void rtw89_phy_bb_wrap_tx_path_by_macid_init(struct rtw89_dev *rtwdev)
 {
+       const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
+       const struct rtw89_bb_wrap_regs *bb_wrap = phy->bb_wrap;
+       u32 cr = bb_wrap->pwr_macid_path;
        int i, max_macid = 32;
-       u32 cr = R_BE_PWR_MACID_PATH_BASE;
 
        for (i = 0; i < max_macid; i++, cr += 4)
                rtw89_write32(rtwdev, cr, 0x03C86000);
@@ -1119,6 +1133,7 @@ const struct rtw89_phy_gen_def rtw89_phy_gen_be = {
        .ccx = &rtw89_ccx_regs_be,
        .physts = &rtw89_physts_regs_be,
        .cfo = &rtw89_cfo_regs_be,
+       .bb_wrap = &rtw89_bb_wrap_regs_be,
        .phy0_phy1_offset = rtw89_phy0_phy1_offset_be,
        .config_bb_gain = rtw89_phy_config_bb_gain_be,
        .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_be,
@@ -1139,6 +1154,7 @@ const struct rtw89_phy_gen_def rtw89_phy_gen_be_v1 = {
        .ccx = &rtw89_ccx_regs_be_v1,
        .physts = &rtw89_physts_regs_be_v1,
        .cfo = &rtw89_cfo_regs_be_v1,
+       .bb_wrap = &rtw89_bb_wrap_regs_be_v1,
        .phy0_phy1_offset = rtw89_phy0_phy1_offset_be_v1,
        .config_bb_gain = rtw89_phy_config_bb_gain_be,
        .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_be_v1,
index 115d3b0084522ed135612678c01b17142461dd06..ab344d0269f763db8dcda22f012c31dcb3e52ea5 100644 (file)
 #define B_BE_PTA_GNT_BT1_BB_SWCTRL BIT(0)
 
 #define R_BE_PWR_MACID_PATH_BASE 0x0E500
+#define R_BE_PWR_MACID_PATH_BASE_V1 0x1C000
 #define R_BE_PWR_MACID_LMT_BASE 0x0ED00
+#define R_BE_PWR_MACID_LMT_BASE_V1 0x1C800
 
 #define R_BE_CMAC_FUNC_EN 0x10000
 #define R_BE_CMAC_FUNC_EN_C1 0x14000