ARM: tegra: Add missing HOST1X device nodes on Tegra124

Add nodes for devices on the HOST1X bus: VI, ISP, ISPB, MSENC and TSEC.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm/boot/dts/nvidia/tegra124.dtsi b/arch/arm/boot/dts/nvidia/tegra124.dtsi
index ec4f0e346b2bf0ddb97ef62ac4a9be61681a3d04..ce4efa1de509b7ff59082ce6c0e5678115a38e9a 100644 (file)
--- a/arch/arm/boot/dts/nvidia/tegra124.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra124.dtsi
@@ -103,6 +103,45 @@
 
                ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
 
+               vi@54080000 {
+                       compatible = "nvidia,tegra124-vi";
+                       reg = <0x0 0x54080000 0x0 0x00040000>;
+                       interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&tegra_car TEGRA124_CLK_VI>;
+                       resets = <&tegra_car 20>;
+                       reset-names = "vi";
+
+                       iommus = <&mc TEGRA_SWGROUP_VI>;
+
+                       status = "disabled";
+               };
+
+               isp@54600000 {
+                       compatible = "nvidia,tegra124-isp";
+                       reg = <0x0 0x54600000 0x0 0x00040000>;
+                       interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&tegra_car TEGRA124_CLK_ISP>;
+                       resets = <&tegra_car TEGRA124_CLK_ISP>;
+                       reset-names = "isp";
+
+                       iommus = <&mc TEGRA_SWGROUP_ISP2>;
+
+                       status = "disabled";
+               };
+
+               isp@54680000 {
+                       compatible = "nvidia,tegra124-isp";
+                       reg = <0x0 0x54680000 0x0 0x00040000>;
+                       interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&tegra_car TEGRA124_CLK_ISPB>;
+                       resets = <&tegra_car TEGRA124_CLK_ISPB>;
+                       reset-names = "isp";
+
+                       iommus = <&mc TEGRA_SWGROUP_ISP2B>;
+
+                       status = "disabled";
+               };
+
                dc@54200000 {
                        compatible = "nvidia,tegra124-dc";
                        reg = <0x0 0x54200000 0x0 0x00040000>;
@@ -209,6 +248,31 @@
                        #size-cells = <0>;
                };
 
+               msenc@544c0000 {
+                       compatible = "nvidia,tegra124-msenc";
+                       reg = <0x0 0x544c0000 0x0 0x00040000>;
+                       interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&tegra_car TEGRA124_CLK_MSENC>;
+                       resets = <&tegra_car TEGRA124_CLK_MSENC>;
+                       reset-names = "mpe";
+
+                       iommus = <&mc TEGRA_SWGROUP_MSENC>;
+
+                       status = "disabled";
+               };
+
+               tsec@54500000 {
+                       compatible = "nvidia,tegra124-tsec";
+                       reg = <0x0 0x54500000 0x0 0x00040000>;
+                       interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&tegra_car TEGRA124_CLK_TSEC>;
+                       resets = <&tegra_car TEGRA124_CLK_TSEC>;
+
+                       iommus = <&mc TEGRA_SWGROUP_TSEC>;
+
+                       status = "disabled";
+               };
+
                sor@54540000 {
                        compatible = "nvidia,tegra124-sor";
                        reg = <0x0 0x54540000 0x0 0x00040000>;