Iimplement 0F 7F encoding of movq between two registers. Fixes

#305042.  (Mans Rullgard, mans@mansr.com)

git-svn-id: svn://svn.valgrind.org/vex/trunk@2476

diff --git a/VEX/priv/guest_amd64_toIR.c b/VEX/priv/guest_amd64_toIR.c
index fcda1e21b6e79680209e8becb15a8503520dde7d..d88cdebdd8a07e95fbbf105a358f931a82ce61f8 100644 (file)
--- a/VEX/priv/guest_amd64_toIR.c
+++ b/VEX/priv/guest_amd64_toIR.c
@@ -7104,9 +7104,11 @@ ULong dis_MMX ( Bool* decode_ok,
             goto mmx_decode_failure;
          modrm = getUChar(delta);
          if (epartIsReg(modrm)) {
-            /* Fall through.  The assembler doesn't appear to generate
-               these. */
-            goto mmx_decode_failure;
+            delta++;
+            putMMXReg( eregLO3ofRM(modrm), getMMXReg(gregLO3ofRM(modrm)) );
+            DIP("movq %s, %s\n",
+                nameMMXReg(gregLO3ofRM(modrm)),
+                nameMMXReg(eregLO3ofRM(modrm)));
          } else {
             IRTemp addr = disAMode( &len, vbi, pfx, delta, dis_buf, 0 );
             delta += len;