drm/msm/disp: set num_planes, fetch_mode and tile_height in INTERLEAVED_RGB_FMT_TILED

All interleaved compressed RGB formats use only 2 planes,
MDP_FETCH_LINEAR and MDP_TILE_HEIGHT_UBWC. Specify num_planes,
fetch_mode and tile_height directly in the macro and remove unused
parameters.

Patchwork: https://patchwork.freedesktop.org/patch/688166/
Link: https://lore.kernel.org/r/20251114-dpu-formats-v3-3-cae312379d49@oss.qualcomm.com
Tested-by: Luca Weiss <luca.weiss@fairphone.com> # qcm6490-fairphone-fp5
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/disp/mdp_format.c b/drivers/gpu/drm/msm/disp/mdp_format.c
index 26be35572fd2ee7456401aa525cc36025bc52ee4..09a5bffd838b8a4fd3c22622e82dcf9fb99b5117 100644 (file)
--- a/drivers/gpu/drm/msm/disp/mdp_format.c
+++ b/drivers/gpu/drm/msm/disp/mdp_format.c
@@ -87,7 +87,7 @@ bp, flg)                                                                  \
 }
 
 #define INTERLEAVED_RGB_FMT_TILED(fmt, a, r, g, b, e0, e1, e2, e3, uc,    \
-alpha, bp, flg, fm, np, th)                                               \
+alpha, bp, flg)                                               \
 {                                                                         \
        .pixel_format = DRM_FORMAT_ ## fmt,                               \
        .fetch_type = MDP_PLANE_INTERLEAVED,                              \
@@ -100,10 +100,10 @@ alpha, bp, flg, fm, np, th)                                               \
        .chroma_sample = CHROMA_FULL,                                     \
        .unpack_count = uc,                                               \
        .bpp = bp,                                                        \
-       .fetch_mode = fm,                                                 \
+       .fetch_mode = MDP_FETCH_UBWC,                                     \
        .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg,                      \
-       .num_planes = np,                                                 \
-       .tile_height = th                                                 \
+       .num_planes = 2,                                                  \
+       .tile_height = MDP_TILE_HEIGHT_UBWC,                              \
 }
 
 #define INTERLEAVED_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, e3,              \
@@ -487,14 +487,12 @@ static const struct msm_format mdp_formats_ubwc[] = {
        INTERLEAVED_RGB_FMT_TILED(BGR565,
                0, BPC5, BPC6, BPC5,
                C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
-               false, 2, MSM_FORMAT_FLAG_COMPRESSED,
-               MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+               false, 2, MSM_FORMAT_FLAG_COMPRESSED),
 
        INTERLEAVED_RGB_FMT_TILED(ABGR8888,
                BPC8A, BPC8, BPC8, BPC8,
                C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
-               true, 4, MSM_FORMAT_FLAG_COMPRESSED,
-               MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+               true, 4, MSM_FORMAT_FLAG_COMPRESSED),
 
        /* ARGB8888 and ABGR8888 purposely have the same color
         * ordering.  The hardware only supports ABGR8888 UBWC
@@ -503,38 +501,32 @@ static const struct msm_format mdp_formats_ubwc[] = {
        INTERLEAVED_RGB_FMT_TILED(ARGB8888,
                BPC8A, BPC8, BPC8, BPC8,
                C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
-               true, 4, MSM_FORMAT_FLAG_COMPRESSED,
-               MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+               true, 4, MSM_FORMAT_FLAG_COMPRESSED),
 
        INTERLEAVED_RGB_FMT_TILED(XBGR8888,
                BPC8A, BPC8, BPC8, BPC8,
                C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
-               false, 4, MSM_FORMAT_FLAG_COMPRESSED,
-               MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+               false, 4, MSM_FORMAT_FLAG_COMPRESSED),
 
        INTERLEAVED_RGB_FMT_TILED(XRGB8888,
                BPC8A, BPC8, BPC8, BPC8,
                C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
-               false, 4, MSM_FORMAT_FLAG_COMPRESSED,
-               MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+               false, 4, MSM_FORMAT_FLAG_COMPRESSED),
 
        INTERLEAVED_RGB_FMT_TILED(ABGR2101010,
                BPC8A, BPC8, BPC8, BPC8,
                C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
-               true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
-               MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+               true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED),
 
        INTERLEAVED_RGB_FMT_TILED(XBGR2101010,
                BPC8A, BPC8, BPC8, BPC8,
                C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
-               true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
-               MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+               true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED),
 
        INTERLEAVED_RGB_FMT_TILED(XRGB2101010,
                BPC8A, BPC8, BPC8, BPC8,
                C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
-               true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
-               MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+               true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED),
 
        /* XRGB2101010 and ARGB2101010 purposely have the same color
        * ordering.  The hardware only supports ARGB2101010 UBWC
@@ -543,8 +535,7 @@ static const struct msm_format mdp_formats_ubwc[] = {
        INTERLEAVED_RGB_FMT_TILED(ARGB2101010,
                BPC8A, BPC8, BPC8, BPC8,
                C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
-               true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
-               MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+               true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED),
 
        PSEUDO_YUV_FMT_TILED(NV12,
                0, BPC8, BPC8, BPC8,