pmdomain: imx: gpcv2: Fix the imx8mm gpu hang due to wrong adb400 reset

On i.MX8MM, the GPUMIX, GPU2D, and GPU3D blocks share a common reset
domain. Due to this hardware limitation, powering off/on GPU2D or GPU3D
also triggers a reset of the GPUMIX domain, including its ADB400 port.
However, the ADB400 interface must always be placed into power‑down mode
before being reset.

Currently the GPUMIX and GPU2D/3D power domains rely on runtime PM to
handle dependency ordering. In some corner cases, the GPUMIX power off
sequence is skipped, leaving the ADB400 port active when GPU2D/3D reset.
This causes the GPUMIX ADB400 port to be reset while still active,
leading to unpredictable bus behavior and GPU hangs.

To avoid this, refine the power‑domain control logic so that the GPUMIX
ADB400 port is explicitly powered down and powered up as part of the GPU
power domain on/off sequence. This ensures proper ordering and prevents
incorrect ADB400 reset.

Suggested-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Philipp Zabel <p.zabel@pengutronix.de>
Cc: stable@vger.kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/pmdomain/imx/gpcv2.c b/drivers/pmdomain/imx/gpcv2.c
index 105fcaf13a34c787b2d568bc64e7fee9bfc23393..cff738e4d54622712f2a391cd78bae5c3dba56f6 100644 (file)
--- a/drivers/pmdomain/imx/gpcv2.c
+++ b/drivers/pmdomain/imx/gpcv2.c
@@ -165,13 +165,11 @@
 #define IMX8M_VPU_HSK_PWRDNREQN                        BIT(5)
 #define IMX8M_DISP_HSK_PWRDNREQN               BIT(4)
 
-#define IMX8MM_GPUMIX_HSK_PWRDNACKN            BIT(29)
-#define IMX8MM_GPU_HSK_PWRDNACKN               (BIT(27) | BIT(28))
+#define IMX8MM_GPU_HSK_PWRDNACKN               GENMASK(29, 27)
 #define IMX8MM_VPUMIX_HSK_PWRDNACKN            BIT(26)
 #define IMX8MM_DISPMIX_HSK_PWRDNACKN           BIT(25)
 #define IMX8MM_HSIO_HSK_PWRDNACKN              (BIT(23) | BIT(24))
-#define IMX8MM_GPUMIX_HSK_PWRDNREQN            BIT(11)
-#define IMX8MM_GPU_HSK_PWRDNREQN               (BIT(9) | BIT(10))
+#define IMX8MM_GPU_HSK_PWRDNREQN               GENMASK(11, 9)
 #define IMX8MM_VPUMIX_HSK_PWRDNREQN            BIT(8)
 #define IMX8MM_DISPMIX_HSK_PWRDNREQN           BIT(7)
 #define IMX8MM_HSIO_HSK_PWRDNREQN              (BIT(5) | BIT(6))
@@ -794,8 +792,6 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
                .bits  = {
                        .pxx = IMX8MM_GPUMIX_SW_Pxx_REQ,
                        .map = IMX8MM_GPUMIX_A53_DOMAIN,
-                       .hskreq = IMX8MM_GPUMIX_HSK_PWRDNREQN,
-                       .hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN,
                },
                .pgc   = BIT(IMX8MM_PGC_GPUMIX),
                .keep_clocks = true,