/* ELR cannot be found. */
+ /* RA_SIGN_STATE cannot be found */
+
/* FP registers (only 64bits are used). */
struct user_fpsimd_struct fregs;
iovec.iov_base = &fregs;
case 33:
return regtype ("integer", DW_ATE_address, "elr");
- case 34 ... 63:
+ case 34:
+ return regtype ("integer", DW_ATE_unsigned, "ra_sign_state");
+
+ case 35 ... 63:
return 0;
case 64 ... 95:
{ ((BYTE_ORDER == LITTLE_ENDIAN && e_ident[EI_DATA] == ELFDATA2MSB) \
|| (BYTE_ORDER == BIG_ENDIAN && e_ident[EI_DATA] == ELFDATA2LSB)) }
+/* AARCH64 DWARF registers. */
+enum
+ {
+ DW_AARCH64_RA_SIGN_STATE = 34
+ };
INTDECL (dwarf_next_cfi)
INTDECL (dwarf_getcfi)
integer reg30 (x30): same_value
integer reg31 (sp): location expression: call_frame_cfa stack_value
integer reg33 (elr): undefined
+ integer reg34 (ra_sign_state): undefined
FP/SIMD reg64 (v0): undefined
FP/SIMD reg65 (v1): undefined
FP/SIMD reg66 (v2): undefined
30: x30 (x30), signed 64 bits
31: sp (sp), address 64 bits
33: elr (elr), address 64 bits
+ 34: ra_sign_state (ra_sign_state), unsigned 64 bits
FP/SIMD registers:
64: v0 (v0), unsigned 128 bits
65: v1 (v1), unsigned 128 bits