spi: cadence-qspi: Add a flag for controllers without indirect access support

Renesas RZ/N1 QSPI controllers embed the Cadence IP with some
limitations/simplifications. One of the is that only direct access is
supported, none of the registers related to indirect writes are
populated, so create a flag to avoid these accesses and make sure only
direct accessors are called.

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
Tested-by: Santhosh Kumar K <s-k6@ti.com>
Link: https://patch.msgid.link/20260122-schneider-6-19-rc1-qspi-v4-11-f9c21419a3e6@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 075505f0abcf1bb4d80bcbac0e234c74e8b9ccba..5df7e6f1bdeaa6f4d49b708e3bafa15c695587c7 100644 (file)
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -47,6 +47,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <= SPI_DEVICE_CS_CNT_MAX);
 #define CQSPI_SUPPORT_DEVICE_RESET     BIT(8)
 #define CQSPI_DISABLE_STIG_MODE                BIT(9)
 #define CQSPI_DISABLE_RUNTIME_PM       BIT(10)
+#define CQSPI_NO_INDIRECT_MODE         BIT(11)
 
 /* Capabilities */
 #define CQSPI_SUPPORTS_OCTAL           BIT(0)
@@ -1425,7 +1426,8 @@ static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata,
        if (ret)
                return ret;
 
-       if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size))
+       if ((cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) ||
+           (cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE))
                return cqspi_direct_read_execute(f_pdata, buf, from, len);
 
        if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma &&
@@ -1626,19 +1628,20 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
        /* Disable all interrupts. */
        writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
 
-       /* Configure the SRAM split to 1:1 . */
-       writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
+       if (!(cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) {
+               /* Configure the SRAM split to 1:1 . */
+               writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
+               /* Load indirect trigger address. */
+               writel(cqspi->trigger_address,
+                      cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
 
-       /* Load indirect trigger address. */
-       writel(cqspi->trigger_address,
-              cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
-
-       /* Program read watermark -- 1/2 of the FIFO. */
-       writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
-              cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
-       /* Program write watermark -- 1/8 of the FIFO. */
-       writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
-              cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
+               /* Program read watermark -- 1/2 of the FIFO. */
+               writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
+                      cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
+               /* Program write watermark -- 1/8 of the FIFO. */
+               writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
+                      cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
+       }
 
        /* Disable direct access controller */
        if (!cqspi->use_direct_mode) {