Fix for the prefixed stq instruction in PC relative mode.

The pstq instruction for R=1, was not using the correct effective address.
The EA_hi and EA_lo should have been based on the value of EA as calculated
by the function calculate_prefix_EA.  Unfortuanely, the EA_hi and EA_lo
addresses were still using the previous code (not PC relative) to calculate
the address from the contants of RA plus the offset.

diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index 8afd7749013fba887a33934d6ee8c2b6aa7dd1e0..543fa95743cf7f9e43d098adbf4ac2f8aae6b9aa 100644 (file)
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -9838,23 +9838,24 @@ static Bool dis_int_store_ds_prefix ( UInt prefix,
             if (host_endness == VexEndnessBE) {
 
                /* upper 64-bits */
-               assign( EA_hi, ea_rAor0_simm( rA_addr, immediate_val ) );
+               assign( EA_hi, mkexpr(EA));
 
                /* lower 64-bits */
-               assign( EA_lo, ea_rAor0_simm( rA_addr, immediate_val+8 ) );
+               assign( EA_lo, binop(Iop_Add64, mkexpr(EA), mkU64(8)));
+
             } else {
                /* upper 64-bits */
-               assign( EA_hi, ea_rAor0_simm( rA_addr, immediate_val+8 ) );
+               assign( EA_hi, binop(Iop_Add64, mkexpr(EA), mkU64(8)));
 
                /* lower 64-bits */
-               assign( EA_lo, ea_rAor0_simm( rA_addr, immediate_val ) );
+               assign( EA_lo, mkexpr(EA));
             }
          } else {
             /* upper half of upper 64-bits */
-            assign( EA_hi, ea_rAor0_simm( rA_addr, immediate_val+4 ) );
+            assign( EA_hi, binop(Iop_Add32, mkexpr(EA), mkU32(4)));
 
             /* lower half of upper 64-bits */
-            assign( EA_lo, ea_rAor0_simm( rA_addr, immediate_val+12 ) );
+            assign( EA_lo, binop(Iop_Add32, mkexpr(EA), mkU32(12)));
          }
 
          /* Note, the store order for stq instruction is the same for BE