RISC-V: Fix division instructions for `m` with `zmmul` extension.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_option_override): Fix wrong
	condition for MASK_DIV and simplify incompatible checking.
	* config/riscv/riscv.md (muldi3): Adding parentheses.

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index b5252b41df702fafe2b5f10c4f831db2e03fbdbb..675d92c0961b304a0acd98701e091754ef673c02 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5277,14 +5277,10 @@ riscv_option_override (void)
   /* The presence of the M extension implies that division instructions
      are present, so include them unless explicitly disabled.  */
   if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
-    if(!TARGET_ZMMUL)
-      target_flags |= MASK_DIV;
+    target_flags |= MASK_DIV;
   else if (!TARGET_MUL && TARGET_DIV)
     error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension");
-  
-  if(TARGET_ZMMUL && !TARGET_MUL && TARGET_DIV)
-    warning (0, "%<-mdiv%> cannot be used when %<ZMMUL%> extension is present");
-  
+
   /* Likewise floating-point division and square root.  */
   if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0)
     target_flags |= MASK_FDIV;

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index d2dfde28e318485f2824d3c4225932d2bf8829d6..014206fb8bd378feb4d3fab3b2870d2f5e8bd6db 100644 (file)
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -752,7 +752,7 @@
   [(set (match_operand:DI          0 "register_operand" "=r")
        (mult:DI (match_operand:DI 1 "register_operand" " r")
                 (match_operand:DI 2 "register_operand" " r")))]
-  "TARGET_ZMMUL || TARGET_MUL && TARGET_64BIT"
+  "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
   "mul\t%0,%1,%2"
   [(set_attr "type" "imul")
    (set_attr "mode" "DI")])