aarch64: Fix move-after-intrinsic function-body tests

Some of the SVE ACLE asm tests tried to be agnostic about the
instruction order, but only one of the alternatives was exercised
in practice.  This patch fixes latent typos in the other versions.

gcc/testsuite/
	* gcc.target/aarch64/sve2/acle/asm/aesd_u8.c: Fix expected register
	allocation in the case where a move occurs after the intrinsic
	instruction.
	* gcc.target/aarch64/sve2/acle/asm/aese_u8.c: Likewise.
	* gcc.target/aarch64/sve2/acle/asm/aesimc_u8.c: Likewise.
	* gcc.target/aarch64/sve2/acle/asm/aesmc_u8.c: Likewise.
	* gcc.target/aarch64/sve2/acle/asm/sm4e_u32.c: Likewise.

diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesd_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesd_u8.c
index 622f5cf4609c197df624a68d5b0924c08d188e31..384b6ffc9aae37a03066c881f5bac84daadfe90c 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesd_u8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesd_u8.c
@@ -28,13 +28,13 @@ TEST_UNIFORM_Z (aesd_u8_tied2, svuint8_t,
 **     mov     z0\.d, z1\.d
 **     aesd    z0\.b, z0\.b, z2\.b
 ** |
-**     aesd    z1\.b, z0\.b, z2\.b
+**     aesd    z1\.b, z1\.b, z2\.b
 **     mov     z0\.d, z1\.d
 ** |
 **     mov     z0\.d, z2\.d
 **     aesd    z0\.b, z0\.b, z1\.b
 ** |
-**     aesd    z2\.b, z0\.b, z1\.b
+**     aesd    z2\.b, z2\.b, z1\.b
 **     mov     z0\.d, z2\.d
 ** )
 **     ret

diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aese_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aese_u8.c
index 6555bbb1de7616dbd57044fc35af8d1d8793be95..6381bce16617335971822625c1cdc5cc44941d25 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aese_u8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aese_u8.c
@@ -28,13 +28,13 @@ TEST_UNIFORM_Z (aese_u8_tied2, svuint8_t,
 **     mov     z0\.d, z1\.d
 **     aese    z0\.b, z0\.b, z2\.b
 ** |
-**     aese    z1\.b, z0\.b, z2\.b
+**     aese    z1\.b, z1\.b, z2\.b
 **     mov     z0\.d, z1\.d
 ** |
 **     mov     z0\.d, z2\.d
 **     aese    z0\.b, z0\.b, z1\.b
 ** |
-**     aese    z2\.b, z0\.b, z1\.b
+**     aese    z2\.b, z2\.b, z1\.b
 **     mov     z0\.d, z2\.d
 ** )
 **     ret

diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesimc_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesimc_u8.c
index 4630595ff209cb9004a8745bf8e1dbdc3fb6281e..76259326467a8bc028de30fc2775e9ef80599500 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesimc_u8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesimc_u8.c
@@ -19,7 +19,7 @@ TEST_UNIFORM_Z (aesimc_u8_tied1, svuint8_t,
 **     mov     z0\.d, z1\.d
 **     aesimc  z0\.b, z0\.b
 ** |
-**     aesimc  z1\.b, z0\.b
+**     aesimc  z1\.b, z1\.b
 **     mov     z0\.d, z1\.d
 ** )
 **     ret

diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesmc_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesmc_u8.c
index 6e8acf48f2aff7193fda4c7752e3d225e5abb094..30e83d381dcd027295e42dcee5455ba7d31471d5 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesmc_u8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesmc_u8.c
@@ -19,7 +19,7 @@ TEST_UNIFORM_Z (aesmc_u8_tied1, svuint8_t,
 **     mov     z0\.d, z1\.d
 **     aesmc   z0\.b, z0\.b
 ** |
-**     aesmc   z1\.b, z0\.b
+**     aesmc   z1\.b, z1\.b
 **     mov     z0\.d, z1\.d
 ** )
 **     ret

diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sm4e_u32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sm4e_u32.c
index 0ff5746d814b7c7bdf6ff70ad8b3b615a9fd8d1e..cf6a2a95235b4bdea475d31b5f654858b4fa1347 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sm4e_u32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sm4e_u32.c
@@ -24,7 +24,7 @@ TEST_UNIFORM_Z (sm4e_u32_tied2, svuint32_t,
 **     mov     z0\.d, z1\.d
 **     sm4e    z0\.s, z0\.s, z2\.s
 ** |
-**     sm4e    z1\.s, z0\.s, z2\.s
+**     sm4e    z1\.s, z1\.s, z2\.s
 **     mov     z0\.d, z1\.d
 ** )
 **     ret