Backport fix for PR target/91769

gcc/ChangeLog:

2019-10-04  Dragan Mladjenovic <dmladjenovic@wavecomp.com>

	Backport from mainline
	2019-10-03  Dragan Mladjenovic  <dmladjenovic@wavecomp.com>

		PR target/91769
		* config/mips/mips.c (mips_split_move): Use reg_overlap_mentioned_p
		instead of REGNO equality check on addr.reg.

gcc/testsuite/ChangeLog:

2019-10-04  Dragan Mladjenovic <dmladjenovic@wavecomp.com>

	Backport from mainline
	2019-10-03  Dragan Mladjenovic  <dmladjenovic@wavecomp.com>

		PR target/91769
		* gcc.target/mips/pr91769.c: New test.

From-SVN: r276570

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ac7ae9ff1e300d5ef276cda9e92bb65804dd2103..39e50092f84ae7e4b3eda49aba18edef2b5713c5 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,4 +1,13 @@
-       2019-10-04  Dragan Mladjenovic <dmladjenovic@wavecomp.com>
+2019-10-04  Dragan Mladjenovic <dmladjenovic@wavecomp.com>
+
+       Backport from mainline
+       2019-10-03  Dragan Mladjenovic  <dmladjenovic@wavecomp.com>
+
+       PR target/91769
+       * config/mips/mips.c (mips_split_move): Use reg_overlap_mentioned_p
+       instead of REGNO equality check on addr.reg.
+
+2019-10-04  Dragan Mladjenovic <dmladjenovic@wavecomp.com>
 
        Backport from mainline
        2019-07-07  Richard Sandiford  <richard.sandiford@arm.com>

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 53429270327c24aa8824423ed899bf006cc5c537..d758fbf1be676a97e8d3e3858d417694e9251d1e 100644 (file)
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -4862,7 +4862,7 @@ mips_split_move (rtx dest, rtx src, enum mips_split_type split_type, rtx insn_)
                {
                  rtx tmp = XEXP (src, 0);
                  mips_classify_address (&addr, tmp, GET_MODE (tmp), true);
-                 if (addr.reg && REGNO (addr.reg) != REGNO (dest))
+                 if (addr.reg && !reg_overlap_mentioned_p (dest, addr.reg))
                    validate_change (next, &SET_SRC (set), src, false);
                }
              else

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 362ed17d1b130a67a87bf993e245b40a424e7c3b..fb7965ffc459ae1836d4e305328142ee3e80f22e 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2019-10-04  Dragan Mladjenovic <dmladjenovic@wavecomp.com>
+
+       Backport from mainline  
+       2019-10-03  Dragan Mladjenovic  <dmladjenovic@wavecomp.com>
+
+       PR target/91769
+       * gcc.target/mips/pr91769.c: New test.
+
 2019-10-02  Bernd Edlinger  <bernd.edlinger@hotmail.de>
 
        Backport from mainline

diff --git a/gcc/testsuite/gcc.target/mips/pr91769.c b/gcc/testsuite/gcc.target/mips/pr91769.c
new file mode 100644 (file)
index 0000000..c9ad70d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/pr91769.c
@@ -0,0 +1,19 @@
+/* PR target/91769 */
+/* { dg-do compile } */
+/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" "-g" } { "" } } */
+/* { dg-options "-EL -mgp32 -mhard-float" } */
+
+NOCOMPRESSION double
+foo (void)
+{
+  register double* pf __asm__ ("$a1");
+  __asm__ __volatile__ ("":"=r"(pf));
+  double f = *pf;
+
+  if (f != f)
+    f = -f;
+  return f;
+}
+
+/* { dg-final { scan-assembler-not "lw\t\\\$4,0\\(\\\$5\\)\n\tlw\t\\\$5,4\\(\\\$5\\)\n\tldc1\t\\\$.*,0\\(\\\$5\\)" } } */
+/* { dg-final { scan-assembler "lw\t\\\$4,0\\(\\\$5\\)\n\tlw\t\\\$5,4\\(\\\$5\\)\n\tmtc1\t\\\$4,\\\$.*\n\tmthc1\t\\\$5,\\\$.*" } } */