Backport a fix to the 2.95 branch

From-SVN: r38047

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1dcac7a8af5c2902c0029e2c9495539ff15f3f44..a36d7c23001b18278478d46965ddf988943a457e 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2000-12-05  Bernd Schmidt  <bernds@redhat.co.uk>
+
+       2000-07-03  Nick Clifton  <nickc@cygnus.com>
+       * config/arm/arm.md: Fix post increment and pre increment
+       peepholes so that they do not generate UNPREDICATBLE opcodes.
+       (ie ones where the increment clobbers the source/destination).
+
 2000-11-30  Bernd Schmidt  <bernds@redhat.co.uk>
 
        * version.c: Bump.

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 7ccbb5cb2d1e68478351e42a8f110a51d9bc878c..d5047f82dae862e4ea9fa1e4748d0b679faeaed4 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -5798,15 +5798,19 @@
 ; It doesn't seem worth adding peepholes for anything but the most common
 ; cases since, unlike combine, the increment must immediately follow the load
 ; for this pattern to match.
-; When loading we must watch to see that the base register isn't trampled by
-; the load.  In such cases this isn't a post-inc expression.
+; We must watch to see that the source/destination register isn't also the
+; same as the base address register, and that if the index is a register,
+; that it is not the same as the base address register.  In such cases the
+; instruction that we would generate would have UNPREDICTABLE behaviour so 
+; we cannot use it.
 
 (define_peephole
   [(set (mem:QI (match_operand:SI 0 "s_register_operand" "+r"))
        (match_operand:QI 2 "s_register_operand" "r"))
    (set (match_dup 0)
        (plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))]
-  ""
+  "(REGNO (operands[2]) != REGNO (operands[0]))
+   && (GET_CODE (operands[1]) != REG || (REGNO (operands[1]) != REGNO (operands[0])))"
   "str%?b\\t%2, [%0], %1")
 
 (define_peephole
@@ -5814,9 +5818,8 @@
        (mem:QI (match_operand:SI 1 "s_register_operand" "+r")))
    (set (match_dup 1)
        (plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))]
-  "REGNO(operands[0]) != REGNO(operands[1])
-   && (GET_CODE (operands[2]) != REG
-       || REGNO(operands[0]) != REGNO (operands[2]))"
+  "REGNO (operands[0]) != REGNO (operands[1])
+   && (GET_CODE (operands[2]) != REG || REGNO (operands[0]) != REGNO (operands[2]))"
   "ldr%?b\\t%0, [%1], %2")
 
 (define_peephole
@@ -5824,7 +5827,8 @@
        (match_operand:SI 2 "s_register_operand" "r"))
    (set (match_dup 0)
        (plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))]
-  ""
+  "(REGNO (operands[2]) != REGNO (operands[0]))
+   && (GET_CODE (operands[1]) != REG || (REGNO (operands[1]) != REGNO (operands[0])))"
   "str%?\\t%2, [%0], %1")
 
 (define_peephole
@@ -5834,9 +5838,8 @@
        (plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))]
   "(! BYTES_BIG_ENDIAN)
    && ! TARGET_SHORT_BY_BYTES
-   && REGNO(operands[0]) != REGNO(operands[1])
-   && (GET_CODE (operands[2]) != REG
-       || REGNO(operands[0]) != REGNO (operands[2]))"
+   && REGNO (operands[0]) != REGNO (operands[1])
+   && (GET_CODE (operands[2]) != REG || REGNO (operands[0]) != REGNO (operands[2]))"
   "ldr%?\\t%0, [%1], %2\\t%@ loadhi")
 
 (define_peephole
@@ -5844,9 +5847,8 @@
        (mem:SI (match_operand:SI 1 "s_register_operand" "+r")))
    (set (match_dup 1)
        (plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))]
-  "REGNO(operands[0]) != REGNO(operands[1])
-   && (GET_CODE (operands[2]) != REG
-       || REGNO(operands[0]) != REGNO (operands[2]))"
+  "REGNO (operands[0]) != REGNO (operands[1])
+   && (GET_CODE (operands[2]) != REG || REGNO (operands[0]) != REGNO (operands[2]))"
   "ldr%?\\t%0, [%1], %2")
 
 (define_peephole
@@ -5854,7 +5856,8 @@
                         (match_operand:SI 1 "index_operand" "rJ")))
        (match_operand:QI 2 "s_register_operand" "r"))
    (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
-  ""
+  "(REGNO (operands[2]) != REGNO (operands[0]))
+   && (GET_CODE (operands[1]) != REG || (REGNO (operands[1]) != REGNO (operands[0])))"
   "str%?b\\t%2, [%0, %1]!")
 
 (define_peephole
@@ -5865,7 +5868,8 @@
        (match_operand:QI 3 "s_register_operand" "r"))
    (set (match_dup 2) (plus:SI (match_op_dup 4 [(match_dup 0) (match_dup 1)])
                               (match_dup 2)))]
-  ""
+  "REGNO (operands[0]) != REGNO (operands[2])
+   && REGNO (operands[3]) != REGNO (operands[2])"
   "str%?b\\t%3, [%2, %0%S4]!")
 
 ; This pattern is never tried by combine, so do it as a peephole