aarch64: Avoid hard-coding specific register allocations

Some tests hard-coded specific allocations for temporary registers,
whereas the RA should be free to pick anything that doesn't force
unnecessary moves or spills.

gcc/testsuite/
	* gcc.target/aarch64/asimd-mul-to-shl-sub.c: Allow any register
	allocation for temporary results, rather than requiring specific
	registers.
	* gcc.target/aarch64/auto-init-padding-1.c: Likewise.
	* gcc.target/aarch64/auto-init-padding-2.c: Likewise.
	* gcc.target/aarch64/auto-init-padding-3.c: Likewise.
	* gcc.target/aarch64/auto-init-padding-4.c: Likewise.
	* gcc.target/aarch64/auto-init-padding-9.c: Likewise.
	* gcc.target/aarch64/memset-corner-cases.c: Likewise.
	* gcc.target/aarch64/memset-q-reg.c: Likewise.
	* gcc.target/aarch64/simd/vaddlv_1.c: Likewise.
	* gcc.target/aarch64/sve-neon-modes_1.c: Likewise.
	* gcc.target/aarch64/sve-neon-modes_3.c: Likewise.
	* gcc.target/aarch64/sve/load_scalar_offset_1.c: Likewise.
	* gcc.target/aarch64/sve/pcs/return_6_256.c: Likewise.
	* gcc.target/aarch64/sve/pcs/return_6_512.c: Likewise.
	* gcc.target/aarch64/sve/pcs/return_6_1024.c: Likewise.
	* gcc.target/aarch64/sve/pcs/return_6_2048.c: Likewise.
	* gcc.target/aarch64/sve/pr89007-1.c: Likewise.
	* gcc.target/aarch64/sve/pr89007-2.c: Likewise.
	* gcc.target/aarch64/sve/store_scalar_offset_1.c: Likewise.
	* gcc.target/aarch64/vadd_reduc-1.c: Likewise.
	* gcc.target/aarch64/vadd_reduc-2.c: Likewise.
	* gcc.target/aarch64/sve/pcs/args_5_be_bf16.c: Allow the temporary
	predicate register to be any of p4-p7, rather than requiring p4
	specifically.
	* gcc.target/aarch64/sve/pcs/args_5_be_f16.c: Likewise.
	* gcc.target/aarch64/sve/pcs/args_5_be_f32.c: Likewise.
	* gcc.target/aarch64/sve/pcs/args_5_be_f64.c: Likewise.
	* gcc.target/aarch64/sve/pcs/args_5_be_s8.c: Likewise.
	* gcc.target/aarch64/sve/pcs/args_5_be_s16.c: Likewise.
	* gcc.target/aarch64/sve/pcs/args_5_be_s32.c: Likewise.
	* gcc.target/aarch64/sve/pcs/args_5_be_s64.c: Likewise.
	* gcc.target/aarch64/sve/pcs/args_5_be_u8.c: Likewise.
	* gcc.target/aarch64/sve/pcs/args_5_be_u16.c: Likewise.
	* gcc.target/aarch64/sve/pcs/args_5_be_u32.c: Likewise.
	* gcc.target/aarch64/sve/pcs/args_5_be_u64.c: Likewise.

diff --git a/gcc/testsuite/gcc.target/aarch64/asimd-mul-to-shl-sub.c b/gcc/testsuite/gcc.target/aarch64/asimd-mul-to-shl-sub.c
index d7c5e5f341b2c56e9c2853859b786e1fe524eb59..28dbe81a37d5a927b0107981b07b2d14e578f962 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/asimd-mul-to-shl-sub.c
+++ b/gcc/testsuite/gcc.target/aarch64/asimd-mul-to-shl-sub.c
@@ -4,8 +4,8 @@
 
 /*
 **foo:
-**     shl     v1.4s, v0.4s, 16
-**     sub     v0.4s, v1.4s, v0.4s
+**     shl     (v[0-9]+.4s), v0.4s, 16
+**     sub     v0.4s, \1, v0.4s
 **     ret
 */
 #include <arm_neon.h>

diff --git a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-1.c b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-1.c
index d3a88c724545445b08246628d5546cb5cff956c6..c747ebdcdf7d87ff5ffbb0c0f6eb7ff0e6862d56 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-1.c
+++ b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-1.c
@@ -14,4 +14,4 @@ int foo ()
   return var.internal1;
 }
 
-/* { dg-final { scan-assembler-times "stp\tq0, q0," 2 } } */
+/* { dg-final { scan-assembler-times {stp\tq[0-9]+, q[0-9]+,} 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-2.c b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-2.c
index aceceb87fbe16ab6e291f75b10c90d47b7fa1b4f..6e280904da1eb6a398e5ab1429ea124247ea2bd6 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-2.c
+++ b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-2.c
@@ -14,5 +14,4 @@ int foo ()
   return var.internal1;
 }
 
-/* { dg-final { scan-assembler-times "stp\tq0, q0," 2 } } */
-
+/* { dg-final { scan-assembler-times {stp\tq[0-9]+, q[0-9]+,} 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-3.c b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-3.c
index 085c3862921053ea0a970b94318078c376a03dc9..9ddea58b468afde66d7ea66ca93938b0df0160ff 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-3.c
+++ b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-3.c
@@ -23,5 +23,4 @@ int foo ()
   return var.four.internal1;
 }
 
-/* { dg-final { scan-assembler-times "stp\tq0, q0," 4 } } */
-
+/* { dg-final { scan-assembler-times {stp\tq[0-9]+, q[0-9]+,} 4 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-4.c b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-4.c
index 7a6ddbc20ee1fc26b485b349f1f897fef0b65155..75bba82ed34151f606f90467a40d5e1ad52b37b2 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-4.c
+++ b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-4.c
@@ -23,5 +23,4 @@ int foo ()
   return var.four.internal1;
 }
 
-/* { dg-final { scan-assembler-times "stp\tq0, q0," 5 } } */
-
+/* { dg-final { scan-assembler-times {stp\tq[0-9]+, q[0-9]+,} 5 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-9.c b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-9.c
index c81e5ff28b0b7a9281b8b0f58fc9cca7adc57797..0f1930f813e78d5e40e12af8fae2d72f6ed2e3d6 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-9.c
+++ b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-9.c
@@ -18,4 +18,4 @@ int foo ()
   return var[2].four;
 }
 
-/* { dg-final { scan-assembler-times "stp\tq0, q0," 5 } } */
+/* { dg-final { scan-assembler-times {stp\tq[0-9]+, q[0-9]+,} 5 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/memset-corner-cases.c b/gcc/testsuite/gcc.target/aarch64/memset-corner-cases.c
index c43f0199adcd348370edabf045a532e9abb436e7..d4c752711f8dd7d5b297d33dd96f39d09048c5aa 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/memset-corner-cases.c
+++ b/gcc/testsuite/gcc.target/aarch64/memset-corner-cases.c
@@ -29,8 +29,8 @@ set0byte (int64_t *src)
 
 /* 35bytes would become 4 scalar instructions.  So favour NEON.
 **set0neon:
-**     movi    v0.4s, 0
-**     stp     q0, q0, \[x0\]
+**     movi    v([0-9]+).4s, 0
+**     stp     q\1, q\1, \[x0\]
 **     str     wzr, \[x0, 31\]
 **     ret
 */
@@ -56,15 +56,15 @@ set0scalar (int64_t *src)
 
 /* 256-bytes expanded
 **set256byte:
-**     dup     v0.16b, w1
-**     stp     q0, q0, \[x0\]
-**     stp     q0, q0, \[x0, 32\]
-**     stp     q0, q0, \[x0, 64\]
-**     stp     q0, q0, \[x0, 96\]
-**     stp     q0, q0, \[x0, 128\]
-**     stp     q0, q0, \[x0, 160\]
-**     stp     q0, q0, \[x0, 192\]
-**     stp     q0, q0, \[x0, 224\]
+**     dup     v([0-9]+).16b, w1
+**     stp     q\1, q\1, \[x0\]
+**     stp     q\1, q\1, \[x0, 32\]
+**     stp     q\1, q\1, \[x0, 64\]
+**     stp     q\1, q\1, \[x0, 96\]
+**     stp     q\1, q\1, \[x0, 128\]
+**     stp     q\1, q\1, \[x0, 160\]
+**     stp     q\1, q\1, \[x0, 192\]
+**     stp     q\1, q\1, \[x0, 224\]
 **     ret
 */
 void __attribute__((__noinline__))

diff --git a/gcc/testsuite/gcc.target/aarch64/memset-q-reg.c b/gcc/testsuite/gcc.target/aarch64/memset-q-reg.c
index 156146badbcd98e63d873a4a1c7657f19c027973..eef5c21f50dcf0cf6a1e13d1f04346ff8ba21519 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/memset-q-reg.c
+++ b/gcc/testsuite/gcc.target/aarch64/memset-q-reg.c
@@ -6,8 +6,8 @@
 
 /*
 **set128bits:
-**     dup     v0.16b, w1
-**     str     q0, \[x0\]
+**     dup     v([0-9]+).16b, w1
+**     str     q\1, \[x0\]
 **     ret
 */
 void __attribute__((__noinline__))
@@ -29,9 +29,9 @@ set128bitszero (int64_t *src)
 
 /*
 ** set128bitsplus:
-**     dup     v0.16b, w1
-**     str     q0, \[x0\]
-**     str     q0, \[x0, 12\]
+**     dup     v([0-9]+).16b, w1
+**     str     q\1, \[x0\]
+**     str     q\1, \[x0, 12\]
 **     ret
 */
 void __attribute__((__noinline__))
@@ -42,8 +42,8 @@ set128bitsplus (int64_t *src, char c)
 
 /*
 ** set256bits:
-**     movi    v0.16b, 0x63
-**     stp     q0, q0, \[x0\]
+**     movi    v([0-9]+).16b, 0x63
+**     stp     q\1, q\1, \[x0\]
 **     ret
 */
 void __attribute__((__noinline__))
@@ -66,10 +66,10 @@ set256bitszero (int64_t *src)
 
 /*
 ** set256bitsplus:
-**     movi    v0.16b, 0x63
-**     stp     q0, q0, \[x0\]
-**     str     q0, \[x0, 32\]
-**     str     d0, \[x0, 48\]
+**     movi    v([0-9]+).16b, 0x63
+**     stp     q\1, q\1, \[x0\]
+**     str     q\1, \[x0, 32\]
+**     str     d\1, \[x0, 48\]
 **     ret
 */
 void __attribute__((__noinline__))

diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vaddlv_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vaddlv_1.c
index d4afaab5ba5fa276078ba54f85cc30f359cbb766..ef1f13efd2e71991b3e54d565bfb3013eaa5b7ca 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/simd/vaddlv_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vaddlv_1.c
@@ -12,22 +12,22 @@ foo_##S (IT a)              \
 }
 
 FUNC (int8x8_t, int16_t, s8)
-/* { dg-final { scan-assembler-times {saddlv\th0, v0\.8b} 1} }  */
+/* { dg-final { scan-assembler-times {saddlv\th[0-9]+, v0\.8b} 1} }  */
 
 FUNC (int16x4_t, int32_t, s16)
-/* { dg-final { scan-assembler-times {saddlv\ts0, v0\.4h} 1} }  */
+/* { dg-final { scan-assembler-times {saddlv\ts[0-9]+, v0\.4h} 1} }  */
 
 FUNC (int32x2_t, int64_t, s32)
-/* { dg-final { scan-assembler-times {saddlp\tv0\.1d, v0\.2s} 1} }  */
+/* { dg-final { scan-assembler-times {saddlp\tv[0-9]+\.1d, v0\.2s} 1} }  */
 
 FUNC (uint8x8_t, uint16_t, u8)
-/* { dg-final { scan-assembler-times {uaddlv\th0, v0\.8b} 1} }  */
+/* { dg-final { scan-assembler-times {uaddlv\th[0-9]+, v0\.8b} 1} }  */
 
 FUNC (uint16x4_t, uint32_t, u16)
-/* { dg-final { scan-assembler-times {uaddlv\ts0, v0\.4h} 1} }  */
+/* { dg-final { scan-assembler-times {uaddlv\ts[0-9]+, v0\.4h} 1} }  */
 
 FUNC (uint32x2_t, uint64_t, u32)
-/* { dg-final { scan-assembler-times {uaddlp\tv0.1d, v0\.2s} 1} }  */
+/* { dg-final { scan-assembler-times {uaddlp\tv[0-9]+\.1d, v0\.2s} 1} }  */
 
 #define FUNCQ(IT, OT, S)       \
 OT                             \
@@ -37,20 +37,20 @@ fooq_##S (IT a)                     \
 }
 
 FUNCQ (int8x16_t, int16_t, s8)
-/* { dg-final { scan-assembler-times {saddlv\th0, v0\.16b} 1} }  */
+/* { dg-final { scan-assembler-times {saddlv\th[0-9]+, v0\.16b} 1} }  */
 
 FUNCQ (int16x8_t, int32_t, s16)
-/* { dg-final { scan-assembler-times {saddlv\ts0, v0\.8h} 1} }  */
+/* { dg-final { scan-assembler-times {saddlv\ts[0-9]+, v0\.8h} 1} }  */
 
 FUNCQ (int32x4_t, int64_t, s32)
-/* { dg-final { scan-assembler-times {saddlv\td0, v0\.4s} 1} }  */
+/* { dg-final { scan-assembler-times {saddlv\td[0-9]+, v0\.4s} 1} }  */
 
 FUNCQ (uint8x16_t, uint16_t, u8)
-/* { dg-final { scan-assembler-times {uaddlv\th0, v0\.16b} 1} }  */
+/* { dg-final { scan-assembler-times {uaddlv\th[0-9]+, v0\.16b} 1} }  */
 
 FUNCQ (uint16x8_t, uint32_t, u16)
-/* { dg-final { scan-assembler-times {uaddlv\ts0, v0\.8h} 1} }  */
+/* { dg-final { scan-assembler-times {uaddlv\ts[0-9]+, v0\.8h} 1} }  */
 
 FUNCQ (uint32x4_t, uint64_t, u32)
-/* { dg-final { scan-assembler-times {uaddlv\td0, v0\.4s} 1} }  */
+/* { dg-final { scan-assembler-times {uaddlv\td[0-9]+, v0\.4s} 1} }  */
 

diff --git a/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_1.c b/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_1.c
index ce4f1c70bccd07fda587cc98ea6b53d2463036bd..c4019aaf4f92dbc9771842f6308cc26980128c4c 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_1.c
@@ -6,8 +6,8 @@ typedef long v2di  __attribute__((vector_size (16)));
 
 /*
 ** foo:
-**     ptrue   p0.b, all
-**     mul     z0.d, p0/m, z0.d, z1.d
+**     ptrue   (p[0-7]).b, all
+**     mul     z0.d, \1/m, z0.d, z1.d
 **     ret
 */
 

diff --git a/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_3.c b/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_3.c
index f1e78a83a9c26aa9a197ab28a09134746eee5535..f7c93659f4daa99f70d3ee6fa5e9043cd9ef9404 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_3.c
@@ -9,8 +9,8 @@ typedef unsigned int v4usi  __attribute__((vector_size (16)));
 
 /*
 ** food:
-**     ptrue   p0.b, all
-**     sdiv    z0.d, p0/m, z0.d, z1.d
+**     ptrue   (p[0-7]).b, all
+**     sdiv    z0.d, \1/m, z0.d, z1.d
 **     ret
 */
 
@@ -22,8 +22,8 @@ food (v2di a, v2di b)
 
 /*
 ** fooud:
-**     ptrue   p0.b, all
-**     udiv    z0.d, p0/m, z0.d, z1.d
+**     ptrue   (p[0-7]).b, all
+**     udiv    z0.d, \1/m, z0.d, z1.d
 **     ret
 */
 
@@ -35,8 +35,8 @@ fooud (v2udi a, v2udi b)
 
 /*
 ** foos:
-**     ptrue   p0.b, all
-**     sdiv    z0.s, p0/m, z0.s, z1.s
+**     ptrue   (p[0-7]).b, all
+**     sdiv    z0.s, \1/m, z0.s, z1.s
 **     ret
 */
 
@@ -48,8 +48,8 @@ foos (v4si a, v4si b)
 
 /*
 ** foous:
-**     ptrue   p0.b, all
-**     udiv    z0.s, p0/m, z0.s, z1.s
+**     ptrue   (p[0-7]).b, all
+**     udiv    z0.s, \1/m, z0.s, z1.s
 **     ret
 */
 

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/load_scalar_offset_1.c b/gcc/testsuite/gcc.target/aarch64/sve/load_scalar_offset_1.c
index 32905350c27877c716bdcf0a46cf46600cb99615..4d1f7969f7df2265165a679a051c2509544de22e 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/load_scalar_offset_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/load_scalar_offset_1.c
@@ -64,7 +64,7 @@ void sve_load_8_s (int8_t *a)
   asm volatile ("" :: "w" (*(vnx16qi *)&a[i]));
 }
 
-/* { dg-final { scan-assembler-times {\tld1d\tz0\.d, p[0-7]/z, \[x0, x1, lsl 3\]\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tld1w\tz0\.s, p[0-7]/z, \[x0, x1, lsl 2\]\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tld1h\tz0\.h, p[0-7]/z, \[x0, x1, lsl 1\]\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tld1b\tz0\.b, p[0-7]/z, \[x0, x1\]\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tld1d\tz[0-9]+\.d, p[0-7]/z, \[x0, x1, lsl 3\]\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.s, p[0-7]/z, \[x0, x1, lsl 2\]\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.h, p[0-7]/z, \[x0, x1, lsl 1\]\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.b, p[0-7]/z, \[x0, x1\]\n} 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_bf16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_bf16.c
index e9b63a45dc3246ffdb783c9c2bb5b8aa37511cb8..4002e047977ca3dfc43252762d947320a212bb79 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_bf16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_bf16.c
@@ -7,21 +7,21 @@
 /*
 ** callee:
 **     addvl   sp, sp, #-1
-**     str     p4, \[sp\]
-**     ptrue   p4\.b, all
+**     str     (p[4-7]), \[sp\]
+**     ptrue   \1\.b, all
 ** (
-**     ld1h    (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\]
-**     ld1h    (z[0-9]+\.h), p4/z, \[x1\]
-**     st2h    {\2 - \1}, p0, \[x0\]
+**     ld1h    (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\]
+**     ld1h    (z[0-9]+\.h), \1/z, \[x1\]
+**     st2h    {\3 - \2}, p0, \[x0\]
 ** |
-**     ld1h    (z[0-9]+\.h), p4/z, \[x1\]
-**     ld1h    (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\]
-**     st2h    {\3 - \4}, p0, \[x0\]
+**     ld1h    (z[0-9]+\.h), \1/z, \[x1\]
+**     ld1h    (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\]
+**     st2h    {\4 - \5}, p0, \[x0\]
 ** )
 **     st4h    {z0\.h - z3\.h}, p1, \[x0\]
 **     st3h    {z4\.h - z6\.h}, p2, \[x0\]
 **     st1h    z7\.h, p3, \[x0\]
-**     ldr     p4, \[sp\]
+**     ldr     \1, \[sp\]
 **     addvl   sp, sp, #1
 **     ret
 */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f16.c
index 4152f91255af61c380c25822c7e684fdfd11180c..6faf8a3d54713e72fca5d5af6bb198377959f367 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f16.c
@@ -7,21 +7,21 @@
 /*
 ** callee:
 **     addvl   sp, sp, #-1
-**     str     p4, \[sp\]
-**     ptrue   p4\.b, all
+**     str     (p[4-7]), \[sp\]
+**     ptrue   \1\.b, all
 ** (
-**     ld1h    (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\]
-**     ld1h    (z[0-9]+\.h), p4/z, \[x1\]
-**     st2h    {\2 - \1}, p0, \[x0\]
+**     ld1h    (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\]
+**     ld1h    (z[0-9]+\.h), \1/z, \[x1\]
+**     st2h    {\3 - \2}, p0, \[x0\]
 ** |
-**     ld1h    (z[0-9]+\.h), p4/z, \[x1\]
-**     ld1h    (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\]
-**     st2h    {\3 - \4}, p0, \[x0\]
+**     ld1h    (z[0-9]+\.h), \1/z, \[x1\]
+**     ld1h    (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\]
+**     st2h    {\4 - \5}, p0, \[x0\]
 ** )
 **     st4h    {z0\.h - z3\.h}, p1, \[x0\]
 **     st3h    {z4\.h - z6\.h}, p2, \[x0\]
 **     st1h    z7\.h, p3, \[x0\]
-**     ldr     p4, \[sp\]
+**     ldr     \1, \[sp\]
 **     addvl   sp, sp, #1
 **     ret
 */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f32.c
index 0f78fac79476a00869bf955576f281a464d08288..7abd279f21fcc9b2b00260b9ab93afe47184303e 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f32.c
@@ -7,21 +7,21 @@
 /*
 ** callee:
 **     addvl   sp, sp, #-1
-**     str     p4, \[sp\]
-**     ptrue   p4\.b, all
+**     str     (p[4-7]), \[sp\]
+**     ptrue   \1\.b, all
 ** (
-**     ld1w    (z[0-9]+\.s), p4/z, \[x1, #1, mul vl\]
-**     ld1w    (z[0-9]+\.s), p4/z, \[x1\]
-**     st2w    {\2 - \1}, p0, \[x0\]
+**     ld1w    (z[0-9]+\.s), \1/z, \[x1, #1, mul vl\]
+**     ld1w    (z[0-9]+\.s), \1/z, \[x1\]
+**     st2w    {\3 - \2}, p0, \[x0\]
 ** |
-**     ld1w    (z[0-9]+\.s), p4/z, \[x1\]
-**     ld1w    (z[0-9]+\.s), p4/z, \[x1, #1, mul vl\]
-**     st2w    {\3 - \4}, p0, \[x0\]
+**     ld1w    (z[0-9]+\.s), \1/z, \[x1\]
+**     ld1w    (z[0-9]+\.s), \1/z, \[x1, #1, mul vl\]
+**     st2w    {\4 - \5}, p0, \[x0\]
 ** )
 **     st4w    {z0\.s - z3\.s}, p1, \[x0\]
 **     st3w    {z4\.s - z6\.s}, p2, \[x0\]
 **     st1w    z7\.s, p3, \[x0\]
-**     ldr     p4, \[sp\]
+**     ldr     \1, \[sp\]
 **     addvl   sp, sp, #1
 **     ret
 */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f64.c
index fe832d0d0a489e71db725944a69fe9ef375341a3..eea79659593cdeef828800df970f566bde9a8830 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f64.c
@@ -7,21 +7,21 @@
 /*
 ** callee:
 **     addvl   sp, sp, #-1
-**     str     p4, \[sp\]
-**     ptrue   p4\.b, all
+**     str     (p[4-7]), \[sp\]
+**     ptrue   \1\.b, all
 ** (
-**     ld1d    (z[0-9]+\.d), p4/z, \[x1, #1, mul vl\]
-**     ld1d    (z[0-9]+\.d), p4/z, \[x1\]
-**     st2d    {\2 - \1}, p0, \[x0\]
+**     ld1d    (z[0-9]+\.d), \1/z, \[x1, #1, mul vl\]
+**     ld1d    (z[0-9]+\.d), \1/z, \[x1\]
+**     st2d    {\3 - \2}, p0, \[x0\]
 ** |
-**     ld1d    (z[0-9]+\.d), p4/z, \[x1\]
-**     ld1d    (z[0-9]+\.d), p4/z, \[x1, #1, mul vl\]
-**     st2d    {\3 - \4}, p0, \[x0\]
+**     ld1d    (z[0-9]+\.d), \1/z, \[x1\]
+**     ld1d    (z[0-9]+\.d), \1/z, \[x1, #1, mul vl\]
+**     st2d    {\4 - \5}, p0, \[x0\]
 ** )
 **     st4d    {z0\.d - z3\.d}, p1, \[x0\]
 **     st3d    {z4\.d - z6\.d}, p2, \[x0\]
 **     st1d    z7\.d, p3, \[x0\]
-**     ldr     p4, \[sp\]
+**     ldr     \1, \[sp\]
 **     addvl   sp, sp, #1
 **     ret
 */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s16.c
index 3f708e0f011679570c04cfebd88dda956cf8cfe0..59b17a4c9e3ba77bd2cd2d46e12f8b28de927e6d 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s16.c
@@ -7,21 +7,21 @@
 /*
 ** callee:
 **     addvl   sp, sp, #-1
-**     str     p4, \[sp\]
-**     ptrue   p4\.b, all
+**     str     (p[4-7]), \[sp\]
+**     ptrue   \1\.b, all
 ** (
-**     ld1h    (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\]
-**     ld1h    (z[0-9]+\.h), p4/z, \[x1\]
-**     st2h    {\2 - \1}, p0, \[x0\]
+**     ld1h    (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\]
+**     ld1h    (z[0-9]+\.h), \1/z, \[x1\]
+**     st2h    {\3 - \2}, p0, \[x0\]
 ** |
-**     ld1h    (z[0-9]+\.h), p4/z, \[x1\]
-**     ld1h    (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\]
-**     st2h    {\3 - \4}, p0, \[x0\]
+**     ld1h    (z[0-9]+\.h), \1/z, \[x1\]
+**     ld1h    (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\]
+**     st2h    {\4 - \5}, p0, \[x0\]
 ** )
 **     st4h    {z0\.h - z3\.h}, p1, \[x0\]
 **     st3h    {z4\.h - z6\.h}, p2, \[x0\]
 **     st1h    z7\.h, p3, \[x0\]
-**     ldr     p4, \[sp\]
+**     ldr     \1, \[sp\]
 **     addvl   sp, sp, #1
 **     ret
 */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s32.c
index 8c57190ea56565de9a60808ba81a678b700f4109..8988f9c9ba9a054512257d873e7241dc9e8b6a56 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s32.c
@@ -7,21 +7,21 @@
 /*
 ** callee:
 **     addvl   sp, sp, #-1
-**     str     p4, \[sp\]
-**     ptrue   p4\.b, all
+**     str     (p[4-7]), \[sp\]
+**     ptrue   \1\.b, all
 ** (
-**     ld1w    (z[0-9]+\.s), p4/z, \[x1, #1, mul vl\]
-**     ld1w    (z[0-9]+\.s), p4/z, \[x1\]
-**     st2w    {\2 - \1}, p0, \[x0\]
+**     ld1w    (z[0-9]+\.s), \1/z, \[x1, #1, mul vl\]
+**     ld1w    (z[0-9]+\.s), \1/z, \[x1\]
+**     st2w    {\3 - \2}, p0, \[x0\]
 ** |
-**     ld1w    (z[0-9]+\.s), p4/z, \[x1\]
-**     ld1w    (z[0-9]+\.s), p4/z, \[x1, #1, mul vl\]
-**     st2w    {\3 - \4}, p0, \[x0\]
+**     ld1w    (z[0-9]+\.s), \1/z, \[x1\]
+**     ld1w    (z[0-9]+\.s), \1/z, \[x1, #1, mul vl\]
+**     st2w    {\4 - \5}, p0, \[x0\]
 ** )
 **     st4w    {z0\.s - z3\.s}, p1, \[x0\]
 **     st3w    {z4\.s - z6\.s}, p2, \[x0\]
 **     st1w    z7\.s, p3, \[x0\]
-**     ldr     p4, \[sp\]
+**     ldr     \1, \[sp\]
 **     addvl   sp, sp, #1
 **     ret
 */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s64.c
index e60d049fbd362eafacd61e016883a47bd76c167d..4719b4120e08e2fbdac942cd0ea728259865b9bd 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s64.c
@@ -7,21 +7,21 @@
 /*
 ** callee:
 **     addvl   sp, sp, #-1
-**     str     p4, \[sp\]
-**     ptrue   p4\.b, all
+**     str     (p[4-7]), \[sp\]
+**     ptrue   \1\.b, all
 ** (
-**     ld1d    (z[0-9]+\.d), p4/z, \[x1, #1, mul vl\]
-**     ld1d    (z[0-9]+\.d), p4/z, \[x1\]
-**     st2d    {\2 - \1}, p0, \[x0\]
+**     ld1d    (z[0-9]+\.d), \1/z, \[x1, #1, mul vl\]
+**     ld1d    (z[0-9]+\.d), \1/z, \[x1\]
+**     st2d    {\3 - \2}, p0, \[x0\]
 ** |
-**     ld1d    (z[0-9]+\.d), p4/z, \[x1\]
-**     ld1d    (z[0-9]+\.d), p4/z, \[x1, #1, mul vl\]
-**     st2d    {\3 - \4}, p0, \[x0\]
+**     ld1d    (z[0-9]+\.d), \1/z, \[x1\]
+**     ld1d    (z[0-9]+\.d), \1/z, \[x1, #1, mul vl\]
+**     st2d    {\4 - \5}, p0, \[x0\]
 ** )
 **     st4d    {z0\.d - z3\.d}, p1, \[x0\]
 **     st3d    {z4\.d - z6\.d}, p2, \[x0\]
 **     st1d    z7\.d, p3, \[x0\]
-**     ldr     p4, \[sp\]
+**     ldr     \1, \[sp\]
 **     addvl   sp, sp, #1
 **     ret
 */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s8.c
index bc0058372cb62a33fad09312e81272609efe1cd5..995f3e70bf2818e8f003dfd9f38a953a02b7ccff 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s8.c
@@ -7,21 +7,21 @@
 /*
 ** callee:
 **     addvl   sp, sp, #-1
-**     str     p4, \[sp\]
-**     ptrue   p4\.b, all
+**     str     (p[4-7]), \[sp\]
+**     ptrue   \1\.b, all
 ** (
-**     ld1b    (z[0-9]+\.b), p4/z, \[x1, #1, mul vl\]
-**     ld1b    (z[0-9]+\.b), p4/z, \[x1\]
-**     st2b    {\2 - \1}, p0, \[x0\]
+**     ld1b    (z[0-9]+\.b), \1/z, \[x1, #1, mul vl\]
+**     ld1b    (z[0-9]+\.b), \1/z, \[x1\]
+**     st2b    {\3 - \2}, p0, \[x0\]
 ** |
-**     ld1b    (z[0-9]+\.b), p4/z, \[x1\]
-**     ld1b    (z[0-9]+\.b), p4/z, \[x1, #1, mul vl\]
-**     st2b    {\3 - \4}, p0, \[x0\]
+**     ld1b    (z[0-9]+\.b), \1/z, \[x1\]
+**     ld1b    (z[0-9]+\.b), \1/z, \[x1, #1, mul vl\]
+**     st2b    {\4 - \5}, p0, \[x0\]
 ** )
 **     st4b    {z0\.b - z3\.b}, p1, \[x0\]
 **     st3b    {z4\.b - z6\.b}, p2, \[x0\]
 **     st1b    z7\.b, p3, \[x0\]
-**     ldr     p4, \[sp\]
+**     ldr     \1, \[sp\]
 **     addvl   sp, sp, #1
 **     ret
 */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u16.c
index 8aa651a415e6670ef8d912e28c34e4b52fc80bb9..0b84622ad4a8ca748d03606d3d57819fc9885fc7 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u16.c
@@ -7,21 +7,21 @@
 /*
 ** callee:
 **     addvl   sp, sp, #-1
-**     str     p4, \[sp\]
-**     ptrue   p4\.b, all
+**     str     (p[4-7]), \[sp\]
+**     ptrue   \1\.b, all
 ** (
-**     ld1h    (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\]
-**     ld1h    (z[0-9]+\.h), p4/z, \[x1\]
-**     st2h    {\2 - \1}, p0, \[x0\]
+**     ld1h    (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\]
+**     ld1h    (z[0-9]+\.h), \1/z, \[x1\]
+**     st2h    {\3 - \2}, p0, \[x0\]
 ** |
-**     ld1h    (z[0-9]+\.h), p4/z, \[x1\]
-**     ld1h    (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\]
-**     st2h    {\3 - \4}, p0, \[x0\]
+**     ld1h    (z[0-9]+\.h), \1/z, \[x1\]
+**     ld1h    (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\]
+**     st2h    {\4 - \5}, p0, \[x0\]
 ** )
 **     st4h    {z0\.h - z3\.h}, p1, \[x0\]
 **     st3h    {z4\.h - z6\.h}, p2, \[x0\]
 **     st1h    z7\.h, p3, \[x0\]
-**     ldr     p4, \[sp\]
+**     ldr     \1, \[sp\]
 **     addvl   sp, sp, #1
 **     ret
 */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u32.c
index 9ea3066edeae40dfa38a747ff9430ecd8ad58457..a5892f7b63bcc818a1818519a5ebbbb133908270 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u32.c
@@ -7,21 +7,21 @@
 /*
 ** callee:
 **     addvl   sp, sp, #-1
-**     str     p4, \[sp\]
-**     ptrue   p4\.b, all
+**     str     (p[4-7]), \[sp\]
+**     ptrue   \1\.b, all
 ** (
-**     ld1w    (z[0-9]+\.s), p4/z, \[x1, #1, mul vl\]
-**     ld1w    (z[0-9]+\.s), p4/z, \[x1\]
-**     st2w    {\2 - \1}, p0, \[x0\]
+**     ld1w    (z[0-9]+\.s), \1/z, \[x1, #1, mul vl\]
+**     ld1w    (z[0-9]+\.s), \1/z, \[x1\]
+**     st2w    {\3 - \2}, p0, \[x0\]
 ** |
-**     ld1w    (z[0-9]+\.s), p4/z, \[x1\]
-**     ld1w    (z[0-9]+\.s), p4/z, \[x1, #1, mul vl\]
-**     st2w    {\3 - \4}, p0, \[x0\]
+**     ld1w    (z[0-9]+\.s), \1/z, \[x1\]
+**     ld1w    (z[0-9]+\.s), \1/z, \[x1, #1, mul vl\]
+**     st2w    {\4 - \5}, p0, \[x0\]
 ** )
 **     st4w    {z0\.s - z3\.s}, p1, \[x0\]
 **     st3w    {z4\.s - z6\.s}, p2, \[x0\]
 **     st1w    z7\.s, p3, \[x0\]
-**     ldr     p4, \[sp\]
+**     ldr     \1, \[sp\]
 **     addvl   sp, sp, #1
 **     ret
 */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u64.c
index b64f3b6d57bb13e254f6ffb083af14b7b100cf49..67438e8e562668afedb48df89775671673e6d753 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u64.c
@@ -7,21 +7,21 @@
 /*
 ** callee:
 **     addvl   sp, sp, #-1
-**     str     p4, \[sp\]
-**     ptrue   p4\.b, all
+**     str     (p[4-7]), \[sp\]
+**     ptrue   \1\.b, all
 ** (
-**     ld1d    (z[0-9]+\.d), p4/z, \[x1, #1, mul vl\]
-**     ld1d    (z[0-9]+\.d), p4/z, \[x1\]
-**     st2d    {\2 - \1}, p0, \[x0\]
+**     ld1d    (z[0-9]+\.d), \1/z, \[x1, #1, mul vl\]
+**     ld1d    (z[0-9]+\.d), \1/z, \[x1\]
+**     st2d    {\3 - \2}, p0, \[x0\]
 ** |
-**     ld1d    (z[0-9]+\.d), p4/z, \[x1\]
-**     ld1d    (z[0-9]+\.d), p4/z, \[x1, #1, mul vl\]
-**     st2d    {\3 - \4}, p0, \[x0\]
+**     ld1d    (z[0-9]+\.d), \1/z, \[x1\]
+**     ld1d    (z[0-9]+\.d), \1/z, \[x1, #1, mul vl\]
+**     st2d    {\4 - \5}, p0, \[x0\]
 ** )
 **     st4d    {z0\.d - z3\.d}, p1, \[x0\]
 **     st3d    {z4\.d - z6\.d}, p2, \[x0\]
 **     st1d    z7\.d, p3, \[x0\]
-**     ldr     p4, \[sp\]
+**     ldr     \1, \[sp\]
 **     addvl   sp, sp, #1
 **     ret
 */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u8.c
index 5575673aeb30a1344aa36f473d44bc26e9881e3a..61d694c6c9c7e3b9f500992b560d13e65e174162 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u8.c
@@ -7,21 +7,21 @@
 /*
 ** callee:
 **     addvl   sp, sp, #-1
-**     str     p4, \[sp\]
-**     ptrue   p4\.b, all
+**     str     (p[4-7]), \[sp\]
+**     ptrue   \1\.b, all
 ** (
-**     ld1b    (z[0-9]+\.b), p4/z, \[x1, #1, mul vl\]
-**     ld1b    (z[0-9]+\.b), p4/z, \[x1\]
-**     st2b    {\2 - \1}, p0, \[x0\]
+**     ld1b    (z[0-9]+\.b), \1/z, \[x1, #1, mul vl\]
+**     ld1b    (z[0-9]+\.b), \1/z, \[x1\]
+**     st2b    {\3 - \2}, p0, \[x0\]
 ** |
-**     ld1b    (z[0-9]+\.b), p4/z, \[x1\]
-**     ld1b    (z[0-9]+\.b), p4/z, \[x1, #1, mul vl\]
-**     st2b    {\3 - \4}, p0, \[x0\]
+**     ld1b    (z[0-9]+\.b), \1/z, \[x1\]
+**     ld1b    (z[0-9]+\.b), \1/z, \[x1, #1, mul vl\]
+**     st2b    {\4 - \5}, p0, \[x0\]
 ** )
 **     st4b    {z0\.b - z3\.b}, p1, \[x0\]
 **     st3b    {z4\.b - z6\.b}, p2, \[x0\]
 **     st1b    z7\.b, p3, \[x0\]
-**     ldr     p4, \[sp\]
+**     ldr     \1, \[sp\]
 **     addvl   sp, sp, #1
 **     ret
 */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_1024.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_1024.c
index de69d9a42ce12afc02dbcad188f27beccf1a45db..6c716ef7c349a5896d5bd7230259331e970e54f4 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_1024.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_1024.c
@@ -30,8 +30,8 @@ typedef double svfloat64_t __attribute__ ((vector_size (128)));
 /*
 ** callee_s8:
 **     ptrue   (p[0-7])\.b, vl128
-**     ld1b    z0\.b, \1/z, \[x0\]
-**     st1b    z0\.b, \1, \[x8\]
+**     ld1b    (z[0-9]+)\.b, \1/z, \[x0\]
+**     st1b    \2\.b, \1, \[x8\]
 **     ret
 */
 CALLEE (s8, svint8_t)
@@ -39,8 +39,8 @@ CALLEE (s8, svint8_t)
 /*
 ** callee_u8:
 **     ptrue   (p[0-7])\.b, vl128
-**     ld1b    z0\.b, \1/z, \[x0\]
-**     st1b    z0\.b, \1, \[x8\]
+**     ld1b    (z[0-9]+)\.b, \1/z, \[x0\]
+**     st1b    \2\.b, \1, \[x8\]
 **     ret
 */
 CALLEE (u8, svuint8_t)
@@ -48,8 +48,8 @@ CALLEE (u8, svuint8_t)
 /*
 ** callee_s16:
 **     ptrue   (p[0-7])\.b, vl128
-**     ld1h    z0\.h, \1/z, \[x0\]
-**     st1h    z0\.h, \1, \[x8\]
+**     ld1h    (z[0-9]+)\.h, \1/z, \[x0\]
+**     st1h    \2\.h, \1, \[x8\]
 **     ret
 */
 CALLEE (s16, svint16_t)
@@ -57,8 +57,8 @@ CALLEE (s16, svint16_t)
 /*
 ** callee_u16:
 **     ptrue   (p[0-7])\.b, vl128
-**     ld1h    z0\.h, \1/z, \[x0\]
-**     st1h    z0\.h, \1, \[x8\]
+**     ld1h    (z[0-9]+)\.h, \1/z, \[x0\]
+**     st1h    \2\.h, \1, \[x8\]
 **     ret
 */
 CALLEE (u16, svuint16_t)
@@ -66,8 +66,8 @@ CALLEE (u16, svuint16_t)
 /*
 ** callee_f16:
 **     ptrue   (p[0-7])\.b, vl128
-**     ld1h    z0\.h, \1/z, \[x0\]
-**     st1h    z0\.h, \1, \[x8\]
+**     ld1h    (z[0-9]+)\.h, \1/z, \[x0\]
+**     st1h    \2\.h, \1, \[x8\]
 **     ret
 */
 CALLEE (f16, svfloat16_t)
@@ -75,8 +75,8 @@ CALLEE (f16, svfloat16_t)
 /*
 ** callee_bf16:
 **     ptrue   (p[0-7])\.b, vl128
-**     ld1h    z0\.h, \1/z, \[x0\]
-**     st1h    z0\.h, \1, \[x8\]
+**     ld1h    (z[0-9]+)\.h, \1/z, \[x0\]
+**     st1h    \2\.h, \1, \[x8\]
 **     ret
 */
 CALLEE (bf16, svbfloat16_t)
@@ -84,8 +84,8 @@ CALLEE (bf16, svbfloat16_t)
 /*
 ** callee_s32:
 **     ptrue   (p[0-7])\.b, vl128
-**     ld1w    z0\.s, \1/z, \[x0\]
-**     st1w    z0\.s, \1, \[x8\]
+**     ld1w    (z[0-9]+)\.s, \1/z, \[x0\]
+**     st1w    \2\.s, \1, \[x8\]
 **     ret
 */
 CALLEE (s32, svint32_t)
@@ -93,8 +93,8 @@ CALLEE (s32, svint32_t)
 /*
 ** callee_u32:
 **     ptrue   (p[0-7])\.b, vl128
-**     ld1w    z0\.s, \1/z, \[x0\]
-**     st1w    z0\.s, \1, \[x8\]
+**     ld1w    (z[0-9]+)\.s, \1/z, \[x0\]
+**     st1w    \2\.s, \1, \[x8\]
 **     ret
 */
 CALLEE (u32, svuint32_t)
@@ -102,8 +102,8 @@ CALLEE (u32, svuint32_t)
 /*
 ** callee_f32:
 **     ptrue   (p[0-7])\.b, vl128
-**     ld1w    z0\.s, \1/z, \[x0\]
-**     st1w    z0\.s, \1, \[x8\]
+**     ld1w    (z[0-9]+)\.s, \1/z, \[x0\]
+**     st1w    \2\.s, \1, \[x8\]
 **     ret
 */
 CALLEE (f32, svfloat32_t)
@@ -111,8 +111,8 @@ CALLEE (f32, svfloat32_t)
 /*
 ** callee_s64:
 **     ptrue   (p[0-7])\.b, vl128
-**     ld1d    z0\.d, \1/z, \[x0\]
-**     st1d    z0\.d, \1, \[x8\]
+**     ld1d    (z[0-9]+)\.d, \1/z, \[x0\]
+**     st1d    \2\.d, \1, \[x8\]
 **     ret
 */
 CALLEE (s64, svint64_t)
@@ -120,8 +120,8 @@ CALLEE (s64, svint64_t)
 /*
 ** callee_u64:
 **     ptrue   (p[0-7])\.b, vl128
-**     ld1d    z0\.d, \1/z, \[x0\]
-**     st1d    z0\.d, \1, \[x8\]
+**     ld1d    (z[0-9]+)\.d, \1/z, \[x0\]
+**     st1d    \2\.d, \1, \[x8\]
 **     ret
 */
 CALLEE (u64, svuint64_t)
@@ -129,8 +129,8 @@ CALLEE (u64, svuint64_t)
 /*
 ** callee_f64:
 **     ptrue   (p[0-7])\.b, vl128
-**     ld1d    z0\.d, \1/z, \[x0\]
-**     st1d    z0\.d, \1, \[x8\]
+**     ld1d    (z[0-9]+)\.d, \1/z, \[x0\]
+**     st1d    \2\.d, \1, \[x8\]
 **     ret
 */
 CALLEE (f64, svfloat64_t)

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_2048.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_2048.c
index 0b64ff2e8c21c1fccef265a4b7505373d797fcc3..0eb9607d9db2079d04c58ba10dc556b6f7482cbd 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_2048.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_2048.c
@@ -30,8 +30,8 @@ typedef double svfloat64_t __attribute__ ((vector_size (256)));
 /*
 ** callee_s8:
 **     ptrue   (p[0-7])\.b, vl256
-**     ld1b    z0\.b, \1/z, \[x0\]
-**     st1b    z0\.b, \1, \[x8\]
+**     ld1b    (z[0-9]+)\.b, \1/z, \[x0\]
+**     st1b    \2\.b, \1, \[x8\]
 **     ret
 */
 CALLEE (s8, svint8_t)
@@ -39,8 +39,8 @@ CALLEE (s8, svint8_t)
 /*
 ** callee_u8:
 **     ptrue   (p[0-7])\.b, vl256
-**     ld1b    z0\.b, \1/z, \[x0\]
-**     st1b    z0\.b, \1, \[x8\]
+**     ld1b    (z[0-9]+)\.b, \1/z, \[x0\]
+**     st1b    \2\.b, \1, \[x8\]
 **     ret
 */
 CALLEE (u8, svuint8_t)
@@ -48,8 +48,8 @@ CALLEE (u8, svuint8_t)
 /*
 ** callee_s16:
 **     ptrue   (p[0-7])\.b, vl256
-**     ld1h    z0\.h, \1/z, \[x0\]
-**     st1h    z0\.h, \1, \[x8\]
+**     ld1h    (z[0-9]+)\.h, \1/z, \[x0\]
+**     st1h    \2\.h, \1, \[x8\]
 **     ret
 */
 CALLEE (s16, svint16_t)
@@ -57,8 +57,8 @@ CALLEE (s16, svint16_t)
 /*
 ** callee_u16:
 **     ptrue   (p[0-7])\.b, vl256
-**     ld1h    z0\.h, \1/z, \[x0\]
-**     st1h    z0\.h, \1, \[x8\]
+**     ld1h    (z[0-9]+)\.h, \1/z, \[x0\]
+**     st1h    \2\.h, \1, \[x8\]
 **     ret
 */
 CALLEE (u16, svuint16_t)
@@ -66,8 +66,8 @@ CALLEE (u16, svuint16_t)
 /*
 ** callee_f16:
 **     ptrue   (p[0-7])\.b, vl256
-**     ld1h    z0\.h, \1/z, \[x0\]
-**     st1h    z0\.h, \1, \[x8\]
+**     ld1h    (z[0-9]+)\.h, \1/z, \[x0\]
+**     st1h    \2\.h, \1, \[x8\]
 **     ret
 */
 CALLEE (f16, svfloat16_t)
@@ -75,8 +75,8 @@ CALLEE (f16, svfloat16_t)
 /*
 ** callee_bf16:
 **     ptrue   (p[0-7])\.b, vl256
-**     ld1h    z0\.h, \1/z, \[x0\]
-**     st1h    z0\.h, \1, \[x8\]
+**     ld1h    (z[0-9]+)\.h, \1/z, \[x0\]
+**     st1h    \2\.h, \1, \[x8\]
 **     ret
 */
 CALLEE (bf16, svbfloat16_t)
@@ -84,8 +84,8 @@ CALLEE (bf16, svbfloat16_t)
 /*
 ** callee_s32:
 **     ptrue   (p[0-7])\.b, vl256
-**     ld1w    z0\.s, \1/z, \[x0\]
-**     st1w    z0\.s, \1, \[x8\]
+**     ld1w    (z[0-9]+)\.s, \1/z, \[x0\]
+**     st1w    \2\.s, \1, \[x8\]
 **     ret
 */
 CALLEE (s32, svint32_t)
@@ -93,8 +93,8 @@ CALLEE (s32, svint32_t)
 /*
 ** callee_u32:
 **     ptrue   (p[0-7])\.b, vl256
-**     ld1w    z0\.s, \1/z, \[x0\]
-**     st1w    z0\.s, \1, \[x8\]
+**     ld1w    (z[0-9]+)\.s, \1/z, \[x0\]
+**     st1w    \2\.s, \1, \[x8\]
 **     ret
 */
 CALLEE (u32, svuint32_t)
@@ -102,8 +102,8 @@ CALLEE (u32, svuint32_t)
 /*
 ** callee_f32:
 **     ptrue   (p[0-7])\.b, vl256
-**     ld1w    z0\.s, \1/z, \[x0\]
-**     st1w    z0\.s, \1, \[x8\]
+**     ld1w    (z[0-9]+)\.s, \1/z, \[x0\]
+**     st1w    \2\.s, \1, \[x8\]
 **     ret
 */
 CALLEE (f32, svfloat32_t)
@@ -111,8 +111,8 @@ CALLEE (f32, svfloat32_t)
 /*
 ** callee_s64:
 **     ptrue   (p[0-7])\.b, vl256
-**     ld1d    z0\.d, \1/z, \[x0\]
-**     st1d    z0\.d, \1, \[x8\]
+**     ld1d    (z[0-9]+)\.d, \1/z, \[x0\]
+**     st1d    \2\.d, \1, \[x8\]
 **     ret
 */
 CALLEE (s64, svint64_t)
@@ -120,8 +120,8 @@ CALLEE (s64, svint64_t)
 /*
 ** callee_u64:
 **     ptrue   (p[0-7])\.b, vl256
-**     ld1d    z0\.d, \1/z, \[x0\]
-**     st1d    z0\.d, \1, \[x8\]
+**     ld1d    (z[0-9]+)\.d, \1/z, \[x0\]
+**     st1d    \2\.d, \1, \[x8\]
 **     ret
 */
 CALLEE (u64, svuint64_t)
@@ -129,8 +129,8 @@ CALLEE (u64, svuint64_t)
 /*
 ** callee_f64:
 **     ptrue   (p[0-7])\.b, vl256
-**     ld1d    z0\.d, \1/z, \[x0\]
-**     st1d    z0\.d, \1, \[x8\]
+**     ld1d    (z[0-9]+)\.d, \1/z, \[x0\]
+**     st1d    \2\.d, \1, \[x8\]
 **     ret
 */
 CALLEE (f64, svfloat64_t)

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_256.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_256.c
index 9eb71e3dcc3ba460194587a318ec777da529c67b..749eb33259904ec51435f596896f1e33ecdd08f4 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_256.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_256.c
@@ -30,8 +30,8 @@ typedef double svfloat64_t __attribute__ ((vector_size (32)));
 /*
 ** callee_s8:
 **     ptrue   (p[0-7])\.b, vl32
-**     ld1b    z0\.b, \1/z, \[x0\]
-**     st1b    z0\.b, \1, \[x8\]
+**     ld1b    (z[0-9]+)\.b, \1/z, \[x0\]
+**     st1b    \2\.b, \1, \[x8\]
 **     ret
 */
 CALLEE (s8, svint8_t)
@@ -39,8 +39,8 @@ CALLEE (s8, svint8_t)
 /*
 ** callee_u8:
 **     ptrue   (p[0-7])\.b, vl32
-**     ld1b    z0\.b, \1/z, \[x0\]
-**     st1b    z0\.b, \1, \[x8\]
+**     ld1b    (z[0-9]+)\.b, \1/z, \[x0\]
+**     st1b    \2\.b, \1, \[x8\]
 **     ret
 */
 CALLEE (u8, svuint8_t)
@@ -48,8 +48,8 @@ CALLEE (u8, svuint8_t)
 /*
 ** callee_s16:
 **     ptrue   (p[0-7])\.b, vl32
-**     ld1h    z0\.h, \1/z, \[x0\]
-**     st1h    z0\.h, \1, \[x8\]
+**     ld1h    (z[0-9]+)\.h, \1/z, \[x0\]
+**     st1h    \2\.h, \1, \[x8\]
 **     ret
 */
 CALLEE (s16, svint16_t)
@@ -57,8 +57,8 @@ CALLEE (s16, svint16_t)
 /*
 ** callee_u16:
 **     ptrue   (p[0-7])\.b, vl32
-**     ld1h    z0\.h, \1/z, \[x0\]
-**     st1h    z0\.h, \1, \[x8\]
+**     ld1h    (z[0-9]+)\.h, \1/z, \[x0\]
+**     st1h    \2\.h, \1, \[x8\]
 **     ret
 */
 CALLEE (u16, svuint16_t)
@@ -66,8 +66,8 @@ CALLEE (u16, svuint16_t)
 /*
 ** callee_f16:
 **     ptrue   (p[0-7])\.b, vl32
-**     ld1h    z0\.h, \1/z, \[x0\]
-**     st1h    z0\.h, \1, \[x8\]
+**     ld1h    (z[0-9]+)\.h, \1/z, \[x0\]
+**     st1h    \2\.h, \1, \[x8\]
 **     ret
 */
 CALLEE (f16, svfloat16_t)
@@ -75,8 +75,8 @@ CALLEE (f16, svfloat16_t)
 /*
 ** callee_bf16:
 **     ptrue   (p[0-7])\.b, vl32
-**     ld1h    z0\.h, \1/z, \[x0\]
-**     st1h    z0\.h, \1, \[x8\]
+**     ld1h    (z[0-9]+)\.h, \1/z, \[x0\]
+**     st1h    \2\.h, \1, \[x8\]
 **     ret
 */
 CALLEE (bf16, svbfloat16_t)
@@ -84,8 +84,8 @@ CALLEE (bf16, svbfloat16_t)
 /*
 ** callee_s32:
 **     ptrue   (p[0-7])\.b, vl32
-**     ld1w    z0\.s, \1/z, \[x0\]
-**     st1w    z0\.s, \1, \[x8\]
+**     ld1w    (z[0-9]+)\.s, \1/z, \[x0\]
+**     st1w    \2\.s, \1, \[x8\]
 **     ret
 */
 CALLEE (s32, svint32_t)
@@ -93,8 +93,8 @@ CALLEE (s32, svint32_t)
 /*
 ** callee_u32:
 **     ptrue   (p[0-7])\.b, vl32
-**     ld1w    z0\.s, \1/z, \[x0\]
-**     st1w    z0\.s, \1, \[x8\]
+**     ld1w    (z[0-9]+)\.s, \1/z, \[x0\]
+**     st1w    \2\.s, \1, \[x8\]
 **     ret
 */
 CALLEE (u32, svuint32_t)
@@ -102,8 +102,8 @@ CALLEE (u32, svuint32_t)
 /*
 ** callee_f32:
 **     ptrue   (p[0-7])\.b, vl32
-**     ld1w    z0\.s, \1/z, \[x0\]
-**     st1w    z0\.s, \1, \[x8\]
+**     ld1w    (z[0-9]+)\.s, \1/z, \[x0\]
+**     st1w    \2\.s, \1, \[x8\]
 **     ret
 */
 CALLEE (f32, svfloat32_t)
@@ -111,8 +111,8 @@ CALLEE (f32, svfloat32_t)
 /*
 ** callee_s64:
 **     ptrue   (p[0-7])\.b, vl32
-**     ld1d    z0\.d, \1/z, \[x0\]
-**     st1d    z0\.d, \1, \[x8\]
+**     ld1d    (z[0-9]+)\.d, \1/z, \[x0\]
+**     st1d    \2\.d, \1, \[x8\]
 **     ret
 */
 CALLEE (s64, svint64_t)
@@ -120,8 +120,8 @@ CALLEE (s64, svint64_t)
 /*
 ** callee_u64:
 **     ptrue   (p[0-7])\.b, vl32
-**     ld1d    z0\.d, \1/z, \[x0\]
-**     st1d    z0\.d, \1, \[x8\]
+**     ld1d    (z[0-9]+)\.d, \1/z, \[x0\]
+**     st1d    \2\.d, \1, \[x8\]
 **     ret
 */
 CALLEE (u64, svuint64_t)
@@ -129,8 +129,8 @@ CALLEE (u64, svuint64_t)
 /*
 ** callee_f64:
 **     ptrue   (p[0-7])\.b, vl32
-**     ld1d    z0\.d, \1/z, \[x0\]
-**     st1d    z0\.d, \1, \[x8\]
+**     ld1d    (z[0-9]+)\.d, \1/z, \[x0\]
+**     st1d    \2\.d, \1, \[x8\]
 **     ret
 */
 CALLEE (f64, svfloat64_t)

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_512.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_512.c
index 8b8d0c7c860d5e42a7da33b03306a004c6d68d58..f6a64cc49441725372b11d8da8a1e39e6a4193d1 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_512.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_512.c
@@ -30,8 +30,8 @@ typedef double svfloat64_t __attribute__ ((vector_size (64)));
 /*
 ** callee_s8:
 **     ptrue   (p[0-7])\.b, vl64
-**     ld1b    z0\.b, \1/z, \[x0\]
-**     st1b    z0\.b, \1, \[x8\]
+**     ld1b    (z[0-9]+)\.b, \1/z, \[x0\]
+**     st1b    \2\.b, \1, \[x8\]
 **     ret
 */
 CALLEE (s8, svint8_t)
@@ -39,8 +39,8 @@ CALLEE (s8, svint8_t)
 /*
 ** callee_u8:
 **     ptrue   (p[0-7])\.b, vl64
-**     ld1b    z0\.b, \1/z, \[x0\]
-**     st1b    z0\.b, \1, \[x8\]
+**     ld1b    (z[0-9]+)\.b, \1/z, \[x0\]
+**     st1b    \2\.b, \1, \[x8\]
 **     ret
 */
 CALLEE (u8, svuint8_t)
@@ -48,8 +48,8 @@ CALLEE (u8, svuint8_t)
 /*
 ** callee_s16:
 **     ptrue   (p[0-7])\.b, vl64
-**     ld1h    z0\.h, \1/z, \[x0\]
-**     st1h    z0\.h, \1, \[x8\]
+**     ld1h    (z[0-9]+)\.h, \1/z, \[x0\]
+**     st1h    \2\.h, \1, \[x8\]
 **     ret
 */
 CALLEE (s16, svint16_t)
@@ -57,8 +57,8 @@ CALLEE (s16, svint16_t)
 /*
 ** callee_u16:
 **     ptrue   (p[0-7])\.b, vl64
-**     ld1h    z0\.h, \1/z, \[x0\]
-**     st1h    z0\.h, \1, \[x8\]
+**     ld1h    (z[0-9]+)\.h, \1/z, \[x0\]
+**     st1h    \2\.h, \1, \[x8\]
 **     ret
 */
 CALLEE (u16, svuint16_t)
@@ -66,8 +66,8 @@ CALLEE (u16, svuint16_t)
 /*
 ** callee_f16:
 **     ptrue   (p[0-7])\.b, vl64
-**     ld1h    z0\.h, \1/z, \[x0\]
-**     st1h    z0\.h, \1, \[x8\]
+**     ld1h    (z[0-9]+)\.h, \1/z, \[x0\]
+**     st1h    \2\.h, \1, \[x8\]
 **     ret
 */
 CALLEE (f16, svfloat16_t)
@@ -75,8 +75,8 @@ CALLEE (f16, svfloat16_t)
 /*
 ** callee_bf16:
 **     ptrue   (p[0-7])\.b, vl64
-**     ld1h    z0\.h, \1/z, \[x0\]
-**     st1h    z0\.h, \1, \[x8\]
+**     ld1h    (z[0-9]+)\.h, \1/z, \[x0\]
+**     st1h    \2\.h, \1, \[x8\]
 **     ret
 */
 CALLEE (bf16, svbfloat16_t)
@@ -84,8 +84,8 @@ CALLEE (bf16, svbfloat16_t)
 /*
 ** callee_s32:
 **     ptrue   (p[0-7])\.b, vl64
-**     ld1w    z0\.s, \1/z, \[x0\]
-**     st1w    z0\.s, \1, \[x8\]
+**     ld1w    (z[0-9]+)\.s, \1/z, \[x0\]
+**     st1w    \2\.s, \1, \[x8\]
 **     ret
 */
 CALLEE (s32, svint32_t)
@@ -93,8 +93,8 @@ CALLEE (s32, svint32_t)
 /*
 ** callee_u32:
 **     ptrue   (p[0-7])\.b, vl64
-**     ld1w    z0\.s, \1/z, \[x0\]
-**     st1w    z0\.s, \1, \[x8\]
+**     ld1w    (z[0-9]+)\.s, \1/z, \[x0\]
+**     st1w    \2\.s, \1, \[x8\]
 **     ret
 */
 CALLEE (u32, svuint32_t)
@@ -102,8 +102,8 @@ CALLEE (u32, svuint32_t)
 /*
 ** callee_f32:
 **     ptrue   (p[0-7])\.b, vl64
-**     ld1w    z0\.s, \1/z, \[x0\]
-**     st1w    z0\.s, \1, \[x8\]
+**     ld1w    (z[0-9]+)\.s, \1/z, \[x0\]
+**     st1w    \2\.s, \1, \[x8\]
 **     ret
 */
 CALLEE (f32, svfloat32_t)
@@ -111,8 +111,8 @@ CALLEE (f32, svfloat32_t)
 /*
 ** callee_s64:
 **     ptrue   (p[0-7])\.b, vl64
-**     ld1d    z0\.d, \1/z, \[x0\]
-**     st1d    z0\.d, \1, \[x8\]
+**     ld1d    (z[0-9]+)\.d, \1/z, \[x0\]
+**     st1d    \2\.d, \1, \[x8\]
 **     ret
 */
 CALLEE (s64, svint64_t)
@@ -120,8 +120,8 @@ CALLEE (s64, svint64_t)
 /*
 ** callee_u64:
 **     ptrue   (p[0-7])\.b, vl64
-**     ld1d    z0\.d, \1/z, \[x0\]
-**     st1d    z0\.d, \1, \[x8\]
+**     ld1d    (z[0-9]+)\.d, \1/z, \[x0\]
+**     st1d    \2\.d, \1, \[x8\]
 **     ret
 */
 CALLEE (u64, svuint64_t)
@@ -129,8 +129,8 @@ CALLEE (u64, svuint64_t)
 /*
 ** callee_f64:
 **     ptrue   (p[0-7])\.b, vl64
-**     ld1d    z0\.d, \1/z, \[x0\]
-**     st1d    z0\.d, \1, \[x8\]
+**     ld1d    (z[0-9]+)\.d, \1/z, \[x0\]
+**     st1d    \2\.d, \1, \[x8\]
 **     ret
 */
 CALLEE (f64, svfloat64_t)

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr89007-1.c b/gcc/testsuite/gcc.target/aarch64/sve/pr89007-1.c
index ff9550c91091cc55e180094f7603eeafba0ac8d1..d65aa94a52a7b57633817a20850d89195a59002b 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/pr89007-1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr89007-1.c
@@ -15,7 +15,7 @@ unsigned char in2[N];
 **     add     (z[0-9]+\.b), (\1, \2|\2, \1)
 **     orr     (z[0-9]+)\.d, z[0-9]+\.d, z[0-9]+\.d
 **     and     (z[0-9]+\.b), \5\.b, #0x1
-**     add     z0\.b, (\3, \6|\6, \3)
+**     add     z[0-9]+\.b, (\3, \6|\6, \3)
 **     ...
 */
 void

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr89007-2.c b/gcc/testsuite/gcc.target/aarch64/sve/pr89007-2.c
index da345fe8bd6e744179fb910aa221e48574af1b61..1de44df96c92b9671bb1a9fe049fba0f5ebc0dd7 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/pr89007-2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr89007-2.c
@@ -15,7 +15,7 @@ unsigned char in2[N];
 **     add     (z[0-9]+\.b), (\1, \2|\2, \1)
 **     and     (z[0-9]+)\.d, z[0-9]+\.d, z[0-9]+\.d
 **     and     (z[0-9]+\.b), \5\.b, #0x1
-**     add     z0\.b, (\3, \6|\6, \3)
+**     add     z[0-9]+\.b, (\3, \6|\6, \3)
 **     ...
 */
 void

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/store_scalar_offset_1.c b/gcc/testsuite/gcc.target/aarch64/sve/store_scalar_offset_1.c
index 4f0655f6d7c6aff2373bbfd6d3459dc95738784f..c742b92b934482989d1a4e5384a6470342949e08 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/store_scalar_offset_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/store_scalar_offset_1.c
@@ -49,7 +49,7 @@ void sve_store_8_s (signed long i, int8_t *a)
   asm volatile ("" : "=w" (*(vnx16qi *) &a[i]));
 }
 
-/* { dg-final { scan-assembler-times {\tst1d\tz0\.d, p[0-7], \[x0, x1, lsl 3\]\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tst1w\tz0\.s, p[0-7], \[x0, x1, lsl 2\]\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tst1h\tz0\.h, p[0-7], \[x0, x1, lsl 1\]\n} 2 } } */
-/* { dg-final { scan-assembler-times {\tst1b\tz0\.b, p[0-7], \[x1, x0\]\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d, p[0-7], \[x0, x1, lsl 3\]\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s, p[0-7], \[x0, x1, lsl 2\]\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+\.h, p[0-7], \[x0, x1, lsl 1\]\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tst1b\tz[0-9]+\.b, p[0-7], \[x1, x0\]\n} 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/vadd_reduc-1.c b/gcc/testsuite/gcc.target/aarch64/vadd_reduc-1.c
index 271a1c3e8c319f7bdb8669e4b3199b6f88ef7f5d..c158db3aa39072292e5821be35ecb62f174359b0 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/vadd_reduc-1.c
+++ b/gcc/testsuite/gcc.target/aarch64/vadd_reduc-1.c
@@ -9,8 +9,8 @@ typedef int v4si __attribute__ ((vector_size (16)));
 /*
 **bar:
 **     ...
-**     addv    s0, v0.4s
-**     fmov    w0, s0
+**     addv    (s[0-9]+), v0.4s
+**     fmov    w0, \1
 **     lsr     w1, w0, 16
 **     add     w0, w1, w0, uxth
 **     ret

diff --git a/gcc/testsuite/gcc.target/aarch64/vadd_reduc-2.c b/gcc/testsuite/gcc.target/aarch64/vadd_reduc-2.c
index 0ad96954ff7daeb983adaafaec655770d9fe77cd..b4d4face2e96a9063578ede41b0cad7604790246 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/vadd_reduc-2.c
+++ b/gcc/testsuite/gcc.target/aarch64/vadd_reduc-2.c
@@ -9,8 +9,8 @@
 /*
 **test:
 **     ...
-**     addv    s0, v0.4s
-**     fmov    w0, s0
+**     addv    (s[0-9]+), v[0-9]+.4s
+**     fmov    w0, \1
 **     and     w1, w0, 65535
 **     add     w0, w1, w0, lsr 16
 **     lsr     w0, w0, 1