arm64: dts: freescale: imx8mm-var-som: Align fsl,pins tables

Reformat the fsl,pins tables in the i.MX8MM VAR-SOM device tree to use
consistent column alignment across all pinctrl groups.

Align the entries to match the formatting already used in the
pinctrl_fec1 group, which contains the longest pin definitions,
for improved readability and consistency.

No functional changes intended.

Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi
index b6560c03639eb45922ec281071b7de7776f48637..da3c7332ec34ff309ee1a7a29e90bfd4e6852fba 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi
@@ -368,171 +368,171 @@
 
        pinctrl_i2c1: i2c1grp {
                fsl,pins = <
-                       MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
-                       MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
+                       MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL                  0x400001c3
+                       MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA                  0x400001c3
                >;
        };
 
        pinctrl_i2c3: i2c3grp {
                fsl,pins = <
-                       MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
-                       MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
+                       MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL                  0x400001c3
+                       MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA                  0x400001c3
                >;
        };
 
        pinctrl_pmic: pmicirqgrp {
                fsl,pins = <
-                       MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8        0x141
+                       MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8                0x141
                >;
        };
 
        pinctrl_reg_eth_phy: regethphygrp {
                fsl,pins = <
-                       MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9        0x41
+                       MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9                0x41
                >;
        };
 
        pinctrl_restouch: restouchgrp {
                fsl,pins = <
-                       MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3       0x1c0
+                       MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3               0x1c0
                >;
        };
 
        pinctrl_uart2: uart2grp {
                fsl,pins = <
-                       MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX     0x140
-                       MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX      0x140
-                       MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B   0x140
-                       MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B   0x140
+                       MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX             0x140
+                       MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX              0x140
+                       MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B           0x140
+                       MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B           0x140
                >;
        };
 
        pinctrl_usdhc1: usdhc1grp {
                fsl,pins = <
-                       MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x190
-                       MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d0
-                       MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d0
-                       MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d0
-                       MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d0
-                       MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d0
+                       MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK                 0x190
+                       MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD                 0x1d0
+                       MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0             0x1d0
+                       MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1             0x1d0
+                       MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2             0x1d0
+                       MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3             0x1d0
                >;
        };
 
        pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
                fsl,pins = <
-                       MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x194
-                       MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d4
-                       MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d4
-                       MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d4
-                       MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d4
-                       MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d4
+                       MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK                 0x194
+                       MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD                 0x1d4
+                       MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0             0x1d4
+                       MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1             0x1d4
+                       MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2             0x1d4
+                       MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3             0x1d4
                >;
        };
 
        pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
                fsl,pins = <
-                       MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x196
-                       MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d6
-                       MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d6
-                       MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d6
-                       MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d6
-                       MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d6
+                       MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK                 0x196
+                       MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD                 0x1d6
+                       MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0             0x1d6
+                       MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1             0x1d6
+                       MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2             0x1d6
+                       MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3             0x1d6
                >;
        };
 
        pinctrl_usdhc2_gpio: usdhc2gpiogrp {
                fsl,pins = <
-                       MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10      0xc1
+                       MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10              0xc1
                >;
        };
 
        pinctrl_usdhc2: usdhc2grp {
                fsl,pins = <
-                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
-                       MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
-                       MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
-                       MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
-                       MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
-                       MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
-                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
+                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x190
+                       MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                 0x1d0
+                       MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0             0x1d0
+                       MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1             0x1d0
+                       MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d0
+                       MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d0
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x1d0
                >;
        };
 
        pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
                fsl,pins = <
-                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
-                       MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
-                       MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
-                       MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
-                       MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
-                       MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
-                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
+                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x194
+                       MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                 0x1d4
+                       MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0             0x1d4
+                       MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1             0x1d4
+                       MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d4
+                       MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d4
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x1d0
                >;
        };
 
        pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
                fsl,pins = <
-                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
-                       MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
-                       MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
-                       MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
-                       MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
-                       MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
-                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
+                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x196
+                       MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                 0x1d6
+                       MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0             0x1d6
+                       MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1             0x1d6
+                       MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d6
+                       MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d6
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x1d0
                >;
        };
 
        pinctrl_usdhc3: usdhc3grp {
                fsl,pins = <
-                       MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x190
-                       MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d0
-                       MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d0
-                       MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d0
-                       MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d0
-                       MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d0
-                       MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d0
-                       MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d0
-                       MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d0
-                       MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d0
-                       MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x190
+                       MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x190
+                       MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
+                       MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
+                       MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
+                       MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
+                       MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
+                       MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
+                       MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
+                       MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
+                       MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
+                       MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
                >;
        };
 
        pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
                fsl,pins = <
-                       MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x194
-                       MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d4
-                       MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d4
-                       MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d4
-                       MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d4
-                       MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d4
-                       MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d4
-                       MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d4
-                       MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d4
-                       MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d4
-                       MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x194
+                       MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x194
+                       MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
+                       MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
+                       MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
+                       MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
+                       MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
+                       MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
+                       MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
+                       MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
+                       MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
+                       MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
                >;
        };
 
        pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
                fsl,pins = <
-                       MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x196
-                       MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d6
-                       MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d6
-                       MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d6
-                       MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d6
-                       MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d6
-                       MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d6
-                       MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d6
-                       MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d6
-                       MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d6
-                       MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x196
+                       MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x196
+                       MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
+                       MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
+                       MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
+                       MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
+                       MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
+                       MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
+                       MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
+                       MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
+                       MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
+                       MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
                >;
        };
 
        pinctrl_wdog: wdoggrp {
                fsl,pins = <
-                       MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B    0x166
+                       MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0x166
                >;
        };
 };