KVM: x86: Move x2APIC ICR helper above kvm_apic_write_nodecode()

commit d33234342f8b468e719e05649fd26549fb37ef8a upstream.

Hoist kvm_x2apic_icr_write() above kvm_apic_write_nodecode() so that a
local helper to _read_ the x2APIC ICR can be added and used in the
nodecode path without needing a forward declaration.

No functional change intended.

Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20240719235107.3023592-3-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 376fc506740206db5eb75856df129ea42dc5353d..f1f54218b0603f09defb135b7f9f4fe56b3b71af 100644 (file)
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -2453,6 +2453,29 @@ void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
 }
 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
 
+#define X2APIC_ICR_RESERVED_BITS (GENMASK_ULL(31, 20) | GENMASK_ULL(17, 16) | BIT(13))
+
+int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data)
+{
+       if (data & X2APIC_ICR_RESERVED_BITS)
+               return 1;
+
+       /*
+        * The BUSY bit is reserved on both Intel and AMD in x2APIC mode, but
+        * only AMD requires it to be zero, Intel essentially just ignores the
+        * bit.  And if IPI virtualization (Intel) or x2AVIC (AMD) is enabled,
+        * the CPU performs the reserved bits checks, i.e. the underlying CPU
+        * behavior will "win".  Arbitrarily clear the BUSY bit, as there is no
+        * sane way to provide consistent behavior with respect to hardware.
+        */
+       data &= ~APIC_ICR_BUSY;
+
+       kvm_apic_send_ipi(apic, (u32)data, (u32)(data >> 32));
+       kvm_lapic_set_reg64(apic, APIC_ICR, data);
+       trace_kvm_apic_write(APIC_ICR, data);
+       return 0;
+}
+
 /* emulate APIC access in a trap manner */
 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
 {
@@ -3183,29 +3206,6 @@ int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
        return 0;
 }
 
-#define X2APIC_ICR_RESERVED_BITS (GENMASK_ULL(31, 20) | GENMASK_ULL(17, 16) | BIT(13))
-
-int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data)
-{
-       if (data & X2APIC_ICR_RESERVED_BITS)
-               return 1;
-
-       /*
-        * The BUSY bit is reserved on both Intel and AMD in x2APIC mode, but
-        * only AMD requires it to be zero, Intel essentially just ignores the
-        * bit.  And if IPI virtualization (Intel) or x2AVIC (AMD) is enabled,
-        * the CPU performs the reserved bits checks, i.e. the underlying CPU
-        * behavior will "win".  Arbitrarily clear the BUSY bit, as there is no
-        * sane way to provide consistent behavior with respect to hardware.
-        */
-       data &= ~APIC_ICR_BUSY;
-
-       kvm_apic_send_ipi(apic, (u32)data, (u32)(data >> 32));
-       kvm_lapic_set_reg64(apic, APIC_ICR, data);
-       trace_kvm_apic_write(APIC_ICR, data);
-       return 0;
-}
-
 static int kvm_lapic_msr_read(struct kvm_lapic *apic, u32 reg, u64 *data)
 {
        u32 low;