interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_i2c14_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_spi14_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_uart14_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_i2c15_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_spi15_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_uart15_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_i2c16_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_spi16_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_uart16_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_i2c17_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_spi17_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_uart17_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_i2c18_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_spi18_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_uart18_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_i2c19_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_spi19_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_uart19_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_i2c20_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_spi20_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_uart20_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_i2c0_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_spi0_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_uart0_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_i2c1_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_spi1_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_uart1_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_i2c2_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_spi2_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_uart2_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_i2c3_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_spi3_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_uart3_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_i2c4_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_spi4_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_uart4_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_i2c5_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_spi5_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_uart5_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_i2c7_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_spi7_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ pinctrl-0 = <&qup_uart7_default>;
+ pinctrl-names = "default";
interconnect-names = "qup-core", "qup-config";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_i2c8_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_spi8_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ pinctrl-0 = <&qup_uart8_default>;
+ pinctrl-names = "default";
interconnect-names = "qup-core", "qup-config";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_i2c9_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_spi9_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_uart9_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_i2c10_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_spi10_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ pinctrl-0 = <&qup_uart10_default>;
+ pinctrl-names = "default";
interconnect-names = "qup-core", "qup-config";
interconnects = <&clk_virt MASTER_QUP_CORE_1 0
&clk_virt SLAVE_QUP_CORE_1 0>,
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_i2c11_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_spi11_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ pinctrl-0 = <&qup_uart11_default>;
+ pinctrl-names = "default";
interconnect-names = "qup-core", "qup-config";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_i2c12_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_spi12_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_uart12_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_i2c13_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_i2c21_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
clock-names = "se";
+ pinctrl-0 = <&qup_spi21_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
interconnect-names = "qup-core", "qup-config";
+ pinctrl-0 = <&qup_uart21_default>;
+ pinctrl-names = "default";
interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 149>;
wakeup-parent = <&pdc>;
+
+ qup_i2c0_default: qup-i2c0-state {
+ pins = "gpio20", "gpio21";
+ function = "qup0_se0";
+ };
+
+ qup_i2c1_default: qup-i2c1-state {
+ pins = "gpio24", "gpio25";
+ function = "qup0_se1";
+ };
+
+ qup_i2c2_default: qup-i2c2-state {
+ pins = "gpio36", "gpio37";
+ function = "qup0_se2";
+ };
+
+ qup_i2c3_default: qup-i2c3-state {
+ pins = "gpio28", "gpio29";
+ function = "qup0_se3";
+ };
+
+ qup_i2c4_default: qup-i2c4-state {
+ pins = "gpio32", "gpio33";
+ function = "qup0_se4";
+ };
+
+ qup_i2c5_default: qup-i2c5-state {
+ pins = "gpio36", "gpio37";
+ function = "qup0_se5";
+ };
+
+ qup_i2c7_default: qup-i2c7-state {
+ pins = "gpio40", "gpio41";
+ function = "qup1_se0";
+ };
+
+ qup_i2c8_default: qup-i2c8-state {
+ pins = "gpio42", "gpio43";
+ function = "qup1_se1";
+ };
+
+ qup_i2c9_default: qup-i2c9-state {
+ pins = "gpio46", "gpio47";
+ function = "qup1_se2";
+ };
+
+ qup_i2c10_default: qup-i2c10-state {
+ pins = "gpio44", "gpio45";
+ function = "qup1_se3";
+ };
+
+ qup_i2c11_default: qup-i2c11-state {
+ pins = "gpio48", "gpio49";
+ function = "qup1_se4";
+ };
+
+ qup_i2c12_default: qup-i2c12-state {
+ pins = "gpio52", "gpio53";
+ function = "qup1_se5";
+ };
+
+ qup_i2c13_default: qup-i2c13-state {
+ pins = "gpio56", "gpio57";
+ function = "qup1_se6";
+ };
+
+ qup_i2c14_default: qup-i2c14-state {
+ pins = "gpio80", "gpio81";
+ function = "qup2_se0";
+ };
+
+ qup_i2c15_default: qup-i2c15-state {
+ pins = "gpio84", "gpio85";
+ function = "qup2_se1";
+ };
+
+ qup_i2c16_default: qup-i2c16-state {
+ pins = "gpio86", "gpio87";
+ function = "qup2_se2";
+ };
+
+ qup_i2c17_default: qup-i2c17-state {
+ pins = "gpio91", "gpio92";
+ function = "qup2_se3";
+ };
+
+ qup_i2c18_default: qup-i2c18-state {
+ pins = "gpio95", "gpio96";
+ function = "qup2_se4";
+ };
+
+ qup_i2c19_default: qup-i2c19-state {
+ pins = "gpio99", "gpio100";
+ function = "qup2_se5";
+ };
+
+ qup_i2c20_default: qup-i2c20-state {
+ pins = "gpio97", "gpio98";
+ function = "qup2_se6";
+ };
+
+ qup_i2c21_default: qup-i2c21-state {
+ pins = "gpio13", "gpio14";
+ function = "qup3_se0";
+ };
+
+ qup_spi0_default: qup-spi0-state {
+ pins = "gpio20", "gpio21", "gpio22", "gpio23";
+ function = "qup0_se0";
+ };
+
+ qup_spi1_default: qup-spi1-state {
+ pins = "gpio24", "gpio25", "gpio26", "gpio27";
+ function = "qup0_se1";
+ };
+
+ qup_spi2_default: qup-spi2-state {
+ pins = "gpio36", "gpio37", "gpio38", "gpio39";
+ function = "qup0_se2";
+ };
+
+ qup_spi3_default: qup-spi3-state {
+ pins = "gpio28", "gpio29", "gpio30", "gpio31";
+ function = "qup0_se3";
+ };
+
+ qup_spi4_default: qup-spi4-state {
+ pins = "gpio32", "gpio33", "gpio34", "gpio35";
+ function = "qup0_se4";
+ };
+
+ qup_spi5_default: qup-spi5-state {
+ pins = "gpio36", "gpio37", "gpio38", "gpio39";
+ function = "qup0_se5";
+ };
+
+ qup_spi7_default: qup-spi7-state {
+ pins = "gpio40", "gpio41", "gpio42", "gpio43";
+ function = "qup1_se0";
+ };
+
+ qup_spi8_default: qup-spi8-state {
+ pins = "gpio42", "gpio43", "gpio40", "gpio41";
+ function = "qup1_se1";
+ };
+
+ qup_spi9_default: qup-spi9-state {
+ pins = "gpio46", "gpio47", "gpio44", "gpio45";
+ function = "qup1_se2";
+ };
+
+ qup_spi10_default: qup-spi10-state {
+ pins = "gpio44", "gpio45", "gpio46", "gpio47";
+ function = "qup1_se3";
+ };
+
+ qup_spi11_default: qup-spi11-state {
+ pins = "gpio48", "gpio49", "gpio50", "gpio51";
+ function = "qup1_se4";
+ };
+
+ qup_spi12_default: qup-spi12-state {
+ pins = "gpio52", "gpio53", "gpio54", "gpio55";
+ function = "qup1_se5";
+ };
+
+ qup_spi14_default: qup-spi14-state {
+ pins = "gpio80", "gpio81", "gpio82", "gpio83";
+ function = "qup2_se0";
+ };
+
+ qup_spi15_default: qup-spi15-state {
+ pins = "gpio84", "gpio85", "gpio99", "gpio100";
+ function = "qup2_se1";
+ };
+
+ qup_spi16_default: qup-spi16-state {
+ pins = "gpio86", "gpio87", "gpio88", "gpio89";
+ function = "qup2_se2";
+ };
+
+ qup_spi17_default: qup-spi17-state {
+ pins = "gpio91", "gpio92", "gpio93", "gpio94";
+ function = "qup2_se3";
+ };
+
+ qup_spi18_default: qup-spi18-state {
+ pins = "gpio95", "gpio96", "gpio97", "gpio98";
+ function = "qup2_se4";
+ };
+
+ qup_spi19_default: qup-spi19-state {
+ pins = "gpio99", "gpio100", "gpio84", "gpio85";
+ function = "qup2_se5";
+ };
+
+ qup_spi20_default: qup-spi20-state {
+ pins = "gpio97", "gpio98", "gpio95", "gpio96";
+ function = "qup2_se6";
+ };
+
+ qup_spi21_default: qup-spi21-state {
+ pins = "gpio13", "gpio14", "gpio15", "gpio16";
+ function = "qup3_se0";
+ };
+
+ qup_uart0_default: qup-uart0-state {
+ qup_uart0_cts: qup-uart0-cts-pins {
+ pins = "gpio20";
+ function = "qup0_se0";
+ };
+
+ qup_uart0_rts: qup-uart0-rts-pins {
+ pins = "gpio21";
+ function = "qup0_se0";
+ };
+
+ qup_uart0_tx: qup-uart0-tx-pins {
+ pins = "gpio22";
+ function = "qup0_se0";
+ };
+
+ qup_uart0_rx: qup-uart0-rx-pins {
+ pins = "gpio23";
+ function = "qup0_se0";
+ };
+ };
+
+ qup_uart1_default: qup-uart1-state {
+ qup_uart1_cts: qup-uart1-cts-pins {
+ pins = "gpio24";
+ function = "qup0_se1";
+ };
+
+ qup_uart1_rts: qup-uart1-rts-pins {
+ pins = "gpio25";
+ function = "qup0_se1";
+ };
+
+ qup_uart1_tx: qup-uart1-tx-pins {
+ pins = "gpio26";
+ function = "qup0_se1";
+ };
+
+ qup_uart1_rx: qup-uart1-rx-pins {
+ pins = "gpio27";
+ function = "qup0_se1";
+ };
+ };
+
+ qup_uart2_default: qup-uart2-state {
+ qup_uart2_cts: qup-uart2-cts-pins {
+ pins = "gpio36";
+ function = "qup0_se2";
+ };
+
+ qup_uart2_rts: qup-uart2-rts-pins {
+ pins = "gpio37";
+ function = "qup0_se2";
+ };
+
+ qup_uart2_tx: qup-uart2-tx-pins {
+ pins = "gpio38";
+ function = "qup0_se2";
+ };
+
+ qup_uart2_rx: qup-uart2-rx-pins {
+ pins = "gpio39";
+ function = "qup0_se2";
+ };
+ };
+
+ qup_uart3_default: qup-uart3-state {
+ qup_uart3_cts: qup-uart3-cts-pins {
+ pins = "gpio28";
+ function = "qup0_se3";
+ };
+
+ qup_uart3_rts: qup-uart3-rts-pins {
+ pins = "gpio29";
+ function = "qup0_se3";
+ };
+
+ qup_uart3_tx: qup-uart3-tx-pins {
+ pins = "gpio30";
+ function = "qup0_se3";
+ };
+
+ qup_uart3_rx: qup-uart3-rx-pins {
+ pins = "gpio31";
+ function = "qup0_se3";
+ };
+ };
+
+ qup_uart4_default: qup-uart4-state {
+ qup_uart4_cts: qup-uart4-cts-pins {
+ pins = "gpio32";
+ function = "qup0_se4";
+ };
+
+ qup_uart4_rts: qup-uart4-rts-pins {
+ pins = "gpio33";
+ function = "qup0_se4";
+ };
+
+ qup_uart4_tx: qup-uart4-tx-pins {
+ pins = "gpio34";
+ function = "qup0_se4";
+ };
+
+ qup_uart4_rx: qup-uart4-rx-pins {
+ pins = "gpio35";
+ function = "qup0_se4";
+ };
+ };
+
+ qup_uart5_default: qup-uart5-state {
+ qup_uart5_cts: qup-uart5-cts-pins {
+ pins = "gpio36";
+ function = "qup0_se5";
+ };
+
+ qup_uart5_rts: qup-uart5-rts-pins {
+ pins = "gpio37";
+ function = "qup0_se5";
+ };
+
+ qup_uart5_tx: qup-uart5-tx-pins {
+ pins = "gpio38";
+ function = "qup0_se5";
+ };
+
+ qup_uart5_rx: qup-uart5-rx-pins {
+ pins = "gpio39";
+ function = "qup0_se5";
+ };
+ };
+
+ qup_uart7_default: qup-uart7-state {
+ qup_uart7_cts: qup-uart7-cts-pins {
+ pins = "gpio40";
+ function = "qup1_se0";
+ };
+
+ qup_uart7_rts: qup-uart7-rts-pins {
+ pins = "gpio41";
+ function = "qup1_se0";
+ };
+
+ qup_uart7_tx: qup-uart7-tx-pins {
+ pins = "gpio42";
+ function = "qup1_se0";
+ };
+
+ qup_uart7_rx: qup-uart7-rx-pins {
+ pins = "gpio43";
+ function = "qup1_se0";
+ };
+ };
+
+ qup_uart8_default: qup-uart8-state {
+ qup_uart8_cts: qup-uart8-cts-pins {
+ pins = "gpio42";
+ function = "qup1_se1";
+ };
+
+ qup_uart8_rts: qup-uart8-rts-pins {
+ pins = "gpio43";
+ function = "qup1_se1";
+ };
+
+ qup_uart8_tx: qup-uart8-tx-pins {
+ pins = "gpio40";
+ function = "qup1_se1";
+ };
+
+ qup_uart8_rx: qup-uart8-rx-pins {
+ pins = "gpio41";
+ function = "qup1_se1";
+ };
+ };
+
+ qup_uart9_default: qup-uart9-state {
+ qup_uart9_cts: qup-uart9-cts-pins {
+ pins = "gpio46";
+ function = "qup1_se2";
+ };
+
+ qup_uart9_rts: qup-uart9-rts-pins {
+ pins = "gpio47";
+ function = "qup1_se2";
+ };
+
+ qup_uart9_tx: qup-uart9-tx-pins {
+ pins = "gpio44";
+ function = "qup1_se2";
+ };
+
+ qup_uart9_rx: qup-uart9-rx-pins {
+ pins = "gpio45";
+ function = "qup1_se2";
+ };
+ };
+
+ qup_uart10_default: qup-uart10-state {
+ pins = "gpio46", "gpio47";
+ function = "qup1_se3";
+ };
+
+ qup_uart11_default: qup-uart11-state {
+ qup_uart11_cts: qup-uart11-cts-pins {
+ pins = "gpio48";
+ function = "qup1_se4";
+ };
+
+ qup_uart11_rts: qup-uart11-rts-pins {
+ pins = "gpio49";
+ function = "qup1_se4";
+ };
+
+ qup_uart11_tx: qup-uart11-tx-pins {
+ pins = "gpio50";
+ function = "qup1_se4";
+ };
+
+ qup_uart11_rx: qup-uart11-rx-pins {
+ pins = "gpio51";
+ function = "qup1_se4";
+ };
+ };
+
+ qup_uart12_default: qup-uart12-state {
+ qup_uart12_cts: qup-uart12-cts-pins {
+ pins = "gpio52";
+ function = "qup1_se5";
+ };
+
+ qup_uart12_rts: qup-uart12-rts-pins {
+ pins = "gpio53";
+ function = "qup1_se5";
+ };
+
+ qup_uart12_tx: qup-uart12-tx-pins {
+ pins = "gpio54";
+ function = "qup1_se5";
+ };
+
+ qup_uart12_rx: qup-uart12-rx-pins {
+ pins = "gpio55";
+ function = "qup1_se5";
+ };
+ };
+
+ qup_uart14_default: qup-uart14-state {
+ qup_uart14_cts: qup-uart14-cts-pins {
+ pins = "gpio80";
+ function = "qup2_se0";
+ };
+
+ qup_uart14_rts: qup-uart14-rts-pins {
+ pins = "gpio81";
+ function = "qup2_se0";
+ };
+
+ qup_uart14_tx: qup-uart14-tx-pins {
+ pins = "gpio82";
+ function = "qup2_se0";
+ };
+
+ qup_uart14_rx: qup-uart14-rx-pins {
+ pins = "gpio83";
+ function = "qup2_se0";
+ };
+ };
+
+ qup_uart15_default: qup-uart15-state {
+ qup_uart15_cts: qup-uart15-cts-pins {
+ pins = "gpio84";
+ function = "qup2_se1";
+ };
+
+ qup_uart15_rts: qup-uart15-rts-pins {
+ pins = "gpio85";
+ function = "qup2_se1";
+ };
+
+ qup_uart15_tx: qup-uart15-tx-pins {
+ pins = "gpio99";
+ function = "qup2_se1";
+ };
+
+ qup_uart15_rx: qup-uart15-rx-pins {
+ pins = "gpio100";
+ function = "qup2_se1";
+ };
+ };
+
+ qup_uart16_default: qup-uart16-state {
+ qup_uart16_cts: qup-uart16-cts-pins {
+ pins = "gpio86";
+ function = "qup2_se2";
+ };
+
+ qup_uart16_rts: qup-uart16-rts-pins {
+ pins = "gpio87";
+ function = "qup2_se2";
+ };
+
+ qup_uart16_tx: qup-uart16-tx-pins {
+ pins = "gpio88";
+ function = "qup2_se2";
+ };
+
+ qup_uart16_rx: qup-uart16-rx-pins {
+ pins = "gpio89";
+ function = "qup2_se2";
+ };
+ };
+
+ qup_uart17_default: qup-uart17-state {
+ qup_uart17_cts: qup-uart17-cts-pins {
+ pins = "gpio91";
+ function = "qup2_se3";
+ };
+
+ qup_uart17_rts: qup0-uart17-rts-pins {
+ pins = "gpio92";
+ function = "qup2_se3";
+ };
+
+ qup_uart17_tx: qup0-uart17-tx-pins {
+ pins = "gpio93";
+ function = "qup2_se3";
+ };
+
+ qup_uart17_rx: qup0-uart17-rx-pins {
+ pins = "gpio94";
+ function = "qup2_se3";
+ };
+ };
+
+ qup_uart18_default: qup-uart18-state {
+ qup_uart18_cts: qup-uart18-cts-pins {
+ pins = "gpio95";
+ function = "qup2_se4";
+ };
+
+ qup_uart18_rts: qup-uart18-rts-pins {
+ pins = "gpio96";
+ function = "qup2_se4";
+ };
+
+ qup_uart18_tx: qup-uart18-tx-pins {
+ pins = "gpio97";
+ function = "qup2_se4";
+ };
+
+ qup_uart18_rx: qup-uart18-rx-pins {
+ pins = "gpio98";
+ function = "qup2_se4";
+ };
+ };
+
+ qup_uart19_default: qup-uart19-state {
+ qup_uart19_cts: qup-uart19-cts-pins {
+ pins = "gpio99";
+ function = "qup2_se5";
+ };
+
+ qup_uart19_rts: qup-uart19-rts-pins {
+ pins = "gpio100";
+ function = "qup2_se5";
+ };
+
+ qup_uart19_tx: qup-uart19-tx-pins {
+ pins = "gpio84";
+ function = "qup2_se5";
+ };
+
+ qup_uart19_rx: qup-uart19-rx-pins {
+ pins = "gpio85";
+ function = "qup2_se5";
+ };
+ };
+
+ qup_uart20_default: qup-uart20-state {
+ qup_uart20_cts: qup-uart20-cts-pins {
+ pins = "gpio97";
+ function = "qup2_se6";
+ };
+
+ qup_uart20_rts: qup-uart20-rts-pins {
+ pins = "gpio98";
+ function = "qup2_se6";
+ };
+
+ qup_uart20_tx: qup-uart20-tx-pins {
+ pins = "gpio95";
+ function = "qup2_se6";
+ };
+
+ qup_uart20_rx: qup-uart20-rx-pins {
+ pins = "gpio96";
+ function = "qup2_se6";
+ };
+ };
+
+ qup_uart21_default: qup-uart21-state {
+ qup_uart21_cts: qup-uart21-cts-pins {
+ pins = "gpio13";
+ function = "qup3_se0";
+ };
+
+ qup_uart21_rts: qup-uart21-rts-pins {
+ pins = "gpio14";
+ function = "qup3_se0";
+ };
+
+ qup_uart21_tx: qup-uart21-tx-pins {
+ pins = "gpio15";
+ function = "qup3_se0";
+ };
+
+ qup_uart21_rx: qup-uart21-rx-pins {
+ pins = "gpio16";
+ function = "qup3_se0";
+ };
+ };
};
sram: sram@146d8000 {
projects / thirdparty / kernel / stable.git / commitdiff
