[arm] PR target/85026: Fix ldrsh length estimate in Thumb state

	Backport from mainline
	2018-03-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	PR target/85026
	* config/arm/arm.md (unaligned_loadhis): Remove first alternative.
	Clean up attributes.

	* g++.dg/pr85026.C: New test.

From-SVN: r258918

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8acb3088d462ab995cec5b97330a53ed6ee65723..6c33f9f143ff55b5dc6768ee8d4a31f5e4ebb6ed 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2018-03-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       Backport from mainline
+       2018-03-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       PR target/85026
+       * config/arm/arm.md (unaligned_loadhis): Remove first alternative.
+       Clean up attributes.
+
 2018-03-28  Segher Boessenkool  <segher@kernel.crashing.org>
 
        Backport from mainline

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 86df1c0366be6c4b9b4ebf76821a8100c4e9fc16..9462ba72c4efb75a0af96ced49c5aeed3e34c292 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -4247,16 +4247,13 @@
    (set_attr "type" "load1")])
 
 (define_insn "unaligned_loadhis"
-  [(set (match_operand:SI 0 "s_register_operand" "=l,r")
+  [(set (match_operand:SI 0 "s_register_operand" "=r")
        (sign_extend:SI
-         (unspec:HI [(match_operand:HI 1 "memory_operand" "Uw,Uh")]
+         (unspec:HI [(match_operand:HI 1 "memory_operand" "Uh")]
                     UNSPEC_UNALIGNED_LOAD)))]
   "unaligned_access"
   "ldrsh%?\t%0, %1\t@ unaligned"
-  [(set_attr "arch" "t2,any")
-   (set_attr "length" "2,4")
-   (set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "yes,no")
+  [(set_attr "predicable" "yes")
    (set_attr "type" "load_byte")])
 
 (define_insn "unaligned_loadhiu"

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 3978f6ddbb08a41c74d9ba73e9738a7a8d66fa5f..a9da15358b837f085b775207a4acc1f599364d00 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2018-03-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       Backport from mainline
+       2018-03-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       PR target/85026
+       * g++.dg/pr85026.C: New test.
+
 2018-03-28  Segher Boessenkool  <segher@kernel.crashing.org>
 
        Backport from mainline

diff --git a/gcc/testsuite/g++.dg/pr85026.C b/gcc/testsuite/g++.dg/pr85026.C
new file mode 100644 (file)
index 0000000..e1e3ccd
--- /dev/null
+++ b/gcc/testsuite/g++.dg/pr85026.C
@@ -0,0 +1,61 @@
+/* PR target/85026.  */
+/* { dg-do assemble } */
+/* { dg-options "-O2 -std=gnu++11" } */
+
+template <class> class a;
+class b;
+struct c {
+  typedef a<b> &g;
+};
+template <typename d> struct e { typedef typename d::f iter; };
+class h {
+public:
+  void __attribute__((noreturn)) i();
+} ab;
+template <class> class a {
+public:
+  typedef b *f;
+  b &operator[](unsigned m) {
+    if (ac)
+      ab.i();
+    return ad[m];
+  }
+  f n() { return ad; }
+  f m_fn3();
+  b *ad;
+  unsigned ac;
+};
+class b {
+public:
+  short j;
+  short k;
+  signed l;
+} __attribute__((__packed__));
+void o(a<b> &m, b &p2, b &p) {
+  p2 = p = m[0];
+  if (bool at = false)
+    ;
+  else
+    for (c::g au(m);; at = true)
+      if (bool av = false)
+        ;
+      else
+        for (e<a<int>>::iter aw = au.n(), ax = au.m_fn3(); ax;
+             av ? (void)0 : (void)0)
+          if (bool ay = 0)
+            ;
+          else
+            for (b az = *aw; !ay; ay = true) {
+              if (p2.j)
+                p2.j = az.j;
+              else if (p.j)
+                p.j = az.j;
+              if (p2.k)
+                p2.k = az.k;
+              else if (az.k > p.k)
+                p.k = az.k;
+              if (az.l < p2.l)
+                if (az.l > p.l)
+                  p.l = az.l;
+            }
+}