net: stmmac: rk: rk3506, rk3528 and rk3588 have rmii_mode in clock register

rk3506, rk3528 and rk3588 have the rmii_mode bit in the clock GRF
register rather than the gmac GRF register. Provide a mask for this
field in the clock register, and convert these SoCs to use this.
Add the necessary code in rk_gmac_powerup() to write this field.

This allows us to get rid of these SoCs set_to_rmii() function. As
such, we need to mark these SoCs as supporting RMII mode.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de> #px30,rk3328,rk3568,rk3588
Link: https://patch.msgid.link/E1vnYyB-00000007hpF-1dwK@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index ed9adac70f0ace0dbb24f16c2dc79954fd37bb25..b0441a368cb130e2984793235caa16f02a6ccdff 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -38,6 +38,7 @@ struct rk_clock_fields {
        u16 gmii_clk_sel_mask;
        u16 rmii_clk_sel_mask;
        u16 rmii_gate_en_mask;
+       u16 rmii_mode_mask;
        u16 mac_speed_mask;
 };
 
@@ -708,21 +709,15 @@ static int rk3506_init(struct rk_priv_data *bsp_priv)
        }
 }
 
-static void rk3506_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
-       unsigned int id = bsp_priv->id, offset;
-
-       offset = (id == 1) ? RK3506_GRF_SOC_CON11 : RK3506_GRF_SOC_CON8;
-       regmap_write(bsp_priv->grf, offset, RK3506_GMAC_RMII_MODE);
-}
-
 static const struct rk_gmac_ops rk3506_ops = {
        .init = rk3506_init,
-       .set_to_rmii = rk3506_set_to_rmii,
 
        .clock.io_clksel_io_mask = BIT_U16(5),
        .clock.rmii_clk_sel_mask = BIT_U16(3),
        .clock.rmii_gate_en_mask = BIT_U16(2),
+       .clock.rmii_mode_mask = BIT_U16(1),
+
+       .supports_rmii = true,
 
        .regs_valid = true,
        .regs = {
@@ -746,10 +741,6 @@ static const struct rk_gmac_ops rk3506_ops = {
 #define RK3528_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(15, 8, val)
 #define RK3528_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(7, 0, val)
 
-#define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1)
-#define RK3528_GMAC1_PHY_INTF_SEL_RGMII        GRF_CLR_BIT(8)
-#define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8)
-
 static int rk3528_init(struct rk_priv_data *bsp_priv)
 {
        switch (bsp_priv->id) {
@@ -757,6 +748,7 @@ static int rk3528_init(struct rk_priv_data *bsp_priv)
                bsp_priv->clock_grf_reg = RK3528_VO_GRF_GMAC_CON;
                bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(3);
                bsp_priv->clock.rmii_gate_en_mask = BIT_U16(2);
+               bsp_priv->clock.rmii_mode_mask = BIT_U16(1);
                bsp_priv->supports_rgmii = false;
                return 0;
 
@@ -766,6 +758,7 @@ static int rk3528_init(struct rk_priv_data *bsp_priv)
                bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(11, 10);
                bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(10);
                bsp_priv->clock.rmii_gate_en_mask = BIT_U16(9);
+               bsp_priv->clock.rmii_mode_mask = BIT_U16(8);
                return 0;
 
        default:
@@ -776,9 +769,6 @@ static int rk3528_init(struct rk_priv_data *bsp_priv)
 static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,
                                int tx_delay, int rx_delay)
 {
-       regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
-                    RK3528_GMAC1_PHY_INTF_SEL_RGMII);
-
        regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
                     DELAY_ENABLE(RK3528, tx_delay, rx_delay));
 
@@ -787,16 +777,6 @@ static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,
                     RK3528_GMAC_CLK_TX_DL_CFG(tx_delay));
 }
 
-static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
-       if (bsp_priv->id == 1)
-               regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
-                            RK3528_GMAC1_PHY_INTF_SEL_RMII);
-       else
-               regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON,
-                            RK3528_GMAC0_PHY_INTF_SEL_RMII);
-}
-
 static void rk3528_integrated_phy_powerup(struct rk_priv_data *bsp_priv)
 {
        rk_gmac_integrated_fephy_powerup(bsp_priv, RK3528_VO_GRF_MACPHY_CON0);
@@ -810,9 +790,11 @@ static void rk3528_integrated_phy_powerdown(struct rk_priv_data *bsp_priv)
 static const struct rk_gmac_ops rk3528_ops = {
        .init = rk3528_init,
        .set_to_rgmii = rk3528_set_to_rgmii,
-       .set_to_rmii = rk3528_set_to_rmii,
        .integrated_phy_powerup = rk3528_integrated_phy_powerup,
        .integrated_phy_powerdown = rk3528_integrated_phy_powerdown,
+
+       .supports_rmii = true,
+
        .regs_valid = true,
        .regs = {
                0xffbd0000, /* gmac0 */
@@ -988,9 +970,6 @@ static const struct rk_gmac_ops rk3576_ops = {
 #define RK3588_GRF_GMAC_CON0                   0X0008
 #define RK3588_GRF_CLK_CON1                    0X0070
 
-#define RK3588_GMAC_CLK_RMII_MODE(id)          GRF_BIT(5 * (id))
-#define RK3588_GMAC_CLK_RGMII_MODE(id)         GRF_CLR_BIT(5 * (id))
-
 static int rk3588_init(struct rk_priv_data *bsp_priv)
 {
        switch (bsp_priv->id) {
@@ -1000,6 +979,7 @@ static int rk3588_init(struct rk_priv_data *bsp_priv)
                bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(3, 2);
                bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(2);
                bsp_priv->clock.rmii_gate_en_mask = BIT_U16(1);
+               bsp_priv->clock.rmii_mode_mask = BIT_U16(0);
                return 0;
 
        case 1:
@@ -1008,6 +988,7 @@ static int rk3588_init(struct rk_priv_data *bsp_priv)
                bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(8, 7);
                bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(7);
                bsp_priv->clock.rmii_gate_en_mask = BIT_U16(6);
+               bsp_priv->clock.rmii_mode_mask = BIT_U16(5);
                return 0;
 
        default:
@@ -1023,9 +1004,6 @@ static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
        offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 :
                                         RK3588_GRF_GMAC_CON8;
 
-       regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
-                    RK3588_GMAC_CLK_RGMII_MODE(id));
-
        regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7,
                     RK3588_GMAC_RXCLK_DLY_ENABLE(id) |
                     RK3588_GMAC_TXCLK_DLY_ENABLE(id));
@@ -1035,16 +1013,9 @@ static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
                     RK3588_GMAC_CLK_TX_DL_CFG(tx_delay));
 }
 
-static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
-       regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
-                    RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id));
-}
-
 static const struct rk_gmac_ops rk3588_ops = {
        .init = rk3588_init,
        .set_to_rgmii = rk3588_set_to_rgmii,
-       .set_to_rmii = rk3588_set_to_rmii,
 
        .gmac_grf_reg_in_php = true,
        .gmac_grf_reg = RK3588_GRF_GMAC_CON0,
@@ -1052,6 +1023,8 @@ static const struct rk_gmac_ops rk3588_ops = {
        .clock_grf_reg_in_php = true,
        .clock_grf_reg = RK3588_GRF_CLK_CON1,
 
+       .supports_rmii = true,
+
        .php_grf_required = true,
        .regs_valid = true,
        .regs = {
@@ -1432,6 +1405,17 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
                }
        }
 
+       if (bsp_priv->clock.rmii_mode_mask) {
+               val = rk_encode_wm16(intf == PHY_INTF_SEL_RMII,
+                                    bsp_priv->clock.rmii_mode_mask);
+
+               ret = rk_write_clock_grf_reg(bsp_priv, val);
+               if (ret < 0) {
+                       gmac_clk_enable(bsp_priv, false);
+                       return ret;
+               }
+       }
+
        /*rmii or rgmii*/
        switch (bsp_priv->phy_iface) {
        case PHY_INTERFACE_MODE_RGMII: