arm64: dts: renesas: r9a09g077: Fix CPG register region sizes

The CPG register regions were incorrectly sized.  Update them to match
the actual hardware specification:
  - First region (0x80280000): 0x1000 -> 0x10000 (64kiB)
  - Second region (0x81280000): 0x9000 -> 0x10000 (64kiB)

Fixes: d17b34744f5e4 ("arm64: dts: renesas: Add initial support for the Renesas RZ/T2H SoC")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260213131742.3606334-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index 14d7fb6f8952e1f571cc72c22eaccbf3332f3478..9d0b4d8d3d5bb1d8910af634ede0557689cb62af 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -974,8 +974,8 @@
 
                cpg: clock-controller@80280000 {
                        compatible = "renesas,r9a09g077-cpg-mssr";
-                       reg = <0 0x80280000 0 0x1000>,
-                             <0 0x81280000 0 0x9000>;
+                       reg = <0 0x80280000 0 0x10000>,
+                             <0 0x81280000 0 0x10000>;
                        clocks = <&extal_clk>;
                        clock-names = "extal";
                        #clock-cells = <2>;