backport: re PR target/64358 (Wrong code for __int128 operations in powerpc64le)

	Backport from mainline
	2014-12-20  Segher Boessenkool  <segher@kernel.crashing.org>

	PR target/64358
	* config/rs6000/rs6000.c (rs6000_split_logical_inner): Swap the
	input operands if only the second is inverted.
	* config/rs6000/rs6000.md (*boolc<mode>3_internal1 for BOOL_128):
	Swap BOOL_REGS_OP1 and BOOL_REGS_OP2.  Correct arguments to
	rs6000_split_logical.
	(*boolc<mode>3_internal2 for TI2): Swap operands[1] and operands[2].

From-SVN: r219548

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 189c068e2cd914e9c41529258061352fdeac7fde..329cc78962ad4992ddda28f3fe37e0ac71371235 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2015-01-13  Pat Haugen  <pthaugen@us.ibm.com>
+
+       Backport from mainline
+       2014-12-20  Segher Boessenkool  <segher@kernel.crashing.org>
+
+       PR target/64358
+       * config/rs6000/rs6000.c (rs6000_split_logical_inner): Swap the
+       input operands if only the second is inverted.
+       * config/rs6000/rs6000.md (*boolc<mode>3_internal1 for BOOL_128):
+       Swap BOOL_REGS_OP1 and BOOL_REGS_OP2.  Correct arguments to
+       rs6000_split_logical.
+       (*boolc<mode>3_internal2 for TI2): Swap operands[1] and operands[2].
+
 2015-01-13  Oleg Endo  <olegendo@gcc.gnu.org>
 
        Backport form mainline

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index bde41bc09395089def5972e8007b3b60511cb5d3..eabdbdfd4140664501765fa1da150a571942d134 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -32628,6 +32628,14 @@ rs6000_split_logical_inner (rtx dest,
   if (complement_op2_p)
     op2 = gen_rtx_NOT (mode, op2);
 
+  /* For canonical RTL, if only one arm is inverted it is the first.  */
+  if (!complement_op1_p && complement_op2_p)
+    {
+      rtx temp = op1;
+      op1 = op2;
+      op2 = temp;
+    }
+
   bool_rtx = ((code == NOT)
              ? gen_rtx_NOT (mode, op1)
              : gen_rtx_fmt_ee (code, mode, op1, op2));

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d31ae4c377f97208956be84d7f9f138332751b81..e8a09601b590eb23c984a44ba3374323a56a47a8 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -8622,8 +8622,8 @@
   [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
        (match_operator:BOOL_128 3 "boolean_operator"
         [(not:BOOL_128
-          (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>"))
-         (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
+          (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))
+         (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")]))]
   "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
 {
   if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
@@ -8638,7 +8638,7 @@
    && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
   [(const_int 0)]
 {
-  rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
+  rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true,
                        NULL_RTX);
   DONE;
 }
@@ -8660,14 +8660,14 @@
   [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
        (match_operator:TI2 3 "boolean_operator"
         [(not:TI2
-          (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
-         (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))]
+          (match_operand:TI2 2 "int_reg_operand" "r,0,r"))
+         (match_operand:TI2 1 "int_reg_operand" "r,r,0")]))]
   "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
   "#"
   "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
   [(const_int 0)]
 {
-  rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
+  rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true,
                        NULL_RTX);
   DONE;
 }