arm64-linux: detect Cavium CPUs (implementer = 0x43) and enable the

fallback LLSC implementation in that case.  Pertains to bug #369459.
(VEX side changes)

git-svn-id: svn://svn.valgrind.org/vex/trunk@3371

diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c
index d4b142daf034010b19ccdb7f11e27ebd00e349e5..7c125cebf3d43dd5001b6206f2308dcf1e69f859 100644 (file)
--- a/VEX/priv/main_main.c
+++ b/VEX/priv/main_main.c
@@ -1468,6 +1468,7 @@ void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai )
    vai->ppc_dcbzl_szB           = 0;
    vai->arm64_dMinLine_lg2_szB  = 0;
    vai->arm64_iMinLine_lg2_szB  = 0;
+   vai->arm64_requires_fallback_LLSC = False;
    vai->hwcache_info.num_levels = 0;
    vai->hwcache_info.num_caches = 0;
    vai->hwcache_info.caches     = NULL;

diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h
index b0ce1da51742bddc27db4a16cbb9ead53dc0f9cb..d75919de48b4fbfe361376e513a2d59eb482a4fc 100644 (file)
--- a/VEX/pub/libvex.h
+++ b/VEX/pub/libvex.h
@@ -323,6 +323,9 @@ typedef
          line size of 64 bytes would be encoded here as 6. */
       UInt arm64_dMinLine_lg2_szB;
       UInt arm64_iMinLine_lg2_szB;
+      /* ARM64: does the host require us to use the fallback LLSC
+         implementation? */
+      Bool arm64_requires_fallback_LLSC;
    }
    VexArchInfo;