drm/amdgpu: Add se cac method to register block

Move se cac access callbacks to register access block.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 469e5aeff61ab3bc736649598af10775fcbcf16d..5bd72261daae119a8c573fb4a812412f05d7370f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -914,10 +914,6 @@ struct amdgpu_device {
        amdgpu_wreg64_t                 pcie_wreg64;
        amdgpu_rreg64_ext_t                     pcie_rreg64_ext;
        amdgpu_wreg64_ext_t pcie_wreg64_ext;
-       /* protects concurrent se_cac register access */
-       spinlock_t se_cac_idx_lock;
-       amdgpu_rreg_t                   se_cac_rreg;
-       amdgpu_wreg_t                   se_cac_wreg;
        /* protects concurrent ENDPOINT (audio) register access */
        spinlock_t audio_endpt_idx_lock;
        amdgpu_block_rreg_t             audio_endpt_rreg;
@@ -1334,8 +1330,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
 #define WREG32_DIDT(reg, v) amdgpu_reg_didt_wr32(adev, (reg), (v))
 #define RREG32_GC_CAC(reg) amdgpu_reg_gc_cac_rd32(adev, (reg))
 #define WREG32_GC_CAC(reg, v) amdgpu_reg_gc_cac_wr32(adev, (reg), (v))
-#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
-#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
+#define RREG32_SE_CAC(reg) amdgpu_reg_se_cac_rd32(adev, (reg))
+#define WREG32_SE_CAC(reg, v) amdgpu_reg_se_cac_wr32(adev, (reg), (v))
 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
 #define WREG32_P(reg, val, mask)                               \

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 0121dc12fd1f0903b54c2b40ec7d6910470c45b9..3872b81cbcb514b9f80e6af2abe847e457797aab 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3889,7 +3889,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 
        spin_lock_init(&adev->mmio_idx_lock);
        spin_lock_init(&adev->pcie_idx_lock);
-       spin_lock_init(&adev->se_cac_idx_lock);
        spin_lock_init(&adev->audio_endpt_idx_lock);
        spin_lock_init(&adev->mm_stats.lock);
        spin_lock_init(&adev->virt.rlcg_reg_lock);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c
index 69db9de507c55eee33f47ccb395906099556bbbd..d75ef23581a05bfec3f4cda977c49e0906f88417 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c
@@ -50,6 +50,10 @@ void amdgpu_reg_access_init(struct amdgpu_device *adev)
        spin_lock_init(&adev->reg.gc_cac.lock);
        adev->reg.gc_cac.rreg = NULL;
        adev->reg.gc_cac.wreg = NULL;
+
+       spin_lock_init(&adev->reg.se_cac.lock);
+       adev->reg.se_cac.rreg = NULL;
+       adev->reg.se_cac.wreg = NULL;
 }
 
 uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg)
@@ -129,6 +133,26 @@ void amdgpu_reg_gc_cac_wr32(struct amdgpu_device *adev, uint32_t reg,
        adev->reg.gc_cac.wreg(adev, reg, v);
 }
 
+uint32_t amdgpu_reg_se_cac_rd32(struct amdgpu_device *adev, uint32_t reg)
+{
+       if (!adev->reg.se_cac.rreg) {
+               dev_err_once(adev->dev, "SE_CAC register read not supported\n");
+               return 0;
+       }
+       return adev->reg.se_cac.rreg(adev, reg);
+}
+
+void amdgpu_reg_se_cac_wr32(struct amdgpu_device *adev, uint32_t reg,
+                           uint32_t v)
+{
+       if (!adev->reg.se_cac.wreg) {
+               dev_err_once(adev->dev,
+                            "SE_CAC register write not supported\n");
+               return;
+       }
+       adev->reg.se_cac.wreg(adev, reg, v);
+}
+
 /*
  * register access helper functions.
  */

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h
index 3736fd5717713711738d9e731a6ff4c2c2b03403..63929999cd76ab887dde908d73c86dc3daf3d6bc 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h
@@ -43,6 +43,7 @@ struct amdgpu_reg_access {
        struct amdgpu_reg_ind uvd_ctx;
        struct amdgpu_reg_ind didt;
        struct amdgpu_reg_ind gc_cac;
+       struct amdgpu_reg_ind se_cac;
 };
 
 void amdgpu_reg_access_init(struct amdgpu_device *adev);
@@ -55,6 +56,9 @@ void amdgpu_reg_didt_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
 uint32_t amdgpu_reg_gc_cac_rd32(struct amdgpu_device *adev, uint32_t reg);
 void amdgpu_reg_gc_cac_wr32(struct amdgpu_device *adev, uint32_t reg,
                            uint32_t v);
+uint32_t amdgpu_reg_se_cac_rd32(struct amdgpu_device *adev, uint32_t reg);
+void amdgpu_reg_se_cac_wr32(struct amdgpu_device *adev, uint32_t reg,
+                           uint32_t v);
 
 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t);
 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t);

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 3099a5e73e9340a31c35ddbe37f6520ca820dcf5..7f2f047bee10f3e3253e4525dd3c647e1d0884a2 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -320,10 +320,10 @@ static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
        unsigned long flags;
        u32 r;
 
-       spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.se_cac.lock, flags);
        WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
        r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
-       spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.se_cac.lock, flags);
        return r;
 }
 
@@ -331,10 +331,10 @@ static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 {
        unsigned long flags;
 
-       spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.se_cac.lock, flags);
        WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
        WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
-       spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.se_cac.lock, flags);
 }
 
 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
@@ -975,8 +975,8 @@ static int soc15_common_early_init(struct amdgpu_ip_block *ip_block)
        adev->reg.didt.wreg = &soc15_didt_wreg;
        adev->reg.gc_cac.rreg = &soc15_gc_cac_rreg;
        adev->reg.gc_cac.wreg = &soc15_gc_cac_wreg;
-       adev->se_cac_rreg = &soc15_se_cac_rreg;
-       adev->se_cac_wreg = &soc15_se_cac_wreg;
+       adev->reg.se_cac.rreg = &soc15_se_cac_rreg;
+       adev->reg.se_cac.wreg = &soc15_se_cac_wreg;
 
        adev->rev_id = amdgpu_device_get_rev_id(adev);
        adev->external_rev_id = 0xFF;