| RS6000_BTC_BINARY), \
CODE_FOR_ ## ICODE) /* ICODE */
+/* Built-ins for ISA 3.1 Altivec instructions. */
+#define BU_P10V_VSX_1(ENUM, NAME, ATTR, ICODE)\
+ RS6000_BUILTIN_1 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
+ "__builtin_vsx_" NAME, /* NAME */ \
+ RS6000_BTM_P10, /* MASK */ \
+ (RS6000_BTC_ ## ATTR /* ATTR */ \
+ | RS6000_BTC_UNARY), \
+ CODE_FOR_ ## ICODE) /* ICODE */
#endif
\f
RS6000_BTC_MISC)
/* POWER10 MMA builtins. */
-BU_VSX_1 (XVCVBF16SPN, "xvcvbf16spn", MISC, vsx_xvcvbf16spn)
-BU_VSX_1 (XVCVSPBF16, "xvcvspbf16", MISC, vsx_xvcvspbf16)
+BU_P10V_VSX_1 (XVCVBF16SPN, "xvcvbf16spn", MISC, vsx_xvcvbf16spn)
+BU_P10V_VSX_1 (XVCVSPBF16, "xvcvspbf16", MISC, vsx_xvcvspbf16)
BU_MMA_1 (XXMFACC, "xxmfacc", QUAD, mma_xxmfacc)
BU_MMA_1 (XXMTACC, "xxmtacc", QUAD, mma_xxmtacc)
case P8V_BUILTIN_VGBBD:
case MISC_BUILTIN_CDTBCD:
case MISC_BUILTIN_CBCDTD:
- case VSX_BUILTIN_XVCVSPBF16:
- case VSX_BUILTIN_XVCVBF16SPN:
+ case P10V_BUILTIN_XVCVSPBF16:
+ case P10V_BUILTIN_XVCVBF16SPN:
h.uns_p[0] = 1;
h.uns_p[1] = 1;
break;