Temporarily restore legacy ppsclock global fdpps for trak, zyfer refclocks

bk: 4d94b5caGq5gE0YZo38ez6cPm_xIUA

diff --git a/ntpd/ntp_refclock.c b/ntpd/ntp_refclock.c
index 72ae82446c245e249de7f0315e811107c742b14b..2e333a59b342bd3c2e3ffa767ed47b5611e50617 100644 (file)
--- a/ntpd/ntp_refclock.c
+++ b/ntpd/ntp_refclock.c
@@ -61,6 +61,9 @@
 #define FUDGEFAC       .1      /* fudge correction factor */
 #define LF             0x0a    /* ASCII LF */
 
+#ifdef PPS     /* fdpps still ref'd by refclock_zyfer.c */
+int    fdpps;                  /* ppsclock legacy */
+#endif /* PPS */
 int    cal_enable;             /* enable refclock calibrate */
 
 /*
@@ -728,7 +731,9 @@ refclock_setup(
 {
        int     i;
        TTY     ttyb, *ttyp;
-
+#ifdef PPS             /* fdpps referenced by refclock_zyfer.c */
+       fdpps = fd;             /* ppsclock legacy */
+#endif /* PPS */
        /*
         * By default, the serial line port is initialized in canonical
         * (line-oriented) mode at specified line speed, 8 bits and no