static const struct svm_direct_access_msrs {
u32 index; /* Index of the MSR */
bool always; /* True if intercept is initially cleared */
-} direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
+} direct_access_msrs[] = {
{ .index = MSR_STAR, .always = true },
{ .index = MSR_IA32_SYSENTER_CS, .always = true },
{ .index = MSR_IA32_SYSENTER_EIP, .always = false },
{ .index = X2APIC_MSR(APIC_TMICT), .always = false },
{ .index = X2APIC_MSR(APIC_TMCCT), .always = false },
{ .index = X2APIC_MSR(APIC_TDCR), .always = false },
- { .index = MSR_INVALID, .always = false },
};
+static_assert(ARRAY_SIZE(direct_access_msrs) ==
+ MAX_DIRECT_ACCESS_MSRS - 6 * !IS_ENABLED(CONFIG_X86_64));
+#undef MAX_DIRECT_ACCESS_MSRS
+
/*
* These 2 parameters are used to config the controls for Pause-Loop Exiting:
* pause_filter_count: On processors that support Pause filtering(indicated
{
u32 i;
- for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
+ for (i = 0; i < ARRAY_SIZE(direct_access_msrs); i++) {
if (direct_access_msrs[i].index == msr)
return i;
+ }
return -ENOENT;
}
{
int i;
- for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
+ for (i = 0; i < ARRAY_SIZE(direct_access_msrs); i++) {
if (!direct_access_msrs[i].always)
continue;
set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
if (!x2avic_enabled)
return;
- for (i = 0; i < MAX_DIRECT_ACCESS_MSRS; i++) {
+ for (i = 0; i < ARRAY_SIZE(direct_access_msrs); i++) {
int index = direct_access_msrs[i].index;
if ((index < APIC_BASE_MSR) ||
* will automatically get filtered through the MSR filter, so we are
* back in sync after this.
*/
- for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
+ for (i = 0; i < ARRAY_SIZE(direct_access_msrs); i++) {
u32 msr = direct_access_msrs[i].index;
u32 read = test_bit(i, svm->shadow_msr_intercept.read);
u32 write = test_bit(i, svm->shadow_msr_intercept.write);
memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
- for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
+ for (i = 0; i < ARRAY_SIZE(direct_access_msrs); i++) {
u32 offset;
offset = svm_msrpm_offset(direct_access_msrs[i].index);