dma: dma-axi-dmac: support bigger than 32bits addresses

In some supported platforms as ARCH_ZYNQMP, part of the memory is mapped
above 32bit addresses and since the DMA mask, by default, is set to 32bits,
we would need to rely on swiotlb (which incurs a performance penalty)
for the DMA mappings. Thus, we can write either the SRC or DEST high
addresses with 1's and read them back. The last bit set on the return
value will reflect the IP address bus width and so we can update the
device DMA mask accordingly.

While at it, support bigger that 32 bits transfers in IP without HW
scatter gather support.

Signed-off-by: Nuno Sá <nuno.sa@analog.com>
base-commit: 398035178503bf662281bbffb4bebce1460a4bc5
change-id: 20251104-axi-dmac-fixes-and-improvs-e3ad512a329c
Acked-by: Michael Hennerich <michael.hennerich@analog.com>
Link: https://patch.msgid.link/20251104-axi-dmac-fixes-and-improvs-v1-3-3e6fd9328f72@analog.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/dma/dma-axi-dmac.c b/drivers/dma/dma-axi-dmac.c
index 0f25f6d8ae71fa73fb24c58b3e2ecfea452cd158..15c569449a28493bd00e9b320ed83aa2a13144e2 100644 (file)
--- a/drivers/dma/dma-axi-dmac.c
+++ b/drivers/dma/dma-axi-dmac.c
@@ -69,7 +69,9 @@
 #define AXI_DMAC_REG_START_TRANSFER    0x408
 #define AXI_DMAC_REG_FLAGS             0x40c
 #define AXI_DMAC_REG_DEST_ADDRESS      0x410
+#define AXI_DMAC_REG_DEST_ADDRESS_HIGH 0x490
 #define AXI_DMAC_REG_SRC_ADDRESS       0x414
+#define AXI_DMAC_REG_SRC_ADDRESS_HIGH  0x494
 #define AXI_DMAC_REG_X_LENGTH          0x418
 #define AXI_DMAC_REG_Y_LENGTH          0x41c
 #define AXI_DMAC_REG_DEST_STRIDE       0x420
@@ -271,11 +273,14 @@ static void axi_dmac_start_transfer(struct axi_dmac_chan *chan)
        if (!chan->hw_sg) {
                if (axi_dmac_dest_is_mem(chan)) {
                        axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, sg->hw->dest_addr);
+                       axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS_HIGH,
+                                      sg->hw->dest_addr >> 32);
                        axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, sg->hw->dst_stride);
                }
 
                if (axi_dmac_src_is_mem(chan)) {
                        axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, sg->hw->src_addr);
+                       axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS_HIGH, sg->hw->src_addr >> 32);
                        axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, sg->hw->src_stride);
                }
        }
@@ -990,6 +995,9 @@ static int axi_dmac_read_chan_config(struct device *dev, struct axi_dmac *dmac)
 static int axi_dmac_detect_caps(struct axi_dmac *dmac, unsigned int version)
 {
        struct axi_dmac_chan *chan = &dmac->chan;
+       struct device *dev = dmac->dma_dev.dev;
+       u32 mask;
+       int ret;
 
        axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, AXI_DMAC_FLAG_CYCLIC);
        if (axi_dmac_read(dmac, AXI_DMAC_REG_FLAGS) == AXI_DMAC_FLAG_CYCLIC)
@@ -1024,6 +1032,22 @@ static int axi_dmac_detect_caps(struct axi_dmac *dmac, unsigned int version)
                return -ENODEV;
        }
 
+       if (axi_dmac_dest_is_mem(chan)) {
+               axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS_HIGH, 0xffffffff);
+               mask = axi_dmac_read(dmac, AXI_DMAC_REG_DEST_ADDRESS_HIGH);
+       } else {
+               axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS_HIGH, 0xffffffff);
+               mask = axi_dmac_read(dmac, AXI_DMAC_REG_SRC_ADDRESS_HIGH);
+       }
+
+       mask = 32 + fls(mask);
+
+       ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(mask));
+       if (ret) {
+               dev_err(dev, "DMA mask set error %d\n", ret);
+               return ret;
+       }
+
        if (version >= ADI_AXI_PCORE_VER(4, 2, 'a'))
                chan->hw_partial_xfer = true;