iommu/amd: Always enable GCR3TRPMode when supported.

The GCR3TRPMode feature allows the DTE[GCR3TRP] field to be configured
with GPA (instead of SPA). This simplifies the implementation, and is
a pre-requisite for nested translation support.

Therefore, always enable this feature if available.

Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>

diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index 14801d734684cd5e7ba7580510252546738b3f51..d8753841cd1f6fa2898e06d7b823629d05b3471a 100644 (file)
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -108,6 +108,7 @@
 
 /* Extended Feature 2 Bits */
 #define FEATURE_SEVSNPIO_SUP   BIT_ULL(1)
+#define FEATURE_GCR3TRPMODE    BIT_ULL(3)
 #define FEATURE_SNPAVICSUP     GENMASK_ULL(7, 5)
 #define FEATURE_SNPAVICSUP_GAM(x) \
        (FIELD_GET(FEATURE_SNPAVICSUP, x) == 0x1)
@@ -186,6 +187,7 @@
 #define CONTROL_EPH_EN         45
 #define CONTROL_XT_EN          50
 #define CONTROL_INTCAPXT_EN    51
+#define CONTROL_GCR3TRPMODE    58
 #define CONTROL_IRTCACHEDIS    59
 #define CONTROL_SNPAVIC_EN     61
 

diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index cfbc9ff105c3608a9667e23b517f36bd9056e091..b1c344ed7dbda2c4f6e48a5d65917ed4cdc67ade 100644 (file)
--- a/drivers/iommu/amd/init.c
+++ b/drivers/iommu/amd/init.c
@@ -1122,6 +1122,14 @@ static void iommu_enable_gt(struct amd_iommu *iommu)
                return;
 
        iommu_feature_enable(iommu, CONTROL_GT_EN);
+
+       /*
+        * This feature needs to be enabled prior to a call
+        * to iommu_snp_enable(). Since this function is called
+        * in early_enable_iommu(), it is safe to enable here.
+        */
+       if (check_feature2(FEATURE_GCR3TRPMODE))
+               iommu_feature_enable(iommu, CONTROL_GCR3TRPMODE);
 }
 
 /* sets a specific bit in the device table entry. */