drm/amdgpu: Move pcie lock to register block

Move pcie register access lock to register access block.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 1e2cacd8caa1ee86ef96c6bbc07a275d0f9128c8..59731014a55a52d9202b1dd690b919e2e1f20806 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -902,8 +902,6 @@ struct amdgpu_device {
        struct amdgpu_mmio_remap        rmmio_remap;
        /* Indirect register access blocks */
        struct amdgpu_reg_access reg;
-       /* protects concurrent PCIE register access */
-       spinlock_t pcie_idx_lock;
        struct amdgpu_doorbell          doorbell;
 
        /* clock/pll info */

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b0dab9b3d08c5fa08fb52a24f054b4e4bda5cb48..6f6973e8cd5374a7c2d66404e109b3465d9da2cf 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3732,7 +3732,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
                return r;
 
        spin_lock_init(&adev->mmio_idx_lock);
-       spin_lock_init(&adev->pcie_idx_lock);
        spin_lock_init(&adev->mm_stats.lock);
        spin_lock_init(&adev->virt.rlcg_reg_lock);
        spin_lock_init(&adev->wb.lock);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c
index 0e2722e3722eac9983ff76e43becc8eecf731184..a996ab1254a1706a699c24ae4b9fcb8864a70741 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c
@@ -59,6 +59,7 @@ void amdgpu_reg_access_init(struct amdgpu_device *adev)
        adev->reg.audio_endpt.rreg = NULL;
        adev->reg.audio_endpt.wreg = NULL;
 
+       spin_lock_init(&adev->reg.pcie.lock);
        adev->reg.pcie.rreg = NULL;
        adev->reg.pcie.wreg = NULL;
        adev->reg.pcie.rreg_ext = NULL;
@@ -526,14 +527,14 @@ u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, u32 reg_addr)
        pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
        pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
        pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
 
        writel(reg_addr, pcie_index_offset);
        readl(pcie_index_offset);
        r = readl(pcie_data_offset);
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
 
        return r;
 }
@@ -565,7 +566,7 @@ u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, u64 reg_addr)
                pcie_index_hi = 0;
        }
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
        pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
        if (pcie_index_hi != 0)
@@ -586,7 +587,7 @@ u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, u64 reg_addr)
                readl(pcie_index_hi_offset);
        }
 
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
 
        return r;
 }
@@ -609,7 +610,7 @@ u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, u32 reg_addr)
        pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
        pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
        pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
 
@@ -621,7 +622,7 @@ u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, u32 reg_addr)
        writel(reg_addr + 4, pcie_index_offset);
        readl(pcie_index_offset);
        r |= ((u64)readl(pcie_data_offset) << 32);
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
 
        return r;
 }
@@ -641,7 +642,7 @@ u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, u64 reg_addr)
                pcie_index_hi =
                        adev->nbio.funcs->get_pcie_index_hi_offset(adev);
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
        pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
        if (pcie_index_hi != 0)
@@ -671,7 +672,7 @@ u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, u64 reg_addr)
                readl(pcie_index_hi_offset);
        }
 
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
 
        return r;
 }
@@ -694,7 +695,7 @@ void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, u32 reg_addr,
        pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
        pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
        pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
 
@@ -702,7 +703,7 @@ void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, u32 reg_addr,
        readl(pcie_index_offset);
        writel(reg_data, pcie_data_offset);
        readl(pcie_data_offset);
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
 }
 
 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, u64 reg_addr,
@@ -721,7 +722,7 @@ void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, u64 reg_addr,
        else
                pcie_index_hi = 0;
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
        pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
        if (pcie_index_hi != 0)
@@ -743,7 +744,7 @@ void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, u64 reg_addr,
                readl(pcie_index_hi_offset);
        }
 
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
 }
 
 /**
@@ -764,7 +765,7 @@ void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, u32 reg_addr,
        pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
        pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
        pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
 
@@ -778,7 +779,7 @@ void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, u32 reg_addr,
        readl(pcie_index_offset);
        writel((u32)(reg_data >> 32), pcie_data_offset);
        readl(pcie_data_offset);
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
 }
 
 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, u64 reg_addr,
@@ -796,7 +797,7 @@ void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, u64 reg_addr,
                pcie_index_hi =
                        adev->nbio.funcs->get_pcie_index_hi_offset(adev);
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
        pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
        if (pcie_index_hi != 0)
@@ -828,7 +829,7 @@ void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, u64 reg_addr,
                readl(pcie_index_hi_offset);
        }
 
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
 }
 
 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, u32 reg)
@@ -839,11 +840,11 @@ u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, u32 reg)
        address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
        data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        WREG32(address, reg * 4);
        (void)RREG32(address);
        r = RREG32(data);
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
        return r;
 }
 
@@ -854,12 +855,12 @@ void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
        address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
        data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        WREG32(address, reg * 4);
        (void)RREG32(address);
        WREG32(data, v);
        (void)RREG32(data);
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
 }
 
 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, uint32_t inst,

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h
index 791b3e50ac9c35447ea4a22995d4e23a3b1e8054..dc0e81cef3b99e770aa057e3113063b54cc659b7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h
@@ -56,6 +56,7 @@ struct amdgpu_reg_ind_blk {
 };
 
 struct amdgpu_reg_pcie_ind {
+       spinlock_t lock;
        amdgpu_rreg_t rreg;
        amdgpu_wreg_t wreg;
        amdgpu_rreg_ext_t rreg_ext;

diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index a4461574f881ea3153b72fea62b7ed1315271367..29954c7d61b06a5c3eeb0a083ba5d4467011df29 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -154,11 +154,11 @@ static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg)
        unsigned long flags;
        u32 r;
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        WREG32(mmPCIE_INDEX, reg);
        (void)RREG32(mmPCIE_INDEX);
        r = RREG32(mmPCIE_DATA);
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
        return r;
 }
 
@@ -166,12 +166,12 @@ static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 {
        unsigned long flags;
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        WREG32(mmPCIE_INDEX, reg);
        (void)RREG32(mmPCIE_INDEX);
        WREG32(mmPCIE_DATA, v);
        (void)RREG32(mmPCIE_DATA);
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
 }
 
 static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg)

diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
index 621aeca5388033b396e8d3381d19da093f8edac6..7e7e6c389895ac454226c5c9b37c8a25d93877d6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
@@ -51,7 +51,7 @@ static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
        address = adev->nbio.funcs->get_pcie_index_offset(adev);
        data = adev->nbio.funcs->get_pcie_data_offset(adev);
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
        WREG32(data, ficaa_val);
 
@@ -61,7 +61,7 @@ static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
        WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);
        ficadh_val = RREG32(data);
 
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
 
        return (((ficadh_val & 0xFFFFFFFFFFFFFFFF) << 32) | ficadl_val);
 }
@@ -74,7 +74,7 @@ static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val,
        address = adev->nbio.funcs->get_pcie_index_offset(adev);
        data = adev->nbio.funcs->get_pcie_data_offset(adev);
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
        WREG32(data, ficaa_val);
 
@@ -84,7 +84,7 @@ static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val,
        WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);
        WREG32(data, ficadh_val);
 
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
 }
 
 /*
@@ -102,12 +102,12 @@ static void df_v3_6_perfmon_rreg(struct amdgpu_device *adev,
        address = adev->nbio.funcs->get_pcie_index_offset(adev);
        data = adev->nbio.funcs->get_pcie_data_offset(adev);
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        WREG32(address, lo_addr);
        *lo_val = RREG32(data);
        WREG32(address, hi_addr);
        *hi_val = RREG32(data);
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
 }
 
 /*
@@ -124,12 +124,12 @@ static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr,
        address = adev->nbio.funcs->get_pcie_index_offset(adev);
        data = adev->nbio.funcs->get_pcie_data_offset(adev);
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        WREG32(address, lo_addr);
        WREG32(data, lo_val);
        WREG32(address, hi_addr);
        WREG32(data, hi_val);
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
 }
 
 /* same as perfmon_wreg but return status on write value check */
@@ -143,7 +143,7 @@ static int df_v3_6_perfmon_arm_with_status(struct amdgpu_device *adev,
        address = adev->nbio.funcs->get_pcie_index_offset(adev);
        data = adev->nbio.funcs->get_pcie_data_offset(adev);
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        WREG32(address, lo_addr);
        WREG32(data, lo_val);
        WREG32(address, hi_addr);
@@ -153,7 +153,7 @@ static int df_v3_6_perfmon_arm_with_status(struct amdgpu_device *adev,
        lo_val_rb = RREG32(data);
        WREG32(address, hi_addr);
        hi_val_rb = RREG32(data);
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
 
        if (!(lo_val == lo_val_rb && hi_val == hi_val_rb))
                return -EBUSY;

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 4aadb7a19a2a39c51b673960b777fe143b08f857..c26cb3e8bff6df8f47496b9da2ec7eb337fd4999 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1027,11 +1027,11 @@ static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg)
        unsigned long flags;
        u32 r;
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        WREG32(AMDGPU_PCIE_INDEX, reg);
        (void)RREG32(AMDGPU_PCIE_INDEX);
        r = RREG32(AMDGPU_PCIE_DATA);
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
        return r;
 }
 
@@ -1039,12 +1039,12 @@ static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 {
        unsigned long flags;
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        WREG32(AMDGPU_PCIE_INDEX, reg);
        (void)RREG32(AMDGPU_PCIE_INDEX);
        WREG32(AMDGPU_PCIE_DATA, v);
        (void)RREG32(AMDGPU_PCIE_DATA);
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
 }
 
 static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
@@ -1052,11 +1052,11 @@ static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
        unsigned long flags;
        u32 r;
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
        (void)RREG32(PCIE_PORT_INDEX);
        r = RREG32(PCIE_PORT_DATA);
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
        return r;
 }
 
@@ -1064,12 +1064,12 @@ static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 {
        unsigned long flags;
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
        (void)RREG32(PCIE_PORT_INDEX);
        WREG32(PCIE_PORT_DATA, (v));
        (void)RREG32(PCIE_PORT_DATA);
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
 }
 
 static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg)
@@ -2380,10 +2380,10 @@ static inline u32 si_pif_phy0_rreg(struct amdgpu_device *adev, u32 reg)
        unsigned long flags;
        u32 r;
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
        r = RREG32(EVERGREEN_PIF_PHY0_DATA);
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
        return r;
 }
 
@@ -2391,10 +2391,10 @@ static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 {
        unsigned long flags;
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
        WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
 }
 
 static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg)
@@ -2402,10 +2402,10 @@ static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg)
        unsigned long flags;
        u32 r;
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
        r = RREG32(EVERGREEN_PIF_PHY1_DATA);
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
        return r;
 }
 
@@ -2413,10 +2413,10 @@ static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 {
        unsigned long flags;
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
        WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
 }
 static void si_program_aspm(struct amdgpu_device *adev)
 {

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 7d1f9a25b109c87cd8e05f21bdfa9ba06d7be8b0..a256320b92f3320f28ad3565a06eb762d347eb55 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -299,11 +299,11 @@ static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
        unsigned long flags;
        u32 r;
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        WREG32_NO_KIQ(mmPCIE_INDEX, reg);
        (void)RREG32_NO_KIQ(mmPCIE_INDEX);
        r = RREG32_NO_KIQ(mmPCIE_DATA);
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
        return r;
 }
 
@@ -311,12 +311,12 @@ static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 {
        unsigned long flags;
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       spin_lock_irqsave(&adev->reg.pcie.lock, flags);
        WREG32_NO_KIQ(mmPCIE_INDEX, reg);
        (void)RREG32_NO_KIQ(mmPCIE_INDEX);
        WREG32_NO_KIQ(mmPCIE_DATA, v);
        (void)RREG32_NO_KIQ(mmPCIE_DATA);
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
 }
 
 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)