sq->phase = ENA_SQE_PHASE;
/* Calculate fill level */
- sq->fill = sq->max;
+ sq->fill = sq->count;
if ( sq->fill > cq->actual )
sq->fill = cq->actual;
ena->acq.phase = ENA_ACQ_PHASE;
ena_cq_init ( &ena->tx.cq, ENA_TX_COUNT,
sizeof ( ena->tx.cq.cqe.tx[0] ) );
- ena_sq_init ( &ena->tx.sq, ENA_SQ_TX, ENA_TX_COUNT, ENA_TX_COUNT,
+ ena_sq_init ( &ena->tx.sq, ENA_SQ_TX, ENA_TX_COUNT,
sizeof ( ena->tx.sq.sqe.tx[0] ), ena->tx_ids );
ena_cq_init ( &ena->rx.cq, ENA_RX_COUNT,
sizeof ( ena->rx.cq.cqe.rx[0] ) );
- ena_sq_init ( &ena->rx.sq, ENA_SQ_RX, ENA_RX_COUNT, ENA_RX_FILL,
+ ena_sq_init ( &ena->rx.sq, ENA_SQ_RX, ENA_RX_COUNT,
sizeof ( ena->rx.sq.sqe.rx[0] ), ena->rx_ids );
/* Fix up PCI device */
#define ENA_TX_COUNT 32
/** Number of receive queue entries */
-#define ENA_RX_COUNT 128
-
-/** Receive queue maximum fill level */
-#define ENA_RX_FILL 32
+#define ENA_RX_COUNT 32
/** Base address low register offset */
#define ENA_BASE_LO 0x0
uint8_t direction;
/** Number of entries */
uint8_t count;
- /** Maximum fill level */
- uint8_t max;
/** Fill level (limited to completion queue size) */
uint8_t fill;
/** Maximum inline header length */
* @v sq Submission queue
* @v direction Direction
* @v count Number of entries
- * @v max Maximum fill level
* @v size Size of each entry
* @v ids Buffer IDs
*/
static inline __attribute__ (( always_inline )) void
ena_sq_init ( struct ena_sq *sq, unsigned int direction, unsigned int count,
- unsigned int max, size_t size, uint8_t *ids ) {
+ size_t size, uint8_t *ids ) {
sq->len = ( count * size );
sq->policy = ( ENA_SQ_HOST_MEMORY | ENA_SQ_CONTIGUOUS );
sq->direction = direction;
sq->count = count;
- sq->max = max;
sq->ids = ids;
}