]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
net: dsa: b53: do not touch DLL_IQQD on bcm53115
authorJonas Gorski <jonas.gorski@gmail.com>
Mon, 2 Jun 2025 19:39:53 +0000 (21:39 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 19 Jun 2025 13:32:19 +0000 (15:32 +0200)
[ Upstream commit bc1a65eb81a21e2aa3c3dca058ee8adf687b6ef5 ]

According to OpenMDK, bit 2 of the RGMII register has a different
meaning for BCM53115 [1]:

"DLL_IQQD         1: In the IDDQ mode, power is down0: Normal function
                  mode"

Configuring RGMII delay works without setting this bit, so let's keep it
at the default. For other chips, we always set it, so not clearing it
is not an issue.

One would assume BCM53118 works the same, but OpenMDK is not quite sure
what this bit actually means [2]:

"BYPASS_IMP_2NS_DEL #1: In the IDDQ mode, power is down#0: Normal
                    function mode1: Bypass dll65_2ns_del IP0: Use
                    dll65_2ns_del IP"

So lets keep setting it for now.

[1] https://github.com/Broadcom-Network-Switching-Software/OpenMDK/blob/master/cdk/PKG/chip/bcm53115/bcm53115_a0_defs.h#L19871
[2] https://github.com/Broadcom-Network-Switching-Software/OpenMDK/blob/master/cdk/PKG/chip/bcm53118/bcm53118_a0_defs.h#L14392

Fixes: 967dd82ffc52 ("net: dsa: b53: Add support for Broadcom RoboSwitch")
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Link: https://patch.msgid.link/20250602193953.1010487-6-jonas.gorski@gmail.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/net/dsa/b53/b53_common.c

index a17a3083180b0afe37ff1f15c4fa749a8ad67883..79039c0941c20cb1ca82eac2ae1d13913060a29e 100644 (file)
@@ -1356,8 +1356,7 @@ static void b53_adjust_531x5_rgmii(struct dsa_switch *ds, int port,
         * tx_clk aligned timing (restoring to reset defaults)
         */
        b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
-       rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
-                       RGMII_CTRL_TIMING_SEL);
+       rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC);
 
        /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
         * sure that we enable the port TX clock internal delay to
@@ -1377,7 +1376,10 @@ static void b53_adjust_531x5_rgmii(struct dsa_switch *ds, int port,
                rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
        if (interface == PHY_INTERFACE_MODE_RGMII)
                rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
-       rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
+
+       if (dev->chip_id != BCM53115_DEVICE_ID)
+               rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
+
        b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
 
        dev_info(ds->dev, "Configured port %d for %s\n", port,