drm/amd/display: Don't share clk source between DP and HDMI

commit 3e27e10e2ecee0d3a0083f8ae76354ac9c6ad15c upstream.

[why]
Prevent clock source sharing between HDMI and DP connectors.
DP shouldn't be sharing its ref clock with phy clock,
which caused an issue of older ASICS booting up with multiple
diplays plugged in.

[how]
Add an extra check that would prevent HDMI and DP sharing clk.

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 751f3ac9d92146c4bfd368d67e487efde7541d46..199399f150103df8c144f358dc40c20d459b1c34 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -330,6 +330,9 @@ bool resource_are_streams_timing_synchronizable(
                                != stream2->timing.pix_clk_khz)
                return false;
 
+       if (stream1->clamping.c_depth != stream2->clamping.c_depth)
+               return false;
+
        if (stream1->phy_pix_clk != stream2->phy_pix_clk
                        && (!dc_is_dp_signal(stream1->signal)
                        || !dc_is_dp_signal(stream2->signal)))
@@ -337,6 +340,20 @@ bool resource_are_streams_timing_synchronizable(
 
        return true;
 }
+static bool is_dp_and_hdmi_sharable(
+               struct dc_stream_state *stream1,
+               struct dc_stream_state *stream2)
+{
+       if (stream1->ctx->dc->caps.disable_dp_clk_share)
+               return false;
+
+       if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
+           stream2->clamping.c_depth != COLOR_DEPTH_888)
+       return false;
+
+       return true;
+
+}
 
 static bool is_sharable_clk_src(
        const struct pipe_ctx *pipe_with_clk_src,
@@ -348,7 +365,10 @@ static bool is_sharable_clk_src(
        if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
                return false;
 
-       if (dc_is_dp_signal(pipe_with_clk_src->stream->signal))
+       if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
+               (dc_is_dp_signal(pipe->stream->signal) &&
+               !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
+                                    pipe->stream)))
                return false;
 
        if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 53c71296f3dd2c3d6eb70bd068ac760e423f4322..efe155d5066839a2f0a542e38e8c071b9921db61 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -77,6 +77,7 @@ struct dc_caps {
        bool dual_link_dvi;
        bool post_blend_color_processing;
        bool force_dp_tps4_for_cp2520;
+       bool disable_dp_clk_share;
 };
 
 struct dc_dcc_surface_param {

diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 344dd2e69e7ceb5177aa2d0762d63862531af31f..aa2f03eb46feec7e8022d49d64b1b0de8a7f48d8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -884,7 +884,7 @@ static bool construct(
        dc->caps.i2c_speed_in_khz = 40;
        dc->caps.max_cursor_size = 128;
        dc->caps.dual_link_dvi = true;
-
+       dc->caps.disable_dp_clk_share = true;
        for (i = 0; i < pool->base.pipe_count; i++) {
                pool->base.timing_generators[i] =
                        dce100_timing_generator_create(

diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 48a0689647225720a9d3f136201a33bd9a5cb2a1..6f4992bdc9ce373dda7a054e183e2deffa673ca2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -902,6 +902,7 @@ static bool dce80_construct(
        }
 
        dc->caps.max_planes =  pool->base.pipe_count;
+       dc->caps.disable_dp_clk_share = true;
 
        if (!resource_construct(num_virtual_links, dc, &pool->base,
                        &res_create_funcs))
@@ -1087,6 +1088,7 @@ static bool dce81_construct(
        }
 
        dc->caps.max_planes =  pool->base.pipe_count;
+       dc->caps.disable_dp_clk_share = true;
 
        if (!resource_construct(num_virtual_links, dc, &pool->base,
                        &res_create_funcs))
@@ -1268,6 +1270,7 @@ static bool dce83_construct(
        }
 
        dc->caps.max_planes =  pool->base.pipe_count;
+       dc->caps.disable_dp_clk_share = true;
 
        if (!resource_construct(num_virtual_links, dc, &pool->base,
                        &res_create_funcs))