re PR target/18932 (ICE in copyprop_hardreg_forward_1, at regrename.c)

        PR target/18932
        * config/i386/i386.md (all splits and peepholes): Use flags_reg_operand
        and compare_operator to propagate the input CC mode to the output.
        * config/i386/i386.c (flags_reg_operand, compare_operator): New.
        * config/i386/i386.h (PREDICATE_CODES): Add them.
        * config/i386/i386-protos.h: Update.

From-SVN: r92060

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 05f9b6cbce5cdaec758542c71dd21b4bd990f2b5..915137d8144c221e62c9771d7c04fa4a3c501965 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2004-12-12  Richard Henderson  <rth@redhat.com>
+
+        PR target/18932
+        * config/i386/i386.md (all splits and peepholes): Use flags_reg_operand
+        and compare_operator to propagate the input CC mode to the output.
+        * config/i386/i386.c (flags_reg_operand, compare_operator): New.
+        * config/i386/i386.h (PREDICATE_CODES): Add them.
+        * config/i386/i386-protos.h: Update.
+
 2004-12-10  Volker Reichelt  <reichelt@igpm.rwth-aachen.de>
 
        PR rtl-optimization/16536

diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h
index b5ddb37bb2a510e9ea3324d9514191995750632a..53b56016956af2a37341e9e30873814fba16ed3e 100644 (file)
--- a/gcc/config/i386/i386-protos.h
+++ b/gcc/config/i386/i386-protos.h
@@ -88,6 +88,8 @@ extern int memory_displacement_operand PARAMS ((rtx, enum machine_mode));
 extern int cmpsi_operand PARAMS ((rtx, enum machine_mode));
 extern int long_memory_operand PARAMS ((rtx, enum machine_mode));
 extern int aligned_operand PARAMS ((rtx, enum machine_mode));
+extern int compare_operator PARAMS ((rtx, enum machine_mode));
+extern int flags_reg_operand PARAMS ((rtx, enum machine_mode));
 extern enum machine_mode ix86_cc_mode PARAMS ((enum rtx_code, rtx, rtx));
 
 extern int ix86_expand_movstr PARAMS ((rtx, rtx, rtx, rtx));

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 74e86a3c21d5fc6b5158ef695531dedba993c654..1f93ce68f594ada87c575a99c98bdb643ff6d20e 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -3609,6 +3609,20 @@ q_regs_operand (op, mode)
   return ANY_QI_REG_P (op);
 }
 
+/* Return true if op is an flags register.  */
+
+int
+flags_reg_operand (op, mode)
+     register rtx op;
+     enum machine_mode mode;
+{
+  if (mode != VOIDmode && GET_MODE (op) != mode)
+    return 0;
+  return (GET_CODE (op) == REG
+         && REGNO (op) == FLAGS_REG
+         && GET_MODE (op) != VOIDmode);
+}
+
 /* Return true if op is a NON_Q_REGS class register.  */
 
 int
@@ -3969,6 +3983,14 @@ aligned_operand (op, mode)
   /* Didn't find one -- this must be an aligned address.  */
   return 1;
 }
+
+int
+compare_operator (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return GET_CODE (op) == COMPARE;
+}
 \f
 /* Return true if the constant is something that can be loaded with
    a special instruction.  Only handle 0.0 and 1.0; others are less

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 796b48bf347b8eba2b91a6b43109dde1a28c756e..3806a0807799ce23095db7f7464b8f49df5e6f85 100644 (file)
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -3319,6 +3319,7 @@ do {                                              \
                        SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}},      \
   {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}},             \
   {"index_register_operand", {SUBREG, REG}},                           \
+  {"flags_reg_operand", {REG}},                                                \
   {"q_regs_operand", {SUBREG, REG}},                                   \
   {"non_q_regs_operand", {SUBREG, REG}},                               \
   {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
@@ -3354,6 +3355,7 @@ do {                                              \
   {"fp_register_operand", {REG}},                                      \
   {"register_and_not_fp_reg_operand", {REG}},                          \
   {"vector_move_operand", {CONST_VECTOR, SUBREG, REG, MEM}},           \
+  {"compare_operator", {COMPARE}},
 
 /* A list of predicates that do special things with modes, and so
    should not elicit warnings for VOIDmode match_operand.  */

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 69c3325cf73927544115d5caeba1c83a3f03e619..ceb0a5c8e9726479f80b72e3908e025c478ade2e 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -7713,51 +7713,53 @@
   "#")
 
 (define_split
-  [(set (reg 17)
-        (compare (zero_extract
-                  (match_operand 0 "nonimmediate_operand" "")
-                  (match_operand 1 "const_int_operand" "")
-                  (match_operand 2 "const_int_operand" ""))
-                (const_int 0)))]
+  [(set (match_operand 0 "flags_reg_operand" "")
+        (match_operator 1 "compare_operator"
+         [(zero_extract
+            (match_operand 2 "nonimmediate_operand" "")
+            (match_operand 3 "const_int_operand" "")
+            (match_operand 4 "const_int_operand" ""))
+          (const_int 0)]))]
   "ix86_match_ccmode (insn, CCNOmode)"
-  [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
+  [(set (match_dup 0) (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
 {
-  HOST_WIDE_INT len = INTVAL (operands[1]);
-  HOST_WIDE_INT pos = INTVAL (operands[2]);
+  rtx val = operands[2];
+  HOST_WIDE_INT len = INTVAL (operands[3]);
+  HOST_WIDE_INT pos = INTVAL (operands[4]);
   HOST_WIDE_INT mask;
   enum machine_mode mode, submode;
 
-  mode = GET_MODE (operands[0]);
-  if (GET_CODE (operands[0]) == MEM)
+  mode = GET_MODE (val);
+  if (GET_CODE (val) == MEM)
     {
       /* ??? Combine likes to put non-volatile mem extractions in QImode
         no matter the size of the test.  So find a mode that works.  */
-      if (! MEM_VOLATILE_P (operands[0]))
+      if (! MEM_VOLATILE_P (val))
        {
          mode = smallest_mode_for_size (pos + len, MODE_INT);
-         operands[0] = adjust_address (operands[0], mode, 0);
+         val = adjust_address (val, mode, 0);
        }
     }
-  else if (GET_CODE (operands[0]) == SUBREG
-          && (submode = GET_MODE (SUBREG_REG (operands[0])),
+  else if (GET_CODE (val) == SUBREG
+          && (submode = GET_MODE (SUBREG_REG (val)),
               GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
           && pos + len <= GET_MODE_BITSIZE (submode))
     {
       /* Narrow a paradoxical subreg to prevent partial register stalls.  */
       mode = submode;
-      operands[0] = SUBREG_REG (operands[0]);
+      val = SUBREG_REG (val);
     }
   else if (mode == HImode && pos + len <= 8)
     {
       /* Small HImode tests can be converted to QImode.  */
       mode = QImode;
-      operands[0] = gen_lowpart (QImode, operands[0]);
+      val = gen_lowpart (QImode, val);
     }
 
   mask  = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
   mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
 
-  operands[3] = gen_rtx_AND (mode, operands[0], gen_int_mode (mask, mode));
+  operands[2] = gen_rtx_AND (mode, val, gen_int_mode (mask, mode));
 })
 
 ;; Convert HImode/SImode test instructions with immediate to QImode ones.
@@ -7766,46 +7768,44 @@
 ;; Do the converison only post-reload to avoid limiting of the register class
 ;; to QI regs.
 (define_split
-  [(set (reg 17)
-       (compare
-         (and (match_operand 0 "register_operand" "")
-              (match_operand 1 "const_int_operand" ""))
-         (const_int 0)))]
+  [(set (match_operand 0 "flags_reg_operand" "")
+       (match_operator 1 "compare_operator"
+         [(and (match_operand 2 "register_operand" "")
+               (match_operand 3 "const_int_operand" ""))
+          (const_int 0)]))]
    "reload_completed
-    && QI_REG_P (operands[0])
+    && QI_REG_P (operands[2])
+    && GET_MODE (operands[2]) != QImode
     && ((ix86_match_ccmode (insn, CCZmode)
-        && !(INTVAL (operands[1]) & ~(255 << 8)))
+        && !(INTVAL (operands[3]) & ~(255 << 8)))
        || (ix86_match_ccmode (insn, CCNOmode)
-           && !(INTVAL (operands[1]) & ~(127 << 8))))
-    && GET_MODE (operands[0]) != QImode"
-  [(set (reg:CCNO 17)
-       (compare:CCNO
-         (and:SI (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
-                 (match_dup 1))
-         (const_int 0)))]
-  "operands[0] = gen_lowpart (SImode, operands[0]);
-   operands[1] = gen_int_mode (INTVAL (operands[1]) >> 8, SImode);")
+           && !(INTVAL (operands[3]) & ~(127 << 8))))"
+  [(set (match_dup 0)
+       (match_op_dup 1
+         [(and:SI (zero_extract:SI (match_dup 2) (const_int 8) (const_int 8))
+                  (match_dup 3))
+          (const_int 0)]))]
+  "operands[2] = gen_lowpart (SImode, operands[2]);
+   operands[3] = gen_int_mode (INTVAL (operands[3]) >> 8, SImode);")
 
 (define_split
-  [(set (reg 17)
-       (compare
-         (and (match_operand 0 "nonimmediate_operand" "")
-              (match_operand 1 "const_int_operand" ""))
-         (const_int 0)))]
+  [(set (match_operand 0 "flags_reg_operand" "")
+       (match_operator 1 "compare_operator"
+         [(and (match_operand 2 "nonimmediate_operand" "")
+               (match_operand 3 "const_int_operand" ""))
+          (const_int 0)]))]
    "reload_completed
-    && (!REG_P (operands[0]) || ANY_QI_REG_P (operands[0]))
+    && GET_MODE (operands[2]) != QImode
+    && (!REG_P (operands[2]) || ANY_QI_REG_P (operands[2]))
     && ((ix86_match_ccmode (insn, CCZmode)
-        && !(INTVAL (operands[1]) & ~255))
+        && !(INTVAL (operands[3]) & ~255))
        || (ix86_match_ccmode (insn, CCNOmode)
-           && !(INTVAL (operands[1]) & ~127)))
-    && GET_MODE (operands[0]) != QImode"
-  [(set (reg:CCNO 17)
-       (compare:CCNO
-         (and:QI (match_dup 0)
-                 (match_dup 1))
-         (const_int 0)))]
-  "operands[0] = gen_lowpart (QImode, operands[0]);
-   operands[1] = gen_lowpart (QImode, operands[1]);")
+           && !(INTVAL (operands[3]) & ~127)))"
+  [(set (match_dup 0)
+       (match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3))
+                        (const_int 0)]))]
+  "operands[2] = gen_lowpart (QImode, operands[2]);
+   operands[3] = gen_lowpart (QImode, operands[3]);")
 
 
 ;; %%% This used to optimize known byte-wide and operations to memory,
@@ -10178,17 +10178,19 @@
    (set_attr "mode" "DI")])
 
 (define_split
-  [(set (reg 17)
-       (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" ""))
-                (const_int 0)))
-   (set (match_operand:DI 0 "nonimmediate_operand" "")
-       (not:DI (match_dup 1)))]
+  [(set (match_operand 0 "flags_reg_operand" "")
+       (match_operator 2 "compare_operator"
+         [(not:DI (match_operand:DI 3 "nonimmediate_operand" ""))
+          (const_int 0)]))
+   (set (match_operand:DI 1 "nonimmediate_operand" "")
+       (not:DI (match_dup 3)))]
   "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
-  [(parallel [(set (reg:CCNO 17)
-                  (compare:CCNO (xor:DI (match_dup 1) (const_int -1))
-                                (const_int 0)))
-             (set (match_dup 0)
-                  (xor:DI (match_dup 1) (const_int -1)))])]
+  [(parallel [(set (match_dup 0)
+                  (match_op_dup 2
+                    [(xor:DI (match_dup 3) (const_int -1))
+                     (const_int 0)]))
+             (set (match_dup 1)
+                  (xor:DI (match_dup 3) (const_int -1)))])]
   "")
 
 (define_expand "one_cmplsi2"
@@ -10227,17 +10229,18 @@
    (set_attr "mode" "SI")])
 
 (define_split
-  [(set (reg 17)
-       (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
-                (const_int 0)))
-   (set (match_operand:SI 0 "nonimmediate_operand" "")
-       (not:SI (match_dup 1)))]
+  [(set (match_operand 0 "flags_reg_operand" "")
+       (match_operator 2 "compare_operator"
+         [(not:SI (match_operand:SI 3 "nonimmediate_operand" ""))
+          (const_int 0)]))
+   (set (match_operand:SI 1 "nonimmediate_operand" "")
+       (not:SI (match_dup 3)))]
   "ix86_match_ccmode (insn, CCNOmode)"
-  [(parallel [(set (reg:CCNO 17)
-                  (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
-                                (const_int 0)))
-             (set (match_dup 0)
-                  (xor:SI (match_dup 1) (const_int -1)))])]
+  [(parallel [(set (match_dup 0)
+                  (match_op_dup 2 [(xor:SI (match_dup 3) (const_int -1))
+                                   (const_int 0)]))
+             (set (match_dup 1)
+                  (xor:SI (match_dup 3) (const_int -1)))])]
   "")
 
 ;; ??? Currently never generated - xor is used instead.
@@ -10254,17 +10257,18 @@
    (set_attr "mode" "SI")])
 
 (define_split
-  [(set (reg 17)
-       (compare (not:SI (match_operand:SI 1 "register_operand" ""))
-                (const_int 0)))
-   (set (match_operand:DI 0 "register_operand" "")
-       (zero_extend:DI (not:SI (match_dup 1))))]
+  [(set (match_operand 0 "flags_reg_operand" "")
+       (match_operator 2 "compare_operator"
+         [(not:SI (match_operand:SI 3 "register_operand" ""))
+          (const_int 0)]))
+   (set (match_operand:DI 1 "register_operand" "")
+       (zero_extend:DI (not:SI (match_dup 3))))]
   "ix86_match_ccmode (insn, CCNOmode)"
-  [(parallel [(set (reg:CCNO 17)
-                  (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
-                                (const_int 0)))
-             (set (match_dup 0)
-                  (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])]
+  [(parallel [(set (match_dup 0)
+                  (match_op_dup 2 [(xor:SI (match_dup 3) (const_int -1))
+                                   (const_int 0)]))
+             (set (match_dup 1)
+                  (zero_extend:DI (xor:SI (match_dup 3) (const_int -1))))])]
   "")
 
 (define_expand "one_cmplhi2"
@@ -10294,17 +10298,18 @@
    (set_attr "mode" "HI")])
 
 (define_split
-  [(set (reg 17)
-       (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
-                (const_int 0)))
-   (set (match_operand:HI 0 "nonimmediate_operand" "")
-       (not:HI (match_dup 1)))]
+  [(set (match_operand 0 "flags_reg_operand" "")
+       (match_operator 2 "compare_operator"
+         [(not:HI (match_operand:HI 3 "nonimmediate_operand" ""))
+          (const_int 0)]))
+   (set (match_operand:HI 1 "nonimmediate_operand" "")
+       (not:HI (match_dup 3)))]
   "ix86_match_ccmode (insn, CCNOmode)"
-  [(parallel [(set (reg:CCNO 17)
-                  (compare:CCNO (xor:HI (match_dup 1) (const_int -1))
-                                (const_int 0)))
-             (set (match_dup 0)
-                  (xor:HI (match_dup 1) (const_int -1)))])]
+  [(parallel [(set (match_dup 0)
+                  (match_op_dup 2 [(xor:HI (match_dup 3) (const_int -1))
+                                   (const_int 0)]))
+             (set (match_dup 1)
+                  (xor:HI (match_dup 3) (const_int -1)))])]
   "")
 
 ;; %%% Potential partial reg stall on alternative 1.  What to do?
@@ -10337,17 +10342,18 @@
    (set_attr "mode" "QI")])
 
 (define_split
-  [(set (reg 17)
-       (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
-                (const_int 0)))
-   (set (match_operand:QI 0 "nonimmediate_operand" "")
-       (not:QI (match_dup 1)))]
+  [(set (match_operand 0 "flags_reg_operand" "")
+       (match_operator 2 "compare_operator"
+         [(not:QI (match_operand:QI 3 "nonimmediate_operand" ""))
+          (const_int 0)]))
+   (set (match_operand:QI 1 "nonimmediate_operand" "")
+       (not:QI (match_dup 3)))]
   "ix86_match_ccmode (insn, CCNOmode)"
-  [(parallel [(set (reg:CCNO 17)
-                  (compare:CCNO (xor:QI (match_dup 1) (const_int -1))
-                                (const_int 0)))
-             (set (match_dup 0)
-                  (xor:QI (match_dup 1) (const_int -1)))])]
+  [(parallel [(set (match_dup 0)
+                  (match_op_dup 2 [(xor:QI (match_dup 3) (const_int -1))
+                                   (const_int 0)]))
+             (set (match_dup 1)
+                  (xor:QI (match_dup 3) (const_int -1)))])]
   "")
 \f
 ;; Arithmetic shift instructions
@@ -16894,52 +16900,56 @@
 ; instruction size is unchanged, except in the %eax case for
 ; which it is increased by one byte, hence the ! optimize_size.
 (define_split
-  [(set (reg 17)
-       (compare (and (match_operand 1 "aligned_operand" "")
-                     (match_operand 2 "const_int_operand" ""))
-                (const_int 0)))
-   (set (match_operand 0 "register_operand" "")
-       (and (match_dup 1) (match_dup 2)))]
+  [(set (match_operand 0 "flags_reg_operand" "")
+       (match_operator 2 "compare_operator"
+         [(and (match_operand 3 "aligned_operand" "")
+               (match_operand 4 "const_int_operand" ""))
+          (const_int 0)]))
+   (set (match_operand 1 "register_operand" "")
+       (and (match_dup 3) (match_dup 4)))]
   "! TARGET_PARTIAL_REG_STALL && reload_completed
    /* Ensure that the operand will remain sign-extended immediate.  */
-   && ix86_match_ccmode (insn, INTVAL (operands[2]) >= 0 ? CCNOmode : CCZmode)
+   && ix86_match_ccmode (insn, INTVAL (operands[4]) >= 0 ? CCNOmode : CCZmode)
    && ! optimize_size
-   && ((GET_MODE (operands[0]) == HImode && ! TARGET_FAST_PREFIX)
-       || (GET_MODE (operands[0]) == QImode && TARGET_PROMOTE_QImode))"
-  [(parallel [(set (reg:CCNO 17)
-                  (compare:CCNO (and:SI (match_dup 1) (match_dup 2))
-                                (const_int 0)))
-             (set (match_dup 0)
-                  (and:SI (match_dup 1) (match_dup 2)))])]
-  "operands[2]
-     = gen_int_mode (INTVAL (operands[2])
-                    & GET_MODE_MASK (GET_MODE (operands[0])),
-                    SImode);
-   operands[0] = gen_lowpart (SImode, operands[0]);
-   operands[1] = gen_lowpart (SImode, operands[1]);")
+   && ((GET_MODE (operands[1]) == HImode && ! TARGET_FAST_PREFIX)
+       || (GET_MODE (operands[1]) == QImode && TARGET_PROMOTE_QImode))"
+  [(parallel [(set (match_dup 0)
+                  (match_op_dup 2 [(and:SI (match_dup 3) (match_dup 4))
+                                   (const_int 0)]))
+             (set (match_dup 1)
+                  (and:SI (match_dup 3) (match_dup 4)))])]
+{
+  operands[4]
+    = gen_int_mode (INTVAL (operands[4])
+                   & GET_MODE_MASK (GET_MODE (operands[1])), SImode);
+  operands[1] = gen_lowpart (SImode, operands[1]);
+  operands[3] = gen_lowpart (SImode, operands[3]);
+})
 
 ; Don't promote the QImode tests, as i386 doesn't have encoding of
 ; the TEST instruction with 32-bit sign-extended immediate and thus
 ; the instruction size would at least double, which is not what we
 ; want even with ! optimize_size.
 (define_split
-  [(set (reg 17)
-       (compare (and (match_operand:HI 0 "aligned_operand" "")
-                     (match_operand:HI 1 "const_int_operand" ""))
-                (const_int 0)))]
+  [(set (match_operand 0 "flags_reg_operand" "")
+       (match_operator 1 "compare_operator"
+         [(and (match_operand:HI 2 "aligned_operand" "")
+               (match_operand:HI 3 "const_int_operand" ""))
+          (const_int 0)]))]
   "! TARGET_PARTIAL_REG_STALL && reload_completed
    /* Ensure that the operand will remain sign-extended immediate.  */
-   && ix86_match_ccmode (insn, INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode)
+   && ix86_match_ccmode (insn, INTVAL (operands[3]) >= 0 ? CCNOmode : CCZmode)
    && ! TARGET_FAST_PREFIX
    && ! optimize_size"
-  [(set (reg:CCNO 17)
-       (compare:CCNO (and:SI (match_dup 0) (match_dup 1))
-                     (const_int 0)))]
-  "operands[1]
-     = gen_int_mode (INTVAL (operands[1])
-                    & GET_MODE_MASK (GET_MODE (operands[0])),
-                    SImode);
-   operands[0] = gen_lowpart (SImode, operands[0]);")
+  [(set (match_dup 0)
+       (match_op_dup 1 [(and:SI (match_dup 2) (match_dup 3))
+                        (const_int 0)]))]
+{
+  operands[3]
+    = gen_int_mode (INTVAL (operands[3])
+                   & GET_MODE_MASK (GET_MODE (operands[2])), SImode);
+  operands[2] = gen_lowpart (SImode, operands[2]);
+})
 
 (define_split
   [(set (match_operand 0 "register_operand" "")
@@ -17112,13 +17122,14 @@
 
 ;; Don't compare memory with zero, load and use a test instead.
 (define_peephole2
-  [(set (reg 17)
-       (compare (match_operand:SI 0 "memory_operand" "")
-                (const_int 0)))
+  [(set (match_operand 0 "flags_reg_operand" "")
+       (match_operator 1 "compare_operator"
+         [(match_operand:SI 2 "memory_operand" "")
+          (const_int 0)]))
    (match_scratch:SI 3 "r")]
   "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
-  [(set (match_dup 3) (match_dup 0))
-   (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
+  [(set (match_dup 3) (match_dup 2))
+   (set (match_dup 0) (match_op_dup 1 [(match_dup 3) (const_int 0)]))]
   "")
 
 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer. 
@@ -17182,77 +17193,77 @@
 ;; versions if we're concerned about partial register stalls.
 
 (define_peephole2
-  [(set (reg 17)
-       (compare (and:SI (match_operand:SI 0 "register_operand" "")
-                        (match_operand:SI 1 "immediate_operand" ""))
-                (const_int 0)))]
+  [(set (match_operand 0 "flags_reg_operand" "")
+       (match_operator 1 "compare_operator"
+         [(and:SI (match_operand:SI 2 "register_operand" "")
+                  (match_operand:SI 3 "immediate_operand" ""))
+          (const_int 0)]))]
   "ix86_match_ccmode (insn, CCNOmode)
-   && (true_regnum (operands[0]) != 0
-       || (GET_CODE (operands[1]) == CONST_INT
-          && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')))
-   && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
+   && (true_regnum (operands[2]) != 0
+       || (GET_CODE (operands[3]) == CONST_INT
+          && CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'K')))
+   && peep2_reg_dead_p (1, operands[2])"
   [(parallel
-     [(set (reg:CCNO 17)
-          (compare:CCNO (and:SI (match_dup 0)
-                                (match_dup 1))
-                        (const_int 0)))
-      (set (match_dup 0)
-          (and:SI (match_dup 0) (match_dup 1)))])]
+     [(set (match_dup 0)
+          (match_op_dup 1 [(and:SI (match_dup 2) (match_dup 3))
+                           (const_int 0)]))
+      (set (match_dup 2)
+          (and:SI (match_dup 2) (match_dup 3)))])]
   "")
 
 ;; We don't need to handle HImode case, because it will be promoted to SImode
 ;; on ! TARGET_PARTIAL_REG_STALL
 
 (define_peephole2
-  [(set (reg 17)
-       (compare (and:QI (match_operand:QI 0 "register_operand" "")
-                        (match_operand:QI 1 "immediate_operand" ""))
-                (const_int 0)))]
+  [(set (match_operand 0 "flags_reg_operand" "")
+       (match_operator 1 "compare_operator"
+         [(and:QI (match_operand:QI 2 "register_operand" "")
+                  (match_operand:QI 3 "immediate_operand" ""))
+          (const_int 0)]))]
   "! TARGET_PARTIAL_REG_STALL
    && ix86_match_ccmode (insn, CCNOmode)
-   && true_regnum (operands[0]) != 0
-   && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
+   && true_regnum (operands[2]) != 0
+   && peep2_reg_dead_p (1, operands[2])"
   [(parallel
-     [(set (reg:CCNO 17)
-          (compare:CCNO (and:QI (match_dup 0)
-                                (match_dup 1))
-                        (const_int 0)))
-      (set (match_dup 0)
-          (and:QI (match_dup 0) (match_dup 1)))])]
+     [(set (match_dup 0)
+          (match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3))
+                           (const_int 0)]))
+      (set (match_dup 2)
+          (and:QI (match_dup 2) (match_dup 3)))])]
   "")
 
 (define_peephole2
-  [(set (reg 17)
-       (compare
-         (and:SI
-           (zero_extract:SI
-             (match_operand 0 "ext_register_operand" "")
-             (const_int 8)
-             (const_int 8))
-           (match_operand 1 "const_int_operand" ""))
-         (const_int 0)))]
+  [(set (match_operand 0 "flags_reg_operand" "")
+       (match_operator 1 "compare_operator"
+         [(and:SI
+            (zero_extract:SI
+              (match_operand 2 "ext_register_operand" "")
+              (const_int 8)
+              (const_int 8))
+            (match_operand 3 "const_int_operand" ""))
+          (const_int 0)]))]
   "! TARGET_PARTIAL_REG_STALL
    && ix86_match_ccmode (insn, CCNOmode)
-   && true_regnum (operands[0]) != 0
-   && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
-  [(parallel [(set (reg:CCNO 17)
-                  (compare:CCNO
-                      (and:SI
-                        (zero_extract:SI
-                        (match_dup 0)
-                        (const_int 8)
-                        (const_int 8))
-                       (match_dup 1))
-                  (const_int 0)))
-             (set (zero_extract:SI (match_dup 0)
+   && true_regnum (operands[2]) != 0
+   && peep2_reg_dead_p (1, operands[2])"
+  [(parallel [(set (match_dup 0)
+                  (match_op_dup 1
+                    [(and:SI
+                       (zero_extract:SI
+                         (match_dup 2)
+                         (const_int 8)
+                         (const_int 8))
+                       (match_dup 3))
+                     (const_int 0)]))
+             (set (zero_extract:SI (match_dup 2)
                                    (const_int 8)
                                    (const_int 8))
                   (and:SI 
                     (zero_extract:SI
-                      (match_dup 0)
+                      (match_dup 2)
                       (const_int 8)
                       (const_int 8))
-                    (match_dup 1)))])]
+                    (match_dup 3)))])]
   "")
 
 ;; Don't do logical operations with memory inputs.
@@ -17554,66 +17565,20 @@
   "")
 \f
 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
-;; required and register dies.
+;; required and register dies.  Similarly for 128 to plus -128.
 (define_peephole2
-  [(set (reg 17)
-       (compare (match_operand:SI 0 "register_operand" "")
-                (match_operand:SI 1 "incdec_operand" "")))]
-  "ix86_match_ccmode (insn, CCGCmode)
-   && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
-  [(parallel [(set (reg:CCGC 17)
-                  (compare:CCGC (match_dup 0)
-                                (match_dup 1)))
-             (clobber (match_dup 0))])]
-  "")
-
-(define_peephole2
-  [(set (reg 17)
-       (compare (match_operand:HI 0 "register_operand" "")
-                (match_operand:HI 1 "incdec_operand" "")))]
-  "ix86_match_ccmode (insn, CCGCmode)
-   && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
-  [(parallel [(set (reg:CCGC 17)
-                  (compare:CCGC (match_dup 0)
-                                (match_dup 1)))
-             (clobber (match_dup 0))])]
-  "")
-
-(define_peephole2
-  [(set (reg 17)
-       (compare (match_operand:QI 0 "register_operand" "")
-                (match_operand:QI 1 "incdec_operand" "")))]
-  "ix86_match_ccmode (insn, CCGCmode)
-   && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
-  [(parallel [(set (reg:CCGC 17)
-                  (compare:CCGC (match_dup 0)
-                                (match_dup 1)))
-             (clobber (match_dup 0))])]
-  "")
-
-;; Convert compares with 128 to shorter add -128
-(define_peephole2
-  [(set (reg 17)
-       (compare (match_operand:SI 0 "register_operand" "")
-                (const_int 128)))]
-  "ix86_match_ccmode (insn, CCGCmode)
-   && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
-  [(parallel [(set (reg:CCGC 17)
-                  (compare:CCGC (match_dup 0)
-                                (const_int 128)))
-             (clobber (match_dup 0))])]
-  "")
-
-(define_peephole2
-  [(set (reg 17)
-       (compare (match_operand:HI 0 "register_operand" "")
-                (const_int 128)))]
-  "ix86_match_ccmode (insn, CCGCmode)
-   && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
-  [(parallel [(set (reg:CCGC 17)
-                  (compare:CCGC (match_dup 0)
-                                (const_int 128)))
-             (clobber (match_dup 0))])]
+  [(set (match_operand 0 "flags_reg_operand" "")
+       (match_operator 1 "compare_operator"
+         [(match_operand 2 "register_operand" "")
+          (match_operand 3 "const_int_operand" "")]))]
+  "(INTVAL (operands[3]) == -1
+    || INTVAL (operands[3]) == 1
+    || INTVAL (operands[3]) == 128)
+   && ix86_match_ccmode (insn, CCGCmode)
+   && peep2_reg_dead_p (1, operands[2])"
+  [(parallel [(set (match_dup 0)
+                  (match_op_dup 1 [(match_dup 2) (match_dup 3)]))
+             (clobber (match_dup 2))])]
   "")
 \f
 (define_peephole2