arm64: dts: ti: k3-am62l: support cpufreq scaling

Enable CPUFreq support for AM62L SoC by adding the relevant OPP efuse table
syscon for speed grade detection.
Add the operating-points-v2 table with CPU frequency steps from 200MHz to
1.25GHz.
Specify the CPU clocks to reference the SCMI clock controller for frequency
scaling.

Signed-off-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Kendall Willis <k-willis@ti.com>
Link: https://patch.msgid.link/20260122-am62l-cpufreq-v5-1-65c50af71681@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi
index 61bfcdcfc66ea8d802a36ed43cd01fbbf3decc70..a42ccd0d2fcc4d204cae81508f839c44ce83f558 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi
@@ -127,6 +127,11 @@
                        bootph-all;
                };
 
+               opp_efuse_table: syscon@18 {
+                       compatible = "ti,am62-opp-efuse-table", "syscon";
+                       reg = <0x18 0x4>;
+               };
+
                cpsw_mac_syscon: ethernet-mac-syscon@2000 {
                        compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
                        reg = <0x2000 0x8>;

diff --git a/arch/arm64/boot/dts/ti/k3-am62l3.dtsi b/arch/arm64/boot/dts/ti/k3-am62l3.dtsi
index da220b85151227c63f59b2b8ec48ae2ebb37e7bf..fc514e19f57d5318f851bad2756817dd7ec29b38 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am62l3.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62l3.dtsi
@@ -39,6 +39,8 @@
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
                        next-level-cache = <&l2_0>;
+                       operating-points-v2 = <&a53_opp_table>;
+                       clocks = <&scmi_clk 356>;
                };
 
                cpu1: cpu@1 {
@@ -53,6 +55,8 @@
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
                        next-level-cache = <&l2_0>;
+                       operating-points-v2 = <&a53_opp_table>;
+                       clocks = <&scmi_clk 357>;
                };
        };
 
@@ -64,4 +68,47 @@
                cache-line-size = <64>;
                cache-sets = <256>;
        };
+
+       a53_opp_table: opp-table {
+               compatible = "operating-points-v2-ti-cpu";
+               opp-shared;
+               syscon = <&opp_efuse_table>;
+
+               opp-200000000 {
+                       opp-hz = /bits/ 64 <200000000>;
+                       opp-supported-hw = <0x01 0x0003>;
+                       clock-latency-ns = <6000000>;
+               };
+
+               opp-400000000 {
+                       opp-hz = /bits/ 64 <400000000>;
+                       opp-supported-hw = <0x01 0x0003>;
+                       clock-latency-ns = <6000000>;
+               };
+
+               opp-600000000 {
+                       opp-hz = /bits/ 64 <600000000>;
+                       opp-supported-hw = <0x01 0x0003>;
+                       clock-latency-ns = <6000000>;
+               };
+
+               opp-800000000 {
+                       opp-hz = /bits/ 64 <800000000>;
+                       opp-supported-hw = <0x01 0x0003>;
+                       clock-latency-ns = <6000000>;
+               };
+
+               opp-1000000000 {
+                       opp-hz = /bits/ 64 <1000000000>;
+                       opp-supported-hw = <0x01 0x0002>;
+                       clock-latency-ns = <6000000>;
+               };
+
+               opp-1250000000 {
+                       opp-hz = /bits/ 64 <1250000000>;
+                       opp-supported-hw = <0x01 0x0002>;
+                       clock-latency-ns = <6000000>;
+                       opp-suspend;
+               };
+       };
 };