dt-bindings: watchdog: aspeed,ast2400-wdt: Add support for AST2700

Add support for the AST2700 SoC in the ASPEED watchdog device tree
bindings. This includes:

- Adding "aspeed,ast2700-wdt" to the compatible string list.
- Extending the "aspeed,reset-mask" property description for AST2700.
- Defining AST2700-specific reset mask bits in aspeed-wdt.h,
  covering RESET1 to RESET5.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>

diff --git a/Documentation/devicetree/bindings/watchdog/aspeed,ast2400-wdt.yaml b/Documentation/devicetree/bindings/watchdog/aspeed,ast2400-wdt.yaml
index be78a9865584d9b802b5a9e3d24ba134c75bfe63..9322cb5b462a2cf2ffe26f41096686b496671209 100644 (file)
--- a/Documentation/devicetree/bindings/watchdog/aspeed,ast2400-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/aspeed,ast2400-wdt.yaml
@@ -15,6 +15,7 @@ properties:
       - aspeed,ast2400-wdt
       - aspeed,ast2500-wdt
       - aspeed,ast2600-wdt
+      - aspeed,ast2700-wdt
 
   reg:
     maxItems: 1
@@ -87,13 +88,15 @@ properties:
   aspeed,reset-mask:
     $ref: /schemas/types.yaml#/definitions/uint32-array
     minItems: 1
-    maxItems: 2
+    maxItems: 5
     description: >
       A bitmask indicating which peripherals will be reset if the watchdog
       timer expires. On AST2500 SoCs this should be a single word defined using
       the AST2500_WDT_RESET_* macros; on AST2600 SoCs this should be a two-word
       array with the first word defined using the AST2600_WDT_RESET1_* macros,
-      and the second word defined using the AST2600_WDT_RESET2_* macros.
+      and the second word defined using the AST2600_WDT_RESET2_* macros; on
+      AST2700 SoCs, this should be five-word array from AST2700_WDT_RESET1_*
+      macros to AST2700_WDT_RESET5_* macros.
 
 required:
   - compatible
@@ -114,6 +117,7 @@ allOf:
           enum:
             - aspeed,ast2500-wdt
             - aspeed,ast2600-wdt
+            - aspeed,ast2700-wdt
   - if:
       required:
         - aspeed,ext-active-high

diff --git a/include/dt-bindings/watchdog/aspeed-wdt.h b/include/dt-bindings/watchdog/aspeed-wdt.h
index 7ae6d84b2bd9d8d3dafdc82e719472e9ccd6bcfe..89fa31ffce2d2962b8bfa8102f3ab9f08313b736 100644 (file)
--- a/include/dt-bindings/watchdog/aspeed-wdt.h
+++ b/include/dt-bindings/watchdog/aspeed-wdt.h
@@ -89,4 +89,142 @@
 
 #define AST2600_WDT_RESET2_DEFAULT 0x03fffff1
 
+#define AST2700_WDT_RESET1_CPU         (1 << 0)
+#define AST2700_WDT_RESET1_DRAM                (1 << 1)
+#define AST2700_WDT_RESET1_SLI0                (1 << 2)
+#define AST2700_WDT_RESET1_EHCI                (1 << 3)
+#define AST2700_WDT_RESET1_HACE                (1 << 4)
+#define AST2700_WDT_RESET1_SOC_MISC0   (1 << 5)
+#define AST2700_WDT_RESET1_VIDEO       (1 << 6)
+#define AST2700_WDT_RESET1_2D_GRAPHIC  (1 << 7)
+#define AST2700_WDT_RESET1_RAVS0       (1 << 8)
+#define AST2700_WDT_RESET1_RAVS1       (1 << 9)
+#define AST2700_WDT_RESET1_GPIO0       (1 << 10)
+#define AST2700_WDT_RESET1_SSP         (1 << 11)
+#define AST2700_WDT_RESET1_TSP         (1 << 12)
+#define AST2700_WDT_RESET1_CRT         (1 << 13)
+#define AST2700_WDT_RESET1_USB20_HOST  (1 << 14)
+#define AST2700_WDT_RESET1_USB11_HOST  (1 << 15)
+#define AST2700_WDT_RESET1_UFS         (1 << 16)
+#define AST2700_WDT_RESET1_EMMC                (1 << 17)
+#define AST2700_WDT_RESET1_AHB_TO_PCIE1        (1 << 18)
+#define AST2700_WDT_RESET1_XDMA0       (1 << 22)
+#define AST2700_WDT_RESET1_MCTP1       (1 << 23)
+#define AST2700_WDT_RESET1_MCTP0       (1 << 24)
+#define AST2700_WDT_RESET1_JTAG0       (1 << 25)
+#define AST2700_WDT_RESET1_ECC         (1 << 26)
+#define AST2700_WDT_RESET1_XDMA1       (1 << 27)
+#define AST2700_WDT_RESET1_DP          (1 << 28)
+#define AST2700_WDT_RESET1_DP_MCU      (1 << 29)
+#define AST2700_WDT_RESET1_AHB_TO_PCIE0        (1 << 31)
+
+#define AST2700_WDT_RESET1_DEFAULT 0x8207ff71
+
+#define AST2700_WDT_RESET2_USB3_A_HOST (1 << 0)
+#define AST2700_WDT_RESET2_USB3_A_VHUB3        (1 << 1)
+#define AST2700_WDT_RESET2_USB3_A_VHUB2        (1 << 2)
+#define AST2700_WDT_RESET2_USB3_B_HOST (1 << 3)
+#define AST2700_WDT_RESET2_USB3_B_VHUB3        (1 << 4)
+#define AST2700_WDT_RESET2_USB3_B_VHUB2        (1 << 5)
+#define AST2700_WDT_RESET2_SM3         (1 << 6)
+#define AST2700_WDT_RESET2_SM4         (1 << 7)
+#define AST2700_WDT_RESET2_SHA3                (1 << 8)
+#define AST2700_WDT_RESET2_RSA         (1 << 9)
+
+#define AST2700_WDT_RESET2_DEFAULT 0x000003f6
+
+#define AST2700_WDT_RESET3_LPC0                (1 << 0)
+#define AST2700_WDT_RESET3_LPC1                (1 << 1)
+#define AST2700_WDT_RESET3_MDIO                (1 << 2)
+#define AST2700_WDT_RESET3_PECI                (1 << 3)
+#define AST2700_WDT_RESET3_PWM         (1 << 4)
+#define AST2700_WDT_RESET3_MAC0                (1 << 5)
+#define AST2700_WDT_RESET3_MAC1                (1 << 6)
+#define AST2700_WDT_RESET3_MAC2                (1 << 7)
+#define AST2700_WDT_RESET3_ADC         (1 << 8)
+#define AST2700_WDT_RESET3_SDC         (1 << 9)
+#define AST2700_WDT_RESET3_ESPI0       (1 << 10)
+#define AST2700_WDT_RESET3_ESPI1       (1 << 11)
+#define AST2700_WDT_RESET3_JTAG1       (1 << 12)
+#define AST2700_WDT_RESET3_SPI0                (1 << 13)
+#define AST2700_WDT_RESET3_SPI1                (1 << 14)
+#define AST2700_WDT_RESET3_SPI2                (1 << 15)
+#define AST2700_WDT_RESET3_I3C0                (1 << 16)
+#define AST2700_WDT_RESET3_I3C1                (1 << 17)
+#define AST2700_WDT_RESET3_I3C2                (1 << 18)
+#define AST2700_WDT_RESET3_I3C3                (1 << 19)
+#define AST2700_WDT_RESET3_I3C4                (1 << 20)
+#define AST2700_WDT_RESET3_I3C5                (1 << 21)
+#define AST2700_WDT_RESET3_I3C6                (1 << 22)
+#define AST2700_WDT_RESET3_I3C7                (1 << 23)
+#define AST2700_WDT_RESET3_I3C8                (1 << 24)
+#define AST2700_WDT_RESET3_I3C9                (1 << 25)
+#define AST2700_WDT_RESET3_I3C10       (1 << 26)
+#define AST2700_WDT_RESET3_I3C11       (1 << 27)
+#define AST2700_WDT_RESET3_I3C12       (1 << 28)
+#define AST2700_WDT_RESET3_I3C13       (1 << 29)
+#define AST2700_WDT_RESET3_I3C14       (1 << 30)
+#define AST2700_WDT_RESET3_I3C15       (1 << 31)
+
+#define AST2700_WDT_RESET3_DEFAULT 0x000093ec
+
+#define AST2700_WDT_RESET4_FMC         (1 << 0)
+#define AST2700_WDT_RESET4_SOC_MISC1   (1 << 1)
+#define AST2700_WDT_RESET4_AHB         (1 << 2)
+#define AST2700_WDT_RESET4_SLI1                (1 << 3)
+#define AST2700_WDT_RESET4_UART0       (1 << 4)
+#define AST2700_WDT_RESET4_UART1       (1 << 5)
+#define AST2700_WDT_RESET4_UART2       (1 << 6)
+#define AST2700_WDT_RESET4_UART3       (1 << 7)
+#define AST2700_WDT_RESET4_I2C_MONITOR (1 << 8)
+#define AST2700_WDT_RESET4_HOST_TO_SPI1        (1 << 9)
+#define AST2700_WDT_RESET4_HOST_TO_SPI2        (1 << 10)
+#define AST2700_WDT_RESET4_GPIO1       (1 << 11)
+#define AST2700_WDT_RESET4_FSI         (1 << 12)
+#define AST2700_WDT_RESET4_CANBUS      (1 << 13)
+#define AST2700_WDT_RESET4_MCTP                (1 << 14)
+#define AST2700_WDT_RESET4_XDMA                (1 << 15)
+#define AST2700_WDT_RESET4_UART5       (1 << 16)
+#define AST2700_WDT_RESET4_UART6       (1 << 17)
+#define AST2700_WDT_RESET4_UART7       (1 << 18)
+#define AST2700_WDT_RESET4_UART8       (1 << 19)
+#define AST2700_WDT_RESET4_BOOT_MCU    (1 << 20)
+#define AST2700_WDT_RESET4_IO_MCU      (1 << 21)
+#define AST2700_WDT_RESET4_LTPI0       (1 << 22)
+#define AST2700_WDT_RESET4_VGA_LINK    (1 << 23)
+#define AST2700_WDT_RESET4_LTPI1       (1 << 24)
+#define AST2700_WDT_RESET4_LTPI_PHY    (1 << 25)
+#define AST2700_WDT_RESET4_ACE         (1 << 26)
+#define AST2700_WDT_RESET4_LTPI_GPIO0  (1 << 28)
+#define AST2700_WDT_RESET4_LTPI_GPIO1  (1 << 29)
+#define AST2700_WDT_RESET4_AHB_TO_PCIE1        (1 << 30)
+#define AST2700_WDT_RESET4_I3C_DMA     (1 << 31)
+
+#define AST2700_WDT_RESET4_DEFAULT 0x40303803
+
+#define AST2700_WDT_RESET5_I2C_GLOBAL  (1 << 0)
+#define AST2700_WDT_RESET5_I2C0                (1 << 1)
+#define AST2700_WDT_RESET5_I2C1                (1 << 2)
+#define AST2700_WDT_RESET5_I2C2                (1 << 3)
+#define AST2700_WDT_RESET5_I2C3                (1 << 4)
+#define AST2700_WDT_RESET5_I2C4                (1 << 5)
+#define AST2700_WDT_RESET5_I2C5                (1 << 6)
+#define AST2700_WDT_RESET5_I2C6                (1 << 7)
+#define AST2700_WDT_RESET5_I2C7                (1 << 8)
+#define AST2700_WDT_RESET5_I2C8                (1 << 9)
+#define AST2700_WDT_RESET5_I2C9                (1 << 10)
+#define AST2700_WDT_RESET5_I2C10       (1 << 11)
+#define AST2700_WDT_RESET5_I2C11       (1 << 12)
+#define AST2700_WDT_RESET5_I2C12       (1 << 13)
+#define AST2700_WDT_RESET5_I2C13       (1 << 14)
+#define AST2700_WDT_RESET5_I2C14       (1 << 15)
+#define AST2700_WDT_RESET5_I2C15       (1 << 16)
+#define AST2700_WDT_RESET5_UHCI                (1 << 17)
+#define AST2700_WDT_RESET5_USB2_C_UART (1 << 18)
+#define AST2700_WDT_RESET5_USB2_C      (1 << 19)
+#define AST2700_WDT_RESET5_USB2_D_UART (1 << 20)
+#define AST2700_WDT_RESET5_USB2_D      (1 << 21)
+
+#define AST2700_WDT_RESET5_DEFAULT 0x00320000
+
 #endif