arm64: dts: freescale: imx93-tqma9352: improve pad configuration

- disable PU/PD if already done with external resistors
- do not configure Schmitt Trigger for outputs
- do not configure DSE / FSEL for inputs

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
index edbd8cad35bca1d99eb2e7c90677d324d81abb05..8993bd3058e95cfb32572fc35c86c6ce7e792299 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
@@ -162,55 +162,63 @@
 &iomuxc {
        pinctrl_flexspi1: flexspi1grp {
                fsl,pins = <
-                       MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B      0x3fe
-                       MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK       0x3fe
-                       MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00   0x3fe
-                       MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01   0x3fe
-                       MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02   0x3fe
-                       MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03   0x3fe
+                       /* FSEL 3  | DSE X6 */
+                       MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B      0x01fe
+                       MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK       0x01fe
+                       /* HYS | PU | FSEL 3  | DSE X6 */
+                       MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00   0x13fe
+                       MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01   0x13fe
+                       /* HYS | FSEL 3  | DSE X6 (external PU) */
+                       MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02   0x11fe
+                       MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03   0x11fe
                >;
        };
 
        pinctrl_lpi2c1: lpi2c1grp {
                fsl,pins = <
-                       MX93_PAD_I2C1_SCL__LPI2C1_SCL           0x40000b9e
-                       MX93_PAD_I2C1_SDA__LPI2C1_SDA           0x40000b9e
+                       /* SION | OD | FSEL 3 | DSE X4 */
+                       MX93_PAD_I2C1_SCL__LPI2C1_SCL           0x4000199e
+                       MX93_PAD_I2C1_SDA__LPI2C1_SDA           0x4000199e
                >;
        };
 
        pinctrl_pca9451: pca9451grp {
                fsl,pins = <
-                       MX93_PAD_I2C2_SDA__GPIO1_IO03           0x1306
+                       /* HYS | PU */
+                       MX93_PAD_I2C2_SDA__GPIO1_IO03           0x1200
                >;
        };
 
        pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
                fsl,pins = <
-                       MX93_PAD_SD2_RESET_B__GPIO3_IO07        0x1306
+                       /* FSEL 2 | DSE X2 */
+                       MX93_PAD_SD2_RESET_B__GPIO3_IO07        0x106
                >;
        };
 
        pinctrl_usdhc1: usdhc1grp {
                fsl,pins = <
-                       /* HYS | PU | PD | FSEL_3 | X5 */
-                       MX93_PAD_SD1_CLK__USDHC1_CLK            0x17be
-                       MX93_PAD_SD1_STROBE__USDHC1_STROBE      0x17be
-                       /* HYS | PU | FSEL_3 | X5 */
-                       MX93_PAD_SD1_CMD__USDHC1_CMD            0x13be
-                       /* HYS | PU | FSEL_3 | X4 */
-                       MX93_PAD_SD1_DATA0__USDHC1_DATA0        0x139e
-                       MX93_PAD_SD1_DATA1__USDHC1_DATA1        0x139e
-                       MX93_PAD_SD1_DATA2__USDHC1_DATA2        0x139e
-                       MX93_PAD_SD1_DATA3__USDHC1_DATA3        0x139e
-                       MX93_PAD_SD1_DATA4__USDHC1_DATA4        0x139e
-                       MX93_PAD_SD1_DATA5__USDHC1_DATA5        0x139e
-                       MX93_PAD_SD1_DATA6__USDHC1_DATA6        0x139e
-                       MX93_PAD_SD1_DATA7__USDHC1_DATA7        0x139e
+                       /* PD | FSEL 3 | DSE X5 */
+                       MX93_PAD_SD1_CLK__USDHC1_CLK            0x5be
+                       /* HYS | FSEL 0 | no drive */
+                       MX93_PAD_SD1_STROBE__USDHC1_STROBE      0x1000
+                       /* HYS | FSEL 3 | X5 */
+                       MX93_PAD_SD1_CMD__USDHC1_CMD            0x11be
+                       /* HYS | FSEL 3 | X4 */
+                       MX93_PAD_SD1_DATA0__USDHC1_DATA0        0x119e
+                       MX93_PAD_SD1_DATA1__USDHC1_DATA1        0x119e
+                       MX93_PAD_SD1_DATA2__USDHC1_DATA2        0x119e
+                       MX93_PAD_SD1_DATA3__USDHC1_DATA3        0x119e
+                       MX93_PAD_SD1_DATA4__USDHC1_DATA4        0x119e
+                       MX93_PAD_SD1_DATA5__USDHC1_DATA5        0x119e
+                       MX93_PAD_SD1_DATA6__USDHC1_DATA6        0x119e
+                       MX93_PAD_SD1_DATA7__USDHC1_DATA7        0x119e
                >;
        };
 
        pinctrl_wdog: wdoggrp {
                fsl,pins = <
+                       /* PU | FSEL 1 | DSE X4 */
                        MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY       0x31e
                >;
        };