override DTC_FLAGS := \
-Wno-avoid_unnecessary_addr_size \
- -Wno-graph_child_address \
-Wno-unique_unit_address \
-Wunique_unit_address_if_enabled
dt_compatible_check: $(obj)/processed-schema.json
$(Q)$(srctree)/scripts/dtc/dt-extract-compatibles $(srctree) | xargs dt-check-compatible -v -s $<
+PHONY += dt_binding_check_one
+dt_binding_check_one: $(obj)/.dt-binding.checked $(obj)/.yamllint.checked
+
PHONY += dt_binding_check
-dt_binding_check: $(obj)/.dt-binding.checked $(obj)/.yamllint.checked $(CHK_DT_EXAMPLES)
+dt_binding_check: dt_binding_check_one $(CHK_DT_EXAMPLES)
maintainers:
- Dinh Nguyen <dinguyen@kernel.org>
+description:
+ Altera/Intel boards with ARM 32/64 bits cores
+
properties:
$nodename:
const: "/"
- altr,socfpga-stratix10-swvp
- const: altr,socfpga-stratix10
+ - description: AgileX boards
+ items:
+ - enum:
+ - intel,n5x-socdk
+ - intel,socfpga-agilex-n6000
+ - intel,socfpga-agilex-socdk
+ - intel,socfpga-agilex-socdk-emmc
+ - const: intel,socfpga-agilex
+
+ - description: Agilex3 boards
+ items:
+ - enum:
+ - intel,socfpga-agilex3-socdk
+ - const: intel,socfpga-agilex3
+ - const: intel,socfpga-agilex5
+
+ - description: Agilex5 boards
+ items:
+ - enum:
+ - intel,socfpga-agilex5-socdk
+ - intel,socfpga-agilex5-socdk-013b
+ - intel,socfpga-agilex5-socdk-nand
+ - const: intel,socfpga-agilex5
+
- description: SoCFPGA VT
items:
- const: altr,socfpga-vt
items:
- enum:
- amlogic,aq222
+ - const: amlogic,s805x2
+ - const: amlogic,s4
+
+ - description: Boards with the Amlogic Meson S4 S905Y4 SoC
+ items:
+ - enum:
+ - khadas,vim1s
+ - const: amlogic,s905y4
- const: amlogic,s4
- description: Boards with the Amlogic S6 S905X5 SoC
- Mike Leach <mike.leach@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
- James Clark <james.clark@linaro.org>
- - Mao Jinlong <quic_jinlmao@quicinc.com>
+ - Mao Jinlong <jinlong.mao@oss.qualcomm.com>
- Hao Zhang <quic_hazha@quicinc.com>
properties:
- Mike Leach <mike.leach@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
- James Clark <james.clark@linaro.org>
- - Mao Jinlong <quic_jinlmao@quicinc.com>
+ - Mao Jinlong <jinlong.mao@oss.qualcomm.com>
- Hao Zhang <quic_hazha@quicinc.com>
properties:
- const: simple-bus
- const: simple-bus
+ "#interrupt-cells":
+ const: 1
+
+ interrupt-map: true
+ interrupt-map-mask: true
+
patternProperties:
'^motherboard-bus@':
type: object
- amd,ethanolx-bmc
- ampere,mtjade-bmc
- aspeed,ast2500-evb
+ - asrock,altrad8-bmc
- asrock,e3c246d4i-bmc
- asrock,e3c256d4i-bmc
- asrock,romed8hm3-bmc
- aspeed,ast2600-evb
- aspeed,ast2600-evb-a1
- asus,x4tf-bmc
+ - facebook,anacapa-bmc
- facebook,bletchley-bmc
- facebook,catalina-bmc
- facebook,clemente-bmc
- inventec,transformer-bmc
- jabil,rbp-bmc
- nvidia,gb200nvl-bmc
+ - nvidia,msx4-bmc
- qcom,dc-scm-v1-bmc
- quanta,s6q-bmc
- ufispace,ncplite-bmc
- const: microchip,lan9662
- const: microchip,lan966
- - description: Microchip LAN9668 PCB8290 Evaluation Board.
+ - description: Microchip LAN9668 Evaluation Board.
items:
- - const: microchip,lan9668-pcb8290
+ - enum:
+ - microchip,lan9668-pcb8290
+ - microchip,lan9668-pcb8385
- const: microchip,lan9668
- const: microchip,lan966
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/arm/bcm/brcm,vulcan-soc.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Broadcom Vulcan
-
-maintainers:
- - Robert Richter <rrichter@marvell.com>
-
-properties:
- $nodename:
- const: '/'
- compatible:
- items:
- - enum:
- - brcm,vulcan-eval
- - cavium,thunderx2-cn9900
- - const: brcm,vulcan-soc
-
-additionalProperties: true
-
-...
gpio-line-names:
minItems: 8
+ patternProperties:
+ '-hog$':
+ required:
+ - gpio-hog
+
required:
- compatible
- gpio-controller
- compatible
- "#reset-cells"
+ power:
+ $ref: /schemas/power/raspberrypi,bcm2835-power.yaml#
+
pwm:
type: object
additionalProperties: false
compatible:
oneOf:
- - description: Radxa Orion O6
+ - description: Sky1 based boards
items:
- - const: radxa,orion-o6
+ - enum:
+ - radxa,orion-o6 # Radxa Orion O6 board
+ - xunlong,orangepi-6-plus # Xunlong orangepi 6 plus board
- const: cix,sky1
additionalProperties: true
- gw,imx8mn-gw7902 # i.MX8MM Gateworks Board
- const: fsl,imx8mn
+ - description: ifm i.MX8MN VHIP4 based boards
+ items:
+ - enum:
+ - ifm,imx8mn-vhip4-evalboard-v1
+ - ifm,imx8mn-vhip4-evalboard-v2
+ - const: ifm,imx8mn-vhip4-evalboard
+ - const: ifm,imx8mn-vhip4
+ - const: fsl,imx8mn
+
- description: Variscite VAR-SOM-MX8MN based boards
items:
- enum:
- emcraft,imx8mp-navqp # i.MX8MP Emcraft Systems NavQ+ Kit
- fsl,imx8mp-evk # i.MX8MP EVK Board
- fsl,imx8mp-evk-revb4 # i.MX8MP EVK Rev B4 Board
+ - fsl,imx8mp-frdm # i.MX8MP Freedom Board
- gateworks,imx8mp-gw71xx-2x # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board
- const: toradex,apalis-imx8
- const: fsl,imx8qm
- - description: i.MX8QM Boards with Toradex Apalis iMX8 V1.1 Modules
+ - description: i.MX8QM/i.MX8QP Boards with Toradex Apalis iMX8 V1.1 Modules
items:
- enum:
- toradex,apalis-imx8-v1.1-eval # Apalis iMX8 V1.1 Module on Apalis Eval. V1.0/V1.1 Board
- toradex,apalis-imx8-v1.1-ixora-v1.1 # Apalis iMX8 V1.1 Module on Ixora V1.1 C. Board
- toradex,apalis-imx8-v1.1-ixora-v1.2 # Apalis iMX8 V1.1 Module on Ixora V1.2 C. Board
- const: toradex,apalis-imx8-v1.1
- - const: fsl,imx8qm
+ - enum:
+ - fsl,imx8qm
+ - fsl,imx8qp
- description: i.MX8QXP based Boards
items:
items:
- enum:
- fsl,imx91-11x11-evk # i.MX91 11x11 EVK Board
+ - fsl,imx91-11x11-frdm # FRDM i.MX91 Development Board
- const: fsl,imx91
- description: i.MX93 based Boards
- enum:
- fsl,imx93-9x9-qsb # i.MX93 9x9 QSB Board
- fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board
+ - fsl,imx93-11x11-frdm # i.MX93 11x11 FRDM Board
- fsl,imx93-14x14-evk # i.MX93 14x14 EVK Board
- const: fsl,imx93
items:
- enum:
- fsl,imx95-15x15-evk # i.MX95 15x15 EVK Board
+ - fsl,imx95-15x15-frdm # i.MX95 15x15 FRDM Board
- fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board
- toradex,verdin-imx95-19x19-evk # i.MX95 Verdin Evaluation Kit (EVK)
- const: fsl,imx95
+ - description: i.MX952 based Boards
+ items:
+ - enum:
+ - fsl,imx952-evk # i.MX952 EVK Board
+ - const: fsl,imx952
+
- description: PHYTEC i.MX 95 FPSC based Boards
items:
- enum:
- const: kontron,sl28
- const: fsl,ls1028a
+ - description:
+ TQ-Systems TQMLS1028A SoM on MBLS1028A/MBLS1028A-IND board
+ items:
+ - enum:
+ - tq,ls1028a-tqmls1028a-mbls1028a
+ - tq,ls1028a-tqmls1028a-mbls1028a-ind
+ - const: tq,ls1028a-tqmls1028a
+ - const: fsl,ls1028a
+
- description: LS1043A based Boards
items:
- enum:
+++ /dev/null
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/arm/intel,socfpga.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Intel SoCFPGA platform
-
-maintainers:
- - Dinh Nguyen <dinguyen@kernel.org>
-
-properties:
- $nodename:
- const: "/"
- compatible:
- oneOf:
- - description: AgileX boards
- items:
- - enum:
- - intel,n5x-socdk
- - intel,socfpga-agilex-n6000
- - intel,socfpga-agilex-socdk
- - const: intel,socfpga-agilex
- - description: Agilex3 boards
- items:
- - enum:
- - intel,socfpga-agilex3-socdk
- - const: intel,socfpga-agilex3
- - const: intel,socfpga-agilex5
- - description: Agilex5 boards
- items:
- - enum:
- - intel,socfpga-agilex5-socdk
- - intel,socfpga-agilex5-socdk-013b
- - intel,socfpga-agilex5-socdk-nand
- - const: intel,socfpga-agilex5
-
-additionalProperties: true
-
-...
- const: mediatek,mt8365
- items:
- enum:
+ - ezurio,mt8370-tungsten-smarc
- grinn,genio-510-sbc
- mediatek,mt8370-evk
- const: mediatek,mt8370
- const: mediatek,mt8188
- items:
- enum:
+ - ezurio,mt8390-tungsten-smarc
- grinn,genio-700-sbc
- mediatek,mt8390-evk
- const: mediatek,mt8390
- compatible
- '#clock-cells'
-if:
- properties:
- compatible:
- contains:
- const: mediatek,mt8183-audiosys
-then:
- properties:
- audio-controller:
- $ref: /schemas/sound/mediatek,mt8183-audio.yaml#
-else:
- properties:
- audio-controller:
- $ref: /schemas/sound/mediatek,mt2701-audio.yaml#
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mediatek,mt2701-audsys
+ - mediatek,mt7622-audsys
+ then:
+ properties:
+ audio-controller:
+ $ref: /schemas/sound/mediatek,mt2701-audio.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8183-audiosys
+ then:
+ properties:
+ audio-controller:
+ $ref: /schemas/sound/mediatek,mt8183-audio.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8192-audsys
+ then:
+ properties:
+ audio-controller:
+ $ref: /schemas/sound/mt8192-afe-pcm.yaml#
+
additionalProperties: false
+++ /dev/null
-OMAP PRM instance bindings
-
-Power and Reset Manager is an IP block on OMAP family of devices which
-handle the power domains and their current state, and provide reset
-handling for the domains and/or separate IP blocks under the power domain
-hierarchy.
-
-Required properties:
-- compatible: Must contain one of the following:
- "ti,am3-prm-inst"
- "ti,am4-prm-inst"
- "ti,omap4-prm-inst"
- "ti,omap5-prm-inst"
- "ti,dra7-prm-inst"
- and additionally must contain:
- "ti,omap-prm-inst"
-- reg: Contains PRM instance register address range
- (base address and length)
-
-Optional properties:
-- #power-domain-cells: Should be 0 if the instance is a power domain provider.
-- #reset-cells: Should be 1 if the PRM instance in question supports resets.
-
-Example:
-
-prm_dsp2: prm@1b00 {
- compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
- reg = <0x1b00 0x40>;
- #power-domain-cells = <0>;
- #reset-cells = <1>;
-};
title: CoreSight TMC Control Unit
maintainers:
- - Yuanfang Zhang <quic_yuanfang@quicinc.com>
- - Mao Jinlong <quic_jinlmao@quicinc.com>
- - Jie Gan <quic_jiegan@quicinc.com>
+ - Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
+ - Mao Jinlong <jinlong.mao@oss.qualcomm.com>
+ - Jie Gan <jie.gan@oss.qualcomm.com>
description: |
The Trace Memory Controller(TMC) is used for Embedded Trace Buffer(ETB),
properties:
compatible:
- enum:
- - qcom,sa8775p-ctcu
+ oneOf:
+ - items:
+ - enum:
+ - qcom,qcs8300-ctcu
+ - const: qcom,sa8775p-ctcu
+ - enum:
+ - qcom,sa8775p-ctcu
reg:
maxItems: 1
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/qcom,coresight-itnoc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Interconnect Trace Network On Chip - ITNOC
+
+maintainers:
+ - Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
+
+description:
+ The Interconnect TNOC is a CoreSight graph link that forwards trace data
+ from a subsystem to the Aggregator TNOC. Compared to Aggregator TNOC, it
+ does not have aggregation and ATID functionality.
+
+properties:
+ $nodename:
+ pattern: "^itnoc(@[0-9a-f]+)?$"
+
+ compatible:
+ const: qcom,coresight-itnoc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: apb
+
+ in-ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ patternProperties:
+ '^port(@[0-9a-f]{1,2})?$':
+ description: Input connections from CoreSight Trace Bus
+ $ref: /schemas/graph.yaml#/properties/port
+
+ out-ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ additionalProperties: false
+
+ properties:
+ port:
+ description: out connections to aggregator TNOC
+ $ref: /schemas/graph.yaml#/properties/port
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - in-ports
+ - out-ports
+
+additionalProperties: false
+
+examples:
+ - |
+ itnoc@109ac000 {
+ compatible = "qcom,coresight-itnoc";
+ reg = <0x109ac000 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tn_ic_in_tpdm_dcc: endpoint {
+ remote-endpoint = <&tpdm_dcc_out_tn_ic>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tn_ic_out_tnoc_aggr: endpoint {
+ /* to Aggregator TNOC input */
+ remote-endpoint = <&tn_ag_in_tn_ic>;
+ };
+ };
+ };
+ };
+...
title: Qualcomm Coresight Remote ETM(Embedded Trace Macrocell)
maintainers:
- - Jinlong Mao <quic_jinlmao@quicinc.com>
- - Tao Zhang <quic_taozha@quicinc.com>
+ - Jinlong Mao <jinlong.mao@oss.qualcomm.com>
+ - Tao Zhang <tao.zhang@oss.qualcomm.com>
description:
Support for ETM trace collection on remote processor using coresight
title: Qualcomm Trace Network On Chip - TNOC
maintainers:
- - Yuanfang Zhang <quic_yuanfang@quicinc.com>
+ - Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
description: >
The Trace Network On Chip (TNOC) is an integration hierarchy hardware
to sink.
maintainers:
- - Mao Jinlong <quic_jinlmao@quicinc.com>
- - Tao Zhang <quic_taozha@quicinc.com>
+ - Mao Jinlong <jinlong.mao@oss.qualcomm.com>
+ - Tao Zhang <tao.zhang@oss.qualcomm.com>
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
sources and send it to a TPDA for packetization, timestamping, and funneling.
maintainers:
- - Mao Jinlong <quic_jinlmao@quicinc.com>
- - Tao Zhang <quic_taozha@quicinc.com>
+ - Mao Jinlong <jinlong.mao@oss.qualcomm.com>
+ - Tao Zhang <tao.zhang@oss.qualcomm.com>
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
- qcom,apq8084-sbc
- const: qcom,apq8084
+ - items:
+ - enum:
+ - fairphone,fp6
+ - const: qcom,milos
+
- items:
- enum:
- microsoft,dempsey
- qcom,ipq9574-ap-al02-c9
- const: qcom,ipq9574
+ - items:
+ - enum:
+ - qcom,kaanapali-mtp
+ - qcom,kaanapali-qrd
+ - const: qcom,kaanapali
+
- description: Sierra Wireless MangOH Green with WP8548 Module
items:
- const: swir,mangoh-green-wp8548
- description: Qualcomm Technologies, Inc. Robotics RB1
items:
- enum:
+ - arduino,imola
- qcom,qrb2210-rb1
- const: qcom,qrb2210
- const: qcom,qcm2290
- qcom,qcs6490-rb3gen2
- radxa,dragon-q6a
- shift,otter
+ - thundercomm,rubikpi3
- const: qcom,qcm6490
- description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform
- items:
- enum:
+ - google,blueline
+ - google,crosshatch
- huawei,planck
- lenovo,yoga-c630
- lg,judyln
- const: qcom,x1e78100
- const: qcom,x1e80100
+ - items:
+ - enum:
+ - medion,sprchrgd14s1
+ - tuxedo,elite14gen1
+ - const: qcom,x1e78100
+ - const: qcom,x1e80100
+
+ - items:
+ - const: microsoft,denali-lcd
+ - const: microsoft,denali
+ - const: qcom,x1p64100
+ - const: qcom,x1e80100
+
- items:
- enum:
- asus,vivobook-s15
- const: qcom,hamoa-iot-som
- const: qcom,x1e80100
+ - items:
+ - const: microsoft,denali-oled
+ - const: microsoft,denali
+ - const: qcom,x1e80100
+
- items:
- enum:
- asus,zenbook-a14-ux3407qa-lcd
const: '/'
compatible:
oneOf:
- # RTD1195 SoC based boards
- - items:
+ - description: RTD1195 SoC based boards
+ items:
- enum:
- mele,x1000 # MeLE X1000
- realtek,horseradish # Realtek Horseradish EVB
- const: realtek,rtd1195
- # RTD1293 SoC based boards
- - items:
+ - description: RTD1293 SoC based boards
+ items:
- enum:
- synology,ds418j # Synology DiskStation DS418j
- const: realtek,rtd1293
- # RTD1295 SoC based boards
- - items:
+ - description: RTD1295 SoC based boards
+ items:
- enum:
- mele,v9 # MeLE V9
- probox2,ava # ProBox2 AVA
- zidoo,x9s # Zidoo X9S
- const: realtek,rtd1295
- # RTD1296 SoC based boards
- - items:
+ - description: RTD1296 SoC based boards
+ items:
- enum:
- synology,ds418 # Synology DiskStation DS418
- const: realtek,rtd1296
- # RTD1395 SoC based boards
- - items:
+ - description: RTD1395 SoC based boards
+ items:
- enum:
- bananapi,bpi-m4 # Banana Pi BPI-M4
- realtek,lion-skin # Realtek Lion Skin EVB
- const: realtek,rtd1395
- # RTD1619 SoC based boards
- - items:
+ - description: RTD1501s SoC based boards
+ items:
+ - enum:
+ - realtek,phantom # Realtek Phantom EVB (8GB)
+ - const: realtek,rtd1501s
+
+ - description: RTD1619 SoC based boards
+ items:
- enum:
- realtek,mjolnir # Realtek Mjolnir EVB
- const: realtek,rtd1619
+ - description: RTD1861b SoC based boards
+ items:
+ - enum:
+ - realtek,krypton # Realtek Krypton EVB (8GB)
+ - const: realtek,rtd1861b
+
+ - description: RTD1920s SoC based boards
+ items:
+ - enum:
+ - realtek,smallville # Realtek Smallville EVB (4GB)
+ - const: realtek,rtd1920s
+
additionalProperties: true
...
- anbernic,rg-arc-s
- const: rockchip,rk3566
+ - description: Anbernic RK3568 Handheld Gaming Console
+ items:
+ - enum:
+ - anbernic,rg-ds
+ - const: rockchip,rk3568
+
- description: Ariaboard Photonicat
items:
- const: ariaboard,photonicat
- const: rockchip,rk3568
- description: QNAP TS-x33 NAS devices
- items:
- - enum:
- - qnap,ts233
- - qnap,ts433
- - const: rockchip,rk3568
+ oneOf:
+ - items:
+ - const: qnap,ts133
+ - const: rockchip,rk3566
+ - items:
+ - enum:
+ - qnap,ts233
+ - qnap,ts433
+ - const: rockchip,rk3568
- description: Radxa Compute Module 3 (CM3)
items:
- const: radxa,cm3
- const: rockchip,rk3566
- - description: Radxa CM3 Industrial
+ - description: Radxa CM3I
items:
- enum:
- radxa,e25
- const: radxa,cm3i
- const: rockchip,rk3568
+ - description: Radxa CM3J
+ items:
+ - enum:
+ - radxa,cm3j-rpi-cm4
+ - const: radxa,cm3j
+ - const: rockchip,rk3568
+
+ - description: Radxa CM5
+ items:
+ - enum:
+ - radxa,cm5-io
+ - const: radxa,cm5
+ - const: rockchip,rk3588s
+
- description: Radxa E20C
items:
- const: radxa,e20c
- xunlong,orangepi-5b
- const: rockchip,rk3588s
+ - description: Xunlong Orange Pi CM5
+ items:
+ - const: xunlong,orangepi-cm5-base
+ - const: xunlong,orangepi-cm5
+ - const: rockchip,rk3588s
+
- description: Zkmagic A95X Z2
items:
- const: zkmagic,a95x-z2
- nvidia,tegra264-pmc
reg:
- minItems: 4
+ minItems: 3
maxItems: 5
reg-names:
- minItems: 4
+ minItems: 3
items:
- const: pmc
- const: wake
- - const: aotag
+ - enum: [ aotag, scratch, misc ]
- enum: [ scratch, misc ]
- const: misc
then:
properties:
reg:
+ minItems: 4
maxItems: 4
reg-names:
maxItems: 4
properties:
compatible:
contains:
- const: nvidia,tegra234-pmc
+ enum:
+ - nvidia,tegra234-pmc
+ - nvidia,tegra264-pmc
then:
properties:
reg-names:
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/ti/ti,omap-prm-inst.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: OMAP PRM instances
+
+maintainers:
+ - Aaro Koskinen <aaro.koskinen@iki.fi>
+ - Andreas Kemnade <andreas@kemnade.info>
+ - Kevin Hilman <khilman@baylibre.com>
+ - Roger Quadros <rogerq@kernel.org>
+ - Tony Lindgren <tony@atomide.com>
+
+description:
+ Power and Reset Manager is an IP block on OMAP family of devices which
+ handle the power domains and their current state, and provide reset
+ handling for the domains and/or separate IP blocks under the power domain
+ hierarchy.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - ti,am3-prm-inst
+ - ti,am4-prm-inst
+ - ti,omap4-prm-inst
+ - ti,omap5-prm-inst
+ - ti,dra7-prm-inst
+ - const: ti,omap-prm-inst
+
+ reg:
+ maxItems: 1
+
+ "#power-domain-cells":
+ const: 0
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ reset-controller@1b00 {
+ compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
+ reg = <0x1b00 0x40>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
- arm,vexpress,config-bridge
patternProperties:
- 'clk[0-9]*$':
+ '^clock-controller.*$':
type: object
description:
clocks
- arm,vexpress-sysreg,func
- "#clock-cells"
- "^volt-.+$":
+ "^regulator-.+$":
$ref: /schemas/regulator/regulator.yaml#
properties:
compatible:
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
- clk0 {
+ clock-controller {
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
#clock-cells = <0>;
- Hans de Goede <hdegoede@redhat.com>
- Jens Axboe <axboe@kernel.dk>
-select:
- properties:
- compatible:
- contains:
- enum:
- - brcm,iproc-ahci
- - cavium,octeon-7130-ahci
- - hisilicon,hisi-ahci
- - ibm,476gtr-ahci
- - marvell,armada-3700-ahci
- - marvell,armada-8k-ahci
- - marvell,berlin2q-ahci
- - qcom,apq8064-ahci
- - qcom,ipq806x-ahci
- - socionext,uniphier-pro4-ahci
- - socionext,uniphier-pxs2-ahci
- - socionext,uniphier-pxs3-ahci
- required:
- - compatible
-
properties:
compatible:
oneOf:
each port can have a Port Multiplier attached thus allowing to
access more than one drive by means of a single SATA port.
+ port:
+ $ref: /schemas/graph.yaml#/properties/port
+
...
required:
- refresh-rate-hz
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
properties:
compatible:
- enum:
- - aspeed,ast2600-ahbc
+ items:
+ - enum:
+ - aspeed,ast2600-ahbc
+ - const: syscon
reg:
maxItems: 1
examples:
- |
ahbc@1e600000 {
- compatible = "aspeed,ast2600-ahbc";
+ compatible = "aspeed,ast2600-ahbc", "syscon";
reg = <0x1e600000 0x100>;
};
the SDMA can access. There are no special clocks for the bus, because
the SDMA controller itself has its interrupt and clock assignments.
+ EMI (External Memory Interface) for legacy i.MX35.
+
select:
properties:
compatible:
contains:
- const: fsl,spba-bus
+ enum:
+ - fsl,aips
+ - fsl,emi
+ - fsl,spba-bus
required:
- compatible
properties:
$nodename:
- pattern: "^spba-bus(@[0-9a-f]+)?$"
+ pattern: "^((spba|emi)-bus|bus)(@[0-9a-f]+)?$"
compatible:
items:
- - const: fsl,spba-bus
+ - enum:
+ - fsl,aips
+ - fsl,emi
+ - fsl,spba-bus
- const: simple-bus
'#address-cells':
const: 1
"#size-cells":
- const: 1
+ enum: [ 1, 2 ]
ranges: true
properties:
compatible:
enum:
+ - qcom,glymur-llcc
- qcom,ipq5424-llcc
- qcom,kaanapali-llcc
- qcom,qcs615-llcc
reg:
minItems: 1
- maxItems: 10
+ maxItems: 14
reg-names:
minItems: 1
- maxItems: 10
+ maxItems: 14
interrupts:
maxItems: 1
items:
- const: llcc0_base
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,glymur-llcc
+ then:
+ properties:
+ reg:
+ items:
+ - description: LLCC0 base register region
+ - description: LLCC1 base register region
+ - description: LLCC2 base register region
+ - description: LLCC3 base register region
+ - description: LLCC4 base register region
+ - description: LLCC5 base register region
+ - description: LLCC6 base register region
+ - description: LLCC7 base register region
+ - description: LLCC8 base register region
+ - description: LLCC9 base register region
+ - description: LLCC10 base register region
+ - description: LLCC11 base register region
+ - description: LLCC broadcast base register region
+ - description: LLCC broadcast AND register region
+ reg-names:
+ items:
+ - const: llcc0_base
+ - const: llcc1_base
+ - const: llcc2_base
+ - const: llcc3_base
+ - const: llcc4_base
+ - const: llcc5_base
+ - const: llcc6_base
+ - const: llcc7_base
+ - const: llcc8_base
+ - const: llcc9_base
+ - const: llcc10_base
+ - const: llcc11_base
+ - const: llcc_broadcast_base
+ - const: llcc_broadcast_and_base
+
- if:
properties:
compatible:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,t7-peripherals-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic T7 Peripherals Clock Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Xianwei Zhao <xianwei.zhao@amlogic.com>
+ - Jian Hu <jian.hu@amlogic.com>
+
+properties:
+ compatible:
+ const: amlogic,t7-peripherals-clkc
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ minItems: 14
+ items:
+ - description: input oscillator
+ - description: input sys clk
+ - description: input fixed pll
+ - description: input fclk div 2
+ - description: input fclk div 2p5
+ - description: input fclk div 3
+ - description: input fclk div 4
+ - description: input fclk div 5
+ - description: input fclk div 7
+ - description: input hifi pll
+ - description: input gp0 pll
+ - description: input gp1 pll
+ - description: input mpll1
+ - description: input mpll2
+ - description: external input rmii oscillator (optional)
+ - description: input video pll0 (optional)
+ - description: external pad input for rtc (optional)
+
+ clock-names:
+ minItems: 14
+ items:
+ - const: xtal
+ - const: sys
+ - const: fix
+ - const: fdiv2
+ - const: fdiv2p5
+ - const: fdiv3
+ - const: fdiv4
+ - const: fdiv5
+ - const: fdiv7
+ - const: hifi
+ - const: gp0
+ - const: gp1
+ - const: mpll1
+ - const: mpll2
+ - const: ext_rmii
+ - const: vid_pll0
+ - const: ext_rtc
+
+required:
+ - compatible
+ - '#clock-cells'
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ apb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clkc_periphs:clock-controller@0 {
+ compatible = "amlogic,t7-peripherals-clkc";
+ reg = <0 0x0 0 0x1c8>;
+ #clock-cells = <1>;
+ clocks = <&xtal>,
+ <&scmi_clk 13>,
+ <&scmi_clk 16>,
+ <&scmi_clk 18>,
+ <&scmi_clk 20>,
+ <&scmi_clk 22>,
+ <&scmi_clk 24>,
+ <&scmi_clk 26>,
+ <&scmi_clk 28>,
+ <&hifi 1>,
+ <&gp0 1>,
+ <&gp1 1>,
+ <&mpll 4>,
+ <&mpll 6>;
+ clock-names = "xtal",
+ "sys",
+ "fix",
+ "fdiv2",
+ "fdiv2p5",
+ "fdiv3",
+ "fdiv4",
+ "fdiv5",
+ "fdiv7",
+ "hifi",
+ "gp0",
+ "gp1",
+ "mpll1",
+ "mpll2";
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic T7 PLL Clock Control Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Jian Hu <jian.hu@amlogic.com>
+ - Xianwei Zhao <xianwei.zhao@amlogic.com>
+
+properties:
+ compatible:
+ enum:
+ - amlogic,t7-gp0-pll
+ - amlogic,t7-gp1-pll
+ - amlogic,t7-hifi-pll
+ - amlogic,t7-pcie-pll
+ - amlogic,t7-mpll
+ - amlogic,t7-hdmi-pll
+ - amlogic,t7-mclk-pll
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ items:
+ - description: mclk pll input oscillator gate
+ - description: oscillator input clock source for mclk_sel_0
+ - description: fixed input clock source for mclk_sel_0
+ minItems: 1
+
+ clock-names:
+ items:
+ - const: in0
+ - const: in1
+ - const: in2
+ minItems: 1
+
+required:
+ - compatible
+ - '#clock-cells'
+ - reg
+ - clocks
+ - clock-names
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: amlogic,t7-mclk-pll
+
+ then:
+ properties:
+ clocks:
+ minItems: 3
+
+ clock-names:
+ minItems: 3
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - amlogic,t7-gp0-pll
+ - amlogic,t7-gp1--pll
+ - amlogic,t7-hifi-pll
+ - amlogic,t7-pcie-pll
+ - amlogic,t7-mpll
+ - amlogic,t7-hdmi-pll
+
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ maxItems: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ apb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clock-controller@8080 {
+ compatible = "amlogic,t7-gp0-pll";
+ reg = <0 0x8080 0 0x20>;
+ clocks = <&scmi_clk 2>;
+ clock-names = "in0";
+ #clock-cells = <1>;
+ };
+
+ clock-controller@8300 {
+ compatible = "amlogic,t7-mclk-pll";
+ reg = <0 0x8300 0 0x18>;
+ clocks = <&scmi_clk 2>,
+ <&xtal>,
+ <&scmi_clk 31>;
+ clock-names = "in0", "in1", "in2";
+ #clock-cells = <1>;
+ };
+ };
enum:
- google,gs101-cmu-top
- google,gs101-cmu-apm
- - google,gs101-cmu-misc
+ - google,gs101-cmu-dpu
- google,gs101-cmu-hsi0
- google,gs101-cmu-hsi2
+ - google,gs101-cmu-misc
- google,gs101-cmu-peric0
- google,gs101-cmu-peric1
reg:
maxItems: 1
+ samsung,sysreg:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to system registers interface.
+
required:
- compatible
- "#clock-cells"
items:
- const: oscclk
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: google,gs101-cmu-dpu
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24.576 MHz)
+ - description: DPU bus clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: bus
+
- if:
properties:
compatible:
- const: bus
- const: ip
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: google,gs101-cmu-top
+ then:
+ properties:
+ samsung,sysreg: false
+ else:
+ required:
+ - samsung,sysreg
+
additionalProperties: false
examples:
cmu_top: clock-controller@1e080000 {
compatible = "google,gs101-cmu-top";
- reg = <0x1e080000 0x8000>;
+ reg = <0x1e080000 0x10000>;
#clock-cells = <1>;
clocks = <&ext_24_5m>;
clock-names = "oscclk";
properties:
compatible:
- oneOf:
- - items:
- - const: mediatek,mt7622-pciesys
- - const: syscon
- - const: mediatek,mt7629-pciesys
+ enum:
+ - mediatek,mt7622-pciesys
+ - mediatek,mt7629-pciesys
reg:
maxItems: 1
examples:
- |
clock-controller@1a100800 {
- compatible = "mediatek,mt7622-pciesys", "syscon";
+ compatible = "mediatek,mt7622-pciesys";
reg = <0x1a100800 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
properties:
compatible:
- const: microchip,mpfs-ccc
+ oneOf:
+ - items:
+ - const: microchip,pic64gx-ccc
+ - const: microchip,mpfs-ccc
+ - const: microchip,mpfs-ccc
reg:
items:
properties:
compatible:
- const: microchip,mpfs-clkcfg
+ oneOf:
+ - items:
+ - const: microchip,pic64gx-clkcfg
+ - const: microchip,mpfs-clkcfg
+ - const: microchip,mpfs-clkcfg
reg:
oneOf:
- clocks
- '#clock-cells'
+if:
+ properties:
+ compatible:
+ contains:
+ const: microchip,pic64gx-clkcfg
+then:
+ properties:
+ reg:
+ maxItems: 1
+
additionalProperties: false
examples:
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8953.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Global Clock & Reset Controller on MSM8953
+title: Qualcomm Global Clock & Reset Controller on MSM8937, MSM8940, MSM8953 and SDM439
maintainers:
- Adam Skladowski <a_skl39@protonmail.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
- domains on MSM8937 or MSM8953.
+ domains on MSM8937, MSM8940, MSM8953 or SDM439.
See also::
include/dt-bindings/clock/qcom,gcc-msm8917.h
compatible:
enum:
- qcom,gcc-msm8937
+ - qcom,gcc-msm8940
- qcom,gcc-msm8953
+ - qcom,gcc-sdm439
clocks:
items:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,kaanapali-gxclkctl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Graphics power domain Controller on Kaanapali
+
+maintainers:
+ - Taniya Das <taniya.das@oss.qualcomm.com>
+
+description: |
+ Qualcomm GX(graphics) is a clock controller which has PLLs, clocks and
+ Power domains (GDSC). This module provides the power domains control
+ of gxclkctl on Qualcomm SoCs which helps the recovery of Graphics subsystem.
+
+ See also:
+ include/dt-bindings/clock/qcom,kaanapali-gxclkctl.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,kaanapali-gxclkctl
+
+ power-domains:
+ description:
+ Power domains required for the clock controller to operate
+ items:
+ - description: GFX power domain
+ - description: GMXC power domain
+ - description: GPUCC(CX) power domain
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - '#power-domain-cells'
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clock-controller@3d64000 {
+ compatible = "qcom,kaanapali-gxclkctl";
+ reg = <0x0 0x03d64000 0x0 0x6000>;
+ power-domains = <&rpmhpd RPMHPD_GFX>,
+ <&rpmhpd RPMHPD_GMXC>,
+ <&gpucc 0>;
+ #power-domain-cells = <1>;
+ };
+ };
+...
maintainers:
- Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
- Jagadeesh Kona <quic_jkona@quicinc.com>
+ - Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and power
domains on SM8450.
See also:
+ include/dt-bindings/clock/qcom,kaanapali-camcc.h
+ include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h
include/dt-bindings/clock/qcom,sm8450-camcc.h
include/dt-bindings/clock/qcom,sm8550-camcc.h
include/dt-bindings/clock/qcom,sm8650-camcc.h
+ include/dt-bindings/clock/qcom,sm8750-cambistmclkcc.h
+ include/dt-bindings/clock/qcom,sm8750-camcc.h
properties:
compatible:
enum:
+ - qcom,kaanapali-cambistmclkcc
+ - qcom,kaanapali-camcc
- qcom,sm8450-camcc
- qcom,sm8475-camcc
- qcom,sm8550-camcc
- qcom,sm8650-camcc
+ - qcom,sm8750-cambistmclkcc
+ - qcom,sm8750-camcc
clocks:
items:
compatible:
contains:
enum:
+ - qcom,kaanapali-cambistmclkcc
+ - qcom,kaanapali-camcc
- qcom,sc8280xp-camcc
- qcom,sm8450-camcc
- qcom,sm8550-camcc
domains on Qualcomm SoCs.
See also::
+ include/dt-bindings/clock/qcom,kaanapali-gpucc.h
include/dt-bindings/clock/qcom,milos-gpucc.h
include/dt-bindings/clock/qcom,sar2130p-gpucc.h
include/dt-bindings/clock/qcom,sm4450-gpucc.h
properties:
compatible:
enum:
+ - qcom,kaanapali-gpucc
- qcom,milos-gpucc
- qcom,sar2130p-gpucc
- qcom,sm4450-gpucc
domains on SM8450.
See also:
+ include/dt-bindings/clock/qcom,kaanapali-videocc.h
include/dt-bindings/clock/qcom,sm8450-videocc.h
include/dt-bindings/clock/qcom,sm8650-videocc.h
include/dt-bindings/clock/qcom,sm8750-videocc.h
properties:
compatible:
enum:
+ - qcom,kaanapali-videocc
- qcom,sm8450-videocc
- qcom,sm8475-videocc
- qcom,sm8550-videocc
compatible:
contains:
enum:
+ - qcom,kaanapali-videocc
- qcom,sm8450-videocc
- qcom,sm8550-videocc
- qcom,sm8750-videocc
domains on SM8550, SM8650, SM8750 and few other platforms.
See also:
+ - include/dt-bindings/clock/qcom,kaanapali-dispcc.h
- include/dt-bindings/clock/qcom,sm8550-dispcc.h
- include/dt-bindings/clock/qcom,sm8650-dispcc.h
- include/dt-bindings/clock/qcom,sm8750-dispcc.h
properties:
compatible:
enum:
+ - qcom,kaanapali-dispcc
- qcom,sar2130p-dispcc
- qcom,sm8550-dispcc
- qcom,sm8650-dispcc
- description: USB4_1 PHY max PIPE clock source
- description: USB4_2 PHY PCIE PIPE clock source
- description: USB4_2 PHY max PIPE clock source
+ - description: UFS PHY RX Symbol 0 clock source
+ - description: UFS PHY RX Symbol 1 clock source
+ - description: UFS PHY TX Symbol 0 clock source
power-domains:
description:
<&usb4_1_phy_pcie_pipe_clk>,
<&usb4_1_phy_max_pipe_clk>,
<&usb4_2_phy_pcie_pipe_clk>,
- <&usb4_2_phy_max_pipe_clk>;
+ <&usb4_2_phy_max_pipe_clk>,
+ <&ufs_phy_rx_symbol_0>,
+ <&ufs_phy_rx_symbol_1>,
+ <&ufs_phy_tx_symbol_0>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
description: Output clock down spread in pcm (1/1000 of percent)
patternProperties:
- "^DIF[0-19]$":
+ "^DIF1?[0-9]$":
type: object
description:
Description of one of the outputs (DIF0..DIF19).
DIF0 {
renesas,slew-rate = <3000000>;
};
+
+ /* Not present on 9FGV0241, used for DT validation only */
+ DIF2 {
+ renesas,slew-rate = <2000000>;
+ };
+
+ DIF19 {
+ renesas,slew-rate = <3000000>;
+ };
};
};
- samsung,exynosautov920-cmu-hsi2
- samsung,exynosautov920-cmu-m2m
- samsung,exynosautov920-cmu-mfc
+ - samsung,exynosautov920-cmu-mfd
- samsung,exynosautov920-cmu-misc
- samsung,exynosautov920-cmu-peric0
- samsung,exynosautov920-cmu-peric1
- const: mfc
- const: wfd
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynosautov920-cmu-mfd
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (38.4 MHz)
+ - description: CMU_MFD NOC clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: noc
+
required:
- compatible
- "#clock-cells"
$id: http://devicetree.org/schemas/clock/spacemit,k1-pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: SpacemiT K1 PLL
+title: SpacemiT K1/K3 PLL
maintainers:
- Haylen Chu <heylenay@4d2.org>
properties:
compatible:
- const: spacemit,k1-pll
+ enum:
+ - spacemit,k1-pll
+ - spacemit,k3-pll
reg:
maxItems: 1
"#clock-cells":
const: 1
description:
- See <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
+ For K1 SoC, check <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
+ For K3 SoC, check <dt-bindings/clock/spacemit,k3-clocks.h> for valid indices.
required:
- compatible
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/connector/pcie-m2-m-connector.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PCIe M.2 Mechanical Key M Connector
+
+maintainers:
+ - Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
+
+description:
+ A PCIe M.2 M connector node represents a physical PCIe M.2 Mechanical Key M
+ connector. The Mechanical Key M connectors are used to connect SSDs to the
+ host system over PCIe/SATA interfaces. These connectors also offer optional
+ interfaces like USB, SMBus.
+
+properties:
+ compatible:
+ const: pcie-m2-m-connector
+
+ vpcie3v3-supply:
+ description: A phandle to the regulator for 3.3v supply.
+
+ vpcie1v8-supply:
+ description: A phandle to the regulator for VIO 1.8v supply.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ description: OF graph bindings modeling the interfaces exposed on the
+ connector. Since a single connector can have multiple interfaces, every
+ interface has an assigned OF graph port number as described below.
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: PCIe interface
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: SATA interface
+
+ port@2:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: USB 2.0 interface
+
+ anyOf:
+ - required:
+ - port@0
+ - required:
+ - port@1
+
+ i2c-parent:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: I2C interface
+
+ clocks:
+ description: 32.768 KHz Suspend Clock (SUSCLK) input from the host system to
+ the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.1 for
+ more details.
+ maxItems: 1
+
+ pedet-gpios:
+ description: GPIO input to PEDET signal. This signal is used by the host
+ systems to determine the communication protocol that the M.2 card uses;
+ SATA signaling (low) or PCIe signaling (high). Refer, PCI Express M.2
+ Specification r4.0, sec 3.3.4.2 for more details.
+ maxItems: 1
+
+ viocfg-gpios:
+ description: GPIO input to IO voltage configuration (VIO_CFG) signal. This
+ signal is used by the host systems to determine whether the card supports
+ an independent IO voltage domain for the sideband signals or not. Refer,
+ PCI Express M.2 Specification r4.0, sec 3.1.15.1 for more details.
+ maxItems: 1
+
+ pwrdis-gpios:
+ description: GPIO output to Power Disable (PWRDIS) signal. This signal is
+ used by the host system to disable power on the M.2 card. Refer, PCI
+ Express M.2 Specification r4.0, sec 3.3.5.2 for more details.
+ maxItems: 1
+
+ pln-gpios:
+ description: GPIO output to Power Loss Notification (PLN#) signal. This
+ signal is used by the host system to notify the M.2 card that the power
+ loss event is about to occur. Refer, PCI Express M.2 Specification r4.0,
+ sec 3.2.17.1 for more details.
+ maxItems: 1
+
+ plas3-gpios:
+ description: GPIO input to Power Loss Acknowledge (PLA_S3#) signal. This
+ signal is used by the host system to receive the acknowledgment of the M.2
+ card's preparation for power loss.
+ maxItems: 1
+
+required:
+ - compatible
+ - vpcie3v3-supply
+
+additionalProperties: false
+
+examples:
+ # PCI M.2 Key M connector for SSDs with PCIe interface
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ connector {
+ compatible = "pcie-m2-m-connector";
+ vpcie3v3-supply = <&vreg_nvme>;
+ i2c-parent = <&i2c0>;
+ pedet-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>;
+ viocfg-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ pwrdis-gpios = <&tlmm 97 GPIO_ACTIVE_HIGH>;
+ pln-gpios = <&tlmm 98 GPIO_ACTIVE_LOW>;
+ plas3-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0>;
+
+ endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&pcie6_port0_ep>;
+ };
+ };
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&usb_hs_ep>;
+ };
+ };
+ };
+ };
maxItems: 4
dependencies:
+ pd-disable: [typec-power-opmode]
sink-vdos-v1: [ sink-vdos ]
sink-vdos: [ sink-vdos-v1 ]
- description: v2 of CPUFREQ HW (EPSS)
items:
- enum:
+ - qcom,milos-cpufreq-epss
- qcom,qcs8300-cpufreq-epss
- qcom,qdu1000-cpufreq-epss
- qcom,sa8255p-cpufreq-epss
compatible:
contains:
enum:
+ - qcom,milos-cpufreq-epss
- qcom,qcs8300-cpufreq-epss
- qcom,sc7280-cpufreq-epss
- qcom,sm8250-cpufreq-epss
interrupts:
maxItems: 1
+ aspeed,ahbc:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ A phandle to the AHB controller node, which must be a syscon
+
required:
- compatible
- reg
- clocks
- interrupts
+ - aspeed,ahbc
additionalProperties: false
reg = <0x1e6fa000 0x400>, <0x1e710000 0x1800>;
interrupts = <160>;
clocks = <&syscon ASPEED_CLK_GATE_RSACLK>;
+ aspeed,ahbc = <&ahbc>;
};
- const: atmel,at91sam9g46-aes
- items:
- enum:
+ - microchip,lan9691-aes
- microchip,sam9x7-aes
- microchip,sama7d65-aes
- const: atmel,at91sam9g46-aes
- const: atmel,at91sam9g46-sha
- items:
- enum:
+ - microchip,lan9691-sha
- microchip,sam9x7-sha
- microchip,sama7d65-sha
- const: atmel,at91sam9g46-sha
properties:
compatible:
oneOf:
+ - items:
+ - const: marvell,armada-cp110-crypto
+ - const: inside-secure,safexcel-eip197b
+ - items:
+ - enum:
+ - marvell,armada-3700-crypto
+ - mediatek,mt7986-crypto
+ - const: inside-secure,safexcel-eip97ies
- const: inside-secure,safexcel-eip197b
- const: inside-secure,safexcel-eip197d
- const: inside-secure,safexcel-eip97ies
maxItems: 1
interrupts:
+ minItems: 4
maxItems: 6
interrupt-names:
+ minItems: 4
items:
- const: ring0
- const: ring1
minItems: 2
required:
- clock-names
+ - if:
+ properties:
+ compatible:
+ not:
+ contains:
+ const: mediatek,mt7986-crypto
+ then:
+ properties:
+ interrupts:
+ minItems: 6
+ interrupt-names:
+ minItems: 6
additionalProperties: false
items:
- enum:
- qcom,kaanapali-inline-crypto-engine
+ - qcom,milos-inline-crypto-engine
- qcom,qcs8300-inline-crypto-engine
- qcom,sa8775p-inline-crypto-engine
- qcom,sc7180-inline-crypto-engine
- qcom,ipq5424-trng
- qcom,ipq9574-trng
- qcom,kaanapali-trng
+ - qcom,milos-trng
- qcom,qcs615-trng
- qcom,qcs8300-trng
- qcom,sa8255p-trng
- qcom,sm8550-trng
- qcom,sm8650-trng
- qcom,sm8750-trng
+ - qcom,x1e80100-trng
- const: qcom,trng
reg:
The ZynqMP AES-GCM hardened cryptographic accelerator is used to
encrypt or decrypt the data with provided key and initialization vector.
+deprecated: true
+
properties:
compatible:
const: xlnx,zynqmp-aes
- compatible
- clocks
- ports
+ - reg
allOf:
- if:
ports:
properties:
port@2: false
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx6sx-ldb
+ then:
+ required:
+ - reg-names
additionalProperties: false
required:
- compatible
- reg
- - reset-gpios
- ports
additionalProperties: false
oneOf:
- items:
- enum:
+ - onnn,fin3385 # OnSemi FIN3385
- ti,ds90c185 # For the TI DS90C185 FPD-Link Serializer
- ti,ds90c187 # For the TI DS90C187 FPD-Link Serializer
- ti,sn75lvds83 # For the TI SN75LVDS83 FlatLink transmitter
interrupts:
maxItems: 1
+ clocks:
+ maxItems: 1
+
video-ports:
$ref: /schemas/types.yaml#/definitions/uint32
default: 0x230145
RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
up to four data lanes.
-allOf:
- - $ref: /schemas/display/dsi-controller.yaml#
-
properties:
compatible:
- items:
+ oneOf:
+ - items:
+ - enum:
+ - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
+ - renesas,r9a07g054-mipi-dsi # RZ/V2L
+ - const: renesas,rzg2l-mipi-dsi
+
+ - items:
+ - const: renesas,r9a09g056-mipi-dsi # RZ/V2N
+ - const: renesas,r9a09g057-mipi-dsi
+
- enum:
- - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
- - renesas,r9a07g054-mipi-dsi # RZ/V2L
- - const: renesas,rzg2l-mipi-dsi
+ - renesas,r9a09g057-mipi-dsi # RZ/V2H(P)
reg:
maxItems: 1
- const: debug
clocks:
- items:
- - description: DSI D-PHY PLL multiplied clock
- - description: DSI D-PHY system clock
- - description: DSI AXI bus clock
- - description: DSI Register access clock
- - description: DSI Video clock
- - description: DSI D-PHY Escape mode transmit clock
+ oneOf:
+ - items:
+ - description: DSI D-PHY PLL multiplied clock
+ - description: DSI D-PHY system clock
+ - description: DSI AXI bus clock
+ - description: DSI Register access clock
+ - description: DSI Video clock
+ - description: DSI D-PHY Escape mode transmit clock
+ - items:
+ - description: DSI D-PHY PLL reference clock
+ - description: DSI AXI bus clock
+ - description: DSI Register access clock
+ - description: DSI Video clock
+ - description: DSI D-PHY Escape mode transmit clock
clock-names:
- items:
- - const: pllclk
- - const: sysclk
- - const: aclk
- - const: pclk
- - const: vclk
- - const: lpclk
+ oneOf:
+ - items:
+ - const: pllclk
+ - const: sysclk
+ - const: aclk
+ - const: pclk
+ - const: vclk
+ - const: lpclk
+ - items:
+ - const: pllrefclk
+ - const: aclk
+ - const: pclk
+ - const: vclk
+ - const: lpclk
resets:
- items:
- - description: MIPI_DSI_CMN_RSTB
- - description: MIPI_DSI_ARESET_N
- - description: MIPI_DSI_PRESET_N
+ oneOf:
+ - items:
+ - description: MIPI_DSI_CMN_RSTB
+ - description: MIPI_DSI_ARESET_N
+ - description: MIPI_DSI_PRESET_N
+ - items:
+ - description: MIPI_DSI_ARESET_N
+ - description: MIPI_DSI_PRESET_N
reset-names:
- items:
- - const: rst
- - const: arst
- - const: prst
+ oneOf:
+ - items:
+ - const: rst
+ - const: arst
+ - const: prst
+ - items:
+ - const: arst
+ - const: prst
power-domains:
maxItems: 1
unevaluatedProperties: false
+allOf:
+ - $ref: ../dsi-controller.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g057-mipi-dsi
+ then:
+ properties:
+ clocks:
+ maxItems: 5
+
+ clock-names:
+ maxItems: 5
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ maxItems: 2
+ else:
+ properties:
+ clocks:
+ minItems: 6
+
+ clock-names:
+ minItems: 6
+
+ resets:
+ minItems: 3
+
+ reset-names:
+ minItems: 3
+
examples:
- |
#include <dt-bindings/clock/r9a07g044-cpg.h>
- const: adi,adv7123
- enum:
- adi,adv7123
+ - algoltek,ag6311
- asl-tek,cs5263
- dumb-vga-dac
- parade,ps185hdm
- 1 # 3.5dB pre-emphasis
- 2 # 6dB pre-emphasis
- oneOf:
+ anyOf:
- required:
- port@0
- required:
+++ /dev/null
-Android Goldfish framebuffer
-
-Android Goldfish framebuffer device used by Android emulator.
-
-Required properties:
-
-- compatible : should contain "google,goldfish-fb"
-- reg : <registers mapping>
-- interrupts : <interrupt mapping>
-
-Example:
-
- display-controller@1f008000 {
- compatible = "google,goldfish-fb";
- interrupts = <0x10>;
- reg = <0x1f008000 0x100>;
- };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/google,goldfish-fb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Android Goldfish Framebuffer
+
+maintainers:
+ - Kuan-Wei Chiu <visitorckw@gmail.com>
+
+description:
+ Android Goldfish framebuffer device used by Android emulator.
+
+properties:
+ compatible:
+ const: google,goldfish-fb
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ display@1f008000 {
+ compatible = "google,goldfish-fb";
+ reg = <0x1f008000 0x100>;
+ interrupts = <16>;
+ };
enum:
# these platforms support 2 streams MST on some interfaces,
# others are SST only
- - qcom,glymur-dp
- qcom,sc8280xp-dp
- qcom,x1e80100-dp
then:
minItems: 6
maxItems: 8
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ # these platforms support 2 streams MST on some interfaces,
+ # others are SST only, but all controllers have 4 ports
+ - qcom,glymur-dp
+ then:
+ properties:
+ reg:
+ minItems: 9
+ maxItems: 9
+ clocks:
+ minItems: 5
+ maxItems: 6
+ clocks-names:
+ minItems: 5
+ maxItems: 6
+
unevaluatedProperties: false
examples:
- items:
- enum:
- qcom,apq8064-dsi-ctrl
+ - qcom,kaanapali-dsi-ctrl
- qcom,msm8226-dsi-ctrl
- qcom,msm8916-dsi-ctrl
- qcom,msm8953-dsi-ctrl
- qcom,sm8650-dsi-ctrl
- qcom,sm8750-dsi-ctrl
- const: qcom,mdss-dsi-ctrl
+ - items:
+ - enum:
+ - qcom,qcs8300-dsi-ctrl
+ - const: qcom,sa8775p-dsi-ctrl
+ - const: qcom,mdss-dsi-ctrl
- enum:
- qcom,dsi-ctrl-6g-qcm2290
- qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible
compatible:
contains:
enum:
+ - qcom,kaanapali-dsi-ctrl
- qcom,sm8750-dsi-ctrl
then:
properties:
properties:
compatible:
- enum:
- - qcom,dsi-phy-7nm
- - qcom,dsi-phy-7nm-8150
- - qcom,sa8775p-dsi-phy-5nm
- - qcom,sar2130p-dsi-phy-5nm
- - qcom,sc7280-dsi-phy-7nm
- - qcom,sm6375-dsi-phy-7nm
- - qcom,sm8350-dsi-phy-5nm
- - qcom,sm8450-dsi-phy-5nm
- - qcom,sm8550-dsi-phy-4nm
- - qcom,sm8650-dsi-phy-4nm
- - qcom,sm8750-dsi-phy-3nm
+ oneOf:
+ - items:
+ - enum:
+ - qcom,dsi-phy-7nm
+ - qcom,dsi-phy-7nm-8150
+ - qcom,kaanapali-dsi-phy-3nm
+ - qcom,sa8775p-dsi-phy-5nm
+ - qcom,sar2130p-dsi-phy-5nm
+ - qcom,sc7280-dsi-phy-7nm
+ - qcom,sm6375-dsi-phy-7nm
+ - qcom,sm8350-dsi-phy-5nm
+ - qcom,sm8450-dsi-phy-5nm
+ - qcom,sm8550-dsi-phy-4nm
+ - qcom,sm8650-dsi-phy-4nm
+ - qcom,sm8750-dsi-phy-3nm
+ - items:
+ - enum:
+ - qcom,qcs8300-dsi-phy-5nm
+ - const: qcom,sa8775p-dsi-phy-5nm
reg:
items:
- const: amd,imageon
clocks:
- minItems: 2
+ minItems: 1
maxItems: 7
clock-names:
- minItems: 2
+ minItems: 1
maxItems: 7
reg:
- const: xo
description: GPUCC clocksource clock
+ required:
+ - clocks
+ - clock-names
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,adreno-612.0
+ then:
+ properties:
+ clocks:
+ items:
+ - description: GPU Core clock
+
+ clock-names:
+ items:
+ - const: core
+
+ reg:
+ minItems: 3
+ maxItems: 3
+
reg-names:
- minItems: 1
items:
- const: kgsl_3d0_reg_memory
+ - const: cx_mem
- const: cx_dbgc
required:
- clocks
- clock-names
- else:
- if:
- properties:
- compatible:
- contains:
- oneOf:
- - pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$'
- - pattern: '^qcom,adreno-[0-9a-f]{8}$'
-
- then: # Starting with A6xx, the clocks are usually defined in the GMU node
- properties:
- clocks: false
- clock-names: false
-
- reg-names:
- minItems: 1
- items:
- - const: kgsl_3d0_reg_memory
- - const: cx_mem
- - const: cx_dbgc
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,adreno-615.0
+ - qcom,adreno-618.0
+ - qcom,adreno-619.0
+ - qcom,adreno-621.0
+ - qcom,adreno-623.0
+ - qcom,adreno-630.2
+ - qcom,adreno-635.0
+ - qcom,adreno-640.1
+ - qcom,adreno-650.2
+ - qcom,adreno-660.1
+ - qcom,adreno-663.0
+ - qcom,adreno-680.1
+ - qcom,adreno-690.0
+ - qcom,adreno-730.1
+ - qcom,adreno-43030c00
+ - qcom,adreno-43050a01
+ - qcom,adreno-43050c01
+ - qcom,adreno-43051401
+
+ then: # Starting with A6xx, the clocks are usually defined in the GMU node
+ properties:
+ clocks: false
+ clock-names: false
+
+ reg-names:
+ minItems: 1
+ items:
+ - const: kgsl_3d0_reg_memory
+ - const: cx_mem
+ - const: cx_dbgc
examples:
- |
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+%YAML 1.2
+---
+
+$id: http://devicetree.org/schemas/display/msm/qcom,adreno-rgmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RGMU attached to certain Adreno GPUs
+
+maintainers:
+ - Rob Clark <robin.clark@oss.qualcomm.com>
+
+description:
+ RGMU (Reduced Graphics Management Unit) IP is present in some GPUs that
+ belong to Adreno A6xx family. It is a small state machine that helps to
+ toggle the GX GDSC (connected to CX rail) to implement IFPC feature and save
+ power.
+
+properties:
+ compatible:
+ items:
+ - const: qcom,adreno-rgmu-612.0
+ - const: qcom,adreno-rgmu
+
+ reg:
+ items:
+ - description: Core RGMU registers
+
+ clocks:
+ items:
+ - description: GMU clock
+ - description: GPU CX clock
+ - description: GPU AXI clock
+ - description: GPU MEMNOC clock
+ - description: GPU SMMU vote clock
+
+ clock-names:
+ items:
+ - const: gmu
+ - const: cxo
+ - const: axi
+ - const: memnoc
+ - const: smmu_vote
+
+ power-domains:
+ items:
+ - description: CX GDSC power domain
+ - description: GX GDSC power domain
+
+ power-domain-names:
+ items:
+ - const: cx
+ - const: gx
+
+ interrupts:
+ items:
+ - description: GMU OOB interrupt
+ - description: GMU interrupt
+
+ interrupt-names:
+ items:
+ - const: oob
+ - const: gmu
+
+ operating-points-v2: true
+ opp-table:
+ type: object
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - power-domains
+ - power-domain-names
+ - interrupts
+ - interrupt-names
+ - operating-points-v2
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,qcs615-gpucc.h>
+ #include <dt-bindings/clock/qcom,qcs615-gcc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ gmu@506a000 {
+ compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu";
+
+ reg = <0x05000000 0x90000>;
+
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+ clock-names = "gmu",
+ "cxo",
+ "axi",
+ "memnoc",
+ "smmu_vote";
+
+ power-domains = <&gpucc CX_GDSC>,
+ <&gpucc GX_GDSC>;
+ power-domain-names = "cx",
+ "gx";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "oob",
+ "gmu";
+
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+ };
+ };
};
};
- displayport-controller@ae90000 {
+ displayport-controller@af54000 {
compatible = "qcom,glymur-dp";
- reg = <0xae90000 0x200>,
- <0xae90200 0x200>,
- <0xae90400 0x600>,
- <0xae91000 0x400>,
- <0xae91400 0x400>;
+ reg = <0xaf54000 0x200>,
+ <0xaf54200 0x200>,
+ <0xaf55000 0xc00>,
+ <0xaf56000 0x400>,
+ <0xaf57000 0x400>,
+ <0xaf58000 0x400>,
+ <0xaf59000 0x400>,
+ <0xaf5a000 0x600>,
+ <0xaf5b000 0x600>;
interrupt-parent = <&mdss>;
interrupts = <12>;
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,kaanapali-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Kaanapali Display MDSS
+
+maintainers:
+ - Yongxing Mou <yongxing.mou@oss.qualcomm.com>
+ - Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
+
+description:
+ Kaanapali MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks
+ like DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,kaanapali-mdss
+
+ clocks:
+ items:
+ - description: Display AHB
+ - description: Display hf AXI
+ - description: Display core
+ - description: Display AHB SWI
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ items:
+ - description: Interconnect path from mdp0 port to the data bus
+ - description: Interconnect path from CPU to the reg bus
+
+ interconnect-names:
+ items:
+ - const: mdp0-mem
+ - const: cpu-cfg
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ const: qcom,kaanapali-dpu
+
+ "^dsi@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ contains:
+ const: qcom,kaanapali-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ const: qcom,kaanapali-dsi-phy-3nm
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/phy/phy-qcom-qmp.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ display-subsystem@9800000 {
+ compatible = "qcom,kaanapali-mdss";
+ reg = <0x09800000 0x1000>;
+ reg-names = "mdss";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&disp_cc_mdss_ahb_clk>,
+ <&gcc_disp_hf_axi_clk>,
+ <&disp_cc_mdss_mdp_clk>,
+ <&disp_cc_mdss_ahb_swi_clk>;
+ resets = <&disp_cc_mdss_core_bcr>;
+
+ power-domains = <&mdss_gdsc>;
+
+ iommus = <&apps_smmu 0x800 0x2>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ display-controller@9801000 {
+ compatible = "qcom,kaanapali-dpu";
+ reg = <0x09801000 0x1c8000>,
+ <0x09b16000 0x3000>;
+ reg-names = "mdp",
+ "vbif";
+
+ interrupts-extended = <&mdss 0>;
+
+ clocks = <&gcc_disp_hf_axi_clk>,
+ <&disp_cc_mdss_ahb_clk>,
+ <&disp_cc_mdss_mdp_lut_clk>,
+ <&disp_cc_mdss_mdp_clk>,
+ <&disp_cc_mdss_vsync_clk>;
+ clock-names = "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&disp_cc_mdss_vsync_clk>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&mdss_dsi1_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-156000000 {
+ opp-hz = /bits/ 64 <156000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>;
+ };
+
+ opp-207000000 {
+ opp-hz = /bits/ 64 <207000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-337000000 {
+ opp-hz = /bits/ 64 <337000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-417000000 {
+ opp-hz = /bits/ 64 <417000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-532000000 {
+ opp-hz = /bits/ 64 <532000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ required-opps = <&rpmhpd_opp_nom_l1>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ };
+ };
+ };
+
+ dsi@9ac0000 {
+ compatible = "qcom,kaanapali-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x09ac0000 0x1000>;
+ reg-names = "dsi_ctrl";
+
+ interrupts-extended = <&mdss 4>;
+
+ clocks = <&disp_cc_mdss_byte0_clk>,
+ <&disp_cc_mdss_byte0_intf_clk>,
+ <&disp_cc_mdss_pclk0_clk>,
+ <&disp_cc_mdss_esc0_clk>,
+ <&disp_cc_mdss_ahb_clk>,
+ <&gcc_disp_hf_axi_clk>,
+ <&mdss_dsi0_phy 1>,
+ <&mdss_dsi0_phy 0>,
+ <&disp_cc_esync0_clk>,
+ <&disp_cc_osc_clk>,
+ <&disp_cc_mdss_byte0_clk_src>,
+ <&disp_cc_mdss_pclk0_clk_src>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus",
+ "dsi_pll_pixel",
+ "dsi_pll_byte",
+ "esync",
+ "osc",
+ "byte_src",
+ "pixel_src";
+
+ operating-points-v2 = <&mdss_dsi_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ phys = <&mdss_dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dsi0_out: endpoint {
+ remote-endpoint = <&panel0_in>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
+
+ mdss_dsi_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>;
+ };
+
+ opp-250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-312500000 {
+ opp-hz = /bits/ 64 <312500000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@9ac1000 {
+ compatible = "qcom,kaanapali-dsi-phy-3nm";
+ reg = <0x09ac1000 0x1cc>,
+ <0x09ac1200 0x80>,
+ <0x09ac1500 0x400>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ clocks = <&disp_cc_mdss_ahb_clk>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface",
+ "ref";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+ };
+ };
- const: core
iommus:
- maxItems: 2
+ maxItems: 1
interconnects:
items:
interconnect-names = "mdp0-mem",
"cpu-cfg";
- iommus = <&apps_smmu 0x420 0x2>,
- <&apps_smmu 0x421 0x0>;
+ iommus = <&apps_smmu 0x420 0x2>;
ranges;
display-controller@5e01000 {
contains:
const: qcom,qcs8300-dp
+ "^dsi@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ contains:
+ const: qcom,qcs8300-dsi-ctrl
+
"^phy@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
contains:
- const: qcom,qcs8300-edp-phy
+ enum:
+ - qcom,qcs8300-dsi-phy-5nm
+ - qcom,qcs8300-edp-phy
required:
- compatible
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,qcs8300-gcc.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
remote-endpoint = <&mdss_dp0_in>;
};
};
+
+ port@1 {
+ reg = <1>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
};
mdp_opp_table: opp-table {
};
};
+ dsi@ae94000 {
+ compatible = "qcom,qcs8300-dsi-ctrl",
+ "qcom,sa8775p-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
+ reg = <0x0ae94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+ assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
+ phys = <&mdss_dsi0_phy>;
+
+ operating-points-v2 = <&dsi0_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ vdda-supply = <&vreg_l5a>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss0_dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss0_dsi0_out: endpoint { };
+ };
+ };
+
+ dsi0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@ae94400 {
+ compatible = "qcom,qcs8300-dsi-phy-5nm",
+ "qcom,sa8775p-dsi-phy-5nm";
+ reg = <0x0ae94400 0x200>,
+ <0x0ae94600 0x280>,
+ <0x0ae94900 0x27c>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ vdds-supply = <&vreg_l4a>;
+ };
+
mdss_dp0_phy: phy@aec2a00 {
compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy";
oneOf:
- enum:
- qcom,glymur-dpu
+ - qcom,kaanapali-dpu
- qcom,sa8775p-dpu
- qcom,sm8650-dpu
- qcom,sm8750-dpu
- Krzysztof Kozlowski <krzk@kernel.org>
description:
- SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
+ SM8750 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
DPU display controller, DSI and DP interfaces etc.
$ref: /schemas/display/msm/mdss-common.yaml#
compatible:
items:
- enum:
+ - anbernic,rg-ds-display-bottom
+ - anbernic,rg-ds-display-top
- chongzhou,cz101b4001
- kingdisplay,kd101ne3-40ti
- melfas,lmfbx101117480
$id: http://devicetree.org/schemas/display/panel/lg,sw43408.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: LG SW43408 1080x2160 DSI panel
+title: LG SW43408 AMOLED DDIC
maintainers:
- Casey Connolly <casey.connolly@linaro.org>
description:
- This panel is used on the Pixel 3, it is a 60hz OLED panel which
- required DSC (Display Stream Compression) and has rounded corners.
+ The SW43408 is display driver IC with connected panel.
+
+ LG LH546WF1-ED01 panel is used on the Pixel 3, it is a 60hz OLED panel
+ which required DSC (Display Stream Compression) and has rounded corners.
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
items:
+ - enum:
+ # LG 5.46 inch, 1080x2160 pixels, 18:9 ratio
+ - lg,sw43408-lh546wf1-ed01
- const: lg,sw43408
reg:
#size-cells = <0>;
panel@0 {
- compatible = "lg,sw43408";
+ compatible = "lg,sw43408-lh546wf1-ed01", "lg,sw43408";
reg = <0>;
vddi-supply = <&vreg_l14a_1p88>;
- panasonic,vvx10f004b00
# Panasonic 10" WUXGA TFT LCD panel
- panasonic,vvx10f034n00
+ # Samsung ltl106hl02 10.6" Full HD TFT LCD panel
+ - samsung,ltl106hl02-001
# Samsung s6e3fa7 1080x2220 based AMS559NK06 AMOLED panel
- samsung,s6e3fa7-ams559nk06
# Shangai Top Display Optoelectronics 7" TL070WSH30 1024x600 TFT LCD panel
- hannstar,hsd070pww1
# HannStar Display Corp. HSD100PXN1 10.1" XGA LVDS panel
- hannstar,hsd100pxn1
+ # HannStar Display Corp. HSD156JUW2 15.6" FHD (1920x1080) TFT LCD panel
+ - hannstar,hsd156juw2
# Hitachi Ltd. Corporation 9" WVGA (800x480) TFT LCD panel
- hit,tx23d38vm0caa
# Innolux AT043TN24 4.3" WQVGA TFT LCD panel
- innolux,g121x1-l03
# Innolux Corporation 12.1" G121XCE-L01 XGA (1024x768) TFT LCD panel
- innolux,g121xce-l01
+ # InnoLux 15.0" G150XGE-L05 XGA (1024x768) TFT LCD panel
+ - innolux,g150xge-l05
# InnoLux 15.6" FHD (1920x1080) TFT LCD panel
- innolux,g156hce-l01
# InnoLux 13.3" FHD (1920x1080) TFT LCD panel
properties:
compatible:
contains:
- const: innolux,g101ice-l01
+ enum:
+ - innolux,g101ice-l01
+ - yes-optoelectronics,ytc700tlag-05-201c
then:
properties:
data-mapping: false
title: Samsung S6E3FC2X01 AMOLED DDIC
-description: The S6E3FC2X01 is display driver IC with connected panel.
-
maintainers:
- David Heidelberg <david@ixit.cz>
+description: The S6E3FC2X01 is display driver IC with connected panel.
+
allOf:
- $ref: panel-common.yaml#
reg:
maxItems: 1
- reset-gpios: true
-
- port: true
-
- vddio-supply:
- description: VDD regulator
+ poc-supply:
+ description: POC regulator
vci-supply:
description: VCI regulator
- poc-supply:
- description: POC regulator
+ vddio-supply:
+ description: VDD regulator
required:
- compatible
- reset-gpios
- - vddio-supply
- - vci-supply
- poc-supply
+ - vci-supply
+ - vddio-supply
unevaluatedProperties: false
spi-cpol: true
spi-rx-bus-width:
- minimum: 0
- maximum: 1
+ items:
+ minimum: 0
+ maximum: 1
dc-gpios:
maxItems: 1
- rockchip,rk3228-dw-hdmi
- rockchip,rk3288-dw-hdmi
- rockchip,rk3328-dw-hdmi
+ - rockchip,rk3368-dw-hdmi
- rockchip,rk3399-dw-hdmi
- rockchip,rk3568-dw-hdmi
- rockchip,rk3288-mipi-dsi
- rockchip,rk3368-mipi-dsi
- rockchip,rk3399-mipi-dsi
+ - rockchip,rk3506-mipi-dsi
- rockchip,rk3568-mipi-dsi
- rockchip,rv1126-mipi-dsi
- const: snps,dw-mipi-dsi
- rockchip,px30-mipi-dsi
- rockchip,rk3128-mipi-dsi
- rockchip,rk3368-mipi-dsi
+ - rockchip,rk3506-mipi-dsi
- rockchip,rk3568-mipi-dsi
- rockchip,rv1126-mipi-dsi
- const: main
- const: hpd
+ no-hpd:
+ type: boolean
+ description:
+ The HPD pin is not present or used for another purpose, and the EDID
+ must be polled instead to determine if a device is attached.
+
phys:
maxItems: 1
description: The HDMI/eDP PHY
- rockchip,rk3368-vop
- rockchip,rk3399-vop-big
- rockchip,rk3399-vop-lit
+ - rockchip,rk3506-vop
- rockchip,rv1126-vop
reg:
};
};
};
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ display@0 {
+ compatible = "sitronix,st7571";
+ reg = <0>;
+ reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+ width-mm = <37>;
+ height-mm = <27>;
+
+ panel-timing {
+ hactive = <128>;
+ vactive = <96>;
+ hback-porch = <0>;
+ vback-porch = <0>;
+ clock-frequency = <0>;
+ hfront-porch = <0>;
+ hsync-len = <0>;
+ vfront-porch = <0>;
+ vsync-len = <0>;
+ };
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/sitronix,st7920.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sitronix ST7920 LCD Display Controllers
+
+maintainers:
+ - Iker Pedrosa <ikerpedrosam@gmail.com>
+
+description:
+ The Sitronix ST7920 is a controller for monochrome dot-matrix graphical LCDs,
+ most commonly used for 128x64 pixel displays.
+
+properties:
+ compatible:
+ const: sitronix,st7920
+
+ reg:
+ maxItems: 1
+
+ vdd-supply:
+ description: Regulator that provides 5V Vdd power supply
+
+ reset-gpios:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 600000
+
+required:
+ - compatible
+ - reg
+ - spi-max-frequency
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ display@0 {
+ compatible = "sitronix,st7920";
+ reg = <0>;
+ vdd-supply = <®_5v>;
+ reset-gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
+ spi-max-frequency = <600000>;
+ spi-cs-high;
+ };
+ };
enum:
- nvidia,tegra114-mipi
- nvidia,tegra124-mipi
+ - nvidia,tegra132-mipi
- nvidia,tegra210-mipi
- nvidia,tegra186-mipi
compatible:
oneOf:
- - const: nvidia,tegra20-vi
- - const: nvidia,tegra30-vi
- - const: nvidia,tegra114-vi
- - const: nvidia,tegra124-vi
+ - enum:
+ - nvidia,tegra20-vi
+ - nvidia,tegra114-vi
+ - nvidia,tegra124-vi
+ - nvidia,tegra210-vi
+ - nvidia,tegra186-vi
+ - nvidia,tegra194-vi
+
+ - items:
+ - const: nvidia,tegra30-vi
+ - const: nvidia,tegra20-vi
+
- items:
- const: nvidia,tegra132-vi
- const: nvidia,tegra124-vi
- - const: nvidia,tegra210-vi
- - const: nvidia,tegra186-vi
- - const: nvidia,tegra194-vi
reg:
maxItems: 1
properties:
compatible:
- enum:
- - nvidia,tegra20-vip
+ oneOf:
+ - enum:
+ - nvidia,tegra20-vip
+
+ - items:
+ - const: nvidia,tegra30-vip
+ - const: nvidia,tegra20-vip
ports:
$ref: /schemas/graph.yaml#/properties/ports
$id: http://devicetree.org/schemas/dma/arm-pl08x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: ARM PrimeCells PL080 and PL081 and derivatives DMA controller
+title: ARM PrimeCell PL080 and PL081 and derivatives DMA controller
maintainers:
- Vinod Koul <vkoul@kernel.org>
- microchip,sam9x7-dma
- const: atmel,sama5d4-dma
- items:
- - const: microchip,sama7d65-dma
+ - enum:
+ - microchip,lan9691-dma
+ - microchip,sama7d65-dma
- const: microchip,sama7g5-dma
"#dma-cells":
title: MediaTek UART APDMA controller
maintainers:
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
- Long Cheng <long.cheng@mediatek.com>
description: |
- enum:
- mediatek,mt2712-uart-dma
- mediatek,mt6795-uart-dma
+ - mediatek,mt8173-uart-dma
+ - mediatek,mt8183-uart-dma
- mediatek,mt8365-uart-dma
- mediatek,mt8516-uart-dma
- const: mediatek,mt6577-uart-dma
+ - items:
+ - enum:
+ - mediatek,mt7988-uart-dma
+ - mediatek,mt8186-uart-dma
+ - mediatek,mt8188-uart-dma
+ - mediatek,mt8192-uart-dma
+ - mediatek,mt8195-uart-dma
+ - const: mediatek,mt6835-uart-dma
+ - items:
+ - enum:
+ - mediatek,mt6991-uart-dma
+ - mediatek,mt8196-uart-dma
+ - const: mediatek,mt6985-uart-dma
- enum:
- mediatek,mt6577-uart-dma
+ - mediatek,mt6795-uart-dma
+ - mediatek,mt6835-uart-dma
+ - mediatek,mt6985-uart-dma
reg:
minItems: 1
mediatek,dma-33bits:
type: boolean
+ deprecated: true
description: Enable 33-bits UART APDMA support
required:
Should contain all of the per-channel DMA interrupts in
ascending order with respect to the DMA channel index.
minItems: 1
- maxItems: 32
+ maxItems: 64
clocks:
description: Must contain one entry for the ADMA module clock
reg:
items:
- description: Full address space range of DMA registers.
+ interrupts:
+ maxItems: 22
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra186-adma
+ then:
+ properties:
+ interrupts:
+ maxItems: 32
- if:
properties:
- qcom,sm6350-gpi-dma
- items:
- enum:
+ - qcom,glymur-gpi-dma
+ - qcom,kaanapali-gpi-dma
- qcom,milos-gpi-dma
- qcom,qcm2290-gpi-dma
- qcom,qcs8300-gpi-dma
description:
Interrupt lines for each GPI instance
minItems: 1
- maxItems: 13
+ maxItems: 16
"#dma-cells":
const: 3
- items:
- enum:
- renesas,r9a09g047-dmac # RZ/G3E
+ - renesas,r9a09g056-dmac # RZ/V2N
- const: renesas,r9a09g057-dmac
- const: renesas,r9a09g057-dmac # RZ/V2H(P)
properties:
compatible:
- enum:
- - snps,axi-dma-1.01a
- - intel,kmb-axi-dma
- - starfive,jh7110-axi-dma
- - starfive,jh8100-axi-dma
+ oneOf:
+ - enum:
+ - snps,axi-dma-1.01a
+ - intel,kmb-axi-dma
+ - starfive,jh7110-axi-dma
+ - starfive,jh8100-axi-dma
+ - items:
+ - const: altr,agilex5-axi-dma
+ - const: snps,axi-dma-1.01a
reg:
minItems: 1
title: MediaTek mt8186 DSP core
maintainers:
- - Tinghan Shen <tinghan.shen@mediatek.com>
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
description: |
MediaTek mt8186 SoC contains a DSP core used for
- const: atmel,24c02
- items:
- enum:
+ - belling,bl24c04a
- giantec,gt24c04a
- onnn,cat24c04
- onnn,cat24c05
- items:
- enum:
- belling,bl24c16a
+ - belling,bl24c16f
- renesas,r1ex24016
- const: atmel,24c16
- items:
- items:
- enum:
- belling,bl24s64
+ - giantec,gt24p64a
- onnn,n24s64b
- puya,p24c64f
- const: atmel,24c64
- enum:
- giantec,gt24p128e
- giantec,gt24p128f
+ - puya,p24c128f
- renesas,r1ex24128
- samsung,s524ad0xd1
- const: atmel,24c128
- fujitsu,mb85rs1mt
- fujitsu,mb85rs256
- fujitsu,mb85rs64
+ - microchip,25aa010a
- microchip,at25160bn
- microchip,25lc040
- st,m95m02
examples:
- |+
#include <dt-bindings/interrupt-controller/irq.h>
- i2c1 {
+ i2c {
clock-frequency = <400000>;
#address-cells = <1>;
+++ /dev/null
-Turris Mox rWTM firmware driver
-
-Required properties:
- - compatible : Should be "cznic,turris-mox-rwtm"
- - mboxes : Must contain a reference to associated mailbox
-
-This device tree node should be used on Turris Mox, or potentially another A3700
-compatible device running the Mox's rWTM firmware in the secure processor (for
-example it is possible to flash this firmware into EspressoBin).
-
-Example:
-
- firmware {
- turris-mox-rwtm {
- compatible = "cznic,turris-mox-rwtm";
- mboxes = <&rwtm 0>;
- status = "okay";
- };
- };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/cznic,turris-mox-rwtm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: CZ.NIC Turris Mox rWTM firmware
+
+maintainers:
+ - Marek Behún <kabel@kernel.org>
+
+description:
+ This device tree node should be used on Turris Mox, or potentially another
+ A3700 compatible device running the Mox's rWTM firmware in the secure
+ processor (for example it is possible to flash this firmware into
+ EspressoBin).
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: marvell,armada-3700-rwtm-firmware
+ - const: cznic,turris-mox-rwtm
+ - const: marvell,armada-3700-rwtm-firmware
+
+ mboxes:
+ maxItems: 1
+
+required:
+ - compatible
+ - mboxes
+
+additionalProperties: false
+
+examples:
+ - |
+ turris-mox-rwtm {
+ compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
+ mboxes = <&rwtm 0>;
+ };
- description: TX0 MU channel
- description: RX0 MU channel
- description: optional MU channel for general interrupt
- - items:
+ - deprecated: true
+ items:
- description: TX0 MU channel
- description: TX1 MU channel
- description: TX2 MU channel
- description: RX1 MU channel
- description: RX2 MU channel
- description: RX3 MU channel
- - items:
+ - deprecated: true
+ items:
- description: TX0 MU channel
- description: TX1 MU channel
- description: TX2 MU channel
- const: tx0
- const: rx0
- const: gip3
- - items:
+ - deprecated: true
+ items:
- const: tx0
- const: tx1
- const: tx2
- const: rx1
- const: rx2
- const: rx3
- - items:
+ - deprecated: true
+ items:
- const: tx0
- const: tx1
- const: tx2
firmware {
system-controller {
compatible = "fsl,imx-scu";
- mbox-names = "tx0", "tx1", "tx2", "tx3",
- "rx0", "rx1", "rx2", "rx3",
- "gip3";
- mboxes = <&lsio_mu1 0 0 &lsio_mu1 0 1 &lsio_mu1 0 2 &lsio_mu1 0 3
- &lsio_mu1 1 0 &lsio_mu1 1 1 &lsio_mu1 1 2 &lsio_mu1 1 3
+ mbox-names = "tx0", "rx0", "gip3";
+ mboxes = <&lsio_mu1 0 0
+ &lsio_mu1 1 0
&lsio_mu1 3 3>;
clock-controller {
interrupts-extended = <&gpa0 6 IRQ_TYPE_LEVEL_LOW>;
regulators {
- LDO1 {
+ ldo1m {
regulator-name = "vdd_ldo1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
// ...
- BUCK1 {
+ buck8m {
regulator-name = "vdd_mif";
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <1300000>;
type: object
pinctrl:
- $ref: /schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
description: The pinctrl node provides access to pinconfig and pincontrol
functionality available in firmware.
type: object
used to encrypt or decrypt the data with provided key and initialization
vector.
type: object
+ deprecated: true
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: xlnx,zynqmp-firmware
+ then:
+ properties:
+ pinctrl:
+ $ref: /schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
+ else:
+ properties:
+ pinctrl:
+ $ref: /schemas/pinctrl/xlnx,versal-pinctrl.yaml#
required:
- compatible
#include <dt-bindings/power/xlnx-zynqmp-power.h>
firmware {
zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
#power-domain-cells = <1>;
soc-nvmem {
compatible = "xlnx,zynqmp-nvmem-fw";
compatible = "xlnx,versal-fpga";
};
+ pinctrl {
+ compatible = "xlnx,versal-pinctrl";
+ };
+
xlnx_aes: zynqmp-aes {
compatible = "xlnx,zynqmp-aes";
};
+++ /dev/null
-Android Goldfish Audio
-
-Android goldfish audio device generated by android emulator.
-
-Required properties:
-
-- compatible : should contain "google,goldfish-audio" to match emulator
-- reg : <registers mapping>
-- interrupts : <interrupt mapping>
-
-Example:
-
- goldfish_audio@9030000 {
- compatible = "google,goldfish-audio";
- reg = <0x9030000 0x100>;
- interrupts = <0x4>;
- };
+++ /dev/null
-Android Goldfish Battery
-
-Android goldfish battery device generated by android emulator.
-
-Required properties:
-
-- compatible : should contain "google,goldfish-battery" to match emulator
-- reg : <registers mapping>
-- interrupts : <interrupt mapping>
-
-Example:
-
- goldfish_battery@9020000 {
- compatible = "google,goldfish-battery";
- reg = <0x9020000 0x1000>;
- interrupts = <0x3>;
- };
+++ /dev/null
-Android Goldfish Events Keypad
-
-Android goldfish events keypad device generated by android emulator.
-
-Required properties:
-
-- compatible : should contain "google,goldfish-events-keypad" to match emulator
-- reg : <registers mapping>
-- interrupts : <interrupt mapping>
-
-Example:
-
- goldfish-events@9040000 {
- compatible = "google,goldfish-events-keypad";
- reg = <0x9040000 0x1000>;
- interrupts = <0x5>;
- };
+++ /dev/null
-Android Goldfish QEMU Pipe
-
-Android pipe virtual device generated by android emulator.
-
-Required properties:
-
-- compatible : should contain "google,android-pipe" to match emulator
-- reg : <registers mapping>
-- interrupts : <interrupt mapping>
-
-Example:
-
- android_pipe@a010000 {
- compatible = "google,android-pipe";
- reg = <ff018000 0x2000>;
- interrupts = <0x12>;
- };
+++ /dev/null
-Android Goldfish TTY
-
-Android goldfish tty device generated by android emulator.
-
-Required properties:
-
-- compatible : should contain "google,goldfish-tty" to match emulator
-- reg : <registers mapping>
-- interrupts : <interrupt mapping>
-
-Example:
-
- goldfish_tty@1f004000 {
- compatible = "google,goldfish-tty";
- reg = <0x1f004000 0x1000>;
- interrupts = <0xc>;
- };
- Andrew Jeffery <andrew@aj.id.au>
description:
- This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC,
+ This SGPIO controller is for ASPEED AST2400, AST2500, AST2600 and AST2700 SoC,
+ AST2700 have two sgpio master both with 256 pins,
AST2600 have two sgpio master one with 128 pins another one with 80 pins,
AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial
GPIO pins can be programmed to support the following options
- aspeed,ast2400-sgpio
- aspeed,ast2500-sgpio
- aspeed,ast2600-sgpiom
+ - aspeed,ast2700-sgpiom
reg:
maxItems: 1
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/gpio-line-mux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: GPIO line mux
+
+maintainers:
+ - Jonas Jelonek <jelonek.jonas@gmail.com>
+
+description: |
+ A GPIO controller to provide virtual GPIOs for a 1-to-many input-only mapping
+ backed by a single shared GPIO and a multiplexer. A simple illustrated
+ example is:
+
+ +----- A
+ IN /
+ <-----o------- B
+ / |\
+ | | +----- C
+ | | \
+ | | +--- D
+ | |
+ M1 M0
+
+ MUX CONTROL
+
+ M1 M0 IN
+ 0 0 A
+ 0 1 B
+ 1 0 C
+ 1 1 D
+
+ This can be used in case a real GPIO is connected to multiple inputs and
+ controlled by a multiplexer, and another subsystem/driver does not work
+ directly with the multiplexer subsystem.
+
+properties:
+ compatible:
+ const: gpio-line-mux
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-line-mux-states:
+ description: Mux states corresponding to the virtual GPIOs.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+ gpio-line-names: true
+
+ mux-controls:
+ maxItems: 1
+ description:
+ Phandle to the multiplexer to control access to the GPIOs.
+
+ ngpios: false
+
+ muxed-gpios:
+ maxItems: 1
+ description:
+ GPIO which is the '1' in 1-to-many and is shared by the virtual GPIOs
+ and controlled via the mux.
+
+required:
+ - compatible
+ - gpio-controller
+ - gpio-line-mux-states
+ - mux-controls
+ - muxed-gpios
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/mux/mux.h>
+
+ sfp_gpio_mux: mux-controller-1 {
+ compatible = "gpio-mux";
+ mux-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>,
+ <&gpio0 1 GPIO_ACTIVE_HIGH>;
+ #mux-control-cells = <0>;
+ idle-state = <MUX_IDLE_AS_IS>;
+ };
+
+ sfp1_gpio: sfp-gpio-1 {
+ compatible = "gpio-line-mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ mux-controls = <&sfp_gpio_mux>;
+ muxed-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
+
+ gpio-line-mux-states = <0>, <1>, <3>;
+ };
+
+ sfp1: sfp-p1 {
+ compatible = "sff,sfp";
+
+ i2c-bus = <&sfp1_i2c>;
+ los-gpios = <&sfp1_gpio 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sfp1_gpio 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sfp1_gpio 2 GPIO_ACTIVE_HIGH>;
+ };
compatible:
enum:
- brcm,bcm6345-gpio
+ - intel,ixp4xx-expansion-bus-mmio-gpio
- ni,169445-nand-gpio
+ - opencores,gpio
- wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller
- - intel,ixp4xx-expansion-bus-mmio-gpio
big-endian: true
- ti,tca9538
- ti,tca9539
- ti,tca9554
+ - ti,tcal6408
+ - ti,tcal6416
reg:
maxItems: 1
const: 2
"#interrupt-cells":
- const: 1
+ const: 2
ngpios:
description:
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
- #interrupt-cells = <1>;
+ #interrupt-cells = <2>;
interrupts = <53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
- nvidia,tegra234-gpio
- nvidia,tegra234-gpio-aon
- nvidia,tegra256-gpio
+ - nvidia,tegra264-gpio
+ - nvidia,tegra264-gpio-uphy
+ - nvidia,tegra264-gpio-aon
reg-names:
items:
ports, in the order the HW manual describes them. The number of entries
required varies depending on compatible value.
+ wakeup-parent:
+ description: Phandle to the parent interrupt controller used for wake-up. On
+ Tegra, this typically references the PMC interrupt controller.
+
gpio-controller: true
gpio-ranges:
- nvidia,tegra194-gpio
- nvidia,tegra234-gpio
- nvidia,tegra256-gpio
+ - nvidia,tegra264-gpio
+ - nvidia,tegra264-gpio-uphy
then:
properties:
interrupts:
- nvidia,tegra186-gpio-aon
- nvidia,tegra194-gpio-aon
- nvidia,tegra234-gpio-aon
+ - nvidia,tegra264-gpio-aon
then:
properties:
interrupts:
minItems: 1
maxItems: 4
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra264-gpio
+ - nvidia,tegra264-gpio-uphy
+ - nvidia,tegra264-gpio-aon
+ then:
+ required:
+ - wakeup-parent
+
required:
- compatible
- reg
pattern: "^gpio@[0-9a-f]+$"
compatible:
- const: spacemit,k1-gpio
+ enum:
+ - spacemit,k1-gpio
+ - spacemit,k3-gpio
reg:
maxItems: 1
- stacks
- const: stacks
+ nvmem-cells:
+ items:
+ - description: bitmask of functional shader cores
+
+ nvmem-cell-names:
+ items:
+ - const: shader-present
+
mali-supply: true
operating-points-v2: true
properties:
clocks:
minItems: 3
+ nvmem-cells: false
+ nvmem-cell-names: false
power-domains:
maxItems: 1
power-domain-names: false
- const: core
- const: stacks
required:
+ - nvmem-cells
+ - nvmem-cell-names
- power-domains
examples:
<GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "job", "mmu", "gpu";
+ nvmem-cells = <&shader_present>;
+ nvmem-cell-names = "shader-present";
power-domains = <&gpufreq>;
};
- const: img,img-rogue
- items:
- enum:
+ - ti,am62p-gpu
- ti,j721s2-gpu
- const: img,img-bxs-4-64
- const: img,img-rogue
contains:
enum:
- ti,am62-gpu
+ - ti,am62p-gpu
- ti,j721s2-gpu
then:
properties:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/aspeed,ast2400-pwm-tacho.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED AST2400/AST2500 PWM and Fan Tacho controller
+
+maintainers:
+ - Joel Stanley <joel@jms.id.au>
+ - Andrew Jeffery <andrew@codeconstruct.com.au>
+
+description: >
+ The ASPEED PWM controller can support up to 8 PWM outputs. The ASPEED Fan
+ Tacho controller can support up to 16 Fan tachometer inputs.
+
+ There can be up to 8 fans supported. Each fan can have 1 PWM output and
+ 1-2 Fan tach inputs.
+
+properties:
+ compatible:
+ enum:
+ - aspeed,ast2400-pwm-tacho
+ - aspeed,ast2500-pwm-tacho
+
+ reg:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ '#cooling-cells':
+ const: 2
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+patternProperties:
+ '^fan@[0-7]$':
+ description: Fan subnode
+ type: object
+ additionalProperties: false
+
+ properties:
+ reg:
+ description: PWM source port index (0 = PWM A, ..., 7 = PWM H)
+ maximum: 7
+
+ cooling-levels:
+ description: PWM duty cycle values for cooling states
+ $ref: /schemas/types.yaml#/definitions/uint8-array
+ minItems: 1
+ maxItems: 16 # Should be enough
+
+ aspeed,fan-tach-ch:
+ description: Fan tachometer input channel
+ $ref: /schemas/types.yaml#/definitions/uint8-array
+ minItems: 1
+ maxItems: 2
+ items:
+ maximum: 15
+
+ required:
+ - reg
+ - aspeed,fan-tach-ch
+
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+ - clocks
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/aspeed-clock.h>
+
+ fan-controller@1e786000 {
+ compatible = "aspeed,ast2500-pwm-tacho";
+ reg = <0x1e786000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #cooling-cells = <2>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_PWM>;
+
+ fan@0 {
+ reg = <0x00>;
+ cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x00>;
+ };
+
+ fan@1 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x01 0x02>;
+ };
+ };
+++ /dev/null
-ASPEED AST2400/AST2500 PWM and Fan Tacho controller device driver
-
-The ASPEED PWM controller can support upto 8 PWM outputs. The ASPEED Fan Tacho
-controller can support upto 16 Fan tachometer inputs.
-
-There can be upto 8 fans supported. Each fan can have one PWM output and
-one/two Fan tach inputs.
-
-Required properties for pwm-tacho node:
-- #address-cells : should be 1.
-
-- #size-cells : should be 1.
-
-- #cooling-cells: should be 2.
-
-- reg : address and length of the register set for the device.
-
-- pinctrl-names : a pinctrl state named "default" must be defined.
-
-- pinctrl-0 : phandle referencing pin configuration of the PWM ports.
-
-- compatible : should be "aspeed,ast2400-pwm-tacho" for AST2400 and
- "aspeed,ast2500-pwm-tacho" for AST2500.
-
-- clocks : phandle to clock provider with the clock number in the second cell
-
-- resets : phandle to reset controller with the reset number in the second cell
-
-fan subnode format:
-===================
-Under fan subnode there can upto 8 child nodes, with each child node
-representing a fan. If there are 8 fans each fan can have one PWM port and
-one/two Fan tach inputs.
-For PWM port can be configured cooling-levels to create cooling device.
-Cooling device could be bound to a thermal zone for the thermal control.
-
-Required properties for each child node:
-- reg : should specify PWM source port.
- integer value in the range 0 to 7 with 0 indicating PWM port A and
- 7 indicating PWM port H.
-
-- cooling-levels: PWM duty cycle values in a range from 0 to 255
- which correspond to thermal cooling states.
-
-- aspeed,fan-tach-ch : should specify the Fan tach input channel.
- integer value in the range 0 through 15, with 0 indicating
- Fan tach channel 0 and 15 indicating Fan tach channel 15.
- At least one Fan tach input channel is required.
-
-Examples:
-
-pwm_tacho: pwmtachocontroller@1e786000 {
- #address-cells = <1>;
- #size-cells = <1>;
- #cooling-cells = <2>;
- reg = <0x1E786000 0x1000>;
- compatible = "aspeed,ast2500-pwm-tacho";
- clocks = <&syscon ASPEED_CLK_APB>;
- resets = <&syscon ASPEED_RESET_PWM>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>;
-
- fan@0 {
- reg = <0x00>;
- cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
- aspeed,fan-tach-ch = /bits/ 8 <0x00>;
- };
-
- fan@1 {
- reg = <0x01>;
- aspeed,fan-tach-ch = /bits/ 8 <0x01 0x02>;
- };
-};
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/iei,wt61p803-puzzle-hwmon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: IEI WT61P803 PUZZLE MCU HWMON module from IEI Integration Corp.
+
+maintainers:
+ - Luka Kovacic <luka.kovacic@sartura.hr>
+
+description: |
+ This module is a part of the IEI WT61P803 PUZZLE MFD device. For more details
+ see Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml.
+
+ The HWMON module is a sub-node of the MCU node in the Device Tree.
+
+properties:
+ compatible:
+ const: iei,wt61p803-puzzle-hwmon
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+patternProperties:
+ '^fan-group@[0-1]$':
+ type: object
+ additionalProperties: false
+
+ properties:
+ reg:
+ minimum: 0
+ maximum: 1
+ description:
+ Fan group ID
+
+ '#cooling-cells':
+ const: 2
+
+ cooling-levels:
+ minItems: 1
+ maxItems: 255
+ description:
+ Cooling levels for the fans (PWM value mapping)
+
+ required:
+ - reg
+ - '#cooling-cells'
+ - cooling-levels
+
+required:
+ - compatible
+ - '#address-cells'
+ - '#size-cells'
+
+additionalProperties: false
properties:
compatible:
enum:
- - kontron,sa67mcu-hwmon
- kontron,sl28cpld-fan
reg:
properties:
compatible:
- enum:
- - microchip,sparx5-temp
+ oneOf:
+ - const: microchip,sparx5-temp
+ - items:
+ - enum:
+ - microchip,lan9691-temp
+ - const: microchip,sparx5-temp
reg:
maxItems: 1
title: Sensirion SHTC1 Humidity and Temperature Sensor IC
maintainers:
- - Christopher Ruehl chris.ruehl@gtsys.com.hk
+ - Christopher Ruehl <chris.ruehl@gtsys.com.hk>
description: |
The SHTC1, SHTW1 and SHTC3 are digital humidity and temperature sensors
$id: http://devicetree.org/schemas/hwmon/ti,tmp108.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: TMP108/P3T1085(NXP) temperature sensor
+title: TMP108/P3T1035/P3T1085/P3T2030 temperature sensor
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
- The TMP108/P3T1085(NXP) is a digital-output temperature sensor with a
- dynamically-programmable limit window, and under- and overtemperature
- alert functions.
+ The TMP108 or NXP P3T Family (P3T1035, P3T1085 and P3T2030) is a digital-
+ output temperature sensor with a dynamically-programmable limit window,
+ and under- and over-temperature alert functions.
- P3T1085(NXP) support I3C.
+ NXP P3T Family (P3T1035, P3T1085 and P3T2030) supports I3C.
Datasheets:
https://www.ti.com/product/TMP108
https://www.nxp.com/docs/en/data-sheet/P3T1085UK.pdf
+ https://www.nxp.com/docs/en/data-sheet/P3T1035XUK_P3T2030XUK.pdf
properties:
compatible:
- enum:
- - nxp,p3t1085
- - ti,tmp108
+ oneOf:
+ - items:
+ - const: nxp,p3t2030
+ - const: nxp,p3t1035
+ - const: nxp,p3t1035
+ - const: nxp,p3t1085
+ - const: ti,tmp108
interrupts:
items:
- microchip,sam9x60-i2c
- items:
- enum:
+ - microchip,lan9691-i2c
- microchip,sama7d65-i2c
- microchip,sama7g5-i2c
- microchip,sam9x7-i2c
- enum:
- mediatek,mt6878-i2c
- mediatek,mt6991-i2c
+ - mediatek,mt8189-i2c
- mediatek,mt8196-i2c
- const: mediatek,mt8188-i2c
- items:
- enum:
- qcom,kaanapali-cci
- qcom,qcm2290-cci
+ - qcom,qcs8300-cci
- qcom,sa8775p-cci
- qcom,sc7280-cci
- qcom,sc8280xp-cci
enum:
- qcom,kaanapali-cci
- qcom,qcm2290-cci
+ - qcom,qcs8300-cci
- qcom,sm8750-cci
then:
properties:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/silabs,cp2112.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: CP2112 HID USB to SMBus/I2C Bridge
+
+maintainers:
+ - Danny Kaehn <danny.kaehn@plexus.com>
+
+description:
+ The CP2112 is a USB HID device which includes an integrated I2C controller
+ and 8 GPIO pins. Its GPIO pins can each be configured as inputs, open-drain
+ outputs, or push-pull outputs.
+
+properties:
+ compatible:
+ const: usb10c4,ea90
+
+ reg:
+ maxItems: 1
+ description: The USB port number
+
+ interrupt-controller: true
+ "#interrupt-cells":
+ const: 2
+
+ gpio-controller: true
+ "#gpio-cells":
+ const: 2
+
+ gpio-line-names:
+ minItems: 1
+ maxItems: 8
+
+ i2c:
+ description: The SMBus/I2C controller node for the CP2112
+ $ref: /schemas/i2c/i2c-controller.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-frequency:
+ minimum: 10000
+ default: 100000
+ maximum: 400000
+
+patternProperties:
+ "-hog(-[0-9]+)?$":
+ type: object
+
+ required:
+ - gpio-hog
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
+
+ usb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cp2112: device@1 {
+ compatible = "usb10c4,ea90";
+ reg = <1>;
+
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #gpio-cells = <2>;
+ gpio-line-names = "CP2112_SDA", "CP2112_SCL", "TEST2",
+ "TEST3","TEST4", "TEST5", "TEST6";
+
+ fan-rst-hog {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "FAN_RST";
+ };
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sda-gpios = <&cp2112 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&cp2112 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ temp@48 {
+ compatible = "national,lm75";
+ reg = <0x48>;
+ };
+ };
+ };
+ };
title: Synopsys DesignWare APB I2C Controller
maintainers:
- - Jarkko Nikula <jarkko.nikula@linux.intel.com>
+ - Mika Westerberg <mika.westerberg@linux.intel.com>
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
default: 400000
maximum: 3300000
+ resets:
+ maxItems: 1
+
required:
- compatible
- reg
wakeup-source: true
+ power-domains:
+ maxItems: 1
+
access-controllers:
minItems: 1
maxItems: 2
maximum: 102040816
spi-rx-bus-width:
- enum: [1, 2, 4]
+ maxItems: 2
+ # all lanes must have the same width
+ oneOf:
+ - contains:
+ const: 1
+ - contains:
+ const: 2
+ - contains:
+ const: 4
vdd-5v-supply: true
vdd-1v8-supply: true
unevaluatedProperties: false
+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - adi,ad4030-24
+ - adi,ad4032-24
+ then:
+ properties:
+ spi-rx-bus-width:
+ maxItems: 1
+
examples:
- |
#include <dt-bindings/gpio/gpio.h>
reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
};
};
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad4630-24";
+ reg = <0>;
+ spi-max-frequency = <80000000>;
+ spi-rx-bus-width = <4>, <4>;
+ vdd-5v-supply = <&supply_5V>;
+ vdd-1v8-supply = <&supply_1_8V>;
+ vio-supply = <&supply_1_8V>;
+ ref-supply = <&supply_5V>;
+ cnv-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2025 Analog Devices Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad4062.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD4062 ADC family device driver
+
+maintainers:
+ - Jorge Marques <jorge.marques@analog.com>
+
+description: |
+ Analog Devices AD4062 Single Channel Precision SAR ADC family
+
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad4060.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad4062.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,ad4060
+ - adi,ad4062
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ Two pins are available that can be configured as either a general purpose
+ digital output, device enable signal (used to synchronise other parts of
+ the signal chain with ADC sampling), device ready (GP1 only) or various
+ interrupt signals. If intended for use as a GPIO or device enable, will not
+ present here.
+ minItems: 1
+ items:
+ - description:
+ GP0 pin, cannot be configured as DEV_RDY.
+ - description:
+ GP1 pin, can be configured to any setting.
+
+ interrupt-names:
+ minItems: 1
+ items:
+ - const: gp0
+ - const: gp1
+
+ gpio-controller:
+ description:
+ Marks the device node as a GPIO controller. GPs not listed as interrupts
+ are exposed as a GPO.
+
+ '#gpio-cells':
+ const: 2
+ description:
+ The first cell is the GPIO number and the second cell specifies
+ GPIO flags, as defined in <dt-bindings/gpio/gpio.h>.
+
+ vdd-supply:
+ description: Analog power supply.
+
+ vio-supply:
+ description: Digital interface logic power supply.
+
+ ref-supply:
+ description:
+ Reference voltage to set the ADC full-scale range. If not present,
+ vdd-supply is used as the reference voltage.
+
+required:
+ - compatible
+ - reg
+ - vdd-supply
+ - vio-supply
+
+allOf:
+ - $ref: /schemas/i3c/i3c.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i3c {
+ #address-cells = <3>;
+ #size-cells = <0>;
+
+ adc@0,2ee007c0000 {
+ reg = <0x0 0x2ee 0x7c0000>;
+ vdd-supply = <&vdd>;
+ vio-supply = <&vio>;
+ ref-supply = <&ref>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <0 0 IRQ_TYPE_EDGE_RISING>,
+ <0 1 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "gp0", "gp1";
+ };
+ };
+
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i3c {
+ #address-cells = <3>;
+ #size-cells = <0>;
+
+ adc@0,2ee007c0000 {
+ reg = <0x0 0x2ee 0x7c0000>;
+ vdd-supply = <&vdd>;
+ vio-supply = <&vio>;
+ ref-supply = <&ref>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad4134.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD4134 ADC
+
+maintainers:
+ - Marcelo Schmitt <marcelo.schmitt@analog.com>
+
+description: |
+ The AD4134 is a quad channel, low noise, simultaneous sampling, precision
+ analog-to-digital converter (ADC).
+ Specifications can be found at:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad4134.pdf
+
+$ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+ compatible:
+ enum:
+ - adi,ad4134
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 50000000
+
+ avdd5-supply:
+ description: A 5V supply that powers the chip's analog circuitry.
+
+ dvdd5-supply:
+ description: A 5V supply that powers the chip's digital circuitry.
+
+ iovdd-supply:
+ description:
+ A 1.8V supply that sets the logic levels for the digital interface pins.
+
+ refin-supply:
+ description:
+ A 4.096V or 5V supply that serves as reference for ADC conversions.
+
+ avdd1v8-supply:
+ description: A 1.8V supply used by the analog circuitry.
+
+ dvdd1v8-supply:
+ description: A 1.8V supply used by the digital circuitry.
+
+ clkvdd-supply:
+ description: A 1.8V supply for the chip's clock management circuit.
+
+ ldoin-supply:
+ description:
+ A 2.6V to 5.5V supply that generates 1.8V for AVDD1V8, DVDD1V8, and CLKVDD
+ pins.
+
+ clocks:
+ maxItems: 1
+ description:
+ Required external clock source. Can specify either a crystal or CMOS clock
+ source. If an external crystal is set, connect the CLKSEL pin to IOVDD.
+ Otherwise, connect the CLKSEL pin to IOGND and the external CMOS clock
+ signal to the XTAL2/CLKIN pin.
+
+ clock-names:
+ enum:
+ - xtal
+ - clkin
+ default: clkin
+
+ '#clock-cells':
+ const: 0
+
+ clock-output-names:
+ maxItems: 1
+
+ regulators:
+ type: object
+ description:
+ list of regulators provided by this controller.
+
+ properties:
+ vcm-output:
+ $ref: /schemas/regulator/regulator.yaml#
+ type: object
+ unevaluatedProperties: false
+
+ additionalProperties: false
+
+ reset-gpios:
+ maxItems: 1
+
+ powerdown-gpios:
+ description:
+ Active low GPIO connected to the /PDN pin. Forces the device into full
+ power-down mode when brought low. Pull this input to IOVDD for normal
+ operation.
+ maxItems: 1
+
+ odr-gpios:
+ description:
+ GPIO connected to ODR pin. Used to sample ADC data in minimum I/O mode.
+ maxItems: 1
+
+ adi,asrc-mode:
+ $ref: /schemas/types.yaml#/definitions/string
+ description:
+ Asynchronous Sample Rate Converter (ASRC) operation mode control input.
+ Describes whether the MODE pin is set to a high level (for master mode
+ operation) or to a low level (for slave mode operation).
+ enum: [ high, low ]
+ default: low
+
+ adi,dclkio:
+ description:
+ DCLK pin I/O direction control for when the device operates in Pin Control
+ Slave Mode or in SPI Control Mode. Describes if DEC0/DCLKIO pin is at a
+ high level (which configures DCLK as an output) or to set to a low level
+ (configuring DCLK for input).
+ enum: [ out, in ]
+ default: in
+
+ adi,dclkmode:
+ description:
+ DCLK mode control for when the device operates in Pin Control Slave Mode
+ or in SPI Control Mode. Describes whether the DEC1/DCLKMODE pin is set to
+ a high level (configuring the DCLK to operate in free running mode) or
+ to a low level (to configure DCLK to operate in gated mode).
+ enum: [ free-running, gated ]
+ default: gated
+
+required:
+ - compatible
+ - reg
+ - avdd5-supply
+ - dvdd5-supply
+ - iovdd-supply
+ - refin-supply
+ - clocks
+ - clock-names
+
+oneOf:
+ - required:
+ - ldoin-supply
+ - required:
+ - avdd1v8-supply
+ - dvdd1v8-supply
+ - clkvdd-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad4134";
+ reg = <0>;
+
+ spi-max-frequency = <1000000>;
+
+ reset-gpios = <&gpio0 86 GPIO_ACTIVE_LOW>;
+ odr-gpios = <&gpio0 87 GPIO_ACTIVE_HIGH>;
+ powerdown-gpios = <&gpio0 88 GPIO_ACTIVE_LOW>;
+
+ clocks = <&sys_clk>;
+ clock-names = "clkin";
+
+ avdd5-supply = <&avdd5>;
+ dvdd5-supply = <&dvdd5>;
+ iovdd-supply = <&iovdd>;
+ refin-supply = <&refin>;
+ avdd1v8-supply = <&avdd1v8>;
+ dvdd1v8-supply = <&dvdd1v8>;
+ clkvdd-supply = <&clkvdd>;
+
+ regulators {
+ vcm_reg: vcm-output {
+ regulator-name = "ad4134-vcm";
+ };
+ };
+
+ };
+ };
+...
spi-cpha: true
spi-rx-bus-width:
- minimum: 1
- maximum: 4
+ items:
+ minimum: 1
+ maximum: 4
avdd-supply:
description: Analog power supply.
$id: http://devicetree.org/schemas/iio/adc/adi,ad7768-1.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Analog Devices AD7768-1 ADC device driver
+title: Analog Devices AD7768-1 ADC family
maintainers:
- Michael Hennerich <michael.hennerich@analog.com>
description: |
- Datasheet at:
- https://www.analog.com/media/en/technical-documentation/data-sheets/ad7768-1.pdf
+ Analog Devices AD7768-1 24-Bit Single Channel Low Power sigma-delta ADC family
+
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad7768-1.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/adaq7767-1.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/adaq7768-1.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/adaq7769-1.pdf
properties:
compatible:
- const: adi,ad7768-1
+ enum:
+ - adi,ad7768-1
+ - adi,adaq7767-1
+ - adi,adaq7768-1
+ - adi,adaq7769-1
reg:
maxItems: 1
description:
ADC reference voltage supply
+ adi,aaf-gain-bp:
+ description: |
+ Specifies the gain applied by the Analog Anti-Aliasing Filter (AAF)
+ to the ADC input in basis points (one hundredth of a percent).
+ The hardware gain is determined by which input pin(s) the signal goes
+ through into the AAF. The possible connections are:
+ * For the ADAQ7767-1: Input connected to IN1±, IN2± or IN3±.
+ * For the ADAQ7769-1: OUT_PGA pin connected to IN1_AAF+, IN2_AAF+,
+ or IN3_AAF+.
+ enum: [1430, 3640, 10000]
+ default: 10000
+
+ pga-gpios:
+ description:
+ GAIN 0, GAIN1 and GAIN2 pins for gain selection. For devices that have
+ PGA configuration input pins, pga-gpios must be defined.
+ minItems: 3
+ maxItems: 3
+
adi,sync-in-gpios:
maxItems: 1
description:
allOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml#
+ # AAF Gain property only applies to ADAQ7767-1 and ADAQ7769-1 devices
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,adaq7767-1
+ - adi,adaq7769-1
+ then:
+ required:
+ - adi,aaf-gain-bp
+ else:
+ properties:
+ adi,aaf-gain-bp: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,adaq7768-1
+ - adi,adaq7769-1
+ then:
+ required:
+ - pga-gpios
+ else:
+ properties:
+ pga-gpios: false
+
unevaluatedProperties: false
examples:
All the parts support the register map described by Application Note AN-877
https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD9211.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/AD9265.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/AD9434.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/AD9467.pdf
properties:
compatible:
enum:
+ - adi,ad9211
- adi,ad9265
- adi,ad9434
- adi,ad9467
Input clock used to derive the sample clock. Expected to be the
SoC's APB clock.
+ interrupts:
+ maxItems: 1
+
resets:
maxItems: 1
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/nxp,s32g2-sar-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP Successive Approximation ADC
+
+description:
+ The NXP SAR ADC provides fast and accurate analog-to-digital
+ conversion using the Successive Approximation Register (SAR) method.
+ It has 12-bit resolution with 8 input channels. Conversions can be
+ launched in software or using hardware triggers. It supports
+ continuous and one-shot modes with separate registers.
+
+maintainers:
+ - Daniel Lezcano <daniel.lezcano@kernel.org>
+
+properties:
+ compatible:
+ oneOf:
+ - const: nxp,s32g2-sar-adc
+ - items:
+ - const: nxp,s32g3-sar-adc
+ - const: nxp,s32g2-sar-adc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ dmas:
+ maxItems: 1
+
+ dma-names:
+ const: rx
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - dmas
+ - dma-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ adc@401f8000 {
+ compatible = "nxp,s32g2-sar-adc";
+ reg = <0x401f8000 0x1000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 0x41>;
+ dmas = <&edma0 0 32>;
+ dma-names = "rx";
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,ads1018.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI ADS1018/ADS1118 SPI analog to digital converter
+
+maintainers:
+ - Kurt Borja <kuurtb@gmail.com>
+
+description: |
+ The ADS1018/ADS1118 is a precision, low-power, 12-bit/16-bit, analog to
+ digital converter (ADC). It integrates a programmable gain amplifier (PGA),
+ internal voltage reference, oscillator and high-accuracy temperature sensor.
+
+ Datasheets:
+ - ADS1018: https://www.ti.com/lit/ds/symlink/ads1018.pdf
+ - ADS1118: https://www.ti.com/lit/ds/symlink/ads1118.pdf
+
+properties:
+ compatible:
+ enum:
+ - ti,ads1018
+ - ti,ads1118
+
+ reg:
+ maxItems: 1
+
+ vdd-supply: true
+
+ spi-max-frequency:
+ maximum: 4000000
+
+ spi-cpha: true
+
+ interrupts:
+ description: DOUT/DRDY (Data Out/Data Ready) line.
+ maxItems: 1
+
+ drdy-gpios:
+ description:
+ Extra GPIO line connected to DOUT/DRDY (Data Out/Data Ready). This allows
+ distinguishing between interrupts triggered by the data-ready signal and
+ interrupts triggered by an SPI transfer.
+ maxItems: 1
+
+ '#io-channel-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - vdd-supply
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,ads1118";
+ reg = <0>;
+
+ spi-max-frequency = <4000000>;
+ spi-cpha;
+
+ vdd-supply = <&vdd_3v3_reg>;
+
+ interrupts-extended = <&gpio 14 IRQ_TYPE_EDGE_FALLING>;
+ drdy-gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,ads131m02.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments ADS131M0x 2-, 3-, 4-, 6- and 8-Channel ADCs
+
+maintainers:
+ - Oleksij Rempel <o.rempel@pengutronix.de>
+
+description: |
+ The ADS131M0x are a family of multichannel, simultaneous sampling,
+ 24-bit, delta-sigma, analog-to-digital converters (ADCs) with a
+ built-in programmable gain amplifier (PGA) and internal reference.
+ Communication with the ADC chip is via SPI.
+
+ Datasheets:
+ - ADS131M02: https://www.ti.com/lit/ds/symlink/ads131m02.pdf
+ - ADS131M03: https://www.ti.com/lit/ds/symlink/ads131m03.pdf
+ - ADS131M04: https://www.ti.com/lit/ds/symlink/ads131m04.pdf
+ - ADS131M06: https://www.ti.com/lit/ds/symlink/ads131m06.pdf
+ - ADS131M08: https://www.ti.com/lit/ds/symlink/ads131m08.pdf
+
+properties:
+ compatible:
+ enum:
+ - ti,ads131m02
+ - ti,ads131m03
+ - ti,ads131m04
+ - ti,ads131m06
+ - ti,ads131m08
+
+ reg:
+ description: SPI chip select number.
+
+ clocks:
+ description:
+ Phandle to the external clock source required by the ADC's CLKIN pin.
+ The datasheet recommends specific frequencies based on the desired power
+ mode (e.g., 8.192 MHz for High-Resolution mode).
+ maxItems: 1
+
+ avdd-supply:
+ description: Analog power supply (AVDD).
+
+ dvdd-supply:
+ description: Digital power supply (DVDD).
+
+ interrupts:
+ description: DRDY (Data Ready) output signal.
+ maxItems: 1
+
+ reset-gpios:
+ description: Optional RESET signal.
+ maxItems: 1
+
+ clock-names:
+ description:
+ Indicates if a crystal oscillator (XTAL) or CMOS signal is connected
+ (CLKIN). Note that XTAL mode is only supported on ADS131M06 and ADS131M08.
+ enum: [xtal, clkin]
+
+ refin-supply:
+ description: Optional external reference supply (REFIN).
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - avdd-supply
+ - dvdd-supply
+
+patternProperties:
+ "^channel@[0-7]$":
+ type: object
+ $ref: /schemas/iio/adc/adc.yaml#
+ description: Properties for a single ADC channel.
+
+ properties:
+ reg:
+ description: The channel index (0-7).
+ minimum: 0
+ maximum: 7 # Max channels on ADS131M08
+
+ label: true
+
+ required:
+ - reg
+
+ unevaluatedProperties: false
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+ - if:
+ # 20-pin devices: M02, M03, M04
+ # These do not support XTAL or REFIN.
+ properties:
+ compatible:
+ enum:
+ - ti,ads131m02
+ - ti,ads131m03
+ - ti,ads131m04
+ then:
+ properties:
+ clock-names:
+ const: clkin
+ refin-supply: false
+
+ - if:
+ # ADS131M02: 2 channels max (0-1)
+ properties:
+ compatible:
+ contains:
+ const: ti,ads131m02
+ then:
+ patternProperties:
+ "^channel@[0-1]$":
+ properties:
+ reg:
+ maximum: 1
+ "^channel@[2-7]$": false
+
+ - if:
+ # ADS131M03: 3 channels max (0-2)
+ properties:
+ compatible:
+ contains:
+ const: ti,ads131m03
+ then:
+ patternProperties:
+ "^channel@[0-2]$":
+ properties:
+ reg:
+ maximum: 2
+ "^channel@[3-7]$": false
+
+ - if:
+ # ADS131M04: 4 channels max (0-3)
+ properties:
+ compatible:
+ contains:
+ const: ti,ads131m04
+ then:
+ patternProperties:
+ "^channel@[0-3]$":
+ properties:
+ reg:
+ maximum: 3
+ "^channel@[4-7]$": false
+
+ - if:
+ # ADS131M06: 6 channels max (0-5)
+ properties:
+ compatible:
+ contains:
+ const: ti,ads131m06
+ then:
+ patternProperties:
+ "^channel@[0-5]$":
+ properties:
+ reg:
+ maximum: 5
+ "^channel@[6-7]$": false
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/stm32mp1-clks.h>
+
+ spi1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,ads131m02";
+ reg = <0>;
+ spi-max-frequency = <8000000>;
+
+ clocks = <&rcc CK_MCO2>;
+ clock-names = "clkin";
+
+ avdd-supply = <&vdd_ana>;
+ dvdd-supply = <&vdd_dig>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ label = "input_voltage";
+ };
+
+ channel@1 {
+ reg = <1>;
+ label = "input_current";
+ };
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/amplifiers/adi,adl8113.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices ADL8113 Low Noise Amplifier with integrated bypass switches
+
+maintainers:
+ - Antoniu Miclaus <antoniu.miclaus@analog.com>
+
+description: |
+ The ADL8113 is a 10MHz to 12GHz Low Noise Amplifier with integrated bypass
+ switches controlled by two GPIO pins (VA and VB). The device supports four
+ operation modes:
+ - Internal Amplifier: VA=0, VB=0 - Signal passes through the internal LNA
+ - Internal Bypass: VA=1, VB=1 - Signal bypasses through internal path
+ - External Bypass A: VA=0, VB=1 - Signal routes from RFIN to OUT_A and from IN_A to RFOUT
+ - External Bypass B: VA=1, VB=0 - Signal routes from RFIN to OUT_B and from IN_B to RFOUT
+
+ https://www.analog.com/en/products/adl8113.html
+
+properties:
+ compatible:
+ const: adi,adl8113
+
+ vdd1-supply: true
+
+ vdd2-supply: true
+
+ vss2-supply: true
+
+ ctrl-gpios:
+ items:
+ - description: VA control pin
+ - description: VB control pin
+
+ adi,external-bypass-a-gain-db:
+ description:
+ Gain in dB of external amplifier connected to bypass path A (OUT_A/IN_A).
+ When specified, this gain value becomes selectable via the hardwaregain
+ attribute and automatically routes through the external A path.
+
+ adi,external-bypass-b-gain-db:
+ description:
+ Gain in dB of external amplifier connected to bypass path B (OUT_B/IN_B).
+ When specified, this gain value becomes selectable via the hardwaregain
+ attribute and automatically routes through the external B path.
+
+required:
+ - compatible
+ - ctrl-gpios
+ - vdd1-supply
+ - vdd2-supply
+ - vss2-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ /* Basic configuration with only internal paths */
+ amplifier {
+ compatible = "adi,adl8113";
+ ctrl-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>,
+ <&gpio 23 GPIO_ACTIVE_HIGH>;
+ vdd1-supply = <&vdd1_5v>;
+ vdd2-supply = <&vdd2_3v3>;
+ vss2-supply = <&vss2_neg>;
+ };
+
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ /* Configuration with external bypass amplifiers */
+ amplifier {
+ compatible = "adi,adl8113";
+ ctrl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>,
+ <&gpio 25 GPIO_ACTIVE_HIGH>;
+ vdd1-supply = <&vdd1_5v>;
+ vdd2-supply = <&vdd2_3v3>;
+ vss2-supply = <&vss2_neg>;
+ adi,external-bypass-a-gain-db = <20>; /* 20dB external amp on path A */
+ adi,external-bypass-b-gain-db = <6>; /* 6dB external amp on path B */
+ };
+...
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/adi,max22007.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices MAX22007 DAC
+
+maintainers:
+ - Janani Sunil <janani.sunil@analog.com>
+
+description:
+ The MAX22007 is a quad-channel, 12-bit digital-to-analog converter (DAC)
+ with integrated precision output amplifiers and current output capability.
+ Each channel can be independently configured for voltage or current output.
+ Datasheet available at https://www.analog.com/en/products/max22007.html
+
+$ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+ compatible:
+ const: adi,max22007
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 500000
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ vdd-supply:
+ description: Low-Voltage Power Supply from +2.7V to +5.5V.
+
+ hvdd-supply:
+ description:
+ Positive High-Voltage Power Supply from +8V to (HVSS +24V) for
+ the Output Channels.
+
+ hvss-supply:
+ description:
+ Optional Negative High-Voltage Power Supply from -2V to 0V for the Output
+ Channels. For most applications HVSS can be connected to GND (0V), but for
+ applications requiring output down to true 0V or 0mA, connect to a -2V supply.
+
+ reset-gpios:
+ maxItems: 1
+ description:
+ Active low GPIO.
+
+patternProperties:
+ "^channel@[0-3]$":
+ $ref: /schemas/iio/dac/dac.yaml#
+ type: object
+ description:
+ Represents the external channels which are connected to the DAC.
+
+ properties:
+ reg:
+ description: Channel number
+ items:
+ minimum: 0
+ maximum: 3
+
+ adi,ch-func:
+ description:
+ Channel output type. Use CH_FUNC_VOLTAGE_OUTPUT for voltage
+ output or CH_FUNC_CURRENT_OUTPUT for current output.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2]
+
+ required:
+ - reg
+ - adi,ch-func
+
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - vdd-supply
+ - hvdd-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/iio/addac/adi,ad74413r.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dac@0 {
+ compatible = "adi,max22007";
+ reg = <0>;
+ spi-max-frequency = <500000>;
+ reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&vdd_reg>;
+ hvdd-supply = <&hvdd_reg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ adi,ch-func = <CH_FUNC_VOLTAGE_OUTPUT>;
+ };
+
+ channel@1 {
+ reg = <1>;
+ adi,ch-func = <CH_FUNC_CURRENT_OUTPUT>;
+ };
+ };
+ };
+...
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/microchip,mcp47feb02.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MCP47F(E/V)B(0/1/2)(1/2/4/8) DAC with I2C Interface Families
+
+maintainers:
+ - Ariana Lazar <ariana.lazar@microchip.com>
+
+description: |
+ Datasheet for MCP47FEB01, MCP47FEB11, MCP47FEB21, MCP47FEB02, MCP47FEB12,
+ MCP47FEB22 can be found here:
+ https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/20005375A.pdf
+ Datasheet for MCP47FVB01, MCP47FVB11, MCP47FVB21, MCP47FVB02, MCP47FVB12,
+ MCP47FVB22 can be found here:
+ https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/20005405A.pdf
+ Datasheet for MCP47FEB04, MCP47FEB14, MCP47FEB24, MCP47FEB08, MCP47FEB18,
+ MCP47FEB28, MCP47FVB04, MCP47FVB14, MCP47FVB24, MCP47FVB08, MCP47FVB18,
+ MCP47FVB28 can be found here:
+ https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/ProductDocuments/DataSheets/MCP47FXBX48-Data-Sheet-DS200006368A.pdf
+
+ +------------+--------------+-------------+-------------+------------+
+ | Device | Resolution | Channels | Vref number | Memory |
+ |------------|--------------|-------------|-------------|------------|
+ | MCP47FEB01 | 8-bit | 1 | 1 | EEPROM |
+ | MCP47FEB11 | 10-bit | 1 | 1 | EEPROM |
+ | MCP47FEB21 | 12-bit | 1 | 1 | EEPROM |
+ |------------|--------------|-------------|-------------|------------|
+ | MCP47FEB02 | 8-bit | 2 | 1 | EEPROM |
+ | MCP47FEB12 | 10-bit | 2 | 1 | EEPROM |
+ | MCP47FEB22 | 12-bit | 2 | 1 | EEPROM |
+ |------------|--------------|-------------|-------------|------------|
+ | MCP47FVB01 | 8-bit | 1 | 1 | RAM |
+ | MCP47FVB11 | 10-bit | 1 | 1 | RAM |
+ | MCP47FVB21 | 12-bit | 1 | 1 | RAM |
+ |------------|--------------|-------------|-------------|------------|
+ | MCP47FVB02 | 8-bit | 2 | 1 | RAM |
+ | MCP47FVB12 | 10-bit | 2 | 1 | RAM |
+ | MCP47FVB22 | 12-bit | 2 | 1 | RAM |
+ |------------|--------------|-------------|-------------|------------|
+ | MCP47FVB04 | 8-bit | 4 | 2 | RAM |
+ | MCP47FVB14 | 10-bit | 4 | 2 | RAM |
+ | MCP47FVB24 | 12-bit | 4 | 2 | RAM |
+ |------------|--------------|-------------|-------------|------------|
+ | MCP47FVB08 | 8-bit | 8 | 2 | RAM |
+ | MCP47FVB18 | 10-bit | 8 | 2 | RAM |
+ | MCP47FVB28 | 12-bit | 8 | 2 | RAM |
+ |------------|--------------|-------------|-------------|------------|
+ | MCP47FEB04 | 8-bit | 4 | 2 | EEPROM |
+ | MCP47FEB14 | 10-bit | 4 | 2 | EEPROM |
+ | MCP47FEB24 | 12-bit | 4 | 2 | EEPROM |
+ |------------|--------------|-------------|-------------|------------|
+ | MCP47FEB08 | 8-bit | 8 | 2 | EEPROM |
+ | MCP47FEB18 | 10-bit | 8 | 2 | EEPROM |
+ | MCP47FEB28 | 12-bit | 8 | 2 | EEPROM |
+ +------------+--------------+-------------+-------------+------------+
+
+properties:
+ compatible:
+ enum:
+ - microchip,mcp47feb01
+ - microchip,mcp47feb11
+ - microchip,mcp47feb21
+ - microchip,mcp47feb02
+ - microchip,mcp47feb12
+ - microchip,mcp47feb22
+ - microchip,mcp47fvb01
+ - microchip,mcp47fvb11
+ - microchip,mcp47fvb21
+ - microchip,mcp47fvb02
+ - microchip,mcp47fvb12
+ - microchip,mcp47fvb22
+ - microchip,mcp47fvb04
+ - microchip,mcp47fvb14
+ - microchip,mcp47fvb24
+ - microchip,mcp47fvb08
+ - microchip,mcp47fvb18
+ - microchip,mcp47fvb28
+ - microchip,mcp47feb04
+ - microchip,mcp47feb14
+ - microchip,mcp47feb24
+ - microchip,mcp47feb08
+ - microchip,mcp47feb18
+ - microchip,mcp47feb28
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ vdd-supply:
+ description:
+ Provides power to the chip and it could be used as reference voltage. The
+ voltage is used to calculate scale. For parts without EEPROM at powerup
+ this will be the selected as voltage reference.
+
+ vref-supply:
+ description: |
+ Vref pin (it could be found as Vref0 into the datasheet) may be used as a
+ voltage reference when this supply is specified. The internal reference
+ will be taken into account for voltage reference besides VDD if this supply
+ does not exist.
+
+ This supply will be voltage reference for the following outputs:
+ - for single-channel device: Vout0;
+ - for dual-channel device: Vout0, Vout1;
+ - for quad-channel device: Vout0, Vout2;
+ - for octal-channel device: Vout0, Vout2, Vout6, Vout8;
+
+ vref1-supply:
+ description: |
+ Vref1 pin may be used as a voltage reference when this supply is specified.
+ The internal reference will be taken into account for voltage reference
+ beside VDD if this supply does not exist.
+
+ This supply will be voltage reference for the following outputs:
+ - for quad-channel device: Vout1, Vout3;
+ - for octal-channel device: Vout1, Vout3, Vout5, Vout7;
+
+ lat-gpios:
+ description:
+ LAT pin to be used as a hardware trigger to synchronously update the DAC
+ channels. The pin is active Low. It could be also found as LAT0 in
+ datasheet.
+ maxItems: 1
+
+ lat1-gpios:
+ description:
+ LAT1 pin to be used as a hardware trigger to synchronously update the odd
+ DAC channels on devices with 4 and 8 channels. The pin is active Low.
+ maxItems: 1
+
+ microchip,vref-buffered:
+ type: boolean
+ description:
+ Enable buffering of the external Vref/Vref0 pin in cases where the
+ external reference voltage does not have sufficient current capability in
+ order not to drop it’s voltage when connected to the internal resistor
+ ladder circuit.
+
+ microchip,vref1-buffered:
+ type: boolean
+ description:
+ Enable buffering of the external Vref1 pin in cases where the external
+ reference voltage does not have sufficient current capability in order not
+ to drop it’s voltage when connected to the internal resistor ladder
+ circuit.
+
+patternProperties:
+ "^channel@[0-7]$":
+ $ref: dac.yaml
+ type: object
+ description: Voltage output channel.
+
+ properties:
+ reg:
+ description: The channel number.
+ minItems: 1
+ maxItems: 8
+
+ label:
+ description: Unique name to identify which channel this is.
+
+ required:
+ - reg
+
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - vdd-supply
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - microchip,mcp47feb01
+ - microchip,mcp47feb11
+ - microchip,mcp47feb21
+ - microchip,mcp47fvb01
+ - microchip,mcp47fvb11
+ - microchip,mcp47fvb21
+ then:
+ properties:
+ lat1-gpios: false
+ vref1-supply: false
+ microchip,vref1-buffered: false
+ channel@0:
+ properties:
+ reg:
+ const: 0
+ patternProperties:
+ "^channel@[1-7]$": false
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - microchip,mcp47feb02
+ - microchip,mcp47feb12
+ - microchip,mcp47feb22
+ - microchip,mcp47fvb02
+ - microchip,mcp47fvb12
+ - microchip,mcp47fvb22
+ then:
+ properties:
+ lat1-gpios: false
+ vref1-supply: false
+ microchip,vref1-buffered: false
+ patternProperties:
+ "^channel@[0-1]$":
+ properties:
+ reg:
+ enum: [0, 1]
+ "^channel@[2-7]$": false
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - microchip,mcp47fvb04
+ - microchip,mcp47fvb14
+ - microchip,mcp47fvb24
+ - microchip,mcp47feb04
+ - microchip,mcp47feb14
+ - microchip,mcp47feb24
+ then:
+ patternProperties:
+ "^channel@[0-3]$":
+ properties:
+ reg:
+ enum: [0, 1, 2, 3]
+ "^channel@[4-7]$": false
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - microchip,mcp47fvb08
+ - microchip,mcp47fvb18
+ - microchip,mcp47fvb28
+ - microchip,mcp47feb08
+ - microchip,mcp47feb18
+ - microchip,mcp47feb28
+ then:
+ patternProperties:
+ "^channel@[0-7]$":
+ properties:
+ reg:
+ enum: [0, 1, 2, 3, 4, 5, 6, 7]
+ - if:
+ not:
+ required:
+ - vref-supply
+ then:
+ properties:
+ microchip,vref-buffered: false
+ - if:
+ not:
+ required:
+ - vref1-supply
+ then:
+ properties:
+ microchip,vref1-buffered: false
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dac@0 {
+ compatible = "microchip,mcp47feb02";
+ reg = <0>;
+ vdd-supply = <&vdac_vdd>;
+ vref-supply = <&vref_reg>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ channel@0 {
+ reg = <0>;
+ label = "Adjustable_voltage_ch0";
+ };
+
+ channel@1 {
+ reg = <0x1>;
+ label = "Adjustable_voltage_ch1";
+ };
+ };
+ };
+...
items:
- const: ref_in
+ '#clock-cells':
+ const: 0
+
+ clock-output-names:
+ maxItems: 1
+
chip-enable-gpios:
description:
GPIO that controls the Chip Enable Pin.
spi-max-frequency = <10000000>;
clocks = <&adf4377_ref_in>;
clock-names = "ref_in";
+ #clock-cells = <0>;
+ clock-output-names = "adf4377";
};
};
...
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/pressure/honeywell,abp2030pa.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Honeywell abp2030pa pressure sensor
+
+maintainers:
+ - Petre Rodan <petre.rodan@subdimension.ro>
+
+description: |
+ Honeywell pressure sensor of model abp2030pa.
+
+ This sensor has an I2C and SPI interface.
+
+ There are many models with different pressure ranges available. The vendor
+ calls them "ABP2 series". All of them have an identical programming model and
+ differ in the pressure range and measurement unit.
+
+ To support different models one needs to specify its pressure triplet.
+
+ For custom silicon chips not covered by the Honeywell ABP2 series datasheet,
+ the pressure values can be specified manually via honeywell,pmin-pascal and
+ honeywell,pmax-pascal.
+
+ Specifications about the devices can be found at:
+ https://prod-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressure-sensors/board-mount-pressure-sensors/basic-abp2-series/documents/sps-siot-abp2-series-datasheet-32350268-en.pdf
+
+properties:
+ compatible:
+ const: honeywell,abp2030pa
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ Optional interrupt for indicating end of conversion.
+ SPI variants of ABP2 chips do not provide this feature.
+ maxItems: 1
+
+ honeywell,pressure-triplet:
+ description: |
+ Case-sensitive five character string that defines pressure range, unit
+ and type as part of the device nomenclature. In the unlikely case of a
+ custom chip, unset and provide pmin-pascal and pmax-pascal instead.
+ enum: [001BA, 1.6BA, 2.5BA, 004BA, 006BA, 008BA, 010BA, 012BA, 001BD,
+ 1.6BD, 2.5BD, 004BD, 001BG, 1.6BG, 2.5BG, 004BG, 006BG, 008BG,
+ 010BG, 012BG, 001GG, 1.2GG, 100KA, 160KA, 250KA, 001KD, 1.6KD,
+ 2.5KD, 004KD, 006KD, 010KD, 016KD, 025KD, 040KD, 060KD, 100KD,
+ 160KD, 250KD, 400KD, 001KG, 1.6KG, 2.5KG, 004KG, 006KG, 010KG,
+ 016KG, 025KG, 040KG, 060KG, 100KG, 160KG, 250KG, 400KG, 600KG,
+ 800KG, 250LD, 600LD, 600LG, 2.5MD, 006MD, 010MD, 016MD, 025MD,
+ 040MD, 060MD, 100MD, 160MD, 250MD, 400MD, 600MD, 006MG, 010MG,
+ 016MG, 025MG, 040MG, 060MG, 100MG, 160MG, 250MG, 400MG, 600MG,
+ 001ND, 002ND, 004ND, 005ND, 010ND, 020ND, 030ND, 002NG, 004NG,
+ 005NG, 010NG, 020NG, 030NG, 015PA, 030PA, 060PA, 100PA, 150PA,
+ 175PA, 001PD, 005PD, 015PD, 030PD, 060PD, 001PG, 005PG, 015PG,
+ 030PG, 060PG, 100PG, 150PG, 175PG]
+ $ref: /schemas/types.yaml#/definitions/string
+
+ honeywell,pmin-pascal:
+ description:
+ Minimum pressure value the sensor can measure in pascal.
+
+ honeywell,pmax-pascal:
+ description:
+ Maximum pressure value the sensor can measure in pascal.
+
+ spi-max-frequency:
+ maximum: 800000
+
+ vdd-supply: true
+
+required:
+ - compatible
+ - reg
+ - vdd-supply
+
+oneOf:
+ - required:
+ - honeywell,pressure-triplet
+ - required:
+ - honeywell,pmin-pascal
+ - honeywell,pmax-pascal
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml
+ - if:
+ required:
+ - honeywell,pressure-triplet
+ then:
+ properties:
+ honeywell,pmin-pascal: false
+ honeywell,pmax-pascal: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pressure@18 {
+ compatible = "honeywell,abp2030pa";
+ reg = <0x18>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <21 IRQ_TYPE_EDGE_RISING>;
+
+ honeywell,pressure-triplet = "001BA";
+ vdd-supply = <&vcc_3v3>;
+ };
+ };
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pressure@0 {
+ compatible = "honeywell,abp2030pa";
+ reg = <0>;
+ spi-max-frequency = <800000>;
+
+ honeywell,pressure-triplet = "001PD";
+ vdd-supply = <&vcc_3v3>;
+ };
+ };
+...
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/proximity/rfdigital,rfd77402.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RF Digital RFD77402 ToF sensor
+
+maintainers:
+ - Shrikant Raskar <raskar.shree97@gmail.com>
+
+description:
+ The RF Digital RFD77402 is a Time-of-Flight (ToF) proximity and distance
+ sensor providing up to 200 mm range measurement over an I2C interface.
+
+properties:
+ compatible:
+ const: rfdigital,rfd77402
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+ description:
+ Interrupt asserted when a new distance measurement is available.
+
+ vdd-supply:
+ description: Regulator that provides power to the sensor.
+
+required:
+ - compatible
+ - reg
+ - vdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ proximity@4c {
+ compatible = "rfdigital,rfd77402";
+ reg = <0x4c>;
+ vdd-supply = <&vdd_3v3>;
+ interrupt-parent = <&gpio>;
+ interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
+...
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/focaltech,ft8112.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: FocalTech FT8112 touchscreen controller
+
+maintainers:
+ - Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
+
+description:
+ Supports the FocalTech FT8112 touchscreen controller.
+ This touchscreen controller uses the i2c-hid protocol with a reset GPIO.
+
+allOf:
+ - $ref: /schemas/input/touchscreen/touchscreen.yaml#
+
+properties:
+ compatible:
+ enum:
+ - focaltech,ft8112
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ panel: true
+
+ reset-gpios:
+ maxItems: 1
+
+ vcc33-supply: true
+
+ vccio-supply: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - vcc33-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen@38 {
+ compatible = "focaltech,ft8112";
+ reg = <0x38>;
+
+ interrupt-parent = <&pio>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+
+ reset-gpios = <&pio 126 GPIO_ACTIVE_LOW>;
+ vcc33-supply = <&pp3300_tchscr_x>;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/google,goldfish-events-keypad.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Android Goldfish Events Keypad
+
+maintainers:
+ - Kuan-Wei Chiu <visitorckw@gmail.com>
+
+allOf:
+ - $ref: input.yaml#
+
+description:
+ Android goldfish events keypad device generated by android emulator.
+
+properties:
+ compatible:
+ const: google,goldfish-events-keypad
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ keypad@9040000 {
+ compatible = "google,goldfish-events-keypad";
+ reg = <0x9040000 0x1000>;
+ interrupts = <5>;
+ };
properties:
compatible:
- enum:
- - qcom,pm8941-pwrkey
- - qcom,pm8941-resin
- - qcom,pmk8350-pwrkey
- - qcom,pmk8350-resin
+ oneOf:
+ - enum:
+ - qcom,pm8941-pwrkey
+ - qcom,pm8941-resin
+ - qcom,pmk8350-pwrkey
+ - qcom,pmk8350-resin
+ - items:
+ - const: qcom,pmm8654au-pwrkey
+ - const: qcom,pmk8350-pwrkey
+ - items:
+ - const: qcom,pmm8654au-resin
+ - const: qcom,pmk8350-resin
interrupts:
maxItems: 1
maintainers:
- Jason A. Donenfeld <Jason@zx2c4.com>
- - Matthias Schiffer <matthias.schiffer@ew.tq-group.com
+ - Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
- Vincent Huang <vincent.huang@tw.synaptics.com>
description: |
- edt,edt-ft5406
- edt,edt-ft5506
- evervision,ev-ft5726
+ - focaltech,ft3518
- focaltech,ft5426
- focaltech,ft5452
- focaltech,ft6236
address, thus it can be driven by the host during the reset sequence.
maxItems: 1
+ panel: true
+
reset-gpios:
maxItems: 1
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/touchscreen/ilitek,ili210x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ilitek ILI21xx/ILI251x V3/V6 touch screen controller with i2c interface
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+ - Marek Vasut <marek.vasut+renesas@mailbox.org>
+
+properties:
+ compatible:
+ enum:
+ - ilitek,ili210x
+ - ilitek,ili2117
+ - ilitek,ili2120
+ - ilitek,ili251x
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+
+ wakeup-source: true
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: touchscreen.yaml
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen@41 {
+ compatible = "ilitek,ili2120";
+ reg = <0x41>;
+ };
+ };
properties:
compatible:
contains:
- const: imagis,ist3032c
+ enum:
+ - imagis,ist3032c
+ - imagis,ist3038
then:
properties:
linux,keycodes: false
properties:
compatible:
- enum:
- - sitronix,st1232
- - sitronix,st1633
+ oneOf:
+ - enum:
+ - sitronix,st1232
+ - sitronix,st1633
+ - items:
+ - const: sitronix,st1624
+ - const: sitronix,st1633
reg:
maxItems: 1
how much time to wait (in milliseconds) before reading again the
values from the tsc2007.
+ "#io-channel-cells":
+ const: 1
+
required:
- compatible
- reg
# Hynitron cstxxx series touchscreen controller
- hynitron,cst340
# Ilitek I2C Touchscreen Controller
- - ilitek,ili210x
- - ilitek,ili2117
- - ilitek,ili2120
- ilitek,ili2130
- ilitek,ili2131
- ilitek,ili2132
- ilitek,ili2322
- ilitek,ili2323
- ilitek,ili2326
- - ilitek,ili251x
- ilitek,ili2520
- ilitek,ili2521
# MAXI MAX11801 Resistive touch screen controller with i2c interface
enum:
- mediatek,mt8183-emi
- mediatek,mt8195-emi
+ - mediatek,mt8196-emi
'#interconnect-cells':
const: 1
- const: qcom,msm8998-bwmon # BWMON v4
- items:
- enum:
+ - qcom,glymur-cpu-bwmon
- qcom,kaanapali-cpu-bwmon
- qcom,qcm2290-cpu-bwmon
- qcom,qcs615-cpu-bwmon
- qcom,qcs615-config-noc
- qcom,qcs615-dc-noc
- qcom,qcs615-gem-noc
- - qcom,qcs615-ipa-virt
- qcom,qcs615-mc-virt
- qcom,qcs615-mmss-noc
- qcom,qcs615-system-noc
contains:
enum:
- qcom,qcs615-camnoc-virt
- - qcom,qcs615-ipa-virt
- qcom,qcs615-mc-virt
then:
properties:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/fsl,qe-ports-ic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale QUICC Engine I/O Ports Interrupt Controller
+
+maintainers:
+ - Christophe Leroy (CS GROUP) <chleroy@kernel.org>
+
+properties:
+ compatible:
+ enum:
+ - fsl,mpc8323-qe-ports-ic
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#address-cells':
+ const: 0
+
+ '#interrupt-cells':
+ const: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - '#address-cells'
+ - '#interrupt-cells'
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ interrupt-controller@c00 {
+ compatible = "fsl,mpc8323-qe-ports-ic";
+ reg = <0xc00 0x18>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupts = <74 0x8>;
+ interrupt-parent = <&ipic>;
+ };
properties:
compatible:
oneOf:
+ - items:
+ - enum:
+ - fsl,imx1-aitc
+ - fsl,imx25-asic
+ - fsl,imx27-aitc
+ - fsl,imx31-avic
+ - fsl,imx35-avic
+ - const: fsl,avic
- items:
- enum:
- fsl,imx51-tzic
interrupts:
maxItems: 1
+ '#address-cells':
+ const: 0
+
interrupt-controller: true
'#interrupt-cells':
- const: isr1
minItems: 2
+ '#address-cells':
+ const: 0
+
interrupt-controller: true
interrupts:
minimum: 0
maximum: 192
+ '#address-cells':
+ const: 0
+
interrupt-controller: true
'#interrupt-cells':
items:
- enum:
- qcom,glymur-pdc
+ - qcom,kaanapali-pdc
+ - qcom,milos-pdc
- qcom,qcs615-pdc
- qcom,qcs8300-pdc
- qcom,qdu1000-pdc
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/renesas,r9a09g077-icu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/{T2H,N2H} Interrupt Controller
+
+maintainers:
+ - Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+description:
+ The Interrupt Controller (ICU) handles software-triggered interrupts
+ (INTCPU), external interrupts (IRQ and SEI), error interrupts and DMAC
+ requests.
+
+properties:
+ compatible:
+ oneOf:
+ - const: renesas,r9a09g077-icu # RZ/T2H
+
+ - items:
+ - enum:
+ - renesas,r9a09g087-icu # RZ/N2H
+ - const: renesas,r9a09g077-icu
+
+ reg:
+ items:
+ - description: Non-safety registers (INTCPU0-13, IRQ0-13)
+ - description: Safety registers (INTCPU14-15, IRQ14-15, SEI)
+
+ '#interrupt-cells':
+ description: The first cell is the SPI number of the interrupt, as per user
+ manual. The second cell is used to specify the flag.
+ const: 2
+
+ '#address-cells':
+ const: 0
+
+ interrupt-controller: true
+
+ interrupts:
+ items:
+ - description: Software interrupt 0
+ - description: Software interrupt 1
+ - description: Software interrupt 2
+ - description: Software interrupt 3
+ - description: Software interrupt 4
+ - description: Software interrupt 5
+ - description: Software interrupt 6
+ - description: Software interrupt 7
+ - description: Software interrupt 8
+ - description: Software interrupt 9
+ - description: Software interrupt 10
+ - description: Software interrupt 11
+ - description: Software interrupt 12
+ - description: Software interrupt 13
+ - description: Software interrupt 14
+ - description: Software interrupt 15
+ - description: External pin interrupt 0
+ - description: External pin interrupt 1
+ - description: External pin interrupt 2
+ - description: External pin interrupt 3
+ - description: External pin interrupt 4
+ - description: External pin interrupt 5
+ - description: External pin interrupt 6
+ - description: External pin interrupt 7
+ - description: External pin interrupt 8
+ - description: External pin interrupt 9
+ - description: External pin interrupt 10
+ - description: External pin interrupt 11
+ - description: External pin interrupt 12
+ - description: External pin interrupt 13
+ - description: External pin interrupt 14
+ - description: External pin interrupt 15
+ - description: System error interrupt
+ - description: Cortex-A55 error event 0
+ - description: Cortex-A55 error event 1
+ - description: Cortex-R52 CPU 0 error event 0
+ - description: Cortex-R52 CPU 0 error event 1
+ - description: Cortex-R52 CPU 1 error event 0
+ - description: Cortex-R52 CPU 1 error event 1
+ - description: Peripherals error event 0
+ - description: Peripherals error event 1
+ - description: DSMIF error event 0
+ - description: DSMIF error event 1
+ - description: ENCIF error event 0
+ - description: ENCIF error event 1
+
+ interrupt-names:
+ items:
+ - const: intcpu0
+ - const: intcpu1
+ - const: intcpu2
+ - const: intcpu3
+ - const: intcpu4
+ - const: intcpu5
+ - const: intcpu6
+ - const: intcpu7
+ - const: intcpu8
+ - const: intcpu9
+ - const: intcpu10
+ - const: intcpu11
+ - const: intcpu12
+ - const: intcpu13
+ - const: intcpu14
+ - const: intcpu15
+ - const: irq0
+ - const: irq1
+ - const: irq2
+ - const: irq3
+ - const: irq4
+ - const: irq5
+ - const: irq6
+ - const: irq7
+ - const: irq8
+ - const: irq9
+ - const: irq10
+ - const: irq11
+ - const: irq12
+ - const: irq13
+ - const: irq14
+ - const: irq15
+ - const: sei
+ - const: ca55-err0
+ - const: ca55-err1
+ - const: cr520-err0
+ - const: cr520-err1
+ - const: cr521-err0
+ - const: cr521-err1
+ - const: peri-err0
+ - const: peri-err1
+ - const: dsmif-err0
+ - const: dsmif-err1
+ - const: encif-err0
+ - const: encif-err1
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - '#interrupt-cells'
+ - '#address-cells'
+ - interrupt-controller
+ - interrupts
+ - interrupt-names
+ - clocks
+ - power-domains
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
+
+ icu: interrupt-controller@802a0000 {
+ compatible = "renesas,r9a09g077-icu";
+ reg = <0x802a0000 0x10000>,
+ <0x812a0000 0x50>;
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 7 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 9 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 14 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 16 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 408 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 409 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 412 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 413 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 415 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 416 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 417 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 418 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "intcpu0", "intcpu1", "intcpu2",
+ "intcpu3", "intcpu4", "intcpu5",
+ "intcpu6", "intcpu7", "intcpu8",
+ "intcpu9", "intcpu10", "intcpu11",
+ "intcpu12", "intcpu13", "intcpu14",
+ "intcpu15",
+ "irq0", "irq1", "irq2", "irq3",
+ "irq4", "irq5", "irq6", "irq7",
+ "irq8", "irq9", "irq10", "irq11",
+ "irq12", "irq13", "irq14", "irq15",
+ "sei",
+ "ca55-err0", "ca55-err1",
+ "cr520-err0", "cr520-err1",
+ "cr521-err0", "cr521-err1",
+ "peri-err0", "peri-err1",
+ "dsmif-err0", "dsmif-err1",
+ "encif-err0", "encif-err1";
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
+ power-domains = <&cpg>;
+ };
compatible:
enum:
- renesas,r9a09g047-icu # RZ/G3E
+ - renesas,r9a09g056-icu # RZ/V2N
- renesas,r9a09g057-icu # RZ/V2H(P)
'#interrupt-cells':
items:
- enum:
- qemu,aplic
+ - spacemit,k3-aplic
- const: riscv,aplic
reg:
items:
- enum:
- qemu,imsics
+ - spacemit,k3-imsics
- const: riscv,imsics
reg:
riscv,ndev:
$ref: /schemas/types.yaml#/definitions/uint32
description:
- Specifies how many external interrupts are supported by this controller.
+ Specifies how many external (device) interrupts are supported by this
+ controller. Note that source 0 is reserved in PLIC, so the valid
+ interrupt sources are 1 to riscv,ndev inclusive.
clocks: true
description: |
The Interrupt Router (INTR) module provides a mechanism to mux M
interrupt inputs to N interrupt outputs, where all M inputs are selectable
- to be driven per N output. An Interrupt Router can either handle edge
- triggered or level triggered interrupts and that is fixed in hardware.
+ to be driven per N output.
Interrupt Router
+----------------------+
interrupt-controller: true
'#interrupt-cells':
- const: 1
+ enum: [1, 2]
description: |
- The 1st cell should contain interrupt router input hw number.
+ Number of cells in interrupt specifier. Depends on ti,intr-trigger-type:
+ - If ti,intr-trigger-type is present: must be 1
+ The 1st cell should contain interrupt router input hw number.
+ - If ti,intr-trigger-type is absent: must be 2
+ The 1st cell should contain interrupt router input hw number.
+ The 2nd cell should contain interrupt trigger type (preserved by router).
ti,interrupt-ranges:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
- description: |
"limit" specifies the limit for translation
+if:
+ required:
+ - ti,intr-trigger-type
+then:
+ properties:
+ '#interrupt-cells':
+ const: 1
+ description: Interrupt ID only. Interrupt type is specified globally
+else:
+ properties:
+ '#interrupt-cells':
+ const: 2
+ description: Interrupt ID and corresponding interrupt type
+
required:
- compatible
- - ti,intr-trigger-type
- interrupt-controller
- '#interrupt-cells'
- ti,sci
ti,sci-dev-id = <131>;
ti,interrupt-ranges = <0 360 32>;
};
+
+ - |
+ interrupt-controller {
+ compatible = "ti,sci-intr";
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <2>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <131>;
+ ti,interrupt-ranges = <0 360 32>;
+ };
$nodename:
pattern: "^iommu@[0-9a-f]*"
compatible:
- const: arm,smmu-v3
+ oneOf:
+ - const: arm,smmu-v3
+ - items:
+ - enum:
+ - nvidia,tegra264-smmu
+ - const: arm,smmu-v3
reg:
maxItems: 1
msi-parent: true
+ nvidia,cmdqv:
+ description: |
+ A phandle to its pairing CMDQV extension for an implementation on NVIDIA
+ Tegra SoC.
+
+ If this property is absent, CMDQ-Virtualization won't be used and SMMU
+ will only use its own CMDQ.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
hisilicon,broken-prefetch-cmd:
type: boolean
description: Avoid sending CMD_PREFETCH_* commands to the SMMU.
register access with page 0 offsets. Set for Cavium ThunderX2 silicon that
doesn't support SMMU page1 register space.
+allOf:
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra264-smmu
+ then:
+ properties:
+ nvidia,cmdqv: false
+
required:
- compatible
- reg
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iommu/nvidia,tegra264-cmdqv.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra264 CMDQV
+
+description:
+ The CMDQ-Virtualization hardware block is part of the SMMUv3 implementation
+ on Tegra264 SoCs. It assists in virtualizing the command queue for the SMMU.
+
+maintainers:
+ - Nicolin Chen <nicolinc@nvidia.com>
+
+properties:
+ compatible:
+ const: nvidia,tegra264-cmdqv
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ cmdqv@5200000 {
+ compatible = "nvidia,tegra264-cmdqv";
+ reg = <0x5200000 0x830000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/ams,as3668.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Osram 4-channel i2c LED driver
+
+maintainers:
+ - Lukas Timmermann <linux@timmermann.space>
+
+description:
+ This IC can drive up to four separate LEDs.
+ Having four channels suggests it could be used with a single RGBW LED.
+
+properties:
+ compatible:
+ const: ams,as3668
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+patternProperties:
+ "^led@[0-3]$":
+ type: object
+ $ref: common.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/leds/common.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led-controller@42 {
+ compatible = "ams,as3668";
+ reg = <0x42>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0x0>;
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@1 {
+ reg = <0x1>;
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+ };
+ };
+
description: |
Over-voltage protection limit. This property is for WLED4 only.
$ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 18100, 19600, 29600, 31100 ]
- default: 29600
+ minimum: 17800
+ maximum: 31100
qcom,num-strings:
description: |
minimum: 0
maximum: 4095
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pmi8950-wled
+ - qcom,pmi8994-wled
+
+ then:
+ properties:
+ qcom,ovp-millivolt:
+ enum: [ 17800, 19400, 29500, 31000 ]
+ default: 29500
+
+ else:
+ properties:
+ qcom,ovp-millivolt:
+ enum: [ 18100, 19600, 29600, 31100 ]
+ default: 29600
+
required:
- compatible
- reg
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/iei,wt61p803-puzzle-leds.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: IEI WT61P803 PUZZLE MCU LED module from IEI Integration Corp.
+
+maintainers:
+ - Luka Kovacic <luka.kovacic@sartura.hr>
+
+description: |
+ This module is a part of the IEI WT61P803 PUZZLE MFD device. For more details
+ see Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml.
+
+ The LED module is a sub-node of the MCU node in the Device Tree.
+
+properties:
+ compatible:
+ const: iei,wt61p803-puzzle-leds
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ led@0:
+ $ref: common.yaml
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ const: 0
+
+required:
+ - compatible
+ - '#address-cells'
+ - '#size-cells'
+
+additionalProperties: false
properties:
$nodename:
- pattern: "^multi-led(@[0-9a-f])?$"
+ pattern: "^multi-led(@[0-9a-f]|-[0-9]+)?$"
color:
description: |
issi,is31fl3235
issi,is31fl3218
issi,is31fl3216
+ issi,is31fl3293
si-en,sn3218
si-en,sn3216
- reg: I2C slave address
+++ /dev/null
-* Texas Instruments - LM3697 Highly Efficient White LED Driver
-
-The LM3697 11-bit LED driver provides high-
-performance backlight dimming for 1, 2, or 3 series
-LED strings while delivering up to 90% efficiency.
-
-This device is suitable for display and keypad lighting
-
-Required properties:
- - compatible:
- "ti,lm3697"
- - reg : I2C slave address
- - #address-cells : 1
- - #size-cells : 0
-
-Optional properties:
- - enable-gpios : GPIO pin to enable/disable the device
- - vled-supply : LED supply
-
-Required child properties:
- - reg : 0 - LED is Controlled by bank A
- 1 - LED is Controlled by bank B
- - led-sources : Indicates which HVLED string is associated to which
- control bank. This is a zero based property so
- HVLED1 = 0, HVLED2 = 1, HVLED3 = 2.
- Additional information is contained
- in Documentation/devicetree/bindings/leds/common.txt
-
-Optional child properties:
- - ti,brightness-resolution - see Documentation/devicetree/bindings/mfd/ti-lmu.txt
- - ramp-up-us: see Documentation/devicetree/bindings/mfd/ti-lmu.txt
- - ramp-down-us: see Documentation/devicetree/bindings/mfd/ti-lmu.txt
- - label : see Documentation/devicetree/bindings/leds/common.txt
- - linux,default-trigger :
- see Documentation/devicetree/bindings/leds/common.txt
-
-Example:
-
-HVLED string 1 and 3 are controlled by control bank A and HVLED 2 string is
-controlled by control bank B.
-
-led-controller@36 {
- compatible = "ti,lm3697";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x36>;
-
- enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
- vled-supply = <&vbatt>;
-
- led@0 {
- reg = <0>;
- led-sources = <0 2>;
- ti,brightness-resolution = <2047>;
- ramp-up-us = <5000>;
- ramp-down-us = <1000>;
- label = "white:first_backlight_cluster";
- linux,default-trigger = "backlight";
- };
-
- led@1 {
- reg = <1>;
- led-sources = <1>;
- ti,brightness-resolution = <255>;
- ramp-up-us = <500>;
- ramp-down-us = <1000>;
- label = "white:second_backlight_cluster";
- linux,default-trigger = "backlight";
- };
-}
-
-For more product information please see the link below:
-https://www.ti.com/lit/ds/symlink/lm3697.pdf
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/leds-lp5860.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LED driver for LP5860 RGB LED from Texas Instruments.
+
+maintainers:
+ - Steffen Trumtrar <kernel@pengutronix.de>
+
+description: |
+ The LP5860 is multi-channel, I2C and SPI RGB LED Driver that can group RGB LEDs
+ into a LED group or control them individually.
+
+ For more product information please see the link below:
+ https://www.ti.com/lit/ds/symlink/lp5860.pdf
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ti,lp5860
+
+ reg:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+patternProperties:
+ '^multi-led@[0-9a-f]+$':
+ type: object
+ $ref: leds-class-multicolor.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ minimum: 0
+ maximum: 198
+ description:
+ This property denotes the LED module number that is used
+ for the child node.
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ patternProperties:
+ "^led@[0-9a-f]+$":
+ type: object
+ $ref: common.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ maxItems: 1
+
+ required:
+ - reg
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/leds/common.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led-controller@0 {
+ compatible = "ti,lp5860";
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ multi-led@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+ color = <LED_COLOR_ID_RGB>;
+
+ led@0 {
+ reg = <0x0>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@1 {
+ reg = <0x1>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@2 {
+ reg = <0x2>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+ };
+ };
- items:
- enum:
- qcom,pm8550-pwm
+ - qcom,pmh0101-pwm
- const: qcom,pm8350c-pwm
- items:
- enum:
- qcom,pm8150l-flash-led
- qcom,pm8350c-flash-led
- qcom,pm8550-flash-led
+ - qcom,pmh0101-flash-led
- qcom,pmi8998-flash-led
- const: qcom,spmi-flash-led
- Matti Vaittinen <mazziesaccount@gmail.com>
description: |
- This module is part of the ROHM BD71828 MFD device. For more details
- see Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml.
+ This module is part of the ROHM BD71828 and BD72720 MFD device. For more
+ details see Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml
+ and Documentation/devicetree/bindings/mfd/rohm,bd72720-pmic.yaml
The LED controller is represented as a sub-node of the PMIC node on the device
- tree.
+ tree. This should be located under "leds" - node in PMIC node.
The device has two LED outputs referred as GRNLED and AMBLED in data-sheet.
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/ti,lm3697.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI LM3697 Highly Efficient White LED Driver
+
+maintainers:
+ - Dan Murphy <dmurphy@ti.com>
+
+description: >
+ The LM3697 11-bit LED driver provides high-performance backlight dimming for
+ 1, 2, or 3 series LED strings while delivering up to 90% efficiency.
+
+ This device is suitable for display and keypad lighting.
+
+properties:
+ compatible:
+ const: ti,lm3697
+
+ reg:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ enable-gpios:
+ description: GPIO pin to enable or disable the device.
+ maxItems: 1
+
+ vled-supply:
+ description: LED supply for the device.
+
+patternProperties:
+ '^led@[01]$':
+ description: LED control bank nodes.
+ $ref: common.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ description: Control bank selection (0 = bank A, 1 = bank B).
+ maximum: 1
+
+ led-sources:
+ description: >
+ HVLED strings associated with this control bank:
+
+ 0 - HVLED1
+ 1 - HVLED2
+ 2 - HVLED3
+ minItems: 1
+ maxItems: 3
+ items:
+ maximum: 2
+
+ ti,brightness-resolution:
+ description: Brightness resolution for the LED string.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 2047
+
+ ramp-up-us:
+ description: Ramp-up time in microseconds.
+ minimum: 117
+ maximum: 2048
+
+ ramp-down-us:
+ description: Ramp-down time in microseconds.
+ minimum: 117
+ maximum: 2048
+
+ required:
+ - reg
+ - led-sources
+
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led-controller@36 {
+ compatible = "ti,lm3697";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x36>;
+
+ enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ vled-supply = <&vbatt>;
+
+ led@0 {
+ reg = <0>;
+ led-sources = <0 2>;
+ ti,brightness-resolution = <2047>;
+ ramp-up-us = <500>;
+ ramp-down-us = <1000>;
+ label = "white:first_backlight_cluster";
+ linux,default-trigger = "backlight";
+ };
+
+ led@1 {
+ reg = <1>;
+ led-sources = <1>;
+ ti,brightness-resolution = <255>;
+ ramp-up-us = <500>;
+ ramp-down-us = <1000>;
+ label = "white:second_backlight_cluster";
+ linux,default-trigger = "backlight";
+ };
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/ti,lp5812.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI LP5812 4x3 Matrix RGB LED Driver with Autonomous Control
+
+maintainers:
+ - Nam Tran <trannamatk@gmail.com>
+
+description: |
+ The LP5812 is a 4x3 matrix RGB LED driver with I2C interface
+ and autonomous animation engine control.
+ For more product information please see the link below:
+ https://www.ti.com/product/LP5812#tech-docs
+
+properties:
+ compatible:
+ const: ti,lp5812
+
+ reg:
+ maxItems: 1
+
+ ti,scan-mode:
+ description: |
+ Selects the LED scan mode of the LP5812. The device supports
+ three modes:
+ - Direct-drive mode (by default if 'ti,scan-mode' is omitted)
+ drives up to 4 LEDs directly by internal current sinks (LED0-LED3).
+ - TCM-drive mode ("tcm:<n>:<order...>") drives up to 12 LEDs
+ (4 RGB) using 1-4 scan multiplexing. The <n> specifies the number
+ of scans (1-4), and <order...> defines the scan order of the outputs.
+ - Mix-drive mode ("mix:<n>:<direct>:<order...>") combines
+ direct-drive and TCM-drive outputs. The <n> specifies the number
+ of scans, <direct> selects the direct-drive outputs, and <order...>
+ defines the scan order.
+ $ref: /schemas/types.yaml#/definitions/string
+ pattern: '^(tcm|mix):[1-4](:[0-3]){1,4}$'
+
+ vcc-supply:
+ description: Regulator providing power to the 'VCC' pin.
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+patternProperties:
+ "^led@[0-3]$":
+ type: object
+ $ref: common.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ minimum: 0
+ maximum: 3
+
+ required:
+ - reg
+
+ "^multi-led@[4-7]$":
+ type: object
+ $ref: leds-class-multicolor.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ minimum: 4
+ maximum: 7
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ patternProperties:
+ "^led@[4-9a-f]$":
+ type: object
+ $ref: common.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ minimum: 4
+ maximum: 15
+
+ required:
+ - reg
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/leds/common.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led-controller@1b {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "ti,lp5812";
+ reg = <0x1b>;
+ ti,scan-mode = "tcm:4:0:1:2:3";
+ vcc-supply = <&vdd_3v3_reg>;
+
+ led@0 {
+ reg = <0x0>;
+ label = "LED0";
+ led-max-microamp = <25500>;
+ };
+
+ led@1 {
+ reg = <0x1>;
+ label = "LED1";
+ led-max-microamp = <25500>;
+ };
+
+ led@2 {
+ reg = <0x2>;
+ label = "LED2";
+ led-max-microamp = <25500>;
+ };
+
+ led@3 {
+ reg = <0x3>;
+ label = "LED3";
+ led-max-microamp = <25500>;
+ };
+
+ multi-led@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4>;
+ color = <LED_COLOR_ID_RGB>;
+ label = "LED_A";
+
+ led@4 {
+ reg = <0x4>;
+ color = <LED_COLOR_ID_GREEN>;
+ led-max-microamp = <25500>;
+ };
+
+ led@5 {
+ reg = <0x5>;
+ color = <LED_COLOR_ID_RED>;
+ led-max-microamp = <25500>;
+ };
+
+ led@6 {
+ reg = <0x6>;
+ color = <LED_COLOR_ID_BLUE>;
+ led-max-microamp = <25500>;
+ };
+ };
+
+ multi-led@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x5>;
+ color = <LED_COLOR_ID_RGB>;
+ label = "LED_B";
+
+ led@7 {
+ reg = <0x7>;
+ color = <LED_COLOR_ID_GREEN>;
+ led-max-microamp = <25500>;
+ };
+
+ led@8 {
+ reg = <0x8>;
+ color = <LED_COLOR_ID_RED>;
+ led-max-microamp = <25500>;
+ };
+
+ led@9 {
+ reg = <0x9>;
+ color = <LED_COLOR_ID_BLUE>;
+ led-max-microamp = <25500>;
+ };
+ };
+
+ multi-led@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x6>;
+ color = <LED_COLOR_ID_RGB>;
+ label = "LED_C";
+
+ led@a {
+ reg = <0xa>;
+ color = <LED_COLOR_ID_GREEN>;
+ led-max-microamp = <25500>;
+ };
+
+ led@b {
+ reg = <0xb>;
+ color = <LED_COLOR_ID_RED>;
+ led-max-microamp = <25500>;
+ };
+
+ led@c {
+ reg = <0xc>;
+ color = <LED_COLOR_ID_BLUE>;
+ led-max-microamp = <25500>;
+ };
+ };
+
+ multi-led@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x7>;
+ color = <LED_COLOR_ID_RGB>;
+ label = "LED_D";
+
+ led@d {
+ reg = <0xd>;
+ color = <LED_COLOR_ID_GREEN>;
+ led-max-microamp = <25500>;
+ };
+
+ led@e {
+ reg = <0xe>;
+ color = <LED_COLOR_ID_RED>;
+ led-max-microamp = <25500>;
+ };
+
+ led@f {
+ reg = <0xf>;
+ color = <LED_COLOR_ID_BLUE>;
+ led-max-microamp = <25500>;
+ };
+ };
+ };
+ };
+
+...
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/mediatek,mt8196-vcp-mbox.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Video Companion Processor (VCP) mailbox
+
+maintainers:
+ - Jjian Zhou <Jjian.Zhou@mediatek.com>
+
+description:
+ The MTK VCP mailbox enables the SoC to communicate with the VCP by passing
+ messages through 64 32-bit wide registers. It has 32 interrupt vectors in
+ either direction for signalling purposes.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8196-vcp-mbox
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#mbox-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#mbox-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ mailbox@31b80000 {
+ compatible = "mediatek,mt8196-vcp-mbox";
+ reg = <0x31b80000 0x1000>;
+ interrupts = <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <0>;
+ };
properties:
compatible:
- const: microchip,mpfs-mailbox
+ oneOf:
+ - items:
+ - const: microchip,pic64gx-mailbox
+ - const: microchip,mpfs-mailbox
+ - const: microchip,mpfs-mailbox
reg:
oneOf:
- items:
- enum:
- qcom,glymur-cpucp-mbox
+ - qcom,kaanapali-cpucp-mbox
+ - qcom,sm8750-cpucp-mbox
- const: qcom,x1e80100-cpucp-mbox
- enum:
- qcom,x1e80100-cpucp-mbox
compatible:
items:
- enum:
+ - qcom,glymur-ipcc
+ - qcom,kaanapali-ipcc
- qcom,milos-ipcc
- qcom,qcs8300-ipcc
- qcom,qdu1000-ipcc
enum:
- sprd,sc9860-mailbox
- sprd,sc9863a-mailbox
+ - sprd,ums9230-mailbox
reg:
items:
messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
agent owns registers used for notification and buffers for message.
+ For Versal devices, there are two types of IPI channels:
+ - Buffered channels: Support message passing and require the "msg"
+ register region to be present on both the host and remote IPI agents.
+ - Buffer-less channels: Support notification only and do not require the
+ "msg" register region. For these channels, the "msg" region should be
+ omitted.
+
+ For message passing, both the host and remote IPI agents must define the "msg"
+ register region. If either agent omits the "msg" region, only notification
+ based communication is possible.
+
+-------------------------------------+
| Xilinx ZynqMP IPI Controller |
+-------------------------------------+
- adi,adv7282-m
reg:
- maxItems: 1
+ minItems: 1
+ items:
+ - description: main register map
+ - description: VPP or CSI register map
+ - description: CSI register map
+ description:
+ The ADV7180 family may have up to three register maps. All chips have
+ the main register map. The availability of the CSI and VPP register maps
+ depends on the chip variant.
+
+ The addresses of the CSI and VPP register maps are programmable by
+ software. They depend on the board layout and other devices on the I2C
+ bus and are determined by the hardware designer to avoid address
+ conflicts on the I2C bus.
+
+ reg-names:
+ minItems: 1
+ items:
+ - const: main
+ - enum: [ csi, vpp ]
+ - const: csi
powerdown-gpios:
maxItems: 1
required:
- ports
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,adv7180
+ - adi,adv7180cp
+ - adi,adv7180st
+ - adi,adv7182
+ then:
+ properties:
+ reg:
+ maxItems: 1
+
+ reg-names:
+ maxItems: 1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,adv7281
+ - adi,adv7281-m
+ - adi,adv7281-ma
+ then:
+ properties:
+ reg:
+ minItems: 1
+ maxItems: 2
+
+ reg-names:
+ minItems: 1
+ items:
+ - const: main
+ - const: csi
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,adv7280
+ - adi,adv7282
+ then:
+ properties:
+ reg:
+ minItems: 1
+ maxItems: 2
+
+ reg-names:
+ minItems: 1
+ items:
+ - const: main
+ - const: vpp
+
examples:
- |
i2c {
};
};
};
+
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ composite-in@20 {
+ compatible = "adi,adv7280-m";
+ reg = <0x20>, <0x42>, <0x44>;
+ reg-names = "main", "vpp", "csi";
+
+ port {
+ adv7280_out: endpoint {
+ bus-width = <8>;
+ remote-endpoint = <&vin1ep>;
+ };
+ };
+ };
+ };
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/media/video-interfaces.h>
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/ovti,os05b10.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: OmniVision OS05B10 Image Sensor
+
+maintainers:
+ - Elgin Perumbilly <elgin.perumbilly@siliconsignals.io>
+
+description:
+ The OmniVision OS05B10 is a 5MP (2592x1944) color CMOS image sensor controlled
+ through an I2C-compatible SCCB bus. it outputs RAW10/RAW12 format and uses a
+ 1/2.78" optical format.
+
+properties:
+ compatible:
+ const: ovti,os05b10
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: XCLK clock
+
+ avdd-supply:
+ description: Analog Domain Power Supply (2.8v)
+
+ dovdd-supply:
+ description: I/O Domain Power Supply (1.8v)
+
+ dvdd-supply:
+ description: Digital Domain Power Supply (1.2v)
+
+ reset-gpios:
+ maxItems: 1
+ description: Reset Pin GPIO Control (active low)
+
+ port:
+ description: MIPI CSI-2 transmitter port
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ additionalProperties: false
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ oneOf:
+ - items:
+ - const: 1
+ - const: 2
+ - const: 3
+ - const: 4
+ - items:
+ - const: 1
+ - const: 2
+ required:
+ - data-lanes
+ - link-frequencies
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - avdd-supply
+ - dovdd-supply
+ - dvdd-supply
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera-sensor@36 {
+ compatible = "ovti,os05b10";
+ reg = <0x36>;
+ clocks = <&os05b10_clk>;
+ reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+
+ avdd-supply = <&os05b10_avdd_2v8>;
+ dvdd-supply = <&os05b10_dvdd_1v2>;
+ dovdd-supply = <&os05b10_dovdd_1v8>;
+
+ port {
+ cam_out: endpoint {
+ remote-endpoint = <&mipi_in_cam>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <600000000>;
+ };
+ };
+ };
+ };
The OV5647 is a raw image sensor with MIPI CSI-2 and CCP2 image data
interfaces and CCI (I2C compatible) control bus.
+allOf:
+ - $ref: /schemas/media/video-interface-devices.yaml#
+
properties:
compatible:
const: ovti,ov5647
description: Reference to the GPIO connected to the pwdn pin. Active high.
maxItems: 1
+ avdd-supply:
+ description: Analog voltage supply, 2.8 volts
+
+ dvdd-supply:
+ description: Digital core voltage supply, 1.5 volts
+
+ dovdd-supply:
+ description: Digital I/O voltage supply, 1.7 - 3.0 volts
+
port:
$ref: /schemas/graph.yaml#/$defs/port-base
additionalProperties: false
- clocks
- port
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/samsung,s5k3m5.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S5K3M5 Image Sensor
+
+description:
+ Samsung S5K3M5 (ISOCELL 3M5) image sensor is a 13MP image sensor.
+ The sensor is controlled over a serial camera control bus protocol,
+ the widest supported output image frame size is 4208x3120 at 30 frames
+ per second, data output format is RAW10 transferred over 4-lane
+ MIPI D-PHY interface.
+
+maintainers:
+ - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
+
+allOf:
+ - $ref: /schemas/media/video-interface-devices.yaml#
+
+properties:
+ compatible:
+ const: samsung,s5k3m5
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description: MCLK supply clock.
+ maxItems: 1
+
+ reset-gpios:
+ description: Active low GPIO connected to RESET pad of the sensor.
+ maxItems: 1
+
+ afvdd-supply:
+ description: Autofocus actuator voltage supply, 2.8-3.0 volts.
+
+ vdda-supply:
+ description: Analogue voltage supply, 2.8 volts.
+
+ vddd-supply:
+ description: Digital core voltage supply, 1.05 volts.
+
+ vddio-supply:
+ description: Digital I/O voltage supply, 2.8 or 1.8 volts.
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ additionalProperties: false
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ items:
+ - const: 1
+ - const: 2
+ - const: 3
+ - const: 4
+
+ required:
+ - link-frequencies
+
+required:
+ - compatible
+ - reg
+ - port
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera@10 {
+ compatible = "samsung,s5k3m5";
+ reg = <0x10>;
+ clocks = <&camera_mclk 0>;
+ assigned-clocks = <&camera_mclk 0>;
+ assigned-clock-rates = <24000000>;
+ reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ vdda-supply = <&vreg_2p8>;
+ vddd-supply = <&vreg_1p05>;
+ vddio-supply = <&vreg_1p8>;
+
+ port {
+ endpoint {
+ link-frequencies = /bits/ 64 <602500000>;
+ remote-endpoint = <&mipi_csi2_ep>;
+ };
+ };
+ };
+ };
+...
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/samsung,s5kjn1.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S5KJN1 Image Sensor
+
+description:
+ Samsung S5KJN1 (ISOCELL JN1) image sensor is a 50MP image sensor.
+ The sensor is controlled over a serial camera control bus protocol,
+ the widest supported output image frame size is 8160x6144 at 10 frames
+ per second, data output format is RAW10 transferred over 4-lane
+ MIPI D-PHY interface.
+
+maintainers:
+ - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
+
+allOf:
+ - $ref: /schemas/media/video-interface-devices.yaml#
+
+properties:
+ compatible:
+ const: samsung,s5kjn1
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description: MCLK supply clock.
+ maxItems: 1
+
+ reset-gpios:
+ description: Active low GPIO connected to RESET pad of the sensor.
+ maxItems: 1
+
+ afvdd-supply:
+ description: Autofocus actuator voltage supply, 2.8-3.0 volts.
+
+ vdda-supply:
+ description: Analogue voltage supply, 2.8 volts.
+
+ vddd-supply:
+ description: Digital core voltage supply, 1.05 volts.
+
+ vddio-supply:
+ description: Digital I/O voltage supply, 1.8 volts.
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ additionalProperties: false
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ items:
+ - const: 1
+ - const: 2
+ - const: 3
+ - const: 4
+
+ required:
+ - link-frequencies
+
+required:
+ - compatible
+ - reg
+ - port
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera@56 {
+ compatible = "samsung,s5kjn1";
+ reg = <0x56>;
+ clocks = <&camera_mclk 0>;
+ assigned-clocks = <&camera_mclk 0>;
+ assigned-clock-rates = <24000000>;
+ reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ vdda-supply = <&vreg_2p8>;
+ vddd-supply = <&vreg_1p05>;
+ vddio-supply = <&vreg_1p8>;
+
+ port {
+ endpoint {
+ link-frequencies = /bits/ 64 <700000000>;
+ remote-endpoint = <&mipi_csi2_ep>;
+ };
+ };
+ };
+ };
+...
+++ /dev/null
-Toshiba et8ek8 5MP sensor
-
-Toshiba et8ek8 5MP sensor is an image sensor found in Nokia N900 device
-
-More detailed documentation can be found in
-Documentation/devicetree/bindings/media/video-interfaces.txt .
-
-
-Mandatory properties
---------------------
-
-- compatible: "toshiba,et8ek8"
-- reg: I2C address (0x3e, or an alternative address)
-- vana-supply: Analogue voltage supply (VANA), 2.8 volts
-- clocks: External clock to the sensor
-- reset-gpios: XSHUTDOWN GPIO. The XSHUTDOWN signal is active low. The sensor
- is in hardware standby mode when the signal is in the low state.
-
-
-Optional properties
--------------------
-
-- flash-leds: See ../video-interfaces.txt
-- lens-focus: See ../video-interfaces.txt
-
-
-Endpoint node mandatory properties
-----------------------------------
-
-- remote-endpoint: A phandle to the bus receiver's endpoint node.
-
-
-Example
--------
-
-&i2c3 {
- clock-frequency = <400000>;
-
- cam1: camera@3e {
- compatible = "toshiba,et8ek8";
- reg = <0x3e>;
- vana-supply = <&vaux4>;
-
- clocks = <&isp 0>;
- assigned-clocks = <&isp 0>;
- assigned-clock-rates = <9600000>;
-
- reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */
- port {
- csi_cam1: endpoint {
- remote-endpoint = <&csi_out1>;
- };
- };
- };
-};
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/toshiba,et8ek8.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Toshiba et8ek8 5MP sensor
+
+maintainers:
+ - Pavel Machek <pavel@ucw.cz>
+ - Sakari Ailus <sakari.ailus@iki.fi>
+
+description:
+ Toshiba et8ek8 5MP sensor is an image sensor found in Nokia N900 device
+
+allOf:
+ - $ref: /schemas/media/video-interface-devices.yaml#
+
+properties:
+ compatible:
+ const: toshiba,et8ek8
+
+ reg:
+ description:
+ I2C address (0x3e, or an alternative address)
+ maxItems: 1
+
+ vana-supply:
+ description:
+ Analogue voltage supply (VANA), 2.8 volts
+
+ clocks:
+ maxItems: 1
+
+ reset-gpios:
+ description:
+ XSHUTDOWN GPIO. The XSHUTDOWN signal is active low. The sensor
+ is in hardware standby mode when the signal is in the low state.
+ maxItems: 1
+
+ flash-leds:
+ maxItems: 1
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ additionalProperties: false
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - vana-supply
+ - clocks
+ - reset-gpios
+ - port
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera@3e {
+ compatible = "toshiba,et8ek8";
+ reg = <0x3e>;
+ vana-supply = <&vaux4>;
+ clocks = <&isp 0>;
+ assigned-clocks = <&isp 0>;
+ assigned-clock-rates = <9600000>;
+ reset-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;
+ flash-leds = <&led>;
+
+ port {
+ csi_cam1: endpoint {
+ remote-endpoint = <&csi_out1>;
+ };
+ };
+ };
+ };
minItems: 1 # Wrapper and all slots
maxItems: 5 # Wrapper and 4 slots
+ sram:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Optional phandle to a reserved on-chip SRAM regions. The SRAM can
+ be used for descriptor storage, which may improve bus utilization.
+
required:
- compatible
- reg
- const: vcodec0_bus
iommus:
- maxItems: 5
+ maxItems: 2
interconnects:
maxItems: 2
memory-region = <&pil_video_mem>;
iommus = <&apps_smmu 0x860 0x0>,
- <&apps_smmu 0x880 0x0>,
- <&apps_smmu 0x861 0x04>,
- <&apps_smmu 0x863 0x0>,
- <&apps_smmu 0x804 0xe0>;
+ <&apps_smmu 0x880 0x0>;
interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
items:
- const: top
+ vdda-phy-supply:
+ description:
+ Phandle to a 0.88V regulator supply to CSI PHYs.
+
+ vdda-pll-supply:
+ description:
+ Phandle to 1.2V regulator supply to CSI PHYs pll block.
+
ports:
$ref: /schemas/graph.yaml#/properties/ports
- power-domains
- power-domain-names
- ports
+ - vdda-phy-supply
+ - vdda-pll-supply
additionalProperties: false
power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
power-domain-names = "top";
+ vdda-phy-supply = <&vreg_l4a_0p88>;
+ vdda-pll-supply = <&vreg_l1c_1p2>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
vdda-phy-supply:
description:
- Phandle to a regulator supply to PHY core block.
+ 0.88V supply to CSIPHY IP blocks.
vdda-pll-supply:
description:
- Phandle to 1.8V regulator supply to PHY refclk pll block.
+ 1.2V supply to CSIPHY IP blocks.
ports:
$ref: /schemas/graph.yaml#/properties/ports
vdda-phy-supply:
description:
- Phandle to a regulator supply to PHY core block.
+ 0.88V supply to CSIPHY IP blocks.
vdda-pll-supply:
description:
- Phandle to 1.8V regulator supply to PHY refclk pll block.
+ 1.2V supply to CSIPHY IP blocks.
ports:
$ref: /schemas/graph.yaml#/properties/ports
vdda-phy-supply:
description:
- Phandle to a regulator supply to PHY core block.
+ 0.88V supply to CSIPHY IP blocks.
vdda-pll-supply:
description:
- Phandle to 1.8V regulator supply to PHY refclk pll block.
+ 1.2V supply to CSIPHY IP blocks.
required:
- clock-names
vdda-phy-supply:
description:
- Phandle to a regulator supply to PHY core block.
+ 0.88V supply to CSIPHY IP blocks.
vdda-pll-supply:
description:
- Phandle to 1.8V regulator supply to PHY refclk pll block.
+ 1.2V supply to CSIPHY IP blocks.
ports:
$ref: /schemas/graph.yaml#/properties/ports
vdda-phy-supply:
description:
- Phandle to a regulator supply to PHY core block.
+ 0.88V supply to CSIPHY IP blocks.
vdda-pll-supply:
description:
- Phandle to 1.8V regulator supply to PHY refclk pll block.
+ 1.2V supply to CSIPHY IP blocks.
required:
- clock-names
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,sm6150-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6150 Camera Subsystem (CAMSS)
+
+maintainers:
+ - Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
+
+description:
+ This binding describes the camera subsystem hardware found on SM6150
+ Qualcomm SoCs. It includes submodules such as CSIPHY (CSI Physical layer)
+ and CSID (CSI Decoder), which comply with the MIPI CSI2 protocol.
+
+ The subsystem also integrates a set of real-time image processing engines
+ and their associated configuration modules, as well as non-real-time engines.
+
+properties:
+ compatible:
+ const: qcom,sm6150-camss
+
+ reg:
+ items:
+ - description: Registers for CSID 0
+ - description: Registers for CSID 1
+ - description: Registers for CSID Lite
+ - description: Registers for CSIPHY 0
+ - description: Registers for CSIPHY 1
+ - description: Registers for CSIPHY 2
+ - description: Registers for VFE 0
+ - description: Registers for VFE 1
+ - description: Registers for VFE Lite
+ - description: Registers for BPS (Bayer Processing Segment)
+ - description: Registers for CAMNOC
+ - description: Registers for CPAS CDM
+ - description: Registers for CPAS TOP
+ - description: Registers for ICP (Imaging Control Processor) CSR (Control and Status Registers)
+ - description: Registers for ICP QGIC (Qualcomm Generic Interrupt Controller)
+ - description: Registers for ICP SIERRA ((A5 subsystem communication))
+ - description: Registers for IPE (Image Postprocessing Engine) 0
+ - description: Registers for JPEG DMA
+ - description: Registers for JPEG ENC
+ - description: Registers for LRME (Low Resolution Motion Estimation)
+
+ reg-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid_lite
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: vfe0
+ - const: vfe1
+ - const: vfe_lite
+ - const: bps
+ - const: camnoc
+ - const: cpas_cdm
+ - const: cpas_top
+ - const: icp_csr
+ - const: icp_qgic
+ - const: icp_sierra
+ - const: ipe0
+ - const: jpeg_dma
+ - const: jpeg_enc
+ - const: lrme
+
+ clocks:
+ maxItems: 33
+
+ clock-names:
+ items:
+ - const: gcc_ahb
+ - const: gcc_axi_hf
+ - const: camnoc_axi
+ - const: cpas_ahb
+ - const: csiphy0
+ - const: csiphy0_timer
+ - const: csiphy1
+ - const: csiphy1_timer
+ - const: csiphy2
+ - const: csiphy2_timer
+ - const: soc_ahb
+ - const: vfe0
+ - const: vfe0_axi
+ - const: vfe0_cphy_rx
+ - const: vfe0_csid
+ - const: vfe1
+ - const: vfe1_axi
+ - const: vfe1_cphy_rx
+ - const: vfe1_csid
+ - const: vfe_lite
+ - const: vfe_lite_cphy_rx
+ - const: vfe_lite_csid
+ - const: bps
+ - const: bps_ahb
+ - const: bps_axi
+ - const: bps_areg
+ - const: icp
+ - const: ipe0
+ - const: ipe0_ahb
+ - const: ipe0_areg
+ - const: ipe0_axi
+ - const: jpeg
+ - const: lrme
+
+ interrupts:
+ maxItems: 15
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid_lite
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: vfe0
+ - const: vfe1
+ - const: vfe_lite
+ - const: camnoc
+ - const: cdm
+ - const: icp
+ - const: jpeg_dma
+ - const: jpeg_enc
+ - const: lrme
+
+ interconnects:
+ maxItems: 4
+
+ interconnect-names:
+ items:
+ - const: ahb
+ - const: hf_0
+ - const: hf_1
+ - const: sf_mnoc
+
+ iommus:
+ items:
+ - description: Camera IFE 0 non-protected stream
+ - description: Camera IFE 1 non-protected stream
+ - description: Camera IFE 3 non-protected stream
+ - description: Camera CDM non-protected stream
+ - description: Camera LRME read non-protected stream
+ - description: Camera IPE 0 read non-protected stream
+ - description: Camera BPS read non-protected stream
+ - description: Camera IPE 0 write non-protected stream
+ - description: Camera BPS write non-protected stream
+ - description: Camera LRME write non-protected stream
+ - description: Camera JPEG read non-protected stream
+ - description: Camera JPEG write non-protected stream
+ - description: Camera ICP stream
+
+ power-domains:
+ items:
+ - description:
+ IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description:
+ IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description:
+ Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
+ - description:
+ Titan BPS - Bayer Processing Segment, Global Distributed Switch Controller.
+ - description:
+ IPE GDSC - Image Postprocessing Engine, Global Distributed Switch Controller.
+
+ power-domain-names:
+ items:
+ - const: ife0
+ - const: ife1
+ - const: top
+ - const: bps
+ - const: ipe
+
+ vdd-csiphy-1p2-supply:
+ description:
+ Phandle to a 1.2V regulator supply to CSI PHYs.
+
+ vdd-csiphy-1p8-supply:
+ description:
+ Phandle to 1.8V regulator supply to CSI PHYs pll block.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ patternProperties:
+ "^port@[0-2]$":
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+
+ description:
+ Input port for receiving CSI data from a CSIPHY.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - data-lanes
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - interconnects
+ - interconnect-names
+ - iommus
+ - power-domains
+ - power-domain-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,qcs615-camcc.h>
+ #include <dt-bindings/clock/qcom,qcs615-gcc.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ camss: isp@acb3000 {
+ compatible = "qcom,sm6150-camss";
+
+ reg = <0x0 0x0acb3000 0x0 0x1000>,
+ <0x0 0x0acba000 0x0 0x1000>,
+ <0x0 0x0acc8000 0x0 0x1000>,
+ <0x0 0x0ac65000 0x0 0x1000>,
+ <0x0 0x0ac66000 0x0 0x1000>,
+ <0x0 0x0ac67000 0x0 0x1000>,
+ <0x0 0x0acaf000 0x0 0x4000>,
+ <0x0 0x0acb6000 0x0 0x4000>,
+ <0x0 0x0acc4000 0x0 0x4000>,
+ <0x0 0x0ac6f000 0x0 0x3000>,
+ <0x0 0x0ac42000 0x0 0x5000>,
+ <0x0 0x0ac48000 0x0 0x1000>,
+ <0x0 0x0ac40000 0x0 0x1000>,
+ <0x0 0x0ac18000 0x0 0x3000>,
+ <0x0 0x0ac00000 0x0 0x6000>,
+ <0x0 0x0ac10000 0x0 0x8000>,
+ <0x0 0x0ac87000 0x0 0x3000>,
+ <0x0 0x0ac52000 0x0 0x4000>,
+ <0x0 0x0ac4e000 0x0 0x4000>,
+ <0x0 0x0ac6b000 0x0 0x0a00>;
+ reg-names = "csid0",
+ "csid1",
+ "csid_lite",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "vfe0",
+ "vfe1",
+ "vfe_lite",
+ "bps",
+ "camnoc",
+ "cpas_cdm",
+ "cpas_top",
+ "icp_csr",
+ "icp_qgic",
+ "icp_sierra",
+ "ipe0",
+ "jpeg_dma",
+ "jpeg_enc",
+ "lrme";
+
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_SOC_AHB_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_AXI_CLK>,
+ <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_0_CSID_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_AXI_CLK>,
+ <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_1_CSID_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&camcc CAM_CC_BPS_CLK>,
+ <&camcc CAM_CC_BPS_AHB_CLK>,
+ <&camcc CAM_CC_BPS_AXI_CLK>,
+ <&camcc CAM_CC_BPS_AREG_CLK>,
+ <&camcc CAM_CC_ICP_CLK>,
+ <&camcc CAM_CC_IPE_0_CLK>,
+ <&camcc CAM_CC_IPE_0_AHB_CLK>,
+ <&camcc CAM_CC_IPE_0_AREG_CLK>,
+ <&camcc CAM_CC_IPE_0_AXI_CLK>,
+ <&camcc CAM_CC_JPEG_CLK>,
+ <&camcc CAM_CC_LRME_CLK>;
+
+ clock-names = "gcc_ahb",
+ "gcc_axi_hf",
+ "camnoc_axi",
+ "cpas_ahb",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "soc_ahb",
+ "vfe0",
+ "vfe0_axi",
+ "vfe0_cphy_rx",
+ "vfe0_csid",
+ "vfe1",
+ "vfe1_axi",
+ "vfe1_cphy_rx",
+ "vfe1_csid",
+ "vfe_lite",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid",
+ "bps",
+ "bps_ahb",
+ "bps_axi",
+ "bps_areg",
+ "icp",
+ "ipe0",
+ "ipe0_ahb",
+ "ipe0_areg",
+ "ipe0_axi",
+ "jpeg",
+ "lrme";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_HF1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_0",
+ "hf_1",
+ "sf_mnoc";
+
+ interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 459 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 461 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 474 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 476 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid_lite",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "vfe0",
+ "vfe1",
+ "vfe_lite",
+ "camnoc",
+ "cdm",
+ "icp",
+ "jpeg_dma",
+ "jpeg_enc",
+ "lrme";
+
+ iommus = <&apps_smmu 0x0820 0x40>,
+ <&apps_smmu 0x0840 0x00>,
+ <&apps_smmu 0x0860 0x40>,
+ <&apps_smmu 0x0c00 0x00>,
+ <&apps_smmu 0x0cc0 0x00>,
+ <&apps_smmu 0x0c80 0x00>,
+ <&apps_smmu 0x0ca0 0x00>,
+ <&apps_smmu 0x0d00 0x00>,
+ <&apps_smmu 0x0d20 0x00>,
+ <&apps_smmu 0x0d40 0x00>,
+ <&apps_smmu 0x0d80 0x20>,
+ <&apps_smmu 0x0da0 0x20>,
+ <&apps_smmu 0x0de2 0x00>;
+
+ power-domains = <&camcc IFE_0_GDSC>,
+ <&camcc IFE_1_GDSC>,
+ <&camcc TITAN_TOP_GDSC>,
+ <&camcc BPS_GDSC>,
+ <&camcc IPE_0_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "top",
+ "bps",
+ "ipe";
+
+ vdd-csiphy-1p2-supply = <&vreg_l11a_1p2>;
+ vdd-csiphy-1p8-supply = <&vreg_l12a_1p8>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ csiphy_ep0: endpoint {
+ data-lanes = <0 1>;
+ remote-endpoint = <&sensor_ep>;
+ };
+ };
+ };
+ };
+ };
vdda-phy-supply:
description:
- Phandle to a regulator supply to PHY core block.
+ 0.88V supply to CSIPHY IP blocks.
vdda-pll-supply:
description:
- Phandle to 1.8V regulator supply to PHY refclk pll block.
+ 1.2V supply to CSIPHY IP blocks.
required:
- clock-names
vdda-phy-supply:
description:
- Phandle to a regulator supply to PHY core block.
+ 0.88V supply to CSIPHY IP blocks.
vdda-pll-supply:
description:
- Phandle to 1.2V regulator supply to PHY refclk pll block.
+ 1.2V supply to CSIPHY IP blocks.
ports:
$ref: /schemas/graph.yaml#/properties/ports
vdd-csiphy-0p8-supply:
description:
- Phandle to a 0.8V regulator supply to a PHY.
+ 0.8V supply to a PHY.
vdd-csiphy-1p2-supply:
description:
- Phandle to 1.2V regulator supply to a PHY.
+ 1.2V supply to a PHY.
ports:
$ref: /schemas/graph.yaml#/properties/ports
- renesas,r9a07g043u-fcpvd
- renesas,r9a07g044-fcpvd
- renesas,r9a07g054-fcpvd
+ - renesas,r9a09g056-fcpvd
- renesas,r9a09g057-fcpvd
then:
properties:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/rockchip,rk3568-mipi-csi2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip MIPI CSI-2 Receiver
+
+maintainers:
+ - Michael Riesch <michael.riesch@collabora.com>
+
+description:
+ The Rockchip MIPI CSI-2 Receiver is a CSI-2 bridge with one input port and
+ one output port. It receives the data with the help of an external MIPI PHY
+ (C-PHY or D-PHY) and passes it to the Rockchip Video Capture (VICAP) block.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3568-mipi-csi2
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: Interrupt that signals changes in CSI2HOST_ERR1.
+ - description: Interrupt that signals changes in CSI2HOST_ERR2.
+
+ interrupt-names:
+ items:
+ - const: err1
+ - const: err2
+
+ clocks:
+ maxItems: 1
+
+ phys:
+ maxItems: 1
+ description: MIPI C-PHY or D-PHY.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: Input port node. Connect to e.g., a MIPI CSI-2 image sensor.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ bus-type:
+ enum:
+ - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
+ - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - bus-type
+ - data-lanes
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Output port connected to a Rockchip VICAP port.
+
+ required:
+ - port@0
+ - port@1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - phys
+ - ports
+ - power-domains
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3568-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/media/video-interfaces.h>
+ #include <dt-bindings/power/rk3568-power.h>
+
+ soc {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ csi: csi@fdfb0000 {
+ compatible = "rockchip,rk3568-mipi-csi2";
+ reg = <0x0 0xfdfb0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "err1", "err2";
+ clocks = <&cru PCLK_CSI2HOST1>;
+ phys = <&csi_dphy>;
+ power-domains = <&power RK3568_PD_VI>;
+ resets = <&cru SRST_P_CSI2HOST1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi_in: port@0 {
+ reg = <0>;
+
+ csi_input: endpoint {
+ bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&imx415_output>;
+ };
+ };
+
+ csi_out: port@1 {
+ reg = <1>;
+
+ csi_output: endpoint {
+ remote-endpoint = <&vicap_mipi_input>;
+ };
+ };
+ };
+ };
+ };
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- - Seung-Woo Kim <sw0312.kim@samsung.com
+ - Seung-Woo Kim <sw0312.kim@samsung.com>
description:
G-Scaler is used for scaling and color space conversion on Samsung Exynos
resets:
maxItems: 1
+ power-domains:
+ maxItems: 1
+
access-controllers:
minItems: 1
maxItems: 2
minItems: 1
maxItems: 2
+ power-domains:
+ maxItems: 1
+
ports:
$ref: /schemas/graph.yaml#/properties/ports
+++ /dev/null
-OMAP 3 ISP Device Tree bindings
-===============================
-
-The DT definitions can be found in include/dt-bindings/media/omap3-isp.h.
-
-Required properties
-===================
-
-compatible : must contain "ti,omap3-isp"
-
-reg : the two registers sets (physical address and length) for the
- ISP. The first set contains the core ISP registers up to
- the end of the SBL block. The second set contains the
- CSI PHYs and receivers registers.
-interrupts : the ISP interrupt specifier
-iommus : phandle and IOMMU specifier for the IOMMU that serves the ISP
-syscon : the phandle and register offset to the Complex I/O or CSI-PHY
- register
-ti,phy-type : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430)
- 1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630)
-#clock-cells : Must be 1 --- the ISP provides two external clocks,
- cam_xclka and cam_xclkb, at indices 0 and 1,
- respectively. Please find more information on common
- clock bindings in ../clock/clock-bindings.txt.
-
-Port nodes (optional)
----------------------
-
-More documentation on these bindings is available in
-video-interfaces.txt in the same directory.
-
-reg : The interface:
- 0 - parallel (CCDC)
- 1 - CSIPHY1 -- CSI2C / CCP2B on 3630;
- CSI1 -- CSIb on 3430
- 2 - CSIPHY2 -- CSI2A / CCP2B on 3630;
- CSI2 -- CSIa on 3430
-
-Optional properties
-===================
-
-vdd-csiphy1-supply : voltage supply of the CSI-2 PHY 1
-vdd-csiphy2-supply : voltage supply of the CSI-2 PHY 2
-
-Endpoint nodes
---------------
-
-lane-polarities : lane polarity (required on CSI-2)
- 0 -- not inverted; 1 -- inverted
-data-lanes : an array of data lanes from 1 to 3. The length can
- be either 1 or 2. (required on CSI-2)
-clock-lanes : the clock lane (from 1 to 3). (required on CSI-2)
-
-
-Example
-=======
-
- isp@480bc000 {
- compatible = "ti,omap3-isp";
- reg = <0x480bc000 0x12fc
- 0x480bd800 0x0600>;
- interrupts = <24>;
- iommus = <&mmu_isp>;
- syscon = <&scm_conf 0x2f0>;
- ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
- #clock-cells = <1>;
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/ti,omap3isp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments OMAP 3 Image Signal Processor (ISP)
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+ - Sakari Ailus <sakari.ailus@iki.fi>
+
+description:
+ The OMAP 3 ISP is an image signal processor present in OMAP 3 SoCs.
+
+properties:
+ compatible:
+ const: ti,omap3-isp
+
+ reg:
+ items:
+ - description: Core ISP registers up to the end of the SBL block
+ - description: CSI PHYs and receivers registers
+
+ interrupts:
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+ syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to System Control Module
+ - description: register offset to Complex I/O or CSI-PHY register
+ description:
+ Phandle and register offset to the Complex I/O or CSI-PHY register
+
+ ti,phy-type:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+ description:
+ 0 - OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. OMAP 3430)
+ 1 - OMAP3ISP_PHY_TYPE_CSIPHY (e.g. OMAP 3630)
+
+ '#clock-cells':
+ const: 1
+ description:
+ The ISP provides two external clocks, cam_xclka and cam_xclkb,
+ at indices 0 and 1 respectively.
+
+ vdd-csiphy1-supply:
+ description: Voltage supply of the CSI-2 PHY 1
+
+ vdd-csiphy2-supply:
+ description: Voltage supply of the CSI-2 PHY 2
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: Parallel (CCDC) interface
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ port@1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: |
+ CSIPHY1 interface:
+ OMAP 3630: CSI2C / CCP2B
+ OMAP 3430: CSI1 (CSIb)
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ lane-polarities:
+ minItems: 2
+ maxItems: 3
+
+ data-lanes:
+ minItems: 1
+ maxItems: 2
+ items:
+ minimum: 1
+ maximum: 3
+
+ clock-lanes:
+ minimum: 1
+ maximum: 3
+
+ port@2:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: |
+ CSIPHY2 interface:
+ OMAP 3630: CSI2A / CCP2B
+ OMAP 3430: CSI2 (CSIa)
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ lane-polarities:
+ minItems: 2
+ maxItems: 3
+
+ data-lanes:
+ minItems: 1
+ maxItems: 2
+ items:
+ minimum: 1
+ maximum: 3
+
+ clock-lanes:
+ minimum: 1
+ maximum: 3
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - iommus
+ - syscon
+ - ti,phy-type
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/media/omap3-isp.h>
+
+ isp@480bc000 {
+ compatible = "ti,omap3-isp";
+ reg = <0x480bc000 0x12fc>,
+ <0x480bd800 0x0600>;
+ interrupts = <24>;
+ iommus = <&mmu_isp>;
+ syscon = <&scm_conf 0x2f0>;
+ ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
+ #clock-cells = <1>;
+ vdd-csiphy1-supply = <&vaux2>;
+ vdd-csiphy2-supply = <&vaux2>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ parallel_ep: endpoint {
+ remote-endpoint = <¶llel>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ csi1_ep: endpoint {
+ remote-endpoint = <&smia_1>;
+ clock-lanes = <1>;
+ data-lanes = <2>;
+ lane-polarities = <0 0>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ csi2a_ep: endpoint {
+ remote-endpoint = <&smia_2>;
+ clock-lanes = <2>;
+ data-lanes = <1 3>;
+ lane-polarities = <1 1 1>;
+ };
+ };
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com/
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/ti,vip.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments DRA7x Video Input Port (VIP)
+
+maintainers:
+ - Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
+
+description: |-
+ Video Input Port (VIP) can be found on devices such as DRA7xx and
+ provides the system interface and the processing capability to
+ connect parallel image-sensor as well as BT.656/1120 capable encoder
+ chip to DRA7x device.
+
+ Each VIP instance supports 2 independently configurable external
+ video input capture slices (Slice 0 and Slice 1) each providing
+ up to two video input ports (Port A and Port B).
+
+properties:
+ compatible:
+ enum:
+ - ti,dra7-vip
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: IRQ index 0 is used for Slice0 interrupts
+ - description: IRQ index 1 is used for Slice1 interrupts
+
+ ti,ctrl-module:
+ description:
+ Reference to the device control module that provides clock-edge
+ inversion control for VIP ports. These controls allow the
+ VIP to sample pixel data on the correct clock edge.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle to device control module
+ - description: offset to the CTRL_CORE_SMA_SW_1 register
+ - description: Bit field to slice 0 port A
+ - description: Bit field to slice 0 port B
+ - description: Bit field to slice 1 port A
+ - description: Bit field to slice 1 port B
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ patternProperties:
+ '^port@[0-3]$':
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: |
+ Each VIP instance supports 2 independently configurable external video
+ input capture slices (Slice 0 and Slice 1) each providing up to two video
+ input ports (Port A and Port B). These ports represent the following
+ port@0 -> Slice 0 Port A
+ port@1 -> Slice 0 Port B
+ port@2 -> Slice 1 Port A
+ port@3 -> Slice 1 Port B
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ bus-width:
+ enum: [8, 16, 24]
+ default: 8
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - ti,ctrl-module
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ video@48970000 {
+ compatible = "ti,dra7-vip";
+ reg = <0x48970000 0x1000>;
+ interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
+ ti,ctrl-module = <&scm_conf 0x534 0x0 0x2 0x1 0x3>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vin1a: port@0 {
+ reg = <0>;
+
+ vin1a_ep: endpoint {
+ remote-endpoint = <&camera1>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ pclk-sample = <0>;
+ bus-width = <8>;
+ };
+ };
+
+ vin1b: port@1 {
+ reg = <1>;
+
+ vin1b_ep: endpoint {
+ remote-endpoint = <&camera2>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ pclk-sample = <0>;
+ bus-width = <8>;
+ };
+ };
+
+ vin2a: port@2 {
+ reg = <2>;
+
+ vin2a_ep: endpoint {
+ remote-endpoint = <&camera3>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ pclk-sample = <0>;
+ bus-width = <16>;
+ };
+ };
+
+ vin2b: port@3 {
+ reg = <3>;
+
+ vin2b_ep: endpoint {
+ remote-endpoint = <&camera4>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ pclk-sample = <0>;
+ bus-width = <8>;
+ };
+ };
+ };
+ };
+...
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,ddr4.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: DDR4 SDRAM compliant to JEDEC JESD79-4D
+
+maintainers:
+ - Krzysztof Kozlowski <krzk@kernel.org>
+
+allOf:
+ - $ref: jedec,sdram-props.yaml#
+
+properties:
+ compatible:
+ items:
+ - pattern: "^ddr4-[0-9a-f]{4},[a-z]{1,20}-[0-9a-f]{2}$"
+ - const: jedec,ddr4
+
+required:
+ - compatible
+ - density
+ - io-width
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ ddr {
+ compatible = "ddr4-00ff,azaz-ff", "jedec,ddr4";
+ density = <8192>;
+ io-width = <8>;
+ };
+++ /dev/null
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-props.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Common properties for LPDDR types
-
-description:
- Different LPDDR types generally use the same properties and only differ in the
- range of legal values for each. This file defines the common parts that can be
- reused for each type. Nodes using this schema should generally be nested under
- an LPDDR channel node.
-
-maintainers:
- - Krzysztof Kozlowski <krzk@kernel.org>
-
-properties:
- compatible:
- description:
- Compatible strings can be either explicit vendor names and part numbers
- (e.g. elpida,ECB240ABACN), or generated strings of the form
- lpddrX-YY,ZZZZ where X is the LPDDR version, YY is the manufacturer ID
- (from MR5) and ZZZZ is the revision ID (from MR6 and MR7). Both IDs are
- formatted in lower case hexadecimal representation with leading zeroes.
- The latter form can be useful when LPDDR nodes are created at runtime by
- boot firmware that doesn't have access to static part number information.
-
- reg:
- description:
- The rank number of this LPDDR rank when used as a subnode to an LPDDR
- channel.
- minimum: 0
- maximum: 3
-
- revision-id:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- description:
- Revision IDs read from Mode Register 6 and 7. One byte per uint32 cell (i.e. <MR6 MR7>).
- maxItems: 2
- items:
- minimum: 0
- maximum: 255
-
- density:
- $ref: /schemas/types.yaml#/definitions/uint32
- description:
- Density in megabits of SDRAM chip. Decoded from Mode Register 8.
- enum:
- - 64
- - 128
- - 256
- - 512
- - 1024
- - 2048
- - 3072
- - 4096
- - 6144
- - 8192
- - 12288
- - 16384
- - 24576
- - 32768
-
- io-width:
- $ref: /schemas/types.yaml#/definitions/uint32
- description:
- IO bus width in bits of SDRAM chip. Decoded from Mode Register 8.
- enum:
- - 8
- - 16
- - 32
-
-additionalProperties: true
- Krzysztof Kozlowski <krzk@kernel.org>
allOf:
- - $ref: jedec,lpddr-props.yaml#
+ - $ref: jedec,sdram-props.yaml#
properties:
compatible:
- Krzysztof Kozlowski <krzk@kernel.org>
allOf:
- - $ref: jedec,lpddr-props.yaml#
+ - $ref: jedec,sdram-props.yaml#
properties:
compatible:
- Krzysztof Kozlowski <krzk@kernel.org>
allOf:
- - $ref: jedec,lpddr-props.yaml#
+ - $ref: jedec,sdram-props.yaml#
properties:
compatible:
- Krzysztof Kozlowski <krzk@kernel.org>
allOf:
- - $ref: jedec,lpddr-props.yaml#
+ - $ref: jedec,sdram-props.yaml#
properties:
compatible:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
+$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-channel.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: LPDDR channel with chip/rank topology description
+title: SDRAM channel with chip/rank topology description
description:
- An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS,
- CK, etc.) that connect one or more LPDDR chips to a host system. The main
- purpose of this node is to overall LPDDR topology of the system, including the
- amount of individual LPDDR chips and the ranks per chip.
+ A memory channel of SDRAM memory like DDR SDRAM or LPDDR SDRAM is a completely
+ independent set of pins (DQ, CA, CS, CK, etc.) that connect one or more memory
+ chips to a host system. The main purpose of this node is to overall memory
+ topology of the system, including the amount of individual memory chips and
+ the ranks per chip.
maintainers:
- Julius Werner <jwerner@chromium.org>
properties:
+ $nodename:
+ pattern: "sdram-channel-[0-9]+$"
+
compatible:
enum:
+ - jedec,ddr4-channel
- jedec,lpddr2-channel
- jedec,lpddr3-channel
- jedec,lpddr4-channel
io-width:
description:
The number of DQ pins in the channel. If this number is different
- from (a multiple of) the io-width of the LPDDR chip, that means that
+ from (a multiple of) the io-width of the SDRAM chip, that means that
multiple instances of that type of chip are wired in parallel on this
channel (with the channel's DQ pins split up between the different
chips, and the CA, CS, etc. pins of the different chips all shorted
together). This means that the total physical memory controlled by a
channel is equal to the sum of the densities of each rank on the
- connected LPDDR chip, times the io-width of the channel divided by
- the io-width of the LPDDR chip.
+ connected SDRAM chip, times the io-width of the channel divided by
+ the io-width of the SDRAM chip.
enum:
- 8
- 16
"^rank@[0-9]+$":
type: object
description:
- Each physical LPDDR chip may have one or more ranks. Ranks are
- internal but fully independent sub-units of the chip. Each LPDDR bus
+ Each physical SDRAM chip may have one or more ranks. Ranks are
+ internal but fully independent sub-units of the chip. Each SDRAM bus
transaction on the channel targets exactly one rank, based on the
state of the CS pins. Different ranks may have different densities and
timing requirements.
- reg
allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: jedec,ddr4-channel
+ then:
+ patternProperties:
+ "^rank@[0-9]+$":
+ $ref: /schemas/memory-controllers/ddr/jedec,ddr4.yaml#
- if:
properties:
compatible:
examples:
- |
- lpddr-channel0 {
+ sdram-channel-0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "jedec,lpddr3-channel";
};
};
- lpddr-channel1 {
+ sdram-channel-1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "jedec,lpddr4-channel";
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-props.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Common properties for SDRAM types
+
+description:
+ Different SDRAM types generally use the same properties and only differ in the
+ range of legal values for each. This file defines the common parts that can be
+ reused for each type. Nodes using this schema should generally be nested under
+ a SDRAM channel node.
+
+maintainers:
+ - Krzysztof Kozlowski <krzk@kernel.org>
+
+properties:
+ compatible:
+ description: |
+ Compatible strings can be either explicit vendor names and part numbers
+ (e.g. elpida,ECB240ABACN), or generated strings of the form
+ lpddrX-YY,ZZZZ or ddrX-YYYY,AAAA...-ZZ where X, Y, and Z are lowercase
+ hexadecimal with leading zeroes, and A is lowercase ASCII.
+ For LPDDR and DDR SDRAM, X is the SDRAM version (2, 3, 4, etc.).
+ For LPDDR SDRAM:
+ - YY is the manufacturer ID (from MR5), 1 byte
+ - ZZZZ is the revision ID (from MR6 and MR7), 2 bytes
+ For DDR4 SDRAM with SPD, according to JEDEC SPD4.1.2.L-6:
+ - YYYY is the manufacturer ID, 2 bytes, from bytes 320 and 321
+ - AAAA... is the part number, 20 bytes (20 chars) from bytes 329 to 348
+ without trailing spaces
+ - ZZ is the revision ID, 1 byte, from byte 349
+ The former form is useful when the SDRAM vendor and part number are
+ known, for example, when memory is soldered on the board. The latter
+ form is useful when SDRAM nodes are created at runtime by boot firmware
+ that doesn't have access to static part number information.
+
+ reg:
+ description:
+ The rank number of this memory rank when used as a subnode to an memory
+ channel.
+ minimum: 0
+ maximum: 3
+
+ revision-id:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ SDRAM revision ID:
+ - LPDDR SDRAM, decoded from Mode Registers 6 and 7, always 2 bytes.
+ - DDR4 SDRAM, decoded from the SPD from byte 349 according to
+ JEDEC SPD4.1.2.L-6, always 1 byte.
+ One byte per uint32 cell (e.g., <MR6 MR7>).
+ maxItems: 2
+ items:
+ minimum: 0
+ maximum: 255
+
+ density:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Density of the SDRAM chip in megabits:
+ - LPDDR SDRAM, decoded from Mode Register 8.
+ - DDR4 SDRAM, decoded from the SPD from bits 3-0 of byte 4 according to
+ JEDEC SPD4.1.2.L-6.
+ enum:
+ - 64
+ - 128
+ - 256
+ - 512
+ - 1024
+ - 2048
+ - 3072
+ - 4096
+ - 6144
+ - 8192
+ - 12288
+ - 16384
+ - 24576
+ - 32768
+
+ io-width:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ I/O bus width in bits of the SDRAM chip:
+ - LPDDR SDRAM, decoded from Mode Register 8.
+ - DDR4 SDRAM, decoded from the SPD from bits 2-0 of byte 12 according to
+ JEDEC SPD4.1.2.L-6.
+ enum:
+ - 8
+ - 16
+ - 32
+
+additionalProperties: true
clocks:
items:
- description: external memory clock
+ - description: data backbone clock
+ minItems: 1
clock-names:
items:
- const: emc
+ - const: dbb
+ minItems: 1
"#interconnect-cells":
const: 0
reg:
maxItems: 1
+ clocks:
+ maxItems: 1
+
- if:
properties:
compatible:
reg:
minItems: 2
+ clocks:
+ maxItems: 1
+
- if:
properties:
compatible:
reg:
minItems: 2
+ clocks:
+ maxItems: 1
+
- if:
properties:
compatible:
- description: silicon id information registers
- description: unique chip id registers
+ '^smp-memram@[0-9a-f]+$':
+ description: Memory region used for the AST2600's custom SMP bringup protocol
+ type: object
+ additionalProperties: false
+
+ properties:
+ compatible:
+ const: aspeed,ast2600-smpmem
+
+ reg:
+ description: The SMP memory region
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+
required:
- compatible
- reg
- atmel,sama5d4-hlcdc
- microchip,sam9x60-hlcdc
- microchip,sam9x75-xlcdc
+ - microchip,sama7d65-xlcdc
reg:
maxItems: 1
- const: atmel,sama5d2-flexcom
- items:
- enum:
+ - microchip,lan9691-flexcom
- microchip,sam9x7-flexcom
- microchip,sama7d65-flexcom
- microchip,sama7g5-flexcom
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/bitmain,bm1880-sctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bitmain BM1880 System Controller
+
+maintainers:
+ - Manivannan Sadhasivam <mani@kernel.org>
+
+properties:
+ compatible:
+ items:
+ - const: bitmain,bm1880-sctrl
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ ranges: true
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+patternProperties:
+ '^pinctrl@[0-9a-f]+$':
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ contains:
+ const: bitmain,bm1880-pinctrl
+
+ '^clock-controller@[0-9a-f]+$':
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ contains:
+ const: bitmain,bm1880-clk
+
+ '^reset-controller@[0-9a-f]+$':
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ contains:
+ const: bitmain,bm1880-reset
+
+required:
+ - compatible
+ - reg
+ - ranges
+ - '#address-cells'
+ - '#size-cells'
+
+additionalProperties: false
+...
is instantiated separately from the PMIC.
For details on accompanying CODEC I2C device, see the following:
-Documentation/devicetree/bindings/sound/da9055.txt
+Documentation/devicetree/bindings/sound/trivial-codec.yaml
======
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/iei,wt61p803-puzzle.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: IEI WT61P803 PUZZLE MCU from IEI Integration Corp.
+
+maintainers:
+ - Luka Kovacic <luka.kovacic@sartura.hr>
+
+description: |
+ IEI WT61P803 PUZZLE MCU is embedded in some IEI Puzzle series boards.
+ It's used for controlling system power states, fans, LEDs and temperature
+ sensors.
+
+ For Device Tree bindings of other sub-modules (HWMON, LEDs) refer to the
+ binding documents under the respective subsystem directories.
+
+properties:
+ compatible:
+ const: iei,wt61p803-puzzle
+
+ current-speed: true
+
+ enable-beep:
+ type: boolean
+
+ hwmon:
+ $ref: /schemas/hwmon/iei,wt61p803-puzzle-hwmon.yaml
+
+ leds:
+ $ref: /schemas/leds/iei,wt61p803-puzzle-leds.yaml
+
+required:
+ - compatible
+ - current-speed
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/leds/common.h>
+ serial {
+ mcu {
+ compatible = "iei,wt61p803-puzzle";
+ current-speed = <115200>;
+ enable-beep;
+
+ leds {
+ compatible = "iei,wt61p803-puzzle-leds";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+
+ hwmon {
+ compatible = "iei,wt61p803-puzzle-hwmon";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fan-group@0 {
+ #cooling-cells = <2>;
+ reg = <0x00>;
+ cooling-levels = <64 102 170 230 250>;
+ };
+
+ fan-group@1 {
+ #cooling-cells = <2>;
+ reg = <0x01>;
+ cooling-levels = <64 102 170 230 250>;
+ };
+ };
+ };
+ };
- enum:
- mediatek,mt6323-regulator
- mediatek,mt6328-regulator
+ - mediatek,mt6331-regulator
- mediatek,mt6358-regulator
- mediatek,mt6359-regulator
- mediatek,mt6397-regulator
title: MediaTek System Control Processor System
maintainers:
- - MandyJH Liu <mandyjh.liu@mediatek.com>
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ - Matthias Brugger <matthias.bgg@gmail.com>
description:
MediaTek System Control Processor System (SCPSYS) has several
compatible:
items:
- enum:
+ - mediatek,mt6795-scpsys
- mediatek,mt6893-scpsys
- mediatek,mt8167-scpsys
- mediatek,mt8173-scpsys
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/nxp,lpc3220-scb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP LPC32xx System Control Block
+
+maintainers:
+ - Vladimir Zapolskiy <vz@mleia.com>
+
+description:
+ NXP LPC32xx SoC series have a System Control Block, which serves for
+ a multitude of purposes including clock management, DMA muxes, storing
+ SoC unique ID etc.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - nxp,lpc3220-scb
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ ranges: true
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+patternProperties:
+ "^clock-controller@[0-9a-f]+$":
+ $ref: /schemas/clock/nxp,lpc3220-clk.yaml#
+
+ "^dma-router@[0-9a-f]+$":
+ $ref: /schemas/dma/nxp,lpc3220-dmamux.yaml#
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@400040000 {
+ compatible = "nxp,lpc3220-scb", "syscon", "simple-mfd";
+ reg = <0x40004000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x40004000 0x1000>;
+
+ clock-controller@0 {
+ compatible = "nxp,lpc3220-clk";
+ reg = <0x0 0x114>;
+ clocks = <&xtal_32k>, <&xtal>;
+ clock-names = "xtal_32k", "xtal";
+ #clock-cells = <1>;
+ };
+
+ dma-router@78 {
+ compatible = "nxp,lpc3220-dmamux";
+ reg = <0x78 0x8>;
+ dma-masters = <&dma>;
+ #dma-cells = <3>;
+ };
+ };
- qcom,pmc8180
- qcom,pmc8180c
- qcom,pmc8380
+ - qcom,pmcx0102
- qcom,pmd8028
- qcom,pmd9635
+ - qcom,pmh0101
+ - qcom,pmh0104
+ - qcom,pmh0110
- qcom,pmi632
- qcom,pmi8950
- qcom,pmi8962
- qcom,pmk8002
- qcom,pmk8350
- qcom,pmk8550
+ - qcom,pmk8850
- qcom,pmm8155au
- qcom,pmm8654au
- qcom,pmp8074
- qcom,pmx75
- qcom,smb2351
- qcom,smb2360
+ - qcom,smb2370
- const: qcom,spmi-pmic
reg:
properties:
compatible:
enum:
+ - qnap,ts133-mcu
- qnap,ts233-mcu
- qnap,ts433-mcu
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/realtek,rtd1xxx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Realtek RTD1xxx system controllers
+
+maintainers:
+ - Andreas Färber <afaerber@suse.de>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - realtek,rtd1293-crt
+ - realtek,rtd1293-iso
+ - realtek,rtd1293-misc
+ - realtek,rtd1293-sb2
+ - realtek,rtd1293-scpu-wrapper
+ - realtek,rtd1295-crt
+ - realtek,rtd1295-iso
+ - realtek,rtd1295-misc
+ - realtek,rtd1295-sb2
+ - realtek,rtd1295-scpu-wrapper
+ - realtek,rtd1296-crt
+ - realtek,rtd1296-iso
+ - realtek,rtd1296-misc
+ - realtek,rtd1296-sb2
+ - realtek,rtd1296-scpu-wrapper
+ - realtek,rtd1395-crt
+ - realtek,rtd1395-iso
+ - realtek,rtd1395-misc
+ - realtek,rtd1395-sb2
+ - realtek,rtd1395-scpu-wrapper
+ - realtek,rtd1619-crt
+ - realtek,rtd1619-iso
+ - realtek,rtd1619-misc
+ - realtek,rtd1619-sb2
+ - realtek,rtd1619-scpu-wrapper
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ reg-io-width:
+ const: 4
+
+ ranges: true
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+patternProperties:
+ '@[0-9a-f]+$':
+ type: object
+
+ required:
+ - compatible
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/rockchip,rk801.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RK801 Power Management Integrated Circuit
+
+maintainers:
+ - Joseph Chen <chenjh@rock-chips.com>
+
+description: |
+ Rockchip RK801 series PMIC. This device consists of an i2c controlled MFD
+ that includes multiple switchable regulators.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk801
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ system-power-controller:
+ type: boolean
+ description:
+ Telling whether or not this PMIC is controlling the system power.
+
+ wakeup-source:
+ type: boolean
+ description:
+ Device can be used as a wakeup source.
+
+ vcc1-supply:
+ description:
+ The input supply for dcdc1.
+
+ vcc2-supply:
+ description:
+ The input supply for dcdc2.
+
+ vcc3-supply:
+ description:
+ The input supply for dcdc3.
+
+ vcc4-supply:
+ description:
+ The input supply for dcdc4.
+
+ vcc5-supply:
+ description:
+ The input supply for ldo1.
+
+ vcc6-supply:
+ description:
+ The input supply for ldo2.
+
+ vcc7-supply:
+ description:
+ The input supply for switch.
+
+ regulators:
+ type: object
+ patternProperties:
+ "^(dcdc[1-4]|ldo[1-2]|switch)$":
+ type: object
+ $ref: /schemas/regulator/regulator.yaml#
+ unevaluatedProperties: false
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/pinctrl/rockchip.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rk801: pmic@27 {
+ compatible = "rockchip,rk801";
+ reg = <0x27>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PC0 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+
+ regulators {
+ vdd_cpu: dcdc1 {
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-initial-mode = <0x1>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-mode = <0x2>;
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc3v3_sys: dcdc2 {
+ regulator-name = "vcc3v3_sys";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <0x1>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-mode = <0x2>;
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_ddr: dcdc3 {
+ regulator-name = "vcc_ddr";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-mode = <0x2>;
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_logic: dcdc4 {
+ regulator-name = "vdd_logic";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-initial-mode = <0x1>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-mode = <0x2>;
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdd0v9_sys: ldo1 {
+ regulator-name = "vdd0v9_sys";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vcc_1v8: ldo2 {
+ regulator-name = "vcc_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_3v3: switch {
+ regulator-name = "vcc_3v3";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+ };
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/rohm,bd72720-pmic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROHM BD72720 Power Management Integrated Circuit
+
+maintainers:
+ - Matti Vaittinen <mazziesaccount@gmail.com>
+
+description:
+ BD72720 is a single-chip power management IC for battery-powered portable
+ devices. The BD72720 integrates 10 bucks and 11 LDOs, and a 3000 mA
+ switching charger. The IC also includes a Coulomb counter, a real-time
+ clock (RTC), GPIOs and a 32.768 kHz clock gate.
+
+# In addition to the properties found from the charger node, the ROHM BD72720
+# uses properties from a static battery node. Please see the:
+# Documentation/devicetree/bindings/power/supply/battery.yaml
+#
+# Following properties are used
+# when present:
+#
+# charge-full-design-microamp-hours: Battry capacity in mAh
+# voltage-max-design-microvolt: Maximum voltage
+# voltage-min-design-microvolt: Minimum voltage system is still operating.
+# degrade-cycle-microamp-hours: Capacity lost due to aging at each full
+# charge cycle.
+# ocv-capacity-celsius: Array of OCV table temperatures. 1/table.
+# ocv-capacity-table-<N>: Table of OCV voltage/SOC pairs. Corresponds
+# N.th temperature in ocv-capacity-celsius
+#
+# volt-drop-thresh-microvolt: Threshold for starting the VDR correction
+# volt-drop-soc: Table of capacity values matching the
+# values in VDR tables.
+#
+# volt-drop-temperatures-millicelsius: Temperatures corresponding to the volage
+# drop values given in volt-drop-[0-9]-microvolt
+#
+# volt-drop-[0-9]-microvolt: VDR table for a temperature specified in
+# volt-drop-temperatures-millicelsius
+#
+# VDR tables are (usually) determined for a specific battery by ROHM.
+# The battery node would then be referred from the charger node:
+#
+# monitored-battery = <&battery>;
+
+properties:
+ compatible:
+ const: rohm,bd72720
+
+ reg:
+ description:
+ I2C slave address.
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+ description:
+ The first cell is the pin number and the second cell is used to specify
+ flags. See the gpio binding document for more information.
+
+ clocks:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 0
+
+ clock-output-names:
+ const: bd71828-32k-out
+
+ rohm,clkout-open-drain:
+ description: clk32kout mode. Set to 1 for "open-drain" or 0 for "cmos".
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 1
+
+ rohm,charger-sense-resistor-micro-ohms:
+ minimum: 10000
+ maximum: 50000
+ description:
+ BD72720 has a SAR ADC for measuring charging currents. External sense
+ resistor (RSENSE in data sheet) should be used. If some other but
+ 30 mOhm resistor is used the resistance value should be given here in
+ micro Ohms.
+
+ regulators:
+ $ref: /schemas/regulator/rohm,bd72720-regulator.yaml
+ description:
+ List of child nodes that specify the regulators.
+
+ leds:
+ $ref: /schemas/leds/rohm,bd71828-leds.yaml
+
+ rohm,pin-fault_b:
+ $ref: /schemas/types.yaml#/definitions/string
+ description:
+ BD72720 has an OTP option to use fault_b-pin for different
+ purposes. Set this property accordingly. OTP options are
+ OTP0 - bi-directional FAULT_B or READY indicator depending on a
+ 'sub option'
+ OTP1 - GPO
+ OTP2 - Power sequencer output.
+ enum:
+ - faultb
+ - readyind
+ - gpo
+ - pwrseq
+
+patternProperties:
+ "^rohm,pin-dvs[0-1]$":
+ $ref: /schemas/types.yaml#/definitions/string
+ description:
+ BD72720 has 4 different OTP options to determine the use of dvs<X>-pins.
+ OTP0 - regulator RUN state control.
+ OTP1 - GPI.
+ OTP2 - GPO.
+ OTP3 - Power sequencer output.
+ This property specifies the use of the pin.
+ enum:
+ - dvs-input
+ - gpi
+ - gpo
+ - pwrseq
+
+ "^rohm,pin-exten[0-1]$":
+ $ref: /schemas/types.yaml#/definitions/string
+ description: BD72720 has an OTP option to use exten0-pin for different
+ purposes. Set this property accordingly.
+ OTP0 - GPO
+ OTP1 - Power sequencer output.
+ enum:
+ - gpo
+ - pwrseq
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - "#clock-cells"
+ - regulators
+ - gpio-controller
+ - "#gpio-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/leds/common.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pmic: pmic@4b {
+ compatible = "rohm,bd72720";
+ reg = <0x4b>;
+
+ interrupt-parent = <&gpio1>;
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+
+ clocks = <&osc 0>;
+ #clock-cells = <0>;
+ clock-output-names = "bd71828-32k-out";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ rohm,pin-dvs0 = "gpi";
+ rohm,pin-dvs1 = "gpi";
+ rohm,pin-exten0 = "gpo";
+ rohm,pin-exten1 = "gpo";
+ rohm,pin-fault_b = "faultb";
+
+ rohm,charger-sense-resistor-micro-ohms = <10000>;
+
+ regulators {
+ buck1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <2500>;
+ };
+ buck2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <2500>;
+ };
+ buck3 {
+ regulator-name = "buck3";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <2000000>;
+ };
+ buck4 {
+ regulator-name = "buck4";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ buck5 {
+ regulator-name = "buck5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ buck6 {
+ regulator-name = "buck6";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <2500>;
+ };
+ buck7 {
+ regulator-name = "buck7";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <2500>;
+ };
+ buck8 {
+ regulator-name = "buck8";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1700000>;
+ regulator-ramp-delay = <2500>;
+ rohm,dvs-run-voltage = <1700000>;
+ rohm,dvs-idle-voltage = <1>;
+ rohm,dvs-suspend-voltage = <1>;
+ rohm,dvs-lpsr-voltage = <0>;
+ regulator-boot-on;
+ };
+ buck9 {
+ regulator-name = "buck9";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1700000>;
+ regulator-ramp-delay = <2500>;
+ rohm,dvs-run-voltage = <1700000>;
+ rohm,dvs-idle-voltage = <1>;
+ rohm,dvs-suspend-voltage = <1>;
+ rohm,dvs-lpsr-voltage = <0>;
+ regulator-boot-on;
+ };
+ buck10 {
+ regulator-name = "buck10";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1700000>;
+ regulator-ramp-delay = <2500>;
+ rohm,dvs-run-voltage = <1700000>;
+ rohm,dvs-idle-voltage = <1>;
+ rohm,dvs-suspend-voltage = <1>;
+ rohm,dvs-lpsr-voltage = <0>;
+ regulator-boot-on;
+ };
+ ldo1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ ldo7 {
+ regulator-name = "ldo7";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ ldo8 {
+ regulator-name = "ldo8";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3300000>;
+ rohm,dvs-suspend-voltage = <0>;
+ rohm,dvs-lpsr-voltage = <1>;
+ rohm,dvs-run-voltage = <750000>;
+ };
+ ldo9 {
+ regulator-name = "ldo9";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3300000>;
+ rohm,dvs-suspend-voltage = <0>;
+ rohm,dvs-lpsr-voltage = <1>;
+ rohm,dvs-run-voltage = <750000>;
+ };
+ ldo10 {
+ regulator-name = "ldo10";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3300000>;
+ rohm,dvs-suspend-voltage = <0>;
+ rohm,dvs-lpsr-voltage = <1>;
+ rohm,dvs-run-voltage = <750000>;
+ };
+ ldo11 {
+ regulator-name = "ldo11";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3300000>;
+ rohm,dvs-suspend-voltage = <0>;
+ rohm,dvs-lpsr-voltage = <1>;
+ rohm,dvs-run-voltage = <750000>;
+ };
+ };
+
+ leds {
+ compatible = "rohm,bd71828-leds";
+
+ led-1 {
+ rohm,led-compatible = "bd71828-grnled";
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+ led-2 {
+ rohm,led-compatible = "bd71828-ambled";
+ function = LED_FUNCTION_CHARGING;
+ color = <LED_COLOR_ID_AMBER>;
+ };
+ };
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/samsung,s2mpg10-pmic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S2MPG10 Power Management IC
+
+maintainers:
+ - André Draszik <andre.draszik@linaro.org>
+
+description: |
+ This is part of the device tree bindings for the S2MPG10 Power Management IC
+ (PMIC).
+
+ The Samsung S2MPG10 is a Power Management IC for mobile applications with buck
+ converters, various LDOs, power meters, RTC, clock outputs, and additional
+ GPIO interfaces and is typically complemented by S2MPG10 PMIC in a main/sub
+ configuration as the main PMIC.
+
+properties:
+ compatible:
+ const: samsung,s2mpg10-pmic
+
+ clocks:
+ $ref: /schemas/clock/samsung,s2mps11.yaml
+ description:
+ Child node describing clock provider.
+
+ interrupts:
+ maxItems: 1
+
+ regulators:
+ type: object
+ $ref: /schemas/regulator/samsung,s2mpg10-regulator.yaml
+ description:
+ List of child nodes that specify the regulators.
+
+ system-power-controller: true
+
+ wakeup-source: true
+
+patternProperties:
+ "^vinb([1-9]|10)m-supply$":
+ description:
+ Phandle to the power supply for each buck rail of this PMIC. There is a
+ 1:1 mapping of supply to rail, e.g. vinb1m-supply supplies buck1m.
+
+ "^vinl([1-9]|1[0-5])m-supply$":
+ description: |
+ Phandle to the power supply for one or multiple LDO rails of this PMIC.
+ The mapping of supply to rail(s) is as follows:
+ vinl1m - ldo13m
+ vinl2m - ldo15m
+ vinl3m - ldo1m, ldo5m, ldo7m
+ vinl4m - ldo3m, ldo8m
+ vinl5m - ldo16m
+ vinl6m - ldo17m
+ vinl7m - ldo6m, ldo11m, ldo24m, ldo28m
+ vinl8m - ldo12m
+ vinl9m - ldo2m, ldo4m
+ vinl10m - ldo9m, ldo14m, ldo18m, 19m, ldo20m, ldo25m
+ vinl11m - ldo23m, ldo31m
+ vinl12m - ldo29m
+ vinl13m - ldo30m
+ vinl14m - ldo21m
+ vinl15m - ldo10m, ldo22m, ldo26m, ldo27m
+
+required:
+ - compatible
+ - interrupts
+ - regulators
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/regulator/samsung,s2mpg10-regulator.h>
+
+ pmic {
+ compatible = "samsung,s2mpg10-pmic";
+ interrupts-extended = <&gpa0 6 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ system-power-controller;
+ wakeup-source;
+
+ vinl3m-supply = <&buck8m>;
+
+ clocks {
+ compatible = "samsung,s2mpg10-clk";
+ #clock-cells = <1>;
+ clock-output-names = "rtc32k_ap", "peri32k1", "peri32k2";
+ };
+
+ regulators {
+ buck8m {
+ regulator-name = "vdd_mif";
+ regulator-min-microvolt = <450000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-ramp-delay = <6250>;
+ };
+
+ ldo1m {
+ regulator-name = "vdd_ldo1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ ldo20m {
+ regulator-name = "vdd_dmics";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ samsung,ext-control = <S2MPG10_EXTCTRL_LDO20M_EN2>;
+ };
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/samsung,s2mpg11-pmic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S2MPG11 Power Management IC
+
+maintainers:
+ - André Draszik <andre.draszik@linaro.org>
+
+description: |
+ This is part of the device tree bindings for the S2MPG11 Power Management IC
+ (PMIC).
+
+ The Samsung S2MPG11 is a Power Management IC for mobile applications with buck
+ converters, various LDOs, power meters, NTC thermistor inputs, and additional
+ GPIO interfaces and typically complements an S2MPG10 PMIC in a main/sub
+ configuration as the sub-PMIC.
+
+properties:
+ compatible:
+ const: samsung,s2mpg11-pmic
+
+ interrupts:
+ maxItems: 1
+
+ regulators:
+ type: object
+ $ref: /schemas/regulator/samsung,s2mpg11-regulator.yaml
+ description:
+ List of child nodes that specify the regulators.
+
+ wakeup-source: true
+
+patternProperties:
+ "^vinb(([1-9]|10)s|[abd])-supply$":
+ description:
+ Phandle to the power supply for each buck rail of this PMIC. There is a
+ 1:1 mapping of numbered supply to rail, e.g. vinb1s-supply supplies
+ buck1s. The remaining mapping is as follows
+ vinba - bucka
+ vinbb - buck boost
+ vinbd - buckd
+
+ "^vinl[1-6]s-supply$":
+ description: |
+ Phandle to the power supply for one or multiple LDO rails of this PMIC.
+ The mapping of supply to rail(s) is as follows
+ vinl1s - ldo1s, ldo2s
+ vinl2s - ldo8s, ldo9s
+ vinl3s - ldo3s, ldo5s, ldo7s, ldo15s
+ vinl4s - ldo10s, ldo11s, ldo12s, ldo14s
+ vinl5s - ldo4s, ldo6s
+ vinl6s - ldo13s
+
+required:
+ - compatible
+ - interrupts
+ - regulators
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/regulator/samsung,s2mpg10-regulator.h>
+
+ pmic {
+ compatible = "samsung,s2mpg11-pmic";
+ interrupts-extended = <&gpa0 7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ wakeup-source;
+
+ vinl1s-supply = <&buck8m>;
+ vinl2s-supply = <&buck6s>;
+
+ regulators {
+ buckd {
+ regulator-name = "vcc_ufs";
+ regulator-ramp-delay = <6250>;
+ enable-gpios = <&gpp0 1 GPIO_ACTIVE_HIGH>;
+ samsung,ext-control = <S2MPG11_EXTCTRL_UFS_EN>;
+ };
+ };
+ };
properties:
compatible:
enum:
- - samsung,s2mpg10-pmic
- samsung,s2mps11-pmic
- samsung,s2mps13-pmic
- samsung,s2mps14-pmic
reset (setting buck voltages to default values).
type: boolean
- system-power-controller: true
-
wakeup-source: true
required:
- compatible
+ - reg
- regulators
additionalProperties: false
allOf:
- - if:
- properties:
- compatible:
- contains:
- const: samsung,s2mpg10-pmic
- then:
- properties:
- reg: false
- samsung,s2mps11-acokb-ground: false
- samsung,s2mps11-wrstbi-ground: false
-
- # oneOf is required, because dtschema's fixups.py doesn't handle this
- # nesting here. Its special treatment to allow either interrupt property
- # when only one is specified in the binding works at the top level only.
- oneOf:
- - required: [interrupts]
- - required: [interrupts-extended]
-
- else:
- properties:
- system-power-controller: false
-
- required:
- - reg
-
- if:
properties:
compatible:
- mstar,msc313-pmsleep
- nuvoton,ma35d1-sys
- nuvoton,wpcm450-shm
+ - nxp,s32g2-gpr
+ - nxp,s32g3-gpr
- qcom,apq8064-mmss-sfpb
- qcom,apq8064-sps-sic
- rockchip,px30-qos
- mediatek,mt2701-pctl-a-syscfg
- mediatek,mt2712-pctl-a-syscfg
- mediatek,mt6397-pctl-pmic-syscfg
+ - mediatek,mt7981-topmisc
- mediatek,mt7988-topmisc
- mediatek,mt8135-pctl-a-syscfg
- mediatek,mt8135-pctl-b-syscfg
- mstar,msc313-pmsleep
- nuvoton,ma35d1-sys
- nuvoton,wpcm450-shm
+ - nxp,s32g2-gpr
+ - nxp,s32g3-gpr
- qcom,apq8064-mmss-sfpb
- qcom,apq8064-sps-sic
- rockchip,px30-qos
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/google,android-pipe.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Android Goldfish QEMU Pipe
+
+maintainers:
+ - Kuan-Wei Chiu <visitorckw@gmail.com>
+
+description:
+ Android QEMU pipe virtual device generated by Android emulator.
+
+properties:
+ compatible:
+ const: google,android-pipe
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ pipe@ff018000 {
+ compatible = "google,android-pipe";
+ reg = <0xff018000 0x2000>;
+ interrupts = <18>;
+ };
properties:
compatible:
- const: qcom,fastrpc
+ enum:
+ - qcom,kaanapali-fastrpc
+ - qcom,fastrpc
label:
enum:
patternProperties:
"^partitions(-boot[12]|-gp[14])?$":
- $ref: /schemas/mtd/partitions/partitions.yaml
+ type: object
+ additionalProperties: true
- patternProperties:
- "^partition@[0-9a-f]+$":
- $ref: /schemas/mtd/partitions/partition.yaml
-
- properties:
- reg:
- description: Must be multiple of 512 as it's converted
- internally from bytes to SECTOR_SIZE (512 bytes)
-
- required:
- - reg
-
- unevaluatedProperties: false
+ properties:
+ compatible:
+ contains:
+ const: fixed-partitions
required:
- compatible
items:
- const: brcm,nand-iproc
- const: brcm,brcmnand-v6.1
- - const: brcm,brcmnand
- description: BCM63168 SoC-specific NAND controller
items:
- const: brcm,nand-bcm63168
dmas:
maxItems: 1
+ dma-coherent: true
+
iommus:
maxItems: 1
+++ /dev/null
-* MTD SPI driver for Microchip 23K256 (and similar) serial SRAM
-
-Required properties:
-- #address-cells, #size-cells : Must be present if the device has sub-nodes
- representing partitions.
-- compatible : Must be one of "microchip,mchp23k256" or "microchip,mchp23lcv1024"
-- reg : Chip-Select number
-- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at
-
-Example:
-
- spi-sram@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "microchip,mchp23k256";
- reg = <0>;
- spi-max-frequency = <20000000>;
- };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/microchip,mchp23k256.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip 23K256 SPI SRAM
+
+maintainers:
+ - Richard Weinberger <richard@nod.at>
+
+description:
+ The Microchip 23K256 is a 256 Kbit (32 Kbyte) serial SRAM with an
+ SPI interface,supporting clock frequencies up to 20 MHz. It features
+ a 32-byte page size for writes and supports byte, page, and
+ sequential access modes.
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+ compatible:
+ enum:
+ - microchip,mchp23k256
+ - microchip,mchp23lcv1024
+
+ reg:
+ maxItems: 1
+
+required:
+ - reg
+ - compatible
+ - spi-max-frequency
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sram@0 {
+ compatible = "microchip,mchp23k256";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ };
+ };
+...
deprecated: true
partitions:
- $ref: /schemas/mtd/partitions/partitions.yaml
+ type: object
required:
- compatible
patternProperties:
- "@[0-9a-f]+$":
- $ref: partitions/partition.yaml
- deprecated: true
-
- "^partition@[0-9a-f]+":
- $ref: partitions/partition.yaml
+ "(^partition)?@[0-9a-f]+$":
+ $ref: /schemas/mtd/partitions/partition.yaml#/$defs/partition-node
deprecated: true
"^otp(-[0-9]+)?$":
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/mxic,multi-itfc-v009-nand-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Macronix Raw NAND Controller
+
+maintainers:
+ - Mason Yang <masonccyang@mxic.com.tw>
+
+description:
+ The Macronix Multi-Interface Raw NAND Controller is a versatile flash
+ memory controller for embedding in SoCs, capable of interfacing with
+ various NAND devices. It requires dedicated clock inputs for core, data
+ transmit, and delayed transmit paths along with register space and an
+ interrupt line for operation.
+
+allOf:
+ - $ref: nand-controller.yaml#
+
+properties:
+ compatible:
+ const: mxic,multi-itfc-v009-nand-controller
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ clocks:
+ minItems: 3
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: ps
+ - const: send
+ - const: send_dly
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#address-cells"
+ - "#size-cells"
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ nand-controller@43c30000 {
+ compatible = "mxic,multi-itfc-v009-nand-controller";
+ reg = <0x43c30000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 0x1d IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
+ clock-names = "ps", "send", "send_dly";
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-mode = "soft";
+ nand-ecc-algo = "bch";
+ };
+ };
+...
+++ /dev/null
-Macronix Raw NAND Controller Device Tree Bindings
--------------------------------------------------
-
-Required properties:
-- compatible: should be "mxic,multi-itfc-v009-nand-controller"
-- reg: should contain 1 entry for the registers
-- #address-cells: should be set to 1
-- #size-cells: should be set to 0
-- interrupts: interrupt line connected to this raw NAND controller
-- clock-names: should contain "ps", "send" and "send_dly"
-- clocks: should contain 3 phandles for the "ps", "send" and
- "send_dly" clocks
-
-Children nodes:
-- children nodes represent the available NAND chips.
-
-See Documentation/devicetree/bindings/mtd/nand-controller.yaml
-for more details on generic bindings.
-
-Example:
-
- nand: nand-controller@43c30000 {
- compatible = "mxic,multi-itfc-v009-nand-controller";
- reg = <0x43c30000 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 0x1d IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
- clock-names = "send", "send_dly", "ps";
-
- nand@0 {
- reg = <0>;
- nand-ecc-mode = "soft";
- nand-ecc-algo = "bch";
- };
- };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/nvidia,tegra20-nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra NAND Flash Controller
+
+maintainers:
+ - Jonathan Hunter <jonathanh@nvidia.com>
+
+allOf:
+ - $ref: nand-controller.yaml
+
+description:
+ The NVIDIA NAND controller provides an interface between NVIDIA SoCs
+ and raw NAND flash devices. It supports standard NAND operations,
+ hardware-assisted ECC, OOB data access, and DMA transfers, and
+ integrates with the Linux MTD NAND subsystem for reliable flash management.
+
+properties:
+ compatible:
+ const: nvidia,tegra20-nand
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: nand
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: nand
+
+ power-domains:
+ maxItems: 1
+
+ operating-points-v2:
+ maxItems: 1
+
+patternProperties:
+ '^nand@':
+ type: object
+ description: Individual NAND chip connected to the NAND controller
+ $ref: raw-nand-chip.yaml#
+
+ properties:
+ reg:
+ maximum: 5
+
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/tegra20-car.h>
+ #include <dt-bindings/gpio/tegra-gpio.h>
+
+ nand-controller@70008000 {
+ compatible = "nvidia,tegra20-nand";
+ reg = <0x70008000 0x100>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
+ clock-names = "nand";
+ resets = <&tegra_car 13>;
+ reset-names = "nand";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ nand-bus-width = <8>;
+ nand-on-flash-bbt;
+ nand-ecc-algo = "bch";
+ nand-ecc-strength = <8>;
+ wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+ };
+ };
+...
+++ /dev/null
-NVIDIA Tegra NAND Flash controller
-
-Required properties:
-- compatible: Must be one of:
- - "nvidia,tegra20-nand"
-- reg: MMIO address range
-- interrupts: interrupt output of the NFC controller
-- clocks: Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
-- clock-names: Must include the following entries:
- - nand
-- resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-- reset-names: Must include the following entries:
- - nand
-
-Optional children nodes:
-Individual NAND chips are children of the NAND controller node. Currently
-only one NAND chip supported.
-
-Required children node properties:
-- reg: An integer ranging from 1 to 6 representing the CS line to use.
-
-Optional children node properties:
-- nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
- "hw" is supported.
-- nand-ecc-algo: string, algorithm of NAND ECC.
- Supported values with "hw" ECC mode are: "rs", "bch".
-- nand-bus-width : See nand-controller.yaml
-- nand-on-flash-bbt: See nand-controller.yaml
-- nand-ecc-strength: integer representing the number of bits to correct
- per ECC step (always 512). Supported strength using HW ECC
- modes are:
- - RS: 4, 6, 8
- - BCH: 4, 8, 14, 16
-- nand-ecc-maximize: See nand-controller.yaml
-- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
- are chosen.
-- wp-gpios: GPIO specifier for the write protect pin.
-
-Optional child node of NAND chip nodes:
-Partitions: see mtd.yaml
-
- Example:
- nand-controller@70008000 {
- compatible = "nvidia,tegra20-nand";
- reg = <0x70008000 0x100>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
- clock-names = "nand";
- resets = <&tegra_car 13>;
- reset-names = "nand";
-
- nand@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- nand-bus-width = <8>;
- nand-on-flash-bbt;
- nand-ecc-algo = "bch";
- nand-ecc-strength = <8>;
- wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
- };
- };
maintainers:
- Linus Walleij <linusw@kernel.org>
-select: false
-
description: |
The ARM Firmware Suite is a flash partitioning system found on the
ARM reference designs: Integrator AP, Integrator CP, Versatile AB,
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/mtd/partitions/binman.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Binman entries
-
-description: |
- This corresponds to a binman 'entry'. It is a single partition which holds
- data of a defined type.
-
- Binman uses the type to indicate what data file / type to place in the
- partition. There are quite a number of binman-specific entry types, such as
- section, fill and files, to be added later.
-
-maintainers:
- - Simon Glass <sjg@chromium.org>
-
-allOf:
- - $ref: /schemas/mtd/partitions/partition.yaml#
-
-properties:
- compatible:
- enum:
- - u-boot # u-boot.bin from U-Boot project
- - tfa-bl31 # bl31.bin or bl31.elf from TF-A project
-
-required:
- - compatible
-
-unevaluatedProperties: false
-
-examples:
- - |
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@100000 {
- compatible = "u-boot";
- reg = <0x100000 0xf00000>;
- align-size = <0x1000>;
- align-end = <0x10000>;
- };
-
- partition@200000 {
- compatible = "tfa-bl31";
- reg = <0x200000 0x100000>;
- align = <0x4000>;
- };
- };
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
-select: false
-
properties:
compatible:
const: brcm,bcm4908-partitions
patternProperties:
"^partition@[0-9a-f]+$":
- $ref: partition.yaml#
- properties:
- compatible:
- const: brcm,bcm4908-firmware
- unevaluatedProperties: false
+ $ref: partition.yaml#/$defs/partition-node
required:
- "#address-cells"
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
-select: false
-
properties:
compatible:
const: brcm,bcm947xx-cfe-partitions
+++ /dev/null
-Broadcom BCM963XX ImageTag Partition Container
-==============================================
-
-Some Broadcom BCM63XX SoC based devices contain additional, non discoverable
-partitions or non standard bootloader partition sizes. For these a mixed layout
-needs to be used with an explicit firmware partition.
-
-The BCM963XX ImageTag is a simple firmware header describing the offsets and
-sizes of the rootfs and kernel parts contained in the firmware.
-
-Required properties:
-- compatible : must be "brcm,bcm963xx-imagetag"
-
-Example:
-
-flash@1e000000 {
- compatible = "cfi-flash";
- reg = <0x1e000000 0x2000000>;
- bank-width = <2>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- cfe@0 {
- reg = <0x0 0x10000>;
- read-only;
- };
-
- firmware@10000 {
- reg = <0x10000 0x7d0000>;
- compatible = "brcm,bcm963xx-imagetag";
- };
-
- caldata@7e0000 {
- reg = <0x7e0000 0x10000>;
- read-only;
- };
-
- nvram@7f0000 {
- reg = <0x7f0000 0x10000>;
- };
- };
-};
+++ /dev/null
-Broadcom TRX Container Partition
-================================
-
-TRX is Broadcom's official firmware format for the BCM947xx boards. It's used by
-most of the vendors building devices based on Broadcom's BCM47xx SoCs and is
-supported by the CFE bootloader.
-
-Design of the TRX format is very minimalistic. Its header contains
-identification fields, CRC32 checksum and the locations of embedded partitions.
-Its purpose is to store a few partitions in a format that can be distributed as
-a standalone file and written in a flash memory.
-
-Container can hold up to 4 partitions. The first partition has to contain a
-device executable binary (e.g. a kernel) as it's what the CFE bootloader starts
-executing. Other partitions can be used for operating system purposes. This is
-useful for systems that keep kernel and rootfs separated.
-
-TRX doesn't enforce any strict partition boundaries or size limits. All
-partitions have to be less than the 4GiB max size limit.
-
-There are two existing/known TRX variants:
-1) v1 which contains 3 partitions
-2) v2 which contains 4 partitions
-
-There aren't separated compatible bindings for them as version can be trivialy
-detected by a software parsing TRX header.
-
-Required properties:
-- compatible : (required) must be "brcm,trx"
-
-Optional properties:
-
-- brcm,trx-magic: TRX magic, if it is different from the default magic
- 0x30524448 as a u32.
-
-Example:
-
-flash@0 {
- partitions {
- compatible = "brcm,trx";
- };
-};
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/partitions/brcm,trx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom TRX Container Partition
+
+maintainers:
+ - Hauke Mehrtens <hauke@hauke-m.de>
+ - Rafał Miłecki <rafal@milecki.pl>
+
+description: >
+ TRX is Broadcom's official firmware format for the BCM947xx boards. It's used by
+ most of the vendors building devices based on Broadcom's BCM47xx SoCs and is
+ supported by the CFE bootloader.
+
+ Design of the TRX format is very minimalistic. Its header contains
+ identification fields, CRC32 checksum and the locations of embedded partitions.
+ Its purpose is to store a few partitions in a format that can be distributed as
+ a standalone file and written in a flash memory.
+
+ Container can hold up to 4 partitions. The first partition has to contain a
+ device executable binary (e.g. a kernel) as it's what the CFE bootloader starts
+ executing. Other partitions can be used for operating system purposes. This is
+ useful for systems that keep kernel and rootfs separated.
+
+ TRX doesn't enforce any strict partition boundaries or size limits. All
+ partitions have to be less than the 4GiB max size limit.
+
+ There are two existing/known TRX variants:
+ 1) v1 which contains 3 partitions
+ 2) v2 which contains 4 partitions
+
+ There aren't separated compatible bindings for them as version can be trivially
+ detected by a software parsing TRX header.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: linksys,ns-firmware
+ - const: brcm,trx
+ - const: brcm,trx
+
+ brcm,trx-magic:
+ description: TRX magic, if it is different from the default magic.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0x30524448
+
+required:
+ - compatible
+
+allOf:
+ - $ref: partition.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ flash {
+ partitions {
+ compatible = "brcm,trx";
+ };
+ };
- const: sercomm,sc-partitions
- const: fixed-partitions
- "#address-cells": true
+ "#address-cells":
+ enum: [ 1, 2 ]
- "#size-cells": true
-
- compression:
- $ref: /schemas/types.yaml#/definitions/string
- description: |
- Compression algorithm used to store the data in this partition, chosen
- from a list of well-known algorithms.
-
- The contents are compressed using this algorithm.
-
- enum:
- - none
- - bzip2
- - gzip
- - lzop
- - lz4
- - lzma
- - xz
- - zstd
+ "#size-cells":
+ enum: [ 1, 2 ]
patternProperties:
"@[0-9a-f]+$":
- $ref: partition.yaml#
-
- properties:
- sercomm,scpart-id:
- description: Partition id in Sercomm partition map. Mtd parser
- uses this id to find a record in the partition map containing
- offset and size of the current partition. The values from
- partition map overrides partition offset and size defined in
- reg property of the dts. Frequently these values are the same,
- but may differ if device has bad eraseblocks on a flash.
- $ref: /schemas/types.yaml#/definitions/uint32
+ $ref: partition.yaml#/$defs/partition-node
required:
- "#address-cells"
- "#size-cells"
-additionalProperties: true
+# fixed-partitions can be nested
+allOf:
+ - $ref: partition.yaml#
+
+unevaluatedProperties: false
examples:
- |
compatible = "fixed-partitions";
label = "calibration";
reg = <0xf00000 0x100000>;
- ranges = <0 0xf00000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
-select: false
-
properties:
compatible:
const: linksys,ns-partitions
patternProperties:
"^partition@[0-9a-f]+$":
- $ref: partition.yaml#
- properties:
- compatible:
- items:
- - const: linksys,ns-firmware
- - const: brcm,trx
- unevaluatedProperties: false
+ $ref: partition.yaml#/$defs/partition-node
required:
- "#address-cells"
with the padding bytes, so may grow. If ‘align-end’ is not provided,
no alignment is performed.
+ compression:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: |
+ Compression algorithm used to store the data in this partition, chosen
+ from a list of well-known algorithms.
+
+ The contents are compressed using this algorithm.
+
+ enum:
+ - none
+ - bzip2
+ - gzip
+ - lzop
+ - lz4
+ - lzma
+ - xz
+ - zstd
+
+ sercomm,scpart-id:
+ description: Partition id in Sercomm partition map. Mtd parser
+ uses this id to find a record in the partition map containing
+ offset and size of the current partition. The values from
+ partition map overrides partition offset and size defined in
+ reg property of the dts. Frequently these values are the same,
+ but may differ if device has bad eraseblocks on a flash.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ nvmem-layout:
+ $ref: /schemas/nvmem/layouts/nvmem-layout.yaml
+
if:
not:
required: [ reg ]
then:
properties:
$nodename:
- pattern: '^partition-.*$'
+ pattern: '^partitions?(-.+)?$'
# This is a generic file other binding inherit from and extend
additionalProperties: true
+$defs:
+ partition-node:
+ type: object
+ if:
+ not:
+ required: [ compatible ]
+ then:
+ $ref: '#'
+ unevaluatedProperties: false
+ else:
+ $ref: '#'
+
examples:
- |
partitions {
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/mtd/partitions/partitions.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Partitions
-
-description: |
- This binding is generic and describes the content of the partitions container
- node. All partition parsers must be referenced here.
-
-maintainers:
- - Miquel Raynal <miquel.raynal@bootlin.com>
-
-oneOf:
- - $ref: arm,arm-firmware-suite.yaml
- - $ref: brcm,bcm4908-partitions.yaml
- - $ref: brcm,bcm947xx-cfe-partitions.yaml
- - $ref: fixed-partitions.yaml
- - $ref: linksys,ns-partitions.yaml
- - $ref: qcom,smem-part.yaml
- - $ref: redboot-fis.yaml
- - $ref: tplink,safeloader-partitions.yaml
-
-properties:
- compatible: true
-
- '#address-cells':
- enum: [1, 2]
-
- '#size-cells':
- enum: [1, 2]
-
-patternProperties:
- "^partition(-.+|@[0-9a-f]+)$":
- $ref: partition.yaml
-
-required:
- - compatible
-
-unevaluatedProperties: false
device. On a flash memory with 32KB eraseblocks, 0 means the first
eraseblock at 0x00000000, 1 means the second eraseblock at 0x00008000 and so on.
- '#address-cells': false
-
- '#size-cells': false
-
required:
- compatible
- fis-index-block
+++ /dev/null
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/mtd/partitions/seama.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Seattle Image Partitions
-
-description: The SEAttle iMAge (SEAMA) partition is a type of partition
- used for NAND flash devices. This type of flash image is found in some
- D-Link routers such as DIR-645, DIR-842, DIR-859, DIR-860L, DIR-885L,
- DIR890L and DCH-M225, as well as in WD and NEC routers on the ath79
- (MIPS), Broadcom BCM53xx, and RAMIPS platforms. This partition type
- does not have children defined in the device tree, they need to be
- detected by software.
-
-allOf:
- - $ref: partition.yaml#
-
-maintainers:
- - Linus Walleij <linusw@kernel.org>
-
-properties:
- compatible:
- const: seama
-
-required:
- - compatible
-
-unevaluatedProperties: false
-
-examples:
- - |
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- compatible = "seama";
- reg = <0x0 0x800000>;
- label = "firmware";
- };
- };
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/partitions/simple-partition.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Simple partition types
+
+description:
+ Simple partition types which only define a "compatible" value and no custom
+ properties.
+
+maintainers:
+ - Rafał Miłecki <rafal@milecki.pl>
+ - Simon Glass <sjg@chromium.org>
+
+allOf:
+ - $ref: partition.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: brcm,bcm4908-firmware
+ description:
+ Broadcom BCM4908 CFE bootloader firmware partition
+
+ - const: brcm,bcm963xx-imagetag
+ description:
+ The BCM963XX ImageTag is a simple firmware header describing the
+ offsets and sizes of the rootfs and kernel parts contained in the
+ firmware.
+
+ - const: seama
+ description:
+ The SEAttle iMAge (SEAMA) partition is a type of partition used for
+ NAND flash devices. This type of flash image is found in some D-Link
+ routers such as DIR-645, DIR-842, DIR-859, DIR-860L, DIR-885L, DIR890L
+ and DCH-M225, as well as in WD and NEC routers on the ath79 (MIPS),
+ Broadcom BCM53xx, and RAMIPS platforms. This partition type does not
+ have children defined in the device tree, they need to be detected by
+ software.
+
+ - const: u-boot
+ description: >
+ u-boot.bin from U-Boot project.
+
+ This corresponds to a binman 'entry'. It is a single partition which holds
+ data of a defined type.
+
+ Binman uses the type to indicate what data file / type to place in the
+ partition. There are quite a number of binman-specific entry types, such as
+ section, fill and files, to be added later.
+
+ - const: tfa-bl31
+ description: >
+ bl31.bin or bl31.elf from TF-A project
+
+ This corresponds to a binman 'entry'. It is a single partition which holds
+ data of a defined type.
+
+unevaluatedProperties: false
patternProperties:
"^partition-.*$":
- $ref: partition.yaml#
+ $ref: partition.yaml#/$defs/partition-node
required:
- partitions-table-offset
patternProperties:
"^partition-.*$":
- $ref: partition.yaml#
+ $ref: partition.yaml#/$defs/partition-node
unevaluatedProperties: false
+++ /dev/null
-* SPEAr SMI
-
-Required properties:
-- compatible : "st,spear600-smi"
-- reg : Address range of the mtd chip
-- #address-cells, #size-cells : Must be present if the device has sub-nodes
- representing partitions.
-- interrupts: Should contain the STMMAC interrupts
-- clock-rate : Functional clock rate of SMI in Hz
-
-Optional properties:
-- st,smi-fast-mode : Flash supports read in fast mode
-
-Example:
-
- smi: flash@fc000000 {
- compatible = "st,spear600-smi";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xfc000000 0x1000>;
- interrupt-parent = <&vic1>;
- interrupts = <12>;
- clock-rate = <50000000>; /* 50MHz */
-
- flash@f8000000 {
- st,smi-fast-mode;
- ...
- };
- };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/st,spear600-smi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics SPEAr600 Serial Memory Interface (SMI) Controller
+
+maintainers:
+ - Richard Weinberger <richard@nod.at>
+
+description:
+ The SPEAr600 Serial Memory Interface (SMI) is a dedicated serial flash
+ controller supporting up to four chip selects for serial NOR flashes
+ connected in parallel. The controller is memory-mapped and the attached
+ flash devices appear in the CPU address space.The driver
+ (drivers/mtd/devices/spear_smi.c) probes the attached flashes
+ dynamically by sending commands (e.g., RDID) to each bank.
+ Flash sub nodes describe the memory range and optional per-flash
+ properties.
+
+properties:
+ compatible:
+ const: st,spear600-smi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ clock-rate:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Functional clock rate of the SMI controller in Hz.
+
+patternProperties:
+ "^flash@.*$":
+ $ref: /schemas/mtd/mtd.yaml#
+
+ properties:
+ reg:
+ maxItems: 1
+
+ st,smi-fast-mode:
+ type: boolean
+ description: Indicates that the attached flash supports fast read mode.
+
+ unevaluatedProperties: false
+
+ required:
+ - reg
+
+required:
+ - compatible
+ - reg
+ - clock-rate
+ - "#address-cells"
+ - "#size-cells"
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ flash@fc000000 {
+ compatible = "st,spear600-smi";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xfc000000 0x1000>;
+ interrupt-parent = <&vic1>;
+ interrupts = <12>;
+ clock-rate = <50000000>; /* 50 MHz */
+
+ flash@fc000000 {
+ reg = <0xfc000000 0x1000>;
+ st,smi-fast-mode;
+ };
+ };
+...
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/st,spi-fsm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics SPI FSM Serial NOR Flash Controller
+
+maintainers:
+ - Angus Clark <angus.clark@st.com>
+
+description:
+ The STMicroelectronics Fast Sequence Mode (FSM) controller is a dedicated
+ hardware accelerator integrated in older STiH4xx/STiDxxx set-top box SoCs
+ (such as STiH407, STiH416, STiD127). It connects directly to a single
+ external serial flash device used as the primary boot device. The FSM
+ executes hard-coded or configurable instruction sequences in hardware,
+ providing low-latency reads suitable for execute-in-place (XIP) boot
+ and high read bandwidth.
+
+properties:
+ compatible:
+ const: st,spi-fsm
+
+ reg:
+ maxItems: 1
+
+ reg-names:
+ const: spi-fsm
+
+ interrupts:
+ maxItems: 1
+
+ st,syscfg:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Phandle to the system configuration registers used for boot-device selection.
+
+ st,boot-device-reg:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Offset of the boot-device register within the st,syscfg node.
+
+ st,boot-device-spi:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Expected boot-device value when booting from this SPI controller.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - pinctrl-0
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ spifsm@fe902000 {
+ compatible = "st,spi-fsm";
+ reg = <0xfe902000 0x1000>;
+ reg-names = "spi-fsm";
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&pinctrl_fsm>;
+ st,syscfg = <&syscfg_rear>;
+ st,boot-device-reg = <0x958>;
+ st,boot-device-spi = <0x1a>;
+ };
+...
+++ /dev/null
-* ST-Microelectronics SPI FSM Serial (NOR) Flash Controller
-
-Required properties:
- - compatible : Should be "st,spi-fsm"
- - reg : Contains register's location and length.
- - reg-names : Should contain the reg names "spi-fsm"
- - interrupts : The interrupt number
- - pinctrl-0 : Standard Pinctrl phandle (see: pinctrl/pinctrl-bindings.txt)
-
-Optional properties:
- - st,syscfg : Phandle to boot-device system configuration registers
- - st,boot-device-reg : Address of the aforementioned boot-device register(s)
- - st,boot-device-spi : Expected boot-device value if booted via this device
-
-Example:
- spifsm: spifsm@fe902000{
- compatible = "st,spi-fsm";
- reg = <0xfe902000 0x1000>;
- reg-names = "spi-fsm";
- pinctrl-0 = <&pinctrl_fsm>;
- st,syscfg = <&syscfg_rear>;
- st,boot-device-reg = <0x958>;
- st,boot-device-spi = <0x1a>;
- };
-
- description: AEMIF control registers.
partitions:
- $ref: /schemas/mtd/partitions/partitions.yaml
+ type: object
+ required:
+ - compatible
ti,davinci-chipselect:
description:
patternProperties:
"@[0-9a-f]+$":
- $ref: /schemas/mtd/partitions/partition.yaml
+ $ref: /schemas/mtd/partitions/partition.yaml#/$defs/partition-node
allOf:
- $ref: /schemas/memory-controllers/ti,gpmc-child.yaml
description: Enable 25MHz reference clock output on CLK25_REF pin.
type: boolean
+ adi,low-cmode-impedance:
+ description: |
+ Configure PHY for the lowest common-mode impedance on the receive pair
+ for 100BASE-TX. This is suited for capacitive coupled applications and
+ other applications where there may be a path for high common-mode noise
+ to reach the PHY.
+ If not present, by default the PHY is configured for normal termination
+ (zero-power termination) mode.
+
+ Note: There is a trade-off of 12 mW increased power consumption with
+ the lowest common-mode impedance setting, but in all cases the
+ differential impedance is 100 ohms.
+ type: boolean
+
unevaluatedProperties: false
examples:
- description: wlan irq line5
memory-region:
- oneOf:
- - items:
- - description: NPU firmware binary region
- - items:
- - description: NPU firmware binary region
- - description: NPU wlan offload RX buffers region
- - description: NPU wlan offload TX buffers region
- - description: NPU wlan offload TX packet identifiers region
+ items:
+ - description: NPU firmware binary region
+ - description: NPU wlan offload RX buffers region
+ - description: NPU wlan offload TX buffers region
+ - description: NPU wlan offload TX packet identifiers region
+ - description: NPU wlan Block Ack buffers region
+ minItems: 1
memory-region-names:
items:
- const: pkt
- const: tx-pkt
- const: tx-bufid
+ - const: ba
+ minItems: 1
+
+ firmware-name:
+ items:
+ - description: Firmware name of RiscV core
+ - description: Firmware name of Data section
required:
- compatible
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&npu_firmware>, <&npu_pkt>, <&npu_txpkt>,
- <&npu_txbufid>;
- memory-region-names = "firmware", "pkt", "tx-pkt", "tx-bufid";
+ <&npu_txbufid>, <&npu_ba>;
+ memory-region-names = "firmware", "pkt", "tx-pkt", "tx-bufid", "ba";
+ firmware-name = "airoha/en7581_npu_rv32.bin",
+ "airoha/en7581_npu_data.bin";
};
};
allOf:
- $ref: ethernet-phy.yaml#
+ - $ref: /schemas/phy/phy-common-props.yaml#
properties:
compatible:
description:
Reverse rx polarity of the SERDES. This is the receiving
side of the lines from the MAC towards the EN881H.
+ This property is deprecated, for details please refer to
+ Documentation/devicetree/bindings/phy/phy-common-props.yaml
+ deprecated: true
airoha,pnswap-tx:
type: boolean
description:
Reverse tx polarity of SERDES. This is the transmitting
side of the lines from EN8811H towards the MAC.
+ This property is deprecated, for details please refer to
+ Documentation/devicetree/bindings/phy/phy-common-props.yaml
+ deprecated: true
required:
- reg
examples:
- |
+ #include <dt-bindings/phy/phy.h>
+
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethernet-phy@1 {
compatible = "ethernet-phy-id03a2.a411";
reg = <1>;
- airoha,pnswap-rx;
+ rx-polarity = <PHY_POL_INVERT>;
};
};
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/bluetooth/qcom,bluetooth-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Bluetooth Common Properties
+
+maintainers:
+ - Balakrishna Godavarthi <quic_bgodavar@quicinc.com>
+ - Rocky Liao <quic_rjliao@quicinc.com>
+
+properties:
+ firmware-name:
+ minItems: 1
+ items:
+ - description: specify the name of nvm firmware to load
+ - description: specify the name of rampatch firmware to load
+
+ qcom,local-bd-address-broken:
+ type: boolean
+ description:
+ boot firmware is incorrectly passing the address in big-endian order
+
+additionalProperties: true
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/bluetooth/qcom,qca2066-bt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QCA2006 Bluetooth
+
+maintainers:
+ - Balakrishna Godavarthi <quic_bgodavar@quicinc.com>
+ - Rocky Liao <quic_rjliao@quicinc.com>
+
+properties:
+ compatible:
+ enum:
+ - qcom,qca2066-bt
+ - qcom,qca6174-bt
+
+ clocks:
+ items:
+ - description: External low-power 32.768 kHz clock input
+
+ enable-gpios:
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - enable-gpios
+
+allOf:
+ - $ref: bluetooth-controller.yaml#
+ - $ref: qcom,bluetooth-common.yaml
+ - $ref: /schemas/serial/serial-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ serial {
+ bluetooth {
+ compatible = "qcom,qca6174-bt";
+ clocks = <&divclk4>;
+ enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>;
+ firmware-name = "nvm_00440302.bin";
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/bluetooth/qcom,qca6390-bt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QCA6390 Bluetooth
+
+maintainers:
+ - Balakrishna Godavarthi <quic_bgodavar@quicinc.com>
+ - Rocky Liao <quic_rjliao@quicinc.com>
+
+properties:
+ compatible:
+ enum:
+ - qcom,qca6390-bt
+
+ vddaon-supply:
+ description: VDD_AON supply regulator handle
+
+ vddbtcmx-supply:
+ description: VDD_BT_CMX supply regulator handle
+
+ vddrfa0p8-supply:
+ description: VDD_RFA_0P8 supply regulator handle
+
+ vddrfa1p2-supply:
+ description: VDD_RFA_1P2 supply regulator handle
+
+ vddrfa1p7-supply:
+ description: VDD_RFA_1P7 supply regulator handle
+
+ vddrfacmn-supply:
+ description: VDD_RFA_CMN supply regulator handle
+
+required:
+ - compatible
+ - vddaon-supply
+ - vddbtcmx-supply
+ - vddrfa0p8-supply
+ - vddrfa1p2-supply
+ - vddrfa1p7-supply
+ - vddrfacmn-supply
+
+allOf:
+ - $ref: bluetooth-controller.yaml#
+ - $ref: qcom,bluetooth-common.yaml
+ - $ref: /schemas/serial/serial-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ serial {
+ bluetooth {
+ compatible = "qcom,qca6390-bt";
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>;
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/bluetooth/qcom,qca9377-bt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QCA9377 Bluetooth
+
+maintainers:
+ - Balakrishna Godavarthi <quic_bgodavar@quicinc.com>
+ - Rocky Liao <quic_rjliao@quicinc.com>
+
+properties:
+ compatible:
+ enum:
+ - qcom,qca9377-bt
+
+ clocks:
+ items:
+ - description: External low-power 32.768 kHz clock input
+
+ enable-gpios:
+ maxItems: 1
+
+ vddio-supply:
+ description: VDD_IO supply regulator handle
+
+ vddxo-supply:
+ description: VDD_XO supply regulator handle
+
+required:
+ - compatible
+ - clocks
+ - enable-gpios
+
+allOf:
+ - $ref: bluetooth-controller.yaml#
+ - $ref: qcom,bluetooth-common.yaml
+ - $ref: /schemas/serial/serial-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ serial {
+ bluetooth {
+ compatible = "qcom,qca9377-bt";
+ clocks = <&rk809 1>;
+ enable-gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
+ max-speed = <2000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_enable>;
+ vddio-supply = <&vcc_1v8>;
+ vddxo-supply = <&vcc3v3_sys>;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/bluetooth/qcom,wcn3950-bt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm WCN3950/WCN3988 Bluetooth
+
+maintainers:
+ - Balakrishna Godavarthi <quic_bgodavar@quicinc.com>
+ - Rocky Liao <quic_rjliao@quicinc.com>
+
+properties:
+ compatible:
+ enum:
+ - qcom,wcn3950-bt
+ - qcom,wcn3988-bt
+
+ enable-gpios:
+ maxItems: 1
+
+ swctrl-gpios:
+ maxItems: 1
+ description: gpio specifier is used to find status
+ of clock supply to SoC
+
+ vddch0-supply:
+ description: VDD_CH0 supply regulator handle
+
+ vddio-supply:
+ description: VDD_IO supply regulator handle
+
+ vddrf-supply:
+ description: VDD_RF supply regulator handle
+
+ vddxo-supply:
+ description: VDD_XO supply regulator handle
+
+required:
+ - compatible
+ - vddch0-supply
+ - vddio-supply
+ - vddrf-supply
+ - vddxo-supply
+
+allOf:
+ - $ref: bluetooth-controller.yaml#
+ - $ref: qcom,bluetooth-common.yaml
+ - $ref: /schemas/serial/serial-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ serial {
+ bluetooth {
+ compatible = "qcom,wcn3950-bt";
+ enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
+ max-speed = <3200000>;
+ vddch0-supply = <&pm4125_l22>;
+ vddio-supply = <&pm4125_l15>;
+ vddrf-supply = <&pm4125_l10>;
+ vddxo-supply = <&pm4125_l13>;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/bluetooth/qcom,wcn3990-bt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm WCN3990/WCN3991/WCN3998 Bluetooth
+
+maintainers:
+ - Balakrishna Godavarthi <quic_bgodavar@quicinc.com>
+ - Rocky Liao <quic_rjliao@quicinc.com>
+
+properties:
+ compatible:
+ enum:
+ - qcom,wcn3990-bt
+ - qcom,wcn3991-bt
+ - qcom,wcn3998-bt
+
+ clocks:
+ items:
+ - description: External low-power 32.768 kHz clock input
+
+ vddch0-supply:
+ description: VDD_CH0 supply regulator handle
+
+ vddch1-supply:
+ description: VDD_CH1 supply regulator handle
+
+ vddio-supply:
+ description: VDD_IO supply regulator handle
+
+ vddrf-supply:
+ description: VDD_RF supply regulator handle
+
+ vddxo-supply:
+ description: VDD_XO supply regulator handle
+
+required:
+ - compatible
+ - vddch0-supply
+ - vddio-supply
+ - vddrf-supply
+ - vddxo-supply
+
+allOf:
+ - $ref: bluetooth-controller.yaml#
+ - $ref: qcom,bluetooth-common.yaml
+ - $ref: /schemas/serial/serial-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ serial {
+ bluetooth {
+ compatible = "qcom,wcn3990-bt";
+ firmware-name = "crnv21.bin";
+ max-speed = <3200000>;
+ vddio-supply = <&vreg_s4a_1p8>;
+ vddch0-supply = <&vreg_l25a_3p3>;
+ vddch1-supply = <&vreg_l23a_3p3>;
+ vddrf-supply = <&vreg_l17a_1p3>;
+ vddxo-supply = <&vreg_l7a_1p8>;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/bluetooth/qcom,wcn6750-bt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm WCN6750 Bluetooth
+
+maintainers:
+ - Balakrishna Godavarthi <quic_bgodavar@quicinc.com>
+ - Rocky Liao <quic_rjliao@quicinc.com>
+
+properties:
+ compatible:
+ enum:
+ - qcom,wcn6750-bt
+
+ enable-gpios:
+ maxItems: 1
+ deprecated: true
+
+ swctrl-gpios:
+ maxItems: 1
+ description: gpio specifier is used to find status
+ of clock supply to SoC
+ deprecated: true
+
+ vddaon-supply:
+ description: VDD_AON supply regulator handle
+
+ vddasd-supply:
+ description: VDD_ASD supply regulator handle
+ deprecated: true
+
+ vddbtcmx-supply:
+ description: VDD_BT_CMX supply regulator handle
+
+ vddbtcxmx-supply:
+ description: VDD_BT_CXMX supply regulator handle
+ deprecated: true
+
+ vddio-supply:
+ description: VDD_IO supply regulator handle
+ deprecated: true
+
+ vddrfa0p8-supply:
+ description: VDD_RFA_0P8 supply regulator handle
+
+ vddrfa1p2-supply:
+ description: VDD_RFA_1P2 supply regulator handle
+
+ vddrfa1p7-supply:
+ description: VDD_RFA_1P7 supply regulator handle
+
+ vddrfa2p2-supply:
+ description: VDD_RFA_2P2 supply regulator handle
+
+ vddrfacmn-supply:
+ description: VDD_RFA_CMN supply regulator handle
+
+required:
+ - compatible
+ - vddaon-supply
+ - vddrfa0p8-supply
+ - vddrfa1p2-supply
+ - vddrfa1p7-supply
+ - vddrfacmn-supply
+
+allOf:
+ - $ref: bluetooth-controller.yaml#
+ - $ref: qcom,bluetooth-common.yaml
+ - $ref: /schemas/serial/serial-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ serial {
+ bluetooth {
+ compatible = "qcom,wcn6750-bt";
+
+ firmware-name = "msnv11.bin";
+ max-speed = <3200000>;
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>;
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/bluetooth/qcom,wcn6855-bt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm WCN6855 Bluetooth
+
+maintainers:
+ - Bartosz Golaszewski <brgl@bgdev.pl>
+ - Balakrishna Godavarthi <quic_bgodavar@quicinc.com>
+ - Rocky Liao <quic_rjliao@quicinc.com>
+
+properties:
+ compatible:
+ enum:
+ - qcom,wcn6855-bt
+
+ enable-gpios:
+ maxItems: 1
+ deprecated: true
+
+ swctrl-gpios:
+ maxItems: 1
+ description: gpio specifier is used to find status
+ of clock supply to SoC
+ deprecated: true
+
+ vddaon-supply:
+ description: VDD_AON supply regulator handle
+
+ vddbtcmx-supply:
+ description: VDD_BT_CMX supply regulator handle
+
+ vddbtcxmx-supply:
+ description: VDD_BT_CXMX supply regulator handle
+ deprecated: true
+
+ vddio-supply:
+ description: VDD_IO supply regulator handle
+ deprecated: true
+
+ vddrfa0p8-supply:
+ description: VDD_RFA_0P8 supply regulator handle
+
+ vddrfa1p2-supply:
+ description: VDD_RFA_1P2 supply regulator handle
+
+ vddrfa1p7-supply:
+ description: VDD_RFA_1P7 supply regulator handle
+ deprecated: true
+
+ vddrfa1p8-supply:
+ description: VDD_RFA_1P8 supply regulator handle
+
+ vddrfacmn-supply:
+ description: VDD_RFA_CMN supply regulator handle
+
+ vddwlcx-supply:
+ description: VDD_WLCX supply regulator handle
+
+ vddwlmx-supply:
+ description: VDD_WLMX supply regulator handle
+
+required:
+ - compatible
+ - vddaon-supply
+ - vddbtcmx-supply
+ - vddrfa0p8-supply
+ - vddrfa1p2-supply
+ - vddrfa1p8-supply
+ - vddrfacmn-supply
+ - vddwlcx-supply
+ - vddwlmx-supply
+
+allOf:
+ - $ref: bluetooth-controller.yaml#
+ - $ref: qcom,bluetooth-common.yaml
+ - $ref: /schemas/serial/serial-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ serial {
+ bluetooth {
+ compatible = "qcom,wcn6855-bt";
+
+ max-speed = <3000000>;
+ vddaon-supply = <&vreg_pmu_aon_0p8>;
+ vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p8>;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/bluetooth/qcom,wcn7850-bt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm WCN7850 Bluetooth
+
+maintainers:
+ - Bartosz Golaszewski <brgl@bgdev.pl>
+ - Balakrishna Godavarthi <quic_bgodavar@quicinc.com>
+ - Rocky Liao <quic_rjliao@quicinc.com>
+
+properties:
+ compatible:
+ enum:
+ - qcom,wcn7850-bt
+
+ enable-gpios:
+ maxItems: 1
+ deprecated: true
+
+ swctrl-gpios:
+ maxItems: 1
+ description: gpio specifier is used to find status
+ of clock supply to SoC
+ deprecated: true
+
+ vddaon-supply:
+ description: VDD_AON supply regulator handle
+
+ vdddig-supply:
+ description: VDD_DIG supply regulator handle
+ deprecated: true
+
+ vddio-supply:
+ description: VDD_IO supply regulator handle
+ deprecated: true
+
+ vddrfa0p8-supply:
+ description: VDD_RFA_0P8 supply regulator handle
+
+ vddrfa1p2-supply:
+ description: VDD_RFA_1P2 supply regulator handle
+
+ vddrfa1p8-supply:
+ description: VDD_RFA_1P8 supply regulator handle
+
+ vddrfa1p9-supply:
+ description: VDD_RFA_1P9 supply regulator handle
+ deprecated: true
+
+ vddrfacmn-supply:
+ description: VDD_RFA_CMN supply regulator handle
+
+ vddwlcx-supply:
+ description: VDD_WLCX supply regulator handle
+
+ vddwlmx-supply:
+ description: VDD_WLMX supply regulator handle
+
+required:
+ - compatible
+ - vddrfacmn-supply
+ - vddaon-supply
+ - vddwlcx-supply
+ - vddwlmx-supply
+ - vddrfa0p8-supply
+ - vddrfa1p2-supply
+ - vddrfa1p8-supply
+
+allOf:
+ - $ref: bluetooth-controller.yaml#
+ - $ref: qcom,bluetooth-common.yaml
+ - $ref: /schemas/serial/serial-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ serial {
+ bluetooth {
+ compatible = "qcom,wcn7850-bt";
+
+ max-speed = <3200000>;
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ };
+ };
+++ /dev/null
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/net/bluetooth/qualcomm-bluetooth.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Bluetooth Chips
-
-maintainers:
- - Balakrishna Godavarthi <quic_bgodavar@quicinc.com>
- - Rocky Liao <quic_rjliao@quicinc.com>
-
-description:
- This binding describes Qualcomm UART-attached bluetooth chips.
-
-properties:
- compatible:
- enum:
- - qcom,qca2066-bt
- - qcom,qca6174-bt
- - qcom,qca9377-bt
- - qcom,wcn3950-bt
- - qcom,wcn3988-bt
- - qcom,wcn3990-bt
- - qcom,wcn3991-bt
- - qcom,wcn3998-bt
- - qcom,qca6390-bt
- - qcom,wcn6750-bt
- - qcom,wcn6855-bt
- - qcom,wcn7850-bt
-
- enable-gpios:
- maxItems: 1
- description: gpio specifier used to enable chip
-
- swctrl-gpios:
- maxItems: 1
- description: gpio specifier is used to find status
- of clock supply to SoC
-
- clocks:
- maxItems: 1
- description: clock provided to the controller (SUSCLK_32KHZ)
-
- vddio-supply:
- description: VDD_IO supply regulator handle
-
- vddxo-supply:
- description: VDD_XO supply regulator handle
-
- vddrf-supply:
- description: VDD_RF supply regulator handle
-
- vddch0-supply:
- description: VDD_CH0 supply regulator handle
-
- vddch1-supply:
- description: VDD_CH1 supply regulator handle
-
- vddaon-supply:
- description: VDD_AON supply regulator handle
-
- vdddig-supply:
- description: VDD_DIG supply regulator handle
-
- vddbtcmx-supply:
- description: VDD_BT_CMX supply regulator handle
-
- vddbtcxmx-supply:
- description: VDD_BT_CXMX supply regulator handle
-
- vddrfacmn-supply:
- description: VDD_RFA_CMN supply regulator handle
-
- vddrfa0p8-supply:
- description: VDD_RFA_0P8 supply regulator handle
-
- vddrfa1p7-supply:
- description: VDD_RFA_1P7 supply regulator handle
-
- vddrfa1p8-supply:
- description: VDD_RFA_1P8 supply regulator handle
-
- vddrfa1p2-supply:
- description: VDD_RFA_1P2 supply regulator handle
-
- vddrfa1p9-supply:
- description: VDD_RFA_1P9 supply regulator handle
-
- vddrfa2p2-supply:
- description: VDD_RFA_2P2 supply regulator handle
-
- vddasd-supply:
- description: VDD_ASD supply regulator handle
-
- vddwlcx-supply:
- description: VDD_WLCX supply regulator handle
-
- vddwlmx-supply:
- description: VDD_WLMX supply regulator handle
-
- max-speed: true
-
- firmware-name:
- minItems: 1
- items:
- - description: specify the name of nvm firmware to load
- - description: specify the name of rampatch firmware to load
-
- local-bd-address: true
-
- qcom,local-bd-address-broken:
- type: boolean
- description:
- boot firmware is incorrectly passing the address in big-endian order
-
-required:
- - compatible
-
-additionalProperties: false
-
-allOf:
- - $ref: bluetooth-controller.yaml#
- - $ref: /schemas/serial/serial-peripheral-props.yaml#
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,qca2066-bt
- - qcom,qca6174-bt
- then:
- required:
- - enable-gpios
- - clocks
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,wcn3950-bt
- - qcom,wcn3988-bt
- - qcom,wcn3990-bt
- - qcom,wcn3991-bt
- - qcom,wcn3998-bt
- then:
- required:
- - vddio-supply
- - vddxo-supply
- - vddrf-supply
- - vddch0-supply
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,wcn6750-bt
- then:
- required:
- - vddaon-supply
- - vddrfacmn-supply
- - vddrfa0p8-supply
- - vddrfa1p7-supply
- - vddrfa1p2-supply
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,wcn6855-bt
- then:
- required:
- - vddrfacmn-supply
- - vddaon-supply
- - vddwlcx-supply
- - vddwlmx-supply
- - vddbtcmx-supply
- - vddrfa0p8-supply
- - vddrfa1p2-supply
- - vddrfa1p8-supply
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,wcn7850-bt
- then:
- required:
- - vddrfacmn-supply
- - vddaon-supply
- - vddwlcx-supply
- - vddwlmx-supply
- - vddrfa0p8-supply
- - vddrfa1p2-supply
- - vddrfa1p8-supply
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,qca6390-bt
- then:
- required:
- - vddrfacmn-supply
- - vddaon-supply
- - vddbtcmx-supply
- - vddrfa0p8-supply
- - vddrfa1p2-supply
- - vddrfa1p7-supply
-
-examples:
- - |
- #include <dt-bindings/gpio/gpio.h>
- serial {
-
- bluetooth {
- compatible = "qcom,qca6174-bt";
- enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>;
- clocks = <&divclk4>;
- firmware-name = "nvm_00440302.bin";
- };
- };
- - |
- serial {
-
- bluetooth {
- compatible = "qcom,wcn3990-bt";
- vddio-supply = <&vreg_s4a_1p8>;
- vddxo-supply = <&vreg_l7a_1p8>;
- vddrf-supply = <&vreg_l17a_1p3>;
- vddch0-supply = <&vreg_l25a_3p3>;
- max-speed = <3200000>;
- firmware-name = "crnv21.bin";
- };
- };
- - |
- serial {
-
- bluetooth {
- compatible = "qcom,wcn6750-bt";
- pinctrl-names = "default";
- pinctrl-0 = <&bt_en_default>;
- enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>;
- swctrl-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>;
- vddio-supply = <&vreg_l19b_1p8>;
- vddaon-supply = <&vreg_s7b_0p9>;
- vddbtcxmx-supply = <&vreg_s7b_0p9>;
- vddrfacmn-supply = <&vreg_s7b_0p9>;
- vddrfa0p8-supply = <&vreg_s7b_0p9>;
- vddrfa1p7-supply = <&vreg_s1b_1p8>;
- vddrfa1p2-supply = <&vreg_s8b_1p2>;
- vddrfa2p2-supply = <&vreg_s1c_2p2>;
- vddasd-supply = <&vreg_l11c_2p8>;
- max-speed = <3200000>;
- firmware-name = "msnv11.bin";
- };
- };
- const: idm_base
- const: nicpm_base
+ dma-coherent: true
+
unevaluatedProperties: false
examples:
allOf:
- $ref: can-controller.yaml#
+ - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml
- if:
properties:
compatible:
properties:
compatible:
oneOf:
+ - enum:
+ - renesas,r9a09g047-canfd # RZ/G3E
+ - renesas,r9a09g077-canfd # RZ/T2H
+
- items:
- enum:
- renesas,r8a774a1-canfd # RZ/G2M
- renesas,r9a07g054-canfd # RZ/V2L
- const: renesas,rzg2l-canfd # RZ/G2L family
- - const: renesas,r9a09g047-canfd # RZ/G3E
+ - items:
+ - enum:
+ - renesas,r9a09g056-canfd # RZ/V2N
+ - renesas,r9a09g057-canfd # RZ/V2H(P)
+ - const: renesas,r9a09g047-canfd
+
+ - items:
+ - const: renesas,r9a09g087-canfd # RZ/N2H
+ - const: renesas,r9a09g077-canfd
reg:
maxItems: 1
resets: true
+ reset-names:
+ items:
+ - const: rstp_n
+ - const: rstc_n
+
renesas,no-can-fd:
$ref: /schemas/types.yaml#/definitions/flag
description:
- The controller can operate in either CAN FD only mode (default) or
- Classical CAN only mode. The mode is global to all channels.
- Specify this property to put the controller in Classical CAN only mode.
+ The controller can operate in either CAN-FD mode (default) or FD-Only
+ mode (RZ/{G2L,G3E} and R-Car Gen4) or Classical CAN mode. Specify this
+ property to put the controller in Classical CAN mode.
+
+ renesas,fd-only:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ The CANFD on RZ/{G2L,G3E} and R-Car Gen4 SoCs support 3 modes FD-Only
+ mode, Classical CAN mode and CAN-FD mode (default). In FD-Only mode,
+ communication in Classical CAN frame format is disabled. Specify this
+ property to put the controller in FD-Only mode.
assigned-clocks:
description:
- clocks
- clock-names
- power-domains
- - resets
- assigned-clocks
- assigned-clock-rates
- channel0
minItems: 2
maxItems: 2
- reset-names:
- minItems: 2
- maxItems: 2
-
- required:
- - reset-names
-
- if:
properties:
compatible:
minItems: 2
maxItems: 2
- reset-names:
- minItems: 2
- maxItems: 2
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g077-canfd
+ then:
+ properties:
+ interrupts:
+ maxItems: 8
- required:
- - reset-names
+ interrupt-names:
+ maxItems: 8
- if:
properties:
compatible:
contains:
enum:
+ - renesas,r9a09g077-canfd
- renesas,rcar-gen3-canfd
- renesas,rzg2l-canfd
then:
patternProperties:
"^channel[6-7]$": false
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,rcar-gen3-canfd
+ then:
+ properties:
+ renesas,fd-only: false
+
+ - if:
+ required:
+ - renesas,no-can-fd
+ then:
+ properties:
+ renesas,fd-only: false
+
+ - if:
+ required:
+ - renesas,fd-only
+ then:
+ properties:
+ renesas,no-can-fd: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g077-canfd
+ then:
+ properties:
+ resets: false
+ reset-names: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,r9a09g047-canfd
+ - renesas,rzg2l-canfd
+ then:
+ required:
+ - resets
+ - reset-names
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,rcar-gen3-canfd
+ - renesas,rcar-gen4-canfd
+ then:
+ required:
+ - resets
+ properties:
+ reset-names: false
+
unevaluatedProperties: false
examples:
properties:
compatible:
enum:
+ - intel,gsw150
+ - lantiq,peb7084
- lantiq,xrx200-gswip
- lantiq,xrx300-gswip
- lantiq,xrx330-gswip
patternProperties:
"^(ethernet-)?port@[0-6]$":
$ref: dsa-port.yaml#
+ allOf:
+ - $ref: /schemas/phy/phy-common-props.yaml#
unevaluatedProperties: false
properties:
+ maxlinear,slew-rate-txc:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+ description: |
+ RMII/RGMII TX Clock Slew Rate:
+
+ 0: Normal
+ 1: Slow
+
+ If not present, the configuration made by the switch bootloader is
+ preserved.
+ maxlinear,slew-rate-txd:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+ description: |
+ RMII/RGMII TX Non-Clock PAD Slew Rate:
+
+ 0: Normal
+ 1: Slow
+
+ If not present, the configuration made by the switch bootloader is
+ preserved.
maxlinear,rmii-refclk-out:
type: boolean
description:
- |
#include <dt-bindings/leds/common.h>
+ #include <dt-bindings/phy/phy.h>
mdio {
#address-cells = <1>;
label = "wan";
phy-mode = "1000base-x";
managed = "in-band-status";
+ tx-polarity = <PHY_POL_INVERT>;
};
port@5 {
#address-cells = <1>;
#size-cells = <0>;
- switchphy0: switchphy@0 {
+ switchphy0: ethernet-phy@0 {
reg = <0>;
leds {
};
};
- switchphy1: switchphy@1 {
+ switchphy1: ethernet-phy@1 {
reg = <1>;
leds {
'#interrupt-cells':
description: The internal interrupt controller only supports triggering
- on active high level interrupts so the second cell must alway be set to
+ on active high level interrupts so the second cell must always be set to
IRQ_TYPE_LEVEL_HIGH.
const: 2
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/maxlinear,mxl862xx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MaxLinear MxL862xx Ethernet Switch Family
+
+maintainers:
+ - Daniel Golle <daniel@makrotopia.org>
+
+description:
+ The MaxLinear MxL862xx switch family are multi-port Ethernet switches with
+ integrated 2.5GE PHYs. The MxL86252 has five PHY ports and the MxL86282
+ has eight PHY ports. Both models come with two 10 Gigabit/s SerDes
+ interfaces to be used to connect external PHYs or SFP cages, or as CPU
+ port.
+
+allOf:
+ - $ref: dsa.yaml#/$defs/ethernet-ports
+
+properties:
+ compatible:
+ enum:
+ - maxlinear,mxl86252
+ - maxlinear,mxl86282
+
+ reg:
+ maxItems: 1
+ description: MDIO address of the switch
+
+ mdio:
+ $ref: /schemas/net/mdio.yaml#
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - mdio
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch@0 {
+ compatible = "maxlinear,mxl86282";
+ reg = <0>;
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Microcontroller port */
+ port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ port@1 {
+ reg = <1>;
+ phy-handle = <&phy0>;
+ phy-mode = "internal";
+ };
+
+ port@2 {
+ reg = <2>;
+ phy-handle = <&phy1>;
+ phy-mode = "internal";
+ };
+
+ port@3 {
+ reg = <3>;
+ phy-handle = <&phy2>;
+ phy-mode = "internal";
+ };
+
+ port@4 {
+ reg = <4>;
+ phy-handle = <&phy3>;
+ phy-mode = "internal";
+ };
+
+ port@5 {
+ reg = <5>;
+ phy-handle = <&phy4>;
+ phy-mode = "internal";
+ };
+
+ port@6 {
+ reg = <6>;
+ phy-handle = <&phy5>;
+ phy-mode = "internal";
+ };
+
+ port@7 {
+ reg = <7>;
+ phy-handle = <&phy6>;
+ phy-mode = "internal";
+ };
+
+ port@8 {
+ reg = <8>;
+ phy-handle = <&phy7>;
+ phy-mode = "internal";
+ };
+
+ port@9 {
+ reg = <9>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "usxgmii";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ };
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+
+ phy4: ethernet-phy@4 {
+ reg = <4>;
+ };
+
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ };
+
+ phy6: ethernet-phy@6 {
+ reg = <6>;
+ };
+
+ phy7: ethernet-phy@7 {
+ reg = <7>;
+ };
+ };
+ };
+ };
- const: reset
description:
Used during reset for strap configuration.
+ minItems: 1
reset-gpios:
description:
const: microchip,ksz8463
then:
properties:
+ pinctrl-names:
+ minItems: 2
straps-rxd-gpios:
description:
RXD0 and RXD1 pins, used to select SPI as bus interface.
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/ethernet-connector.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic Ethernet Connector
+
+maintainers:
+ - Maxime Chevallier <maxime.chevallier@bootlin.com>
+
+description:
+ An Ethernet Connector represents the output of a network component such as
+ a PHY, an Ethernet controller with no PHY, or an SFP module.
+
+properties:
+
+ pairs:
+ description:
+ Defines the number of BaseT pairs that are used on the connector.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 4]
+
+ media:
+ description:
+ The mediums, as defined in 802.3, that can be used on the port.
+ enum:
+ - BaseT
+ - BaseK
+ - BaseS
+ - BaseC
+ - BaseL
+ - BaseD
+ - BaseE
+ - BaseF
+ - BaseV
+ - BaseMLD
+
+required:
+ - media
+
+allOf:
+ - if:
+ properties:
+ media:
+ const: BaseT
+ then:
+ required:
+ - pairs
+ else:
+ properties:
+ pairs: false
+
+additionalProperties: true
+
+...
additionalProperties: false
+ mdi:
+ type: object
+
+ patternProperties:
+ '^connector-[0-9]+$':
+ $ref: /schemas/net/ethernet-connector.yaml#
+
+ unevaluatedProperties: false
+
+ additionalProperties: false
+
required:
- reg
default-state = "keep";
};
};
+ /* Fast Ethernet port, with only 2 pairs wired */
+ mdi {
+ connector-0 {
+ pairs = <2>;
+ media = "BaseT";
+ };
+ };
};
};
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/micrel,gigabit.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Micrel series Gigabit Ethernet PHYs
+
+maintainers:
+ - Andrew Lunn <andrew@lunn.ch>
+ - Stefan Eichenberger <eichest@gmail.com>
+
+description:
+ Some boards require special skew tuning values, particularly when it comes
+ to clock delays. These values can be specified in the device tree using
+ the properties listed here.
+
+properties:
+ compatible:
+ enum:
+ - ethernet-phy-id0022.1610 # KSZ9021
+ - ethernet-phy-id0022.1611 # KSZ9021RLRN
+ - ethernet-phy-id0022.1620 # KSZ9031
+ - ethernet-phy-id0022.1631 # KSZ9477
+ - ethernet-phy-id0022.1640 # KSZ9131
+ - ethernet-phy-id0022.1650 # LAN8841
+ - ethernet-phy-id0022.1660 # LAN8814
+ - ethernet-phy-id0022.1670 # LAN8804
+
+ micrel,force-master:
+ type: boolean
+ description: |
+ Force phy to master mode. Only set this option if the phy reference
+ clock provided at CLK125_NDO pin is used as MAC reference clock
+ because the clock jitter in slave mode is too high (errata#2).
+ Attention: The link partner must be configurable as slave otherwise
+ no link will be established.
+
+ coma-mode-gpios:
+ maxItems: 1
+ description: |
+ If present the given gpio will be deasserted when the PHY is probed.
+
+ Some PHYs have a COMA mode input pin which puts the PHY into
+ isolate and power-down mode. On some boards this input is connected
+ to a GPIO of the SoC.
+
+ micrel,led-mode:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ LED mode value to set for PHYs with configurable LEDs.
+
+ Configure the LED mode with single value. The list of PHYs and the
+ bits that are currently supported:
+
+ LAN8814: register EP5.0, bit 6
+
+ See the respective PHY datasheet for the mode values.
+ minimum: 0
+ maximum: 1
+
+patternProperties:
+ '^([rt]xc)-skew-psec$':
+ $ref: /schemas/types.yaml#/definitions/int32
+ description:
+ Skew control of the pad in picoseconds.
+ minimum: -700
+ maximum: 2400
+ multipleOf: 100
+ default: 0
+
+ '^([rt]xd[0-3]|rxdv|txen)-skew-psec$':
+ $ref: /schemas/types.yaml#/definitions/int32
+ description: |
+ Skew control of the pad in picoseconds.
+ minimum: -700
+ maximum: 800
+ multipleOf: 100
+ default: 0
+
+allOf:
+ - $ref: ethernet-phy.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ethernet-phy-id0022.1610
+ - ethernet-phy-id0022.1611
+ then:
+ patternProperties:
+ '^([rt]xd[0-3]|[rt]xc|rxdv|txen)-skew-ps$':
+ description: |
+ Skew control of the pad in picoseconds.
+ The actual increment on the chip is 120ps ranging from -840ps to
+ 960ps, this mismatch comes from a documentation error before
+ datasheet revision 1.2 (Feb 2014).
+
+ The device tree value to delay mapping looks as follows:
+ Device Tree Value Delay
+ --------------------------
+ 0 -840ps
+ 200 -720ps
+ 400 -600ps
+ 600 -480ps
+ 800 -360ps
+ 1000 -240ps
+ 1200 -120ps
+ 1400 0ps
+ 1600 120ps
+ 1800 240ps
+ 2000 360ps
+ 2200 480ps
+ 2400 600ps
+ 2600 720ps
+ 2800 840ps
+ 3000 960ps
+ minimum: 0
+ maximum: 3000
+ multipleOf: 200
+ default: 1400
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ethernet-phy-id0022.1620
+ then:
+ patternProperties:
+ '^([rt]xc)-skew-ps$':
+ description: |
+ Skew control of the pad in picoseconds.
+
+ The device tree value to delay mapping is as follows:
+ Device Tree Value Delay
+ --------------------------
+ 0 -900ps
+ 60 -840ps
+ 120 -780ps
+ 180 -720ps
+ 240 -660ps
+ 300 -600ps
+ 360 -540ps
+ 420 -480ps
+ 480 -420ps
+ 540 -360ps
+ 600 -300ps
+ 660 -240ps
+ 720 -180ps
+ 780 -120ps
+ 840 -60ps
+ 900 0ps
+ 960 60ps
+ 1020 120ps
+ 1080 180ps
+ 1140 240ps
+ 1200 300ps
+ 1260 360ps
+ 1320 420ps
+ 1380 480ps
+ 1440 540ps
+ 1500 600ps
+ 1560 660ps
+ 1620 720ps
+ 1680 780ps
+ 1740 840ps
+ 1800 900ps
+ 1860 960ps
+ minimum: 0
+ maximum: 1860
+ multipleOf: 60
+ default: 900
+ '^([rt]xd[0-3]|rxdv|txen)-skew-ps$':
+ description: |
+ Skew control of the pad in picoseconds.
+
+ The device tree value to delay mapping is as follows:
+ Device Tree Value Delay
+ --------------------------
+ 0 -420ps
+ 60 -360ps
+ 120 -300ps
+ 180 -240ps
+ 240 -180ps
+ 300 -120ps
+ 360 -60ps
+ 420 0ps
+ 480 60ps
+ 540 120ps
+ 600 180ps
+ 660 240ps
+ 720 300ps
+ 780 360ps
+ 840 420ps
+ 900 480ps
+ minimum: 0
+ maximum: 900
+ multipleOf: 60
+ default: 420
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ethernet-phy-id0022.1640
+ - ethernet-phy-id0022.1650
+ then:
+ patternProperties:
+ '^([rt]xd[0-3]|[rt]xc|rxdv|txen)-skew-psec$': false
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: ethernet-phy-id0022.1620
+ then:
+ properties:
+ micrel,force-master: false
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: ethernet-phy-id0022.1660
+ then:
+ properties:
+ coma-mode-gpios: false
+ micrel,led-mode: false
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@7 {
+ compatible = "ethernet-phy-id0022.1610";
+ reg = <7>;
+ rxc-skew-ps = <3000>;
+ rxdv-skew-ps = <0>;
+ txc-skew-ps = <3000>;
+ txen-skew-ps = <0>;
+ };
+
+ ethernet-phy@9 {
+ compatible = "ethernet-phy-id0022.1640";
+ reg = <9>;
+ rxc-skew-psec = <(-100)>;
+ txc-skew-psec = <(-100)>;
+ };
+ };
+++ /dev/null
-Micrel KSZ9021/KSZ9031/KSZ9131 Gigabit Ethernet PHY
-
-Some boards require special tuning values, particularly when it comes
-to clock delays. You can specify clock delay values in the PHY OF
-device node. Deprecated, but still supported, these properties can
-also be added to an Ethernet OF device node.
-
-Note that these settings are applied after any phy-specific fixup from
-phy_fixup_list (see phy_init_hw() from drivers/net/phy/phy_device.c),
-and therefore may overwrite them.
-
-KSZ9021:
-
- All skew control options are specified in picoseconds. The minimum
- value is 0, the maximum value is 3000, and it can be specified in 200ps
- steps, *but* these values are in no way what you get because this chip's
- skew values actually increase in 120ps steps, starting from -840ps. The
- incorrect values came from an error in the original KSZ9021 datasheet
- before it was corrected in revision 1.2 (Feb 2014), but it is too late to
- change the driver now because of the many existing device trees that have
- been created using values that go up in increments of 200.
-
- The following table shows the actual skew delay you will get for each of the
- possible devicetree values, and the number that will be programmed into the
- corresponding pad skew register:
-
- Device Tree Value Delay Pad Skew Register Value
- -----------------------------------------------------
- 0 -840ps 0000
- 200 -720ps 0001
- 400 -600ps 0010
- 600 -480ps 0011
- 800 -360ps 0100
- 1000 -240ps 0101
- 1200 -120ps 0110
- 1400 0ps 0111
- 1600 120ps 1000
- 1800 240ps 1001
- 2000 360ps 1010
- 2200 480ps 1011
- 2400 600ps 1100
- 2600 720ps 1101
- 2800 840ps 1110
- 3000 960ps 1111
-
- Optional properties:
-
- - rxc-skew-ps : Skew control of RXC pad
- - rxdv-skew-ps : Skew control of RX CTL pad
- - txc-skew-ps : Skew control of TXC pad
- - txen-skew-ps : Skew control of TX CTL pad
- - rxd0-skew-ps : Skew control of RX data 0 pad
- - rxd1-skew-ps : Skew control of RX data 1 pad
- - rxd2-skew-ps : Skew control of RX data 2 pad
- - rxd3-skew-ps : Skew control of RX data 3 pad
- - txd0-skew-ps : Skew control of TX data 0 pad
- - txd1-skew-ps : Skew control of TX data 1 pad
- - txd2-skew-ps : Skew control of TX data 2 pad
- - txd3-skew-ps : Skew control of TX data 3 pad
-
-KSZ9031:
-
- All skew control options are specified in picoseconds. The minimum
- value is 0, and the maximum is property-dependent. The increment
- step is 60ps. The default value is the neutral setting, so setting
- rxc-skew-ps=<0> actually results in -900 picoseconds adjustment.
-
- The KSZ9031 hardware supports a range of skew values from negative to
- positive, where the specific range is property dependent. All values
- specified in the devicetree are offset by the minimum value so they
- can be represented as positive integers in the devicetree since it's
- difficult to represent a negative number in the devictree.
-
- The following 5-bit values table apply to rxc-skew-ps and txc-skew-ps.
-
- Pad Skew Value Delay (ps) Devicetree Value
- ------------------------------------------------------
- 0_0000 -900ps 0
- 0_0001 -840ps 60
- 0_0010 -780ps 120
- 0_0011 -720ps 180
- 0_0100 -660ps 240
- 0_0101 -600ps 300
- 0_0110 -540ps 360
- 0_0111 -480ps 420
- 0_1000 -420ps 480
- 0_1001 -360ps 540
- 0_1010 -300ps 600
- 0_1011 -240ps 660
- 0_1100 -180ps 720
- 0_1101 -120ps 780
- 0_1110 -60ps 840
- 0_1111 0ps 900
- 1_0000 60ps 960
- 1_0001 120ps 1020
- 1_0010 180ps 1080
- 1_0011 240ps 1140
- 1_0100 300ps 1200
- 1_0101 360ps 1260
- 1_0110 420ps 1320
- 1_0111 480ps 1380
- 1_1000 540ps 1440
- 1_1001 600ps 1500
- 1_1010 660ps 1560
- 1_1011 720ps 1620
- 1_1100 780ps 1680
- 1_1101 840ps 1740
- 1_1110 900ps 1800
- 1_1111 960ps 1860
-
- The following 4-bit values table apply to the txdX-skew-ps, rxdX-skew-ps
- data pads, and the rxdv-skew-ps, txen-skew-ps control pads.
-
- Pad Skew Value Delay (ps) Devicetree Value
- ------------------------------------------------------
- 0000 -420ps 0
- 0001 -360ps 60
- 0010 -300ps 120
- 0011 -240ps 180
- 0100 -180ps 240
- 0101 -120ps 300
- 0110 -60ps 360
- 0111 0ps 420
- 1000 60ps 480
- 1001 120ps 540
- 1010 180ps 600
- 1011 240ps 660
- 1100 300ps 720
- 1101 360ps 780
- 1110 420ps 840
- 1111 480ps 900
-
- Optional properties:
-
- Maximum value of 1860, default value 900:
-
- - rxc-skew-ps : Skew control of RX clock pad
- - txc-skew-ps : Skew control of TX clock pad
-
- Maximum value of 900, default value 420:
-
- - rxdv-skew-ps : Skew control of RX CTL pad
- - txen-skew-ps : Skew control of TX CTL pad
- - rxd0-skew-ps : Skew control of RX data 0 pad
- - rxd1-skew-ps : Skew control of RX data 1 pad
- - rxd2-skew-ps : Skew control of RX data 2 pad
- - rxd3-skew-ps : Skew control of RX data 3 pad
- - txd0-skew-ps : Skew control of TX data 0 pad
- - txd1-skew-ps : Skew control of TX data 1 pad
- - txd2-skew-ps : Skew control of TX data 2 pad
- - txd3-skew-ps : Skew control of TX data 3 pad
-
- - micrel,force-master:
- Boolean, force phy to master mode. Only set this option if the phy
- reference clock provided at CLK125_NDO pin is used as MAC reference
- clock because the clock jitter in slave mode is too high (errata#2).
- Attention: The link partner must be configurable as slave otherwise
- no link will be established.
-
-KSZ9131:
-LAN8841:
-
- All skew control options are specified in picoseconds. The increment
- step is 100ps. Unlike KSZ9031, the values represent picoseccond delays.
- A negative value can be assigned as rxc-skew-psec = <(-100)>;.
-
- Optional properties:
-
- Range of the value -700 to 2400, default value 0:
-
- - rxc-skew-psec : Skew control of RX clock pad
- - txc-skew-psec : Skew control of TX clock pad
-
- Range of the value -700 to 800, default value 0:
-
- - rxdv-skew-psec : Skew control of RX CTL pad
- - txen-skew-psec : Skew control of TX CTL pad
- - rxd0-skew-psec : Skew control of RX data 0 pad
- - rxd1-skew-psec : Skew control of RX data 1 pad
- - rxd2-skew-psec : Skew control of RX data 2 pad
- - rxd3-skew-psec : Skew control of RX data 3 pad
- - txd0-skew-psec : Skew control of TX data 0 pad
- - txd1-skew-psec : Skew control of TX data 1 pad
- - txd2-skew-psec : Skew control of TX data 2 pad
- - txd3-skew-psec : Skew control of TX data 3 pad
-
-Examples:
-
- /* Attach to an Ethernet device with autodetected PHY */
- &enet {
- rxc-skew-ps = <1800>;
- rxdv-skew-ps = <0>;
- txc-skew-ps = <1800>;
- txen-skew-ps = <0>;
- status = "okay";
- };
-
- /* Attach to an explicitly-specified PHY */
- mdio {
- phy0: ethernet-phy@0 {
- rxc-skew-ps = <1800>;
- rxdv-skew-ps = <0>;
- txc-skew-ps = <1800>;
- txen-skew-ps = <0>;
- reg = <0>;
- };
- };
- ethernet@70000 {
- phy = <&phy0>;
- phy-mode = "rgmii-id";
- };
-
-References
-
- Micrel ksz9021rl/rn Data Sheet, Revision 1.2. Dated 2/13/2014.
- http://www.micrel.com/_PDF/Ethernet/datasheets/ksz9021rl-rn_ds.pdf
-
- Micrel ksz9031rnx Data Sheet, Revision 2.1. Dated 11/20/2014.
- http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf
-
-Notes:
-
- Note that a previous version of the Micrel ksz9021rl/rn Data Sheet
- was missing extended register 106 (transmit data pad skews), and
- incorrectly specified the ps per step as 200ps/step instead of
- 120ps/step. The latest update to this document reflects the latest
- revision of the Micrel specification even though usage in the kernel
- still reflects that incorrect document.
+++ /dev/null
-Micrel PHY properties.
-
-These properties cover the base properties Micrel PHYs.
-
-Optional properties:
-
- - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
-
- Configure the LED mode with single value. The list of PHYs and the
- bits that are currently supported:
-
- KSZ8001: register 0x1e, bits 15..14
- KSZ8041: register 0x1e, bits 15..14
- KSZ8021: register 0x1f, bits 5..4
- KSZ8031: register 0x1f, bits 5..4
- KSZ8051: register 0x1f, bits 5..4
- KSZ8081: register 0x1f, bits 5..4
- KSZ8091: register 0x1f, bits 5..4
- LAN8814: register EP5.0, bit 6
-
- See the respective PHY datasheet for the mode values.
-
- - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
- bit selects 25 MHz mode
-
- Setting the RMII Reference Clock Select bit enables 25 MHz rather
- than 50 MHz clock mode.
-
- Note that this option is only needed for certain PHY revisions with a
- non-standard, inverted function of this configuration bit.
- Specifically, a clock reference ("rmii-ref" below) is always needed to
- actually select a mode.
-
- - clocks, clock-names: contains clocks according to the common clock bindings.
-
- supported clocks:
- - KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference
- input clock. Used to determine the XI input clock.
-
- - micrel,fiber-mode: If present the PHY is configured to operate in fiber mode
-
- Some PHYs, such as the KSZ8041FTL variant, support fiber mode, enabled
- by the FXEN boot strapping pin. It can't be determined from the PHY
- registers whether the PHY is in fiber mode, so this boolean device tree
- property can be used to describe it.
-
- In fiber mode, auto-negotiation is disabled and the PHY can only work in
- 100base-fx (full and half duplex) modes.
-
- - coma-mode-gpios: If present the given gpio will be deasserted when the
- PHY is probed.
-
- Some PHYs have a COMA mode input pin which puts the PHY into
- isolate and power-down mode. On some boards this input is connected
- to a GPIO of the SoC.
-
- Supported on the LAN8814.
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/micrel.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Micrel KSZ series PHYs and switches
+
+maintainers:
+ - Andrew Lunn <andrew@lunn.ch>
+ - Stefan Eichenberger <eichest@gmail.com>
+
+description:
+ The Micrel KSZ series contains different network phys and switches.
+
+properties:
+ compatible:
+ enum:
+ - ethernet-phy-id000e.7237 # KSZ8873MLL
+ - ethernet-phy-id0022.1430 # KSZ886X
+ - ethernet-phy-id0022.1435 # KSZ8863
+ - ethernet-phy-id0022.1510 # KSZ8041
+ - ethernet-phy-id0022.1537 # KSZ8041RNLI
+ - ethernet-phy-id0022.1550 # KSZ8051
+ - ethernet-phy-id0022.1555 # KSZ8021
+ - ethernet-phy-id0022.1556 # KSZ8031
+ - ethernet-phy-id0022.1560 # KSZ8081, KSZ8091
+ - ethernet-phy-id0022.1570 # KSZ8061
+ - ethernet-phy-id0022.161a # KSZ8001
+ - ethernet-phy-id0022.1720 # KS8737
+
+ micrel,fiber-mode:
+ type: boolean
+ description: |
+ If present the PHY is configured to operate in fiber mode.
+
+ The KSZ8041FTL variant supports fiber mode, enabled by the FXEN
+ boot strapping pin. It can't be determined from the PHY registers
+ whether the PHY is in fiber mode, so this boolean device tree
+ property can be used to describe it.
+
+ In fiber mode, auto-negotiation is disabled and the PHY can only
+ work in 100base-fx (full and half duplex) modes.
+
+ micrel,led-mode:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ LED mode value to set for PHYs with configurable LEDs.
+
+ Configure the LED mode with single value. The list of PHYs and the
+ bits that are currently supported:
+
+ KSZ8001: register 0x1e, bits 15..14
+ KSZ8041: register 0x1e, bits 15..14
+ KSZ8021: register 0x1f, bits 5..4
+ KSZ8031: register 0x1f, bits 5..4
+ KSZ8051: register 0x1f, bits 5..4
+ KSZ8081: register 0x1f, bits 5..4
+ KSZ8091: register 0x1f, bits 5..4
+
+ See the respective PHY datasheet for the mode values.
+ minimum: 0
+ maximum: 3
+
+allOf:
+ - $ref: ethernet-phy.yaml#
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: ethernet-phy-id0022.1510
+ then:
+ properties:
+ micrel,fiber-mode: false
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ethernet-phy-id0022.1510
+ - ethernet-phy-id0022.1555
+ - ethernet-phy-id0022.1556
+ - ethernet-phy-id0022.1550
+ - ethernet-phy-id0022.1560
+ - ethernet-phy-id0022.161a
+ then:
+ properties:
+ micrel,led-mode: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ethernet-phy-id0022.1555
+ - ethernet-phy-id0022.1556
+ - ethernet-phy-id0022.1560
+ then:
+ properties:
+ clock-names:
+ const: rmii-ref
+ description:
+ The RMII reference input clock. Used to determine the XI input
+ clock.
+ micrel,rmii-reference-clock-select-25-mhz:
+ type: boolean
+ description: |
+ RMII Reference Clock Select bit selects 25 MHz mode
+
+ Setting the RMII Reference Clock Select bit enables 25 MHz rather
+ than 50 MHz clock mode.
+
+dependentRequired:
+ micrel,rmii-reference-clock-select-25-mhz: [ clock-names ]
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@5 {
+ compatible = "ethernet-phy-id0022.1510";
+ reg = <5>;
+ micrel,led-mode = <2>;
+ micrel,fiber-mode;
+ };
+ };
required:
- reg
- - phys
- phy-mode
- microchip,bandwidth
+ if:
+ not:
+ properties:
+ phy-mode:
+ contains:
+ enum:
+ - rgmii
+ - rgmii-id
+ - rgmii-rxid
+ - rgmii-txid
+ then:
+ required:
+ - phys
+
oneOf:
- required:
- phy-handle
properties:
compatible:
- enum:
- - mscc,ocelot-miim
- - microchip,lan966x-miim
+ oneOf:
+ - enum:
+ - mscc,ocelot-miim
+ - microchip,lan966x-miim
+ - items:
+ - enum:
+ - microchip,lan9691-miim
+ - const: mscc,ocelot-miim
"#address-cells":
const: 1
- const: mgbe
- const: mac
- const: mac-divider
- - const: ptp-ref
+ - const: ptp_ref
- const: rx-input-m
- const: rx-input
- const: tx
<&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
<&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
<&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
- clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ clock-names = "mgbe", "mac", "mac-divider", "ptp_ref", "rx-input-m",
"rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
"rx-pcs", "tx-pcs";
resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
- description: Main GMAC registers
- description: GMAC PHY mode control register
+ nxp,phy-sel:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to the GPR syscon node
+ - description: offset of PHY selection register
+ description:
+ This phandle points to the GMAC_0_CTRL_STS register which controls the
+ GMAC_0 configuration options. The register lets you select the PHY
+ interface and the PHY mode. It also controls if the FTM_0 or FTM_1
+ FlexTimer Modules connect to GMAC_0.
+
interrupts:
maxItems: 1
compatible = "nxp,s32g2-dwmac";
reg = <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */
<0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */
+ nxp,phy-sel = <&gpr 0x4>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
const: 1
mediatek,pnswap:
- description: Invert polarity of the SGMII data lanes
+ description:
+ Invert polarity of the SGMII data lanes.
+ This property is deprecated, for details please refer to
+ Documentation/devicetree/bindings/phy/phy-common-props.yaml.
type: boolean
+ deprecated: true
pcs:
type: object
description: MediaTek LynxI HSGMII PCS
+ $ref: /schemas/phy/phy-common-props.yaml#
properties:
compatible:
const: mediatek,mt7988-sgmii
and include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h for RZ/N2H, RZ/T2H SoCs.
$ref: /schemas/types.yaml#/definitions/uint32
+ renesas,miic-phy-link-active-low:
+ type: boolean
+ description: Indicates that the PHY-link signal provided by the Ethernet switch,
+ EtherCAT, or SERCOS3 interface is active low. When present, this property
+ sets the corresponding signal polarity to active low. When omitted, the signal
+ defaults to active high.
+
required:
- reg
- renesas,miic-input
properties:
compatible:
oneOf:
+ - items:
+ - const: renesas,r9a08g046-gbeth # RZ/G3L
+ - const: snps,dwmac-5.30a
- items:
- enum:
- renesas,r9a09g047-gbeth # RZ/G3E
clocks:
oneOf:
- items:
- - description: CSR clock
- - description: AXI system clock
+ - description: CSR/Register access clock
+ - description: AXI system/Main clock
- description: PTP clock
- description: TX clock
- description: RX clock
- description: TX clock phase-shifted by 180 degrees
- description: RX clock phase-shifted by 180 degrees
+ - description: RMII clock
+ - description: RMII TX clock
+ - description: RMII RX clock
+
+ minItems: 7
+
- items:
- description: CSR clock
- description: AXI system clock
- const: rx
- const: tx-180
- const: rx-180
+ - const: rmii
+ - const: rmii_tx
+ - const: rmii_rx
+
+ minItems: 7
+
- items:
- const: stmmaceth
- const: pclk
- const: tx-queue-1
- const: tx-queue-2
- const: tx-queue-3
+ - items:
+ - const: macirq
+ - const: eth_wake_irq
+ - const: eth_lpi
+ - const: rx-queue-0
+ - const: rx-queue-1
+ - const: rx-queue-2
+ - const: rx-queue-3
+ - const: tx-queue-0
+ - const: tx-queue-1
+ - const: tx-queue-2
+ - const: tx-queue-3
+ - const: ptp-pps-0
+ - const: ptp-pps-1
+ - const: ptp-pps-2
+ - const: ptp-pps-3
- items:
- const: macirq
- const: eth_wake_irq
allOf:
- $ref: snps,dwmac.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a08g046-gbeth
+ then:
+ properties:
+ clocks:
+ minItems: 10
+
+ clock-names:
+ minItems: 10
+
+ interrupts:
+ minItems: 15
+ maxItems: 15
+
+ interrupt-names:
+ minItems: 15
+ maxItems: 15
+
- if:
properties:
compatible:
required:
- reset-names
else:
+ properties:
+ resets:
+ maxItems: 1
+
+ pcs-handle: false
+
+ reset-names: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,rzv2h-gbeth
+ then:
properties:
clocks:
- minItems: 7
+ maxItems: 7
clock-names:
- minItems: 7
+ maxItems: 7
interrupts:
minItems: 11
minItems: 11
maxItems: 11
- resets:
- maxItems: 1
-
- pcs-handle: false
-
- reset-names: false
-
unevaluatedProperties: false
examples:
- clk_mac_refout
- clk_mac_speed
+ dma-coherent: true
+
clock_in_out:
description:
For RGMII, it must be "input", means main clock(125MHz)
- qcom,sc8280xp-ethqos
- qcom,sm8150-ethqos
- renesas,r9a06g032-gmac
+ - renesas,r9a08g046-gbeth
- renesas,r9a09g077-gbeth
- renesas,rzn1-gmac
- renesas,rzv2h-gbeth
pattern: '^rx-queue-[0-7]$'
- description: Per channel transmit completion interrupt
pattern: '^tx-queue-[0-7]$'
+ - description: PPS interrupt
+ pattern: '^ptp-pps-[0-3]$'
clocks:
minItems: 1
is disabled.
In fiber mode, auto-negotiation is disabled and the PHY can only work in
100base-fx (full and half duplex) modes.
+ This property is deprecated, for details please refer to
+ Documentation/devicetree/bindings/net/ethernet-connector.yaml
+ deprecated: true
rx-internal-delay-ps:
description: |
tx-internal-delay-ps = <1>;
ti,gpio2-clk-out = "xi";
mac-termination-ohms = <43>;
+ mdi {
+ connector-0 {
+ media = "BaseF";
+ };
+ };
};
};
-
...
firmware-name:
maxItems: 1
+ deprecated: true
description:
If present, a board or platform specific string used to lookup
usecase-specific firmware files for the device.
- const: wbm2host-tx-completions-ring2
- const: wbm2host-tx-completions-ring1
- const: tcl2host-status-ring
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,ipq8074-wifi
- - qcom,ipq6018-wifi
- then:
required:
- interrupt-names
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/google,gs101-otp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google GS101 OTP Controller
+
+maintainers:
+ - Tudor Ambarus <tudor.ambarus@linaro.org>
+
+description: |
+ OTP controller drives a NVMEM memory where system or user specific data
+ can be stored. The OTP controller register space is of interest as well
+ because it contains dedicated registers where it stores the Product ID
+ and the Chip ID (apart other things like TMU or ASV info).
+
+allOf:
+ - $ref: nvmem.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: google,gs101-otp
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: pclk
+
+ interrupts:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/google,gs101.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ efuse@10000000 {
+ compatible = "google,gs101-otp";
+ reg = <0x10000000 0xf084>;
+ clocks = <&cmu_misc CLK_GOUT_MISC_OTP_CON_TOP_PCLK>;
+ clock-names = "pclk";
+ interrupts = <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>;
+ };
- enum:
- mediatek,mt8188-efuse
- mediatek,mt8189-efuse
+ - mediatek,mt8196-efuse
- const: mediatek,mt8186-efuse
- const: mediatek,mt8186-efuse
- qcom,sm8450-qfprom
- qcom,sm8550-qfprom
- qcom,sm8650-qfprom
+ - qcom,sm8750-qfprom
- qcom,x1e80100-qfprom
- const: qcom,qfprom
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/aspeed,ast2600-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED PCIe Root Complex Controller
+
+maintainers:
+ - Jacky Chou <jacky_chou@aspeedtech.com>
+
+description:
+ The ASPEED PCIe Root Complex controller provides PCI Express Root Complex
+ functionality for ASPEED SoCs, such as the AST2600 and AST2700.
+ This controller enables connectivity to PCIe endpoint devices, supporting
+ memory and I/O windows, MSI and INTx interrupts, and integration with
+ the SoC's clock, reset, and pinctrl subsystems. On AST2600, the PCIe Root
+ Port device number is always 8.
+
+properties:
+ compatible:
+ enum:
+ - aspeed,ast2600-pcie
+ - aspeed,ast2700-pcie
+
+ reg:
+ maxItems: 1
+
+ ranges:
+ minItems: 2
+ maxItems: 2
+
+ interrupts:
+ maxItems: 1
+ description: INTx and MSI interrupt
+
+ resets:
+ items:
+ - description: PCIe controller reset
+
+ reset-names:
+ items:
+ - const: h2x
+
+ aspeed,ahbc:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the ASPEED AHB Controller (AHBC) syscon node.
+ This reference is used by the PCIe controller to access
+ system-level configuration registers related to the AHB bus.
+ To enable AHB access for the PCIe controller.
+
+ aspeed,pciecfg:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the ASPEED PCIe configuration syscon node.
+ This reference allows the PCIe controller to access
+ SoC-specific PCIe configuration registers. There are the others
+ functions such PCIe RC and PCIe EP will use this common register
+ to configure the SoC interfaces.
+
+ interrupt-controller: true
+
+patternProperties:
+ "^pcie@[0-9a-f]+,0$":
+ type: object
+ $ref: /schemas/pci/pci-pci-bridge.yaml#
+
+ properties:
+ reg:
+ maxItems: 1
+
+ resets:
+ items:
+ - description: PERST# signal
+
+ reset-names:
+ items:
+ - const: perst
+
+ clocks:
+ maxItems: 1
+
+ phys:
+ maxItems: 1
+
+ required:
+ - resets
+ - reset-names
+ - clocks
+ - phys
+ - ranges
+
+ unevaluatedProperties: false
+
+allOf:
+ - $ref: /schemas/pci/pci-host-bridge.yaml#
+ - $ref: /schemas/interrupt-controller/msi-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: aspeed,ast2600-pcie
+ then:
+ required:
+ - aspeed,ahbc
+ else:
+ properties:
+ aspeed,ahbc: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: aspeed,ast2700-pcie
+ then:
+ required:
+ - aspeed,pciecfg
+ else:
+ properties:
+ aspeed,pciecfg: false
+
+required:
+ - reg
+ - interrupts
+ - bus-range
+ - ranges
+ - resets
+ - reset-names
+ - msi-controller
+ - interrupt-controller
+ - interrupt-map-mask
+ - interrupt-map
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/ast2600-clock.h>
+
+ pcie0: pcie@1e770000 {
+ compatible = "aspeed,ast2600-pcie";
+ device_type = "pci";
+ reg = <0x1e770000 0x100>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+
+ ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000
+ 0x02000000 0x0 0x60000000 0x60000000 0x0 0x20000000>;
+
+ resets = <&syscon ASPEED_RESET_H2X>;
+ reset-names = "h2x";
+
+ #interrupt-cells = <1>;
+ msi-controller;
+
+ aspeed,ahbc = <&ahbc>;
+
+ interrupt-controller;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie0 0>,
+ <0 0 0 2 &pcie0 1>,
+ <0 0 0 3 &pcie0 2>,
+ <0 0 0 4 &pcie0 3>;
+
+ pcie@8,0 {
+ compatible = "pciclass,0604";
+ reg = <0x00004000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ resets = <&syscon ASPEED_RESET_PCIE_RC_O>;
+ reset-names = "perst";
+ clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcierc1_default>;
+ phys = <&pcie_phy1>;
+ ranges;
+ };
+ };
clock-names:
minItems: 3
- maxItems: 5
+ maxItems: 6
interrupts:
minItems: 1
then:
properties:
clocks:
- maxItems: 5
+ minItems: 5
+ maxItems: 6
clock-names:
+ minItems: 5
items:
- const: pcie
- const: pcie_bus
- const: pcie_phy
- const: pcie_aux
- const: ref
+ - const: extref # Optional
unevaluatedProperties: false
minItems: 1
maxItems: 3
+ msi-parent: true
+
required:
- compatible
- reg
title: Mobiveil AXI PCIe Host Bridge
maintainers:
- - Frank Li <Frank Li@nxp.com>
+ - Frank Li <Frank.Li@nxp.com>
description:
Mobiveil's GPEX 4.0 is a PCIe Gen4 host bridge IP. This configurable IP
oneOf:
- items:
- enum:
+ - mediatek,mt7981-pcie
- mediatek,mt7986-pcie
- mediatek,mt8188-pcie
- mediatek,mt8195-pcie
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-apq8064.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm APQ8064/IPQ8064 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <mani@kernel.org>
+
+properties:
+ compatible:
+ enum:
+ - qcom,pcie-apq8064
+ - qcom,pcie-ipq8064
+ - qcom,pcie-ipq8064-v2
+
+ reg:
+ maxItems: 4
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: elbi
+ - const: parf
+ - const: config
+
+ clocks:
+ minItems: 3
+ maxItems: 5
+
+ clock-names:
+ minItems: 3
+ items:
+ - const: core # Clocks the pcie hw block
+ - const: iface # Configuration AHB clock
+ - const: phy
+ - const: aux
+ - const: ref
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ items:
+ - const: msi
+
+ resets:
+ minItems: 5
+ maxItems: 6
+
+ reset-names:
+ minItems: 5
+ items:
+ - const: axi
+ - const: ahb
+ - const: por
+ - const: pci
+ - const: phy
+ - const: ext
+
+ vdda-supply:
+ description: A phandle to the core analog power supply
+
+ vdda_phy-supply:
+ description: A phandle to the core analog power supply for PHY
+
+ vdda_refclk-supply:
+ description: A phandle to the core analog power supply for IC which generates reference clock
+
+required:
+ - resets
+ - reset-names
+ - vdda-supply
+ - vdda_phy-supply
+ - vdda_refclk-supply
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-apq8064
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+ clock-names:
+ maxItems: 3
+ resets:
+ maxItems: 5
+ reset-names:
+ maxItems: 5
+ else:
+ properties:
+ clocks:
+ minItems: 5
+ clock-names:
+ minItems: 5
+ resets:
+ minItems: 6
+ reset-names:
+ minItems: 6
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-msm8960.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/reset/qcom,gcc-msm8960.h>
+
+ pcie@1b500000 {
+ compatible = "qcom,pcie-apq8064";
+ reg = <0x1b500000 0x1000>,
+ <0x1b502000 0x80>,
+ <0x1b600000 0x100>,
+ <0x0ff00000 0x100000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */
+ <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */
+
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ clocks = <&gcc PCIE_A_CLK>,
+ <&gcc PCIE_H_CLK>,
+ <&gcc PCIE_PHY_REF_CLK>;
+ clock-names = "core", "iface", "phy";
+
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ resets = <&gcc PCIE_ACLK_RESET>,
+ <&gcc PCIE_HCLK_RESET>,
+ <&gcc PCIE_POR_RESET>,
+ <&gcc PCIE_PCI_RESET>,
+ <&gcc PCIE_PHY_RESET>;
+ reset-names = "axi", "ahb", "por", "pci", "phy";
+
+ perst-gpios = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>;
+ vdda-supply = <&pm8921_s3>;
+ vdda_phy-supply = <&pm8921_lvs6>;
+ vdda_refclk-supply = <&v3p3_fixed>;
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-apq8084.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm APQ8084 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <mani@kernel.org>
+
+properties:
+ compatible:
+ enum:
+ - qcom,pcie-apq8084
+
+ reg:
+ minItems: 4
+ maxItems: 5
+
+ reg-names:
+ minItems: 4
+ items:
+ - const: parf
+ - const: dbi
+ - const: elbi
+ - const: config
+ - const: mhi
+
+ clocks:
+ maxItems: 4
+
+ clock-names:
+ items:
+ - const: iface # Configuration AHB clock
+ - const: master_bus # Master AXI clock
+ - const: slave_bus # Slave AXI clock
+ - const: aux
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ items:
+ - const: msi
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: core
+
+ vdda-supply:
+ description: A phandle to the core analog power supply
+
+required:
+ - power-domains
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/gpio/gpio.h>
+ pcie@fc520000 {
+ compatible = "qcom,pcie-apq8084";
+ reg = <0xfc520000 0x2000>,
+ <0xff000000 0x1000>,
+ <0xff001000 0x1000>,
+ <0xff002000 0x2000>;
+ reg-names = "parf", "dbi", "elbi", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,
+ <0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc 324>,
+ <&gcc 325>,
+ <&gcc 327>,
+ <&gcc 323>;
+ clock-names = "iface", "master_bus", "slave_bus", "aux";
+ resets = <&gcc 81>;
+ reset-names = "core";
+ power-domains = <&gcc 1>;
+ vdda-supply = <&pma8084_l3>;
+ phys = <&pciephy0>;
+ phy-names = "pciephy";
+ perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pcie0_pins_default>;
+ pinctrl-names = "default";
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq4019.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm IPQ4019 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <mani@kernel.org>
+
+properties:
+ compatible:
+ enum:
+ - qcom,pcie-ipq4019
+
+ reg:
+ maxItems: 4
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: elbi
+ - const: parf
+ - const: config
+
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: aux
+ - const: master_bus # Master AXI clock
+ - const: slave_bus # Slave AXI clock
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ items:
+ - const: msi
+
+ resets:
+ maxItems: 12
+
+ reset-names:
+ items:
+ - const: axi_m # AXI master reset
+ - const: axi_s # AXI slave reset
+ - const: pipe
+ - const: axi_m_vmid
+ - const: axi_s_xpu
+ - const: parf
+ - const: phy
+ - const: axi_m_sticky # AXI master sticky reset
+ - const: pipe_sticky
+ - const: pwr
+ - const: ahb
+ - const: phy_ahb
+
+required:
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ pcie@40000000 {
+ compatible = "qcom,pcie-ipq4019";
+ reg = <0x40000000 0xf1d>,
+ <0x40000f20 0xa8>,
+ <0x80000 0x2000>,
+ <0x40100000 0x1000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>,
+ <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>;
+
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_PCIE_AHB_CLK>,
+ <&gcc GCC_PCIE_AXI_M_CLK>,
+ <&gcc GCC_PCIE_AXI_S_CLK>;
+ clock-names = "aux",
+ "master_bus",
+ "slave_bus";
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ resets = <&gcc PCIE_AXI_M_ARES>,
+ <&gcc PCIE_AXI_S_ARES>,
+ <&gcc PCIE_PIPE_ARES>,
+ <&gcc PCIE_AXI_M_VMIDMT_ARES>,
+ <&gcc PCIE_AXI_S_XPU_ARES>,
+ <&gcc PCIE_PARF_XPU_ARES>,
+ <&gcc PCIE_PHY_ARES>,
+ <&gcc PCIE_AXI_M_STICKY_ARES>,
+ <&gcc PCIE_PIPE_STICKY_ARES>,
+ <&gcc PCIE_PWR_ARES>,
+ <&gcc PCIE_AHB_ARES>,
+ <&gcc PCIE_PHY_AHB_ARES>;
+ reset-names = "axi_m",
+ "axi_s",
+ "pipe",
+ "axi_m_vmid",
+ "axi_s_xpu",
+ "parf",
+ "phy",
+ "axi_m_sticky",
+ "pipe_sticky",
+ "pwr",
+ "ahb",
+ "phy_ahb";
+
+ perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq5018.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm IPQ5018 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <mani@kernel.org>
+
+properties:
+ compatible:
+ enum:
+ - qcom,pcie-ipq5018
+
+ reg:
+ minItems: 5
+ maxItems: 6
+
+ reg-names:
+ minItems: 5
+ items:
+ - const: dbi
+ - const: elbi
+ - const: atu
+ - const: parf
+ - const: config
+ - const: mhi
+
+ clocks:
+ maxItems: 6
+
+ clock-names:
+ items:
+ - const: iface # PCIe to SysNOC BIU clock
+ - const: axi_m # AXI Master clock
+ - const: axi_s # AXI Slave clock
+ - const: ahb
+ - const: aux
+ - const: axi_bridge
+
+ interrupts:
+ maxItems: 9
+
+ interrupt-names:
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+ - const: global
+
+ resets:
+ maxItems: 8
+
+ reset-names:
+ items:
+ - const: pipe
+ - const: sleep
+ - const: sticky # Core sticky reset
+ - const: axi_m # AXI master reset
+ - const: axi_s # AXI slave reset
+ - const: ahb
+ - const: axi_m_sticky # AXI master sticky reset
+ - const: axi_s_sticky # AXI slave sticky reset
+
+required:
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
+
+ pcie@a0000000 {
+ compatible = "qcom,pcie-ipq5018";
+ reg = <0xa0000000 0xf1d>,
+ <0xa0000f20 0xa8>,
+ <0xa0001000 0x1000>,
+ <0x00080000 0x3000>,
+ <0xa0100000 0x1000>,
+ <0x00083000 0x1000>;
+ reg-names = "dbi",
+ "elbi",
+ "atu",
+ "parf",
+ "config",
+ "mhi";
+ ranges = <0x01000000 0 0x00000000 0xa0200000 0 0x00100000>,
+ <0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>;
+
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ /* The controller supports Gen3, but the connected PHY is Gen2-capable */
+ max-link-speed = <2>;
+
+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
+ <&gcc GCC_PCIE0_AXI_M_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_CLK>,
+ <&gcc GCC_PCIE0_AHB_CLK>,
+ <&gcc GCC_PCIE0_AUX_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>;
+ clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux",
+ "axi_bridge";
+
+ msi-map = <0x0 &v2m0 0x0 0xff8>;
+
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+ <&gcc GCC_PCIE0_SLEEP_ARES>,
+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE0_AHB_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
+ reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "axi_m_sticky",
+ "axi_s_sticky";
+
+ perst-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 16 GPIO_ACTIVE_LOW>;
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq6018.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm IPQ6018 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <mani@kernel.org>
+
+properties:
+ compatible:
+ enum:
+ - qcom,pcie-ipq6018
+ - qcom,pcie-ipq8074-gen3
+
+ reg:
+ minItems: 5
+ maxItems: 6
+
+ reg-names:
+ minItems: 5
+ items:
+ - const: dbi
+ - const: elbi
+ - const: atu
+ - const: parf
+ - const: config
+ - const: mhi
+
+ clocks:
+ maxItems: 5
+
+ clock-names:
+ items:
+ - const: iface # PCIe to SysNOC BIU clock
+ - const: axi_m # AXI Master clock
+ - const: axi_s # AXI Slave clock
+ - const: axi_bridge
+ - const: rchng
+
+ interrupts:
+ maxItems: 9
+
+ interrupt-names:
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+ - const: global
+
+ resets:
+ maxItems: 8
+
+ reset-names:
+ items:
+ - const: pipe
+ - const: sleep
+ - const: sticky # Core sticky reset
+ - const: axi_m # AXI master reset
+ - const: axi_s # AXI slave reset
+ - const: ahb
+ - const: axi_m_sticky # AXI master sticky reset
+ - const: axi_s_sticky # AXI slave sticky reset
+
+required:
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@20000000 {
+ compatible = "qcom,pcie-ipq6018";
+ reg = <0x0 0x20000000 0x0 0xf1d>,
+ <0x0 0x20000f20 0x0 0xa8>,
+ <0x0 0x20001000 0x0 0x1000>,
+ <0x0 0x80000 0x0 0x4000>,
+ <0x0 0x20100000 0x0 0x1000>;
+ reg-names = "dbi", "elbi", "atu", "parf", "config";
+ ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
+ <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
+
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ max-link-speed = <3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
+ <&gcc GCC_PCIE0_AXI_M_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
+ <&gcc PCIE0_RCHNG_CLK>;
+ clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng";
+
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ phys = <&pcie_phy>;
+ phy-names = "pciephy";
+
+ resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+ <&gcc GCC_PCIE0_SLEEP_ARES>,
+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE0_AHB_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
+ reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "axi_m_sticky",
+ "axi_s_sticky";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq8074.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm IPQ8074 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <mani@kernel.org>
+
+properties:
+ compatible:
+ enum:
+ - qcom,pcie-ipq8074
+
+ reg:
+ maxItems: 4
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: elbi
+ - const: parf
+ - const: config
+
+ clocks:
+ maxItems: 5
+
+ clock-names:
+ items:
+ - const: iface # PCIe to SysNOC BIU clock
+ - const: axi_m # AXI Master clock
+ - const: axi_s # AXI Slave clock
+ - const: ahb
+ - const: aux
+
+ interrupts:
+ maxItems: 9
+
+ interrupt-names:
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+ - const: global
+
+ resets:
+ maxItems: 7
+
+ reset-names:
+ items:
+ - const: pipe
+ - const: sleep
+ - const: sticky # Core sticky reset
+ - const: axi_m # AXI master reset
+ - const: axi_s # AXI slave reset
+ - const: ahb
+ - const: axi_m_sticky # AXI master sticky reset
+
+required:
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ pcie@10000000 {
+ compatible = "qcom,pcie-ipq8074";
+ reg = <0x10000000 0xf1d>,
+ <0x10000f20 0xa8>,
+ <0x00088000 0x2000>,
+ <0x10100000 0x1000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
+ <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
+
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ max-link-speed = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
+ <&gcc GCC_PCIE1_AXI_M_CLK>,
+ <&gcc GCC_PCIE1_AXI_S_CLK>,
+ <&gcc GCC_PCIE1_AHB_CLK>,
+ <&gcc GCC_PCIE1_AUX_CLK>;
+ clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux";
+
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ phys = <&pcie_qmp1>;
+ phy-names = "pciephy";
+
+ resets = <&gcc GCC_PCIE1_PIPE_ARES>,
+ <&gcc GCC_PCIE1_SLEEP_ARES>,
+ <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE1_AHB_ARES>,
+ <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
+ reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "axi_m_sticky";
+
+ perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq9574.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm IPQ9574 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <mani@kernel.org>
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - qcom,pcie-ipq9574
+ - items:
+ - enum:
+ - qcom,pcie-ipq5332
+ - qcom,pcie-ipq5424
+ - const: qcom,pcie-ipq9574
+
+ reg:
+ maxItems: 6
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: elbi
+ - const: atu
+ - const: parf
+ - const: config
+ - const: mhi
+
+ clocks:
+ maxItems: 6
+
+ clock-names:
+ items:
+ - const: axi_m # AXI Master clock
+ - const: axi_s # AXI Slave clock
+ - const: axi_bridge
+ - const: rchng
+ - const: ahb
+ - const: aux
+
+ interrupts:
+ minItems: 8
+ maxItems: 9
+
+ interrupt-names:
+ minItems: 8
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+ - const: global
+
+ resets:
+ maxItems: 8
+
+ reset-names:
+ items:
+ - const: pipe
+ - const: sticky # Core sticky reset
+ - const: axi_s_sticky # AXI Slave Sticky reset
+ - const: axi_s # AXI slave reset
+ - const: axi_m_sticky # AXI Master Sticky reset
+ - const: axi_m # AXI master reset
+ - const: aux
+ - const: ahb
+
+required:
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interconnect/qcom,ipq9574.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
+
+ pcie@10000000 {
+ compatible = "qcom,pcie-ipq9574";
+ reg = <0x10000000 0xf1d>,
+ <0x10000f20 0xa8>,
+ <0x10001000 0x1000>,
+ <0x000f8000 0x4000>,
+ <0x10100000 0x1000>,
+ <0x000fe000 0x1000>;
+ reg-names = "dbi",
+ "elbi",
+ "atu",
+ "parf",
+ "config",
+ "mhi";
+ ranges = <0x01000000 0x0 0x00000000 0x10200000 0x0 0x100000>,
+ <0x02000000 0x0 0x10300000 0x10300000 0x0 0x7d00000>;
+
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
+ <&gcc GCC_PCIE1_AXI_S_CLK>,
+ <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE1_RCHNG_CLK>,
+ <&gcc GCC_PCIE1_AHB_CLK>,
+ <&gcc GCC_PCIE1_AUX_CLK>;
+ clock-names = "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng",
+ "ahb",
+ "aux";
+
+ interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>,
+ <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+
+ resets = <&gcc GCC_PCIE1_PIPE_ARES>,
+ <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE1_AXI_S_STICKY_ARES>,
+ <&gcc GCC_PCIE1_AXI_S_ARES>,
+ <&gcc GCC_PCIE1_AXI_M_STICKY_ARES>,
+ <&gcc GCC_PCIE1_AXI_M_ARES>,
+ <&gcc GCC_PCIE1_AUX_ARES>,
+ <&gcc GCC_PCIE1_AHB_ARES>;
+ reset-names = "pipe",
+ "sticky",
+ "axi_s_sticky",
+ "axi_s",
+ "axi_m_sticky",
+ "axi_m",
+ "aux",
+ "ahb";
+
+ phys = <&pcie1_phy>;
+ phy-names = "pciephy";
+
+ perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-msm8996.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm MSM8996 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <mani@kernel.org>
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - qcom,pcie-msm8996
+ - items:
+ - const: qcom,pcie-msm8998
+ - const: qcom,pcie-msm8996
+
+ reg:
+ minItems: 4
+ maxItems: 5
+
+ reg-names:
+ minItems: 4
+ items:
+ - const: parf
+ - const: dbi
+ - const: elbi
+ - const: config
+ - const: mhi
+
+ clocks:
+ maxItems: 5
+
+ clock-names:
+ items:
+ - const: pipe # Pipe Clock driving internal logic
+ - const: aux
+ - const: cfg
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+
+ interrupts:
+ minItems: 8
+ maxItems: 9
+
+ interrupt-names:
+ minItems: 8
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+ - const: global
+
+ vdda-supply:
+ description: A phandle to the core analog power supply
+
+ vddpe-3v3-supply:
+ description: A phandle to the PCIe endpoint power supply
+
+required:
+ - power-domains
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-msm8996.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ pcie@600000 {
+ compatible = "qcom,pcie-msm8996";
+ reg = <0x00600000 0x2000>,
+ <0x0c000000 0xf1d>,
+ <0x0c000f20 0xa8>,
+ <0x0c100000 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "config";
+ ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
+ <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
+
+ device_type = "pci";
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ linux,pci-domain = <0>;
+
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+ <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
+ clock-names = "pipe",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave";
+
+ interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pcie0_state_on>;
+ pinctrl-1 = <&pcie0_state_off>;
+
+ phys = <&pciephy_0>;
+ phy-names = "pciephy";
+
+ power-domains = <&gcc PCIE0_GDSC>;
+
+ perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+ vddpe-3v3-supply = <&wlan_en>;
+ vdda-supply = <&vreg_l28a_0p925>;
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-qcs404.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QCS404 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <mani@kernel.org>
+
+properties:
+ compatible:
+ enum:
+ - qcom,pcie-qcs404
+
+ reg:
+ maxItems: 4
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: elbi
+ - const: parf
+ - const: config
+
+ clocks:
+ maxItems: 4
+
+ clock-names:
+ items:
+ - const: iface # AHB clock
+ - const: aux
+ - const: master_bus # AXI Master clock
+ - const: slave_bus # AXI Slave clock
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ items:
+ - const: msi
+
+ resets:
+ maxItems: 6
+
+ reset-names:
+ items:
+ - const: axi_m # AXI Master reset
+ - const: axi_s # AXI Slave reset
+ - const: axi_m_sticky # AXI Master Sticky reset
+ - const: pipe_sticky
+ - const: pwr
+ - const: ahb
+
+required:
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-qcs404.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ pcie@10000000 {
+ compatible = "qcom,pcie-qcs404";
+ reg = <0x10000000 0xf1d>,
+ <0x10000f20 0xa8>,
+ <0x07780000 0x2000>,
+ <0x10001000 0x2000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */
+ <0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */
+
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
+ clock-names = "iface", "aux", "master_bus", "slave_bus";
+
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ phys = <&pcie_phy>;
+ phy-names = "pciephy";
+
+ perst-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
+
+ resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>,
+ <&gcc GCC_PCIE_0_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE_0_BCR>,
+ <&gcc GCC_PCIE_0_AHB_ARES>;
+ reset-names = "axi_m",
+ "axi_s",
+ "axi_m_sticky",
+ "pipe_sticky",
+ "pwr",
+ "ahb";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+++ /dev/null
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8180x.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm SC8180x PCI Express Root Complex
-
-maintainers:
- - Bjorn Andersson <andersson@kernel.org>
- - Manivannan Sadhasivam <mani@kernel.org>
-
-description:
- Qualcomm SC8180x SoC PCIe root complex controller is based on the Synopsys
- DesignWare PCIe IP.
-
-properties:
- compatible:
- const: qcom,pcie-sc8180x
-
- reg:
- minItems: 5
- maxItems: 6
-
- reg-names:
- minItems: 5
- items:
- - const: parf # Qualcomm specific registers
- - const: dbi # DesignWare PCIe registers
- - const: elbi # External local bus interface registers
- - const: atu # ATU address space
- - const: config # PCIe configuration space
- - const: mhi # MHI registers
-
- clocks:
- minItems: 6
- maxItems: 6
-
- clock-names:
- items:
- - const: pipe # PIPE clock
- - const: aux # Auxiliary clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: slave_q2a # Slave Q2A clock
-
- interrupts:
- minItems: 8
- maxItems: 9
-
- interrupt-names:
- minItems: 8
- items:
- - const: msi0
- - const: msi1
- - const: msi2
- - const: msi3
- - const: msi4
- - const: msi5
- - const: msi6
- - const: msi7
- - const: global
-
- resets:
- maxItems: 1
-
- reset-names:
- items:
- - const: pci
-
-allOf:
- - $ref: qcom,pcie-common.yaml#
-
-unevaluatedProperties: false
-
-examples:
- - |
- #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
- #include <dt-bindings/interconnect/qcom,sc8180x.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
-
- soc {
- #address-cells = <2>;
- #size-cells = <2>;
-
- pcie@1c00000 {
- compatible = "qcom,pcie-sc8180x";
- reg = <0 0x01c00000 0 0x3000>,
- <0 0x60000000 0 0xf1d>,
- <0 0x60000f20 0 0xa8>,
- <0 0x60001000 0 0x1000>,
- <0 0x60100000 0 0x100000>;
- reg-names = "parf",
- "dbi",
- "elbi",
- "atu",
- "config";
- ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
- <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
-
- bus-range = <0x00 0xff>;
- device_type = "pci";
- linux,pci-domain = <0>;
- num-lanes = <2>;
-
- #address-cells = <3>;
- #size-cells = <2>;
-
- assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
- assigned-clock-rates = <19200000>;
-
- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
- <&gcc GCC_PCIE_0_AUX_CLK>,
- <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
- <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
- <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
- <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
- clock-names = "pipe",
- "aux",
- "cfg",
- "bus_master",
- "bus_slave",
- "slave_q2a";
-
- dma-coherent;
-
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi0",
- "msi1",
- "msi2",
- "msi3",
- "msi4",
- "msi5",
- "msi6",
- "msi7",
- "global";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
- <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
- <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
- <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
-
- interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,
- <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
- interconnect-names = "pcie-mem", "cpu-pcie";
-
- iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
- <0x100 &apps_smmu 0x1d81 0x1>;
-
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
-
- power-domains = <&gcc PCIE_0_GDSC>;
-
- resets = <&gcc GCC_PCIE_0_BCR>;
- reset-names = "pci";
- };
- };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-sdm845.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SDM845 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <mani@kernel.org>
+
+properties:
+ compatible:
+ enum:
+ - qcom,pcie-sdm845
+
+ reg:
+ minItems: 4
+ maxItems: 5
+
+ reg-names:
+ minItems: 4
+ items:
+ - const: parf
+ - const: dbi
+ - const: elbi
+ - const: config
+ - const: mhi
+
+ clocks:
+ minItems: 7
+ maxItems: 8
+
+ clock-names:
+ minItems: 7
+ items:
+ - const: pipe
+ - const: aux
+ - const: cfg
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a
+ - enum: [ ref, tbu ]
+ - const: tbu
+
+ interrupts:
+ minItems: 8
+ maxItems: 9
+
+ interrupt-names:
+ minItems: 8
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+ - const: global
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: pci
+
+required:
+ - power-domains
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@1c00000 {
+ compatible = "qcom,pcie-sdm845";
+ reg = <0x0 0x01c00000 0x0 0x2000>,
+ <0x0 0x60000000 0x0 0xf1d>,
+ <0x0 0x60000f20 0x0 0xa8>,
+ <0x0 0x60100000 0x0 0x100000>,
+ <0x0 0x01c07000 0x0 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "config", "mhi";
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
+
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+ <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+ clock-names = "pipe",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "tbu";
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
+ <0x100 &apps_smmu 0x1c11 0x1>,
+ <0x200 &apps_smmu 0x1c12 0x1>,
+ <0x300 &apps_smmu 0x1c13 0x1>,
+ <0x400 &apps_smmu 0x1c14 0x1>,
+ <0x500 &apps_smmu 0x1c15 0x1>,
+ <0x600 &apps_smmu 0x1c16 0x1>,
+ <0x700 &apps_smmu 0x1c17 0x1>,
+ <0x800 &apps_smmu 0x1c18 0x1>,
+ <0x900 &apps_smmu 0x1c19 0x1>,
+ <0xa00 &apps_smmu 0x1c1a 0x1>,
+ <0xb00 &apps_smmu 0x1c1b 0x1>,
+ <0xc00 &apps_smmu 0x1c1c 0x1>,
+ <0xd00 &apps_smmu 0x1c1d 0x1>,
+ <0xe00 &apps_smmu 0x1c1e 0x1>,
+ <0xf00 &apps_smmu 0x1c1f 0x1>;
+
+ power-domains = <&gcc PCIE_0_GDSC>;
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+
+ perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 134 GPIO_ACTIVE_HIGH>;
+
+ vddpe-3v3-supply = <&pcie0_3p3v_dual>;
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-sdx55.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SDX55 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Manivannan Sadhasivam <mani@kernel.org>
+
+properties:
+ compatible:
+ enum:
+ - qcom,pcie-sdx55
+
+ reg:
+ minItems: 5
+ maxItems: 6
+
+ reg-names:
+ minItems: 5
+ items:
+ - const: parf
+ - const: dbi
+ - const: elbi
+ - const: atu
+ - const: config
+ - const: mhi
+
+ clocks:
+ maxItems: 7
+
+ clock-names:
+ items:
+ - const: pipe
+ - const: aux
+ - const: cfg
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a
+ - const: sleep
+
+ interrupts:
+ maxItems: 8
+
+ interrupt-names:
+ items:
+ - const: msi
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+ - const: msi8
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: pci
+
+required:
+ - power-domains
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sdx55.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ pcie@1c00000 {
+ compatible = "qcom,pcie-sdx55";
+ reg = <0x01c00000 0x3000>,
+ <0x40000000 0xf1d>,
+ <0x40000f20 0xc8>,
+ <0x40001000 0x1000>,
+ <0x40100000 0x100000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config";
+ ranges = <0x01000000 0x0 0x00000000 0x40200000 0x0 0x100000>,
+ <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>;
+
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "msi8";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_PCIE_PIPE_CLK>,
+ <&gcc GCC_PCIE_AUX_CLK>,
+ <&gcc GCC_PCIE_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_PCIE_SLEEP_CLK>;
+ clock-names = "pipe",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "sleep";
+
+ assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ iommu-map = <0x0 &apps_smmu 0x0200 0x1>,
+ <0x100 &apps_smmu 0x0201 0x1>,
+ <0x200 &apps_smmu 0x0202 0x1>,
+ <0x300 &apps_smmu 0x0203 0x1>,
+ <0x400 &apps_smmu 0x0204 0x1>;
+
+ power-domains = <&gcc PCIE_GDSC>;
+
+ phys = <&pcie_phy>;
+ phy-names = "pciephy";
+
+ resets = <&gcc GCC_PCIE_BCR>;
+ reset-names = "pci";
+
+ perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>;
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
properties:
compatible:
oneOf:
+ - const: qcom,pcie-sc8180x
- const: qcom,pcie-sm8150
- items:
- enum:
properties:
compatible:
- const: qcom,pcie-x1e80100
+ oneOf:
+ - const: qcom,pcie-x1e80100
+ - items:
+ - enum:
+ - qcom,glymur-pcie
+ - const: qcom,pcie-x1e80100
reg:
minItems: 6
+++ /dev/null
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm PCI express root complex
-
-maintainers:
- - Bjorn Andersson <bjorn.andersson@linaro.org>
- - Manivannan Sadhasivam <mani@kernel.org>
-
-description: |
- Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
- PCIe IP.
-
-properties:
- compatible:
- oneOf:
- - enum:
- - qcom,pcie-apq8064
- - qcom,pcie-apq8084
- - qcom,pcie-ipq4019
- - qcom,pcie-ipq5018
- - qcom,pcie-ipq6018
- - qcom,pcie-ipq8064
- - qcom,pcie-ipq8064-v2
- - qcom,pcie-ipq8074
- - qcom,pcie-ipq8074-gen3
- - qcom,pcie-ipq9574
- - qcom,pcie-msm8996
- - qcom,pcie-qcs404
- - qcom,pcie-sdm845
- - qcom,pcie-sdx55
- - items:
- - enum:
- - qcom,pcie-ipq5332
- - qcom,pcie-ipq5424
- - const: qcom,pcie-ipq9574
- - items:
- - const: qcom,pcie-msm8998
- - const: qcom,pcie-msm8996
-
- reg:
- minItems: 4
- maxItems: 6
-
- reg-names:
- minItems: 4
- maxItems: 6
-
- interrupts:
- minItems: 1
- maxItems: 9
-
- interrupt-names:
- minItems: 1
- maxItems: 9
-
- iommu-map:
- minItems: 1
- maxItems: 16
-
- # Common definitions for clocks, clock-names and reset.
- # Platform constraints are described later.
- clocks:
- minItems: 3
- maxItems: 13
-
- clock-names:
- minItems: 3
- maxItems: 13
-
- dma-coherent: true
-
- interconnects:
- maxItems: 2
-
- interconnect-names:
- items:
- - const: pcie-mem
- - const: cpu-pcie
-
- resets:
- minItems: 1
- maxItems: 12
-
- reset-names:
- minItems: 1
- maxItems: 12
-
- vdda-supply:
- description: A phandle to the core analog power supply
-
- vdda_phy-supply:
- description: A phandle to the core analog power supply for PHY
-
- vdda_refclk-supply:
- description: A phandle to the core analog power supply for IC which generates reference clock
-
- vddpe-3v3-supply:
- description: A phandle to the PCIe endpoint power supply
-
- phys:
- maxItems: 1
-
- phy-names:
- items:
- - const: pciephy
-
- power-domains:
- maxItems: 1
-
- perst-gpios:
- description: GPIO controlled connection to PERST# signal
- maxItems: 1
-
- required-opps:
- maxItems: 1
-
- wake-gpios:
- description: GPIO controlled connection to WAKE# signal
- maxItems: 1
-
-required:
- - compatible
- - reg
- - reg-names
- - interrupt-map-mask
- - interrupt-map
- - clocks
- - clock-names
-
-anyOf:
- - required:
- - interrupts
- - interrupt-names
- - "#interrupt-cells"
- - required:
- - msi-map
-
-allOf:
- - $ref: /schemas/pci/pci-host-bridge.yaml#
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-apq8064
- - qcom,pcie-ipq4019
- - qcom,pcie-ipq8064
- - qcom,pcie-ipq8064v2
- - qcom,pcie-ipq8074
- - qcom,pcie-qcs404
- then:
- properties:
- reg:
- minItems: 4
- maxItems: 4
- reg-names:
- items:
- - const: dbi # DesignWare PCIe registers
- - const: elbi # External local bus interface registers
- - const: parf # Qualcomm specific registers
- - const: config # PCIe configuration space
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-ipq5018
- - qcom,pcie-ipq6018
- - qcom,pcie-ipq8074-gen3
- - qcom,pcie-ipq9574
- then:
- properties:
- reg:
- minItems: 5
- maxItems: 6
- reg-names:
- minItems: 5
- items:
- - const: dbi # DesignWare PCIe registers
- - const: elbi # External local bus interface registers
- - const: atu # ATU address space
- - const: parf # Qualcomm specific registers
- - const: config # PCIe configuration space
- - const: mhi # MHI registers
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-apq8084
- - qcom,pcie-msm8996
- - qcom,pcie-sdm845
- then:
- properties:
- reg:
- minItems: 4
- maxItems: 5
- reg-names:
- minItems: 4
- items:
- - const: parf # Qualcomm specific registers
- - const: dbi # DesignWare PCIe registers
- - const: elbi # External local bus interface registers
- - const: config # PCIe configuration space
- - const: mhi # MHI registers
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-sdx55
- then:
- properties:
- reg:
- minItems: 5
- maxItems: 6
- reg-names:
- minItems: 5
- items:
- - const: parf # Qualcomm specific registers
- - const: dbi # DesignWare PCIe registers
- - const: elbi # External local bus interface registers
- - const: atu # ATU address space
- - const: config # PCIe configuration space
- - const: mhi # MHI registers
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-apq8064
- - qcom,pcie-ipq8064
- - qcom,pcie-ipq8064v2
- then:
- properties:
- clocks:
- minItems: 3
- maxItems: 5
- clock-names:
- minItems: 3
- items:
- - const: core # Clocks the pcie hw block
- - const: iface # Configuration AHB clock
- - const: phy # Clocks the pcie PHY block
- - const: aux # Clocks the pcie AUX block, not on apq8064
- - const: ref # Clocks the pcie ref block, not on apq8064
- resets:
- minItems: 5
- maxItems: 6
- reset-names:
- minItems: 5
- items:
- - const: axi # AXI reset
- - const: ahb # AHB reset
- - const: por # POR reset
- - const: pci # PCI reset
- - const: phy # PHY reset
- - const: ext # EXT reset, not on apq8064
- required:
- - vdda-supply
- - vdda_phy-supply
- - vdda_refclk-supply
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-apq8084
- then:
- properties:
- clocks:
- minItems: 4
- maxItems: 4
- clock-names:
- items:
- - const: iface # Configuration AHB clock
- - const: master_bus # Master AXI clock
- - const: slave_bus # Slave AXI clock
- - const: aux # Auxiliary (AUX) clock
- resets:
- maxItems: 1
- reset-names:
- items:
- - const: core # Core reset
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-ipq4019
- then:
- properties:
- clocks:
- minItems: 3
- maxItems: 3
- clock-names:
- items:
- - const: aux # Auxiliary (AUX) clock
- - const: master_bus # Master AXI clock
- - const: slave_bus # Slave AXI clock
- resets:
- minItems: 12
- maxItems: 12
- reset-names:
- items:
- - const: axi_m # AXI master reset
- - const: axi_s # AXI slave reset
- - const: pipe # PIPE reset
- - const: axi_m_vmid # VMID reset
- - const: axi_s_xpu # XPU reset
- - const: parf # PARF reset
- - const: phy # PHY reset
- - const: axi_m_sticky # AXI sticky reset
- - const: pipe_sticky # PIPE sticky reset
- - const: pwr # PWR reset
- - const: ahb # AHB reset
- - const: phy_ahb # PHY AHB reset
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-ipq5018
- then:
- properties:
- clocks:
- minItems: 6
- maxItems: 6
- clock-names:
- items:
- - const: iface # PCIe to SysNOC BIU clock
- - const: axi_m # AXI Master clock
- - const: axi_s # AXI Slave clock
- - const: ahb # AHB clock
- - const: aux # Auxiliary clock
- - const: axi_bridge # AXI bridge clock
- resets:
- minItems: 8
- maxItems: 8
- reset-names:
- items:
- - const: pipe # PIPE reset
- - const: sleep # Sleep reset
- - const: sticky # Core sticky reset
- - const: axi_m # AXI master reset
- - const: axi_s # AXI slave reset
- - const: ahb # AHB reset
- - const: axi_m_sticky # AXI master sticky reset
- - const: axi_s_sticky # AXI slave sticky reset
- interrupts:
- minItems: 9
- maxItems: 9
- interrupt-names:
- items:
- - const: msi0
- - const: msi1
- - const: msi2
- - const: msi3
- - const: msi4
- - const: msi5
- - const: msi6
- - const: msi7
- - const: global
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-msm8996
- then:
- properties:
- clocks:
- minItems: 5
- maxItems: 5
- clock-names:
- items:
- - const: pipe # Pipe Clock driving internal logic
- - const: aux # Auxiliary (AUX) clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- resets: false
- reset-names: false
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-ipq8074
- then:
- properties:
- clocks:
- minItems: 5
- maxItems: 5
- clock-names:
- items:
- - const: iface # PCIe to SysNOC BIU clock
- - const: axi_m # AXI Master clock
- - const: axi_s # AXI Slave clock
- - const: ahb # AHB clock
- - const: aux # Auxiliary clock
- resets:
- minItems: 7
- maxItems: 7
- reset-names:
- items:
- - const: pipe # PIPE reset
- - const: sleep # Sleep reset
- - const: sticky # Core Sticky reset
- - const: axi_m # AXI Master reset
- - const: axi_s # AXI Slave reset
- - const: ahb # AHB Reset
- - const: axi_m_sticky # AXI Master Sticky reset
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-ipq6018
- - qcom,pcie-ipq8074-gen3
- then:
- properties:
- clocks:
- minItems: 5
- maxItems: 5
- clock-names:
- items:
- - const: iface # PCIe to SysNOC BIU clock
- - const: axi_m # AXI Master clock
- - const: axi_s # AXI Slave clock
- - const: axi_bridge # AXI bridge clock
- - const: rchng
- resets:
- minItems: 8
- maxItems: 8
- reset-names:
- items:
- - const: pipe # PIPE reset
- - const: sleep # Sleep reset
- - const: sticky # Core Sticky reset
- - const: axi_m # AXI Master reset
- - const: axi_s # AXI Slave reset
- - const: ahb # AHB Reset
- - const: axi_m_sticky # AXI Master Sticky reset
- - const: axi_s_sticky # AXI Slave Sticky reset
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-ipq9574
- then:
- properties:
- clocks:
- minItems: 6
- maxItems: 6
- clock-names:
- items:
- - const: axi_m # AXI Master clock
- - const: axi_s # AXI Slave clock
- - const: axi_bridge
- - const: rchng
- - const: ahb
- - const: aux
-
- resets:
- minItems: 8
- maxItems: 8
- reset-names:
- items:
- - const: pipe # PIPE reset
- - const: sticky # Core Sticky reset
- - const: axi_s_sticky # AXI Slave Sticky reset
- - const: axi_s # AXI Slave reset
- - const: axi_m_sticky # AXI Master Sticky reset
- - const: axi_m # AXI Master reset
- - const: aux # AUX Reset
- - const: ahb # AHB Reset
-
- interrupts:
- minItems: 8
- interrupt-names:
- minItems: 8
- items:
- - const: msi0
- - const: msi1
- - const: msi2
- - const: msi3
- - const: msi4
- - const: msi5
- - const: msi6
- - const: msi7
- - const: global
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-qcs404
- then:
- properties:
- clocks:
- minItems: 4
- maxItems: 4
- clock-names:
- items:
- - const: iface # AHB clock
- - const: aux # Auxiliary clock
- - const: master_bus # AXI Master clock
- - const: slave_bus # AXI Slave clock
- resets:
- minItems: 6
- maxItems: 6
- reset-names:
- items:
- - const: axi_m # AXI Master reset
- - const: axi_s # AXI Slave reset
- - const: axi_m_sticky # AXI Master Sticky reset
- - const: pipe_sticky # PIPE sticky reset
- - const: pwr # PWR reset
- - const: ahb # AHB reset
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-sdm845
- then:
- oneOf:
- # Unfortunately the "optional" ref clock is used in the middle of the list
- - properties:
- clocks:
- minItems: 8
- maxItems: 8
- clock-names:
- items:
- - const: pipe # PIPE clock
- - const: aux # Auxiliary clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: slave_q2a # Slave Q2A clock
- - const: ref # REFERENCE clock
- - const: tbu # PCIe TBU clock
- - properties:
- clocks:
- minItems: 7
- maxItems: 7
- clock-names:
- items:
- - const: pipe # PIPE clock
- - const: aux # Auxiliary clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: slave_q2a # Slave Q2A clock
- - const: tbu # PCIe TBU clock
- properties:
- resets:
- maxItems: 1
- reset-names:
- items:
- - const: pci # PCIe core reset
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-sdx55
- then:
- properties:
- clocks:
- minItems: 7
- maxItems: 7
- clock-names:
- items:
- - const: pipe # PIPE clock
- - const: aux # Auxiliary clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: slave_q2a # Slave Q2A clock
- - const: sleep # PCIe Sleep clock
- resets:
- maxItems: 1
- reset-names:
- items:
- - const: pci # PCIe core reset
-
- - if:
- not:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-apq8064
- - qcom,pcie-ipq4019
- - qcom,pcie-ipq5018
- - qcom,pcie-ipq8064
- - qcom,pcie-ipq8064v2
- - qcom,pcie-ipq8074
- - qcom,pcie-ipq8074-gen3
- - qcom,pcie-ipq9574
- - qcom,pcie-qcs404
- then:
- required:
- - power-domains
-
- - if:
- not:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-msm8996
- then:
- required:
- - resets
- - reset-names
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-ipq6018
- - qcom,pcie-ipq8074
- - qcom,pcie-ipq8074-gen3
- - qcom,pcie-msm8996
- - qcom,pcie-msm8998
- - qcom,pcie-sdm845
- then:
- oneOf:
- - properties:
- interrupts:
- maxItems: 1
- interrupt-names:
- items:
- - const: msi
- - properties:
- interrupts:
- minItems: 8
- maxItems: 9
- interrupt-names:
- minItems: 8
- items:
- - const: msi0
- - const: msi1
- - const: msi2
- - const: msi3
- - const: msi4
- - const: msi5
- - const: msi6
- - const: msi7
- - const: global
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-apq8064
- - qcom,pcie-apq8084
- - qcom,pcie-ipq4019
- - qcom,pcie-ipq8064
- - qcom,pcie-ipq8064-v2
- - qcom,pcie-qcs404
- then:
- properties:
- interrupts:
- maxItems: 1
- interrupt-names:
- items:
- - const: msi
-
-unevaluatedProperties: false
-
-examples:
- - |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- pcie@1b500000 {
- compatible = "qcom,pcie-ipq8064";
- reg = <0x1b500000 0x1000>,
- <0x1b502000 0x80>,
- <0x1b600000 0x100>,
- <0x0ff00000 0x100000>;
- reg-names = "dbi", "elbi", "parf", "config";
- device_type = "pci";
- linux,pci-domain = <0>;
- bus-range = <0x00 0xff>;
- num-lanes = <1>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,
- <0x82000000 0 0 0x08000000 0 0x07e00000>;
- interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc 41>,
- <&gcc 43>,
- <&gcc 44>,
- <&gcc 42>,
- <&gcc 248>;
- clock-names = "core", "iface", "phy", "aux", "ref";
- resets = <&gcc 27>,
- <&gcc 26>,
- <&gcc 25>,
- <&gcc 24>,
- <&gcc 23>,
- <&gcc 22>;
- reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
- pinctrl-0 = <&pcie_pins_default>;
- pinctrl-names = "default";
- vdda-supply = <&pm8921_s3>;
- vdda_phy-supply = <&pm8921_lvs6>;
- vdda_refclk-supply = <&ext_3p3v>;
- };
- - |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/gpio/gpio.h>
- pcie@fc520000 {
- compatible = "qcom,pcie-apq8084";
- reg = <0xfc520000 0x2000>,
- <0xff000000 0x1000>,
- <0xff001000 0x1000>,
- <0xff002000 0x2000>;
- reg-names = "parf", "dbi", "elbi", "config";
- device_type = "pci";
- linux,pci-domain = <0>;
- bus-range = <0x00 0xff>;
- num-lanes = <1>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,
- <0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
- interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc 324>,
- <&gcc 325>,
- <&gcc 327>,
- <&gcc 323>;
- clock-names = "iface", "master_bus", "slave_bus", "aux";
- resets = <&gcc 81>;
- reset-names = "core";
- power-domains = <&gcc 1>;
- vdda-supply = <&pma8084_l3>;
- phys = <&pciephy0>;
- phy-names = "pciephy";
- perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
- pinctrl-0 = <&pcie0_pins_default>;
- pinctrl-names = "default";
- };
-...
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,sa8255p-pcie-ep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm firmware managed PCIe Endpoint Controller
+
+description:
+ Qualcomm SA8255p SoC PCIe endpoint controller is based on the Synopsys
+ DesignWare PCIe IP which is managed by firmware.
+
+maintainers:
+ - Manivannan Sadhasivam <mani@kernel.org>
+
+properties:
+ compatible:
+ const: qcom,sa8255p-pcie-ep
+
+ reg:
+ items:
+ - description: Qualcomm-specific PARF configuration registers
+ - description: DesignWare PCIe registers
+ - description: External local bus interface registers
+ - description: Address Translation Unit (ATU) registers
+ - description: Memory region used to map remote RC address space
+ - description: BAR memory region
+ - description: DMA register space
+
+ reg-names:
+ items:
+ - const: parf
+ - const: dbi
+ - const: elbi
+ - const: atu
+ - const: addr_space
+ - const: mmio
+ - const: dma
+
+ interrupts:
+ items:
+ - description: PCIe Global interrupt
+ - description: PCIe Doorbell interrupt
+ - description: DMA interrupt
+
+ interrupt-names:
+ items:
+ - const: global
+ - const: doorbell
+ - const: dma
+
+ iommus:
+ maxItems: 1
+
+ reset-gpios:
+ description: GPIO used as PERST# input signal
+ maxItems: 1
+
+ wake-gpios:
+ description: GPIO used as WAKE# output signal
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ dma-coherent: true
+
+ num-lanes:
+ default: 2
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+ - reset-gpios
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ pcie1_ep: pcie-ep@1c10000 {
+ compatible = "qcom,sa8255p-pcie-ep";
+ reg = <0x0 0x01c10000 0x0 0x3000>,
+ <0x0 0x60000000 0x0 0xf20>,
+ <0x0 0x60000f20 0x0 0xa8>,
+ <0x0 0x60001000 0x0 0x4000>,
+ <0x0 0x60200000 0x0 0x100000>,
+ <0x0 0x01c13000 0x0 0x1000>,
+ <0x0 0x60005000 0x0 0x2000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "addr_space", "mmio", "dma";
+ interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global", "doorbell", "dma";
+ reset-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
+ dma-coherent;
+ iommus = <&pcie_smmu 0x80 0x7f>;
+ power-domains = <&scmi6_pd 1>;
+ num-lanes = <4>;
+ };
+ };
define it with this name (for instance pipe, core and aux can
be connected to a single source of the periodic signal).
const: ref
+ - description:
+ Some dwc wrappers (like i.MX95 PCIes) have two reference clock
+ inputs, one from an internal PLL, the other from an off-chip crystal
+ oscillator. If present, 'extref' refers to a reference clock from
+ an external oscillator.
+ const: extref
- description:
Clock for the PHY registers interface. Originally this is
a PHY-viewport-based interface, but some platform may have
phy-names:
const: pcie-phy
- interrupt-controller:
+ legacy-interrupt-controller:
type: object
additionalProperties: false
<0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>;
- pcie_intc: interrupt-controller {
+ pcie_intc: legacy-interrupt-controller {
#address-cells = <0>;
interrupt-controller;
#interrupt-cells = <1>;
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/apple,atcphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Apple Type-C PHY (ATCPHY)
+
+maintainers:
+ - Sven Peter <sven@kernel.org>
+
+description: >
+ The Apple Type-C PHY (ATCPHY) is a combined PHY for USB 2.0, USB 3.x,
+ USB4/Thunderbolt, and DisplayPort connectivity via Type-C ports found in
+ Apple Silicon SoCs.
+
+ The PHY handles muxing between these different protocols and also provides the
+ reset controller for the attached DWC3 USB controller.
+
+ It is designed for USB4 operation and does not handle individual differential
+ pairs as distinct DisplayPort lanes. Any reference to lane in this binding
+ hence refers to two differential pairs (RX and TX) as used in USB terminology.
+
+ In order to correctly setup these lanes for the various modes calibration
+ values copied from Apple's firmware and converted to the format described
+ below by our bootloader m1n1 are required. Without these only USB2 operation
+ is possible.
+
+allOf:
+ - $ref: /schemas/usb/usb-switch.yaml#
+
+$defs:
+ apple,tunable:
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ items:
+ items:
+ - description: Register offset
+ - description: Mask to be applied to the register value
+ - description: Bits to be set after applying the mask
+ description: >
+ List of (register offset, mask, value) tuples copied from Apple's Device
+ Tree by our bootloader m1n1 and used to configure the PHY. These values
+ even vary for a single product/device and likely contain calibration
+ values determined by Apple at manufacturing time.
+ Unless otherwise noted these tunables are always applied to the core
+ register region.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - apple,t6000-atcphy
+ - apple,t6020-atcphy
+ - apple,t8112-atcphy
+ - const: apple,t8103-atcphy
+ - const: apple,t8103-atcphy
+
+ reg:
+ items:
+ - description: Common controls for all PHYs (USB2/3/4, DisplayPort, TBT)
+ - description: DisplayPort Alternate Mode PHY specific controls
+ - description: Type-C PHY AXI to Apple Fabric interconnect controls
+ - description: USB2 PHY specific controls
+ - description: USB3 PIPE interface controls
+
+ reg-names:
+ items:
+ - const: core
+ - const: lpdptx
+ - const: axi2af
+ - const: usb2phy
+ - const: pipehandler
+
+ "#phy-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 0
+
+ mode-switch: true
+ orientation-switch: true
+
+ power-domains:
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Outgoing connection to the SS port of the Type-C connector.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Incoming endpoint from the USB3 controller.
+
+ port@2:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Incoming endpoint from the DisplayPort controller.
+
+ port@3:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Incoming endpoint from the USB4/Thunderbolt controller.
+
+ apple,tunable-common-a:
+ $ref: "#/$defs/apple,tunable"
+ description: >
+ Common tunables required for all modes, applied before tunable-axi2af.
+
+ apple,tunable-axi2af:
+ $ref: "#/$defs/apple,tunable"
+ description: >
+ AXI to Apple Fabric tunables, required for all modes. Unlike all other
+ tunables these are applied to the axi2af region.
+
+ apple,tunable-common-b:
+ $ref: "#/$defs/apple,tunable"
+ description: >
+ Common tunables required for all modes, applied after tunable-axi2af.
+
+ apple,tunable-lane0-usb:
+ $ref: "#/$defs/apple,tunable"
+ description: USB3 tunables for lane 0.
+
+ apple,tunable-lane1-usb:
+ $ref: "#/$defs/apple,tunable"
+ description: USB3 tunables for lane 1.
+
+ apple,tunable-lane0-cio:
+ $ref: "#/$defs/apple,tunable"
+ description: USB4/Thunderbolt ("Converged IO") tunables for lane 0.
+
+ apple,tunable-lane1-cio:
+ $ref: "#/$defs/apple,tunable"
+ description: USB4/Thunderbolt ("Converged IO") tunables for lane 1.
+
+ apple,tunable-lane0-dp:
+ $ref: "#/$defs/apple,tunable"
+ description: >
+ DisplayPort tunables for lane 0.
+
+ Note that lane here refers to a USB RX and TX pair re-used for DisplayPort
+ and not to an individual DisplayPort differential lane.
+
+ apple,tunable-lane1-dp:
+ $ref: "#/$defs/apple,tunable"
+ description: >
+ DisplayPort tunables for lane 1.
+
+ Note that lane here refers to a USB RX and TX pair re-used for DisplayPort
+ and not to an individual DisplayPort differential lane.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#phy-cells"
+ - "#reset-cells"
+ - orientation-switch
+ - mode-switch
+ - power-domains
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@83000000 {
+ compatible = "apple,t8103-atcphy";
+ reg = <0x83000000 0x4c000>,
+ <0x83050000 0x8000>,
+ <0x80000000 0x4000>,
+ <0x82a90000 0x4000>,
+ <0x82a84000 0x4000>;
+ reg-names = "core", "lpdptx", "axi2af", "usb2phy",
+ "pipehandler";
+
+ #phy-cells = <1>;
+ #reset-cells = <0>;
+
+ orientation-switch;
+ mode-switch;
+ power-domains = <&ps_atc0_usb>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ endpoint {
+ remote-endpoint = <&typec_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ endpoint {
+ remote-endpoint = <&dwc3_ss_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ endpoint {
+ remote-endpoint = <&dcp_dp_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ endpoint {
+ remote-endpoint = <&acio_tbt_out>;
+ };
+ };
+ };
+ };
"#phy-cells":
const: 1
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+patternProperties:
+ "^phy@[0-7]$":
+ type: object
+ description: SerDes lane (single RX/TX differential pair)
+
+ properties:
+ reg:
+ minimum: 0
+ maximum: 7
+ description: Lane index as seen in register map
+
+ "#phy-cells":
+ const: 0
+
+ required:
+ - reg
+ - "#phy-cells"
+
+ additionalProperties: false
+
required:
- compatible
- reg
soc {
#address-cells = <2>;
#size-cells = <2>;
- serdes_1: phy@1ea0000 {
+
+ serdes@1ea0000 {
compatible = "fsl,lynx-28g";
reg = <0x0 0x1ea0000 0x0 0x1e30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
#phy-cells = <1>;
+
+ phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+
+ phy@4 {
+ reg = <4>;
+ #phy-cells = <0>;
+ };
+
+ phy@5 {
+ reg = <5>;
+ #phy-cells = <0>;
+ };
+
+ phy@6 {
+ reg = <6>;
+ #phy-cells = <0>;
+ };
+
+ phy@7 {
+ reg = <7>;
+ #phy-cells = <0>;
+ };
};
};
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2025, Google LLC
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/google,lga-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google Tensor Series G5 (Laguna) USB PHY
+
+maintainers:
+ - Roy Luo <royluo@google.com>
+
+description:
+ Describes the USB PHY interfaces integrated with the DWC3 USB controller on
+ Google Tensor SoCs, starting with the G5 generation (laguna).
+ Two specific PHY IPs from Synopsys are integrated, including eUSB 2.0 PHY IP
+ and USB3.2/DisplayPort combo PHY IP.
+
+properties:
+ compatible:
+ const: google,lga-usb-phy
+
+ reg:
+ items:
+ - description: USB3.2/DisplayPort combo PHY core registers.
+ - description: USB3.2/DisplayPort combo PHY Type-C Assist registers.
+ - description: eUSB 2.0 PHY core registers.
+ - description: Top-level wrapper registers for the integrated PHYs.
+
+ reg-names:
+ items:
+ - const: usb3_core
+ - const: usb3_tca
+ - const: usb2_core
+ - const: usbdp_top
+
+ "#phy-cells":
+ description: |
+ The phandle's argument in the PHY specifier selects one of the three
+ following PHY interfaces.
+ - 0 for USB high-speed.
+ - 1 for USB super-speed.
+ - 2 for DisplayPort.
+ const: 1
+
+ clocks:
+ items:
+ - description: USB2 PHY clock.
+ - description: USB2 PHY APB clock.
+ - description: USB3.2/DisplayPort combo PHY clock.
+ - description: USB3.2/DisplayPort combo PHY firmware clock.
+
+ clock-names:
+ items:
+ - const: usb2
+ - const: usb2_apb
+ - const: usb3
+ - const: usb3_fw
+
+ resets:
+ items:
+ - description: USB2 PHY reset.
+ - description: USB2 PHY APB reset.
+ - description: USB3.2/DisplayPort combo PHY reset.
+
+ reset-names:
+ items:
+ - const: usb2
+ - const: usb2_apb
+ - const: usb3
+
+ power-domains:
+ maxItems: 1
+
+ orientation-switch:
+ type: boolean
+ description:
+ Indicates the PHY as a handler of USB Type-C orientation changes
+
+ google,usb-cfg-csr:
+ description:
+ A phandle to a syscon node used to access the USB configuration
+ registers. These registers are the top-level wrapper of the USB
+ subsystem and provide control and status for the integrated USB
+ controller and USB PHY.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to the syscon node.
+ - description: USB2 PHY configuration register offset.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#phy-cells"
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - power-domains
+ - orientation-switch
+ - google,usb-cfg-csr
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ usb-phy@c410000 {
+ compatible = "google,lga-usb-phy";
+ reg = <0 0x0c410000 0 0x20000>,
+ <0 0x0c430000 0 0x1000>,
+ <0 0x0c440000 0 0x10000>,
+ <0 0x0c637000 0 0xa0>;
+ reg-names = "usb3_core", "usb3_tca", "usb2_core", "usbdp_top";
+ #phy-cells = <1>;
+ clocks = <&hsion_usb2_phy_clk>, <&hsion_u2phy_apb_clk>,
+ <&hsion_usb3_phy_clk>, <&hsion_usb3_phy_fw_clk>;
+ clock-names = "usb2", "usb2_apb", "usb3", "usb3_fw";
+ resets = <&hsion_resets_usb2_phy>,
+ <&hsion_resets_u2phy_apb>,
+ <&hsion_resets_usb3_phy>;
+ reset-names = "usb2", "usb2_apb", "usb3";
+ power-domains = <&hsio_n_usb_pd>;
+ orientation-switch;
+ google,usb-cfg-csr = <&usb_cfg_csr 0x14>;
+ };
+ };
+...
- enum:
- mediatek,mt7623-hdmi-phy
- const: mediatek,mt2701-hdmi-phy
+ - items:
+ - enum:
+ - mediatek,mt8188-hdmi-phy
+ - const: mediatek,mt8195-hdmi-phy
- const: mediatek,mt2701-hdmi-phy
- const: mediatek,mt8173-hdmi-phy
- const: mediatek,mt8195-hdmi-phy
maxItems: 1
clocks:
+ minItems: 1
items:
- description: PLL reference clock
+ - description: HDMI 26MHz clock
+ - description: HDMI PLL1 clock
+ - description: HDMI PLL2 clock
clock-names:
+ minItems: 1
items:
- const: pll_ref
+ - const: 26m
+ - const: pll1
+ - const: pll2
clock-output-names:
- items:
- - const: hdmitx_dig_cts
+ maxItems: 1
"#phy-cells":
const: 0
- "#phy-cells"
- "#clock-cells"
+allOf:
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8195-hdmi-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+ clock-names:
+ maxItems: 1
+
additionalProperties: false
examples:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/phy-common-props.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Common PHY and network PCS properties
+
+description:
+ Common PHY and network PCS properties, such as peak-to-peak transmit
+ amplitude.
+
+maintainers:
+ - Marek Behún <kabel@kernel.org>
+
+$defs:
+ protocol-names:
+ description:
+ Names of the PHY modes. If a value of 'default' is provided, the system
+ should use it for any PHY mode that is otherwise not defined here. If
+ 'default' is not provided, the system should use manufacturer default value.
+ minItems: 1
+ maxItems: 16
+ uniqueItems: true
+ items:
+ enum:
+ - default
+
+ # ethernet modes
+ - sgmii
+ - qsgmii
+ - xgmii
+ - 1000base-x
+ - 2500base-x
+ - 5gbase-r
+ - rxaui
+ - xaui
+ - 10gbase-kr
+ - usxgmii
+ - 10gbase-r
+ - 25gbase-r
+
+ # PCIe modes
+ - pcie
+ - pcie1
+ - pcie2
+ - pcie3
+ - pcie4
+ - pcie5
+ - pcie6
+
+ # USB modes
+ - usb
+ - usb-ls
+ - usb-fs
+ - usb-hs
+ - usb-ss
+ - usb-ss+
+ - usb-4
+
+ # storage modes
+ - sata
+ - ufs-hs
+ - ufs-hs-a
+ - ufs-hs-b
+
+ # display modes
+ - lvds
+ - dp
+ - dp-rbr
+ - dp-hbr
+ - dp-hbr2
+ - dp-hbr3
+ - dp-uhbr-10
+ - dp-uhbr-13.5
+ - dp-uhbr-20
+
+ # camera modes
+ - mipi-dphy
+ - mipi-dphy-univ
+ - mipi-dphy-v2.5-univ
+
+properties:
+ tx-p2p-microvolt:
+ description:
+ Transmit amplitude voltages in microvolts, peak-to-peak. If this property
+ contains multiple values for various PHY modes, the
+ 'tx-p2p-microvolt-names' property must be provided and contain
+ corresponding mode names.
+
+ tx-p2p-microvolt-names:
+ description:
+ Names of the modes corresponding to voltages in the 'tx-p2p-microvolt'
+ property. Required only if multiple voltages are provided.
+ $ref: "#/$defs/protocol-names"
+
+ rx-polarity:
+ description:
+ An array of values indicating whether the differential receiver's
+ polarity is inverted. Each value can be one of
+ PHY_POL_NORMAL (0) which means the negative signal is decoded from the
+ RXN input, and the positive signal from the RXP input;
+ PHY_POL_INVERT (1) which means the negative signal is decoded from the
+ RXP input, and the positive signal from the RXN input;
+ PHY_POL_AUTO (2) which means the receiver performs automatic polarity
+ detection and correction, which is a mandatory part of link training for
+ some protocols (PCIe, USB SS).
+
+ The values are defined in <dt-bindings/phy/phy.h>. If the property is
+ absent, the default value is undefined.
+
+ Note that the RXP and RXN inputs refer to the block that this property is
+ under, and do not necessarily directly translate to external pins.
+
+ If this property contains multiple values for various protocols, the
+ 'rx-polarity-names' property must be provided.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 16
+ items:
+ enum: [0, 1, 2]
+
+ rx-polarity-names:
+ $ref: '#/$defs/protocol-names'
+
+ tx-polarity:
+ description:
+ Like 'rx-polarity', except it applies to differential transmitters,
+ and only the values of PHY_POL_NORMAL and PHY_POL_INVERT are possible.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 16
+ items:
+ enum: [0, 1]
+
+ tx-polarity-names:
+ $ref: '#/$defs/protocol-names'
+
+dependencies:
+ tx-p2p-microvolt-names: [ tx-p2p-microvolt ]
+ rx-polarity-names: [ rx-polarity ]
+ tx-polarity-names: [ tx-polarity ]
+
+additionalProperties: true
+
+examples:
+ - |
+ #include <dt-bindings/phy/phy.h>
+
+ phy: phy {
+ #phy-cells = <1>;
+ tx-p2p-microvolt = <915000>, <1100000>, <1200000>;
+ tx-p2p-microvolt-names = "2500base-x", "usb-hs", "usb-ss";
+ rx-polarity = <PHY_POL_AUTO>, <PHY_POL_NORMAL>;
+ rx-polarity-names = "usb-ss", "default";
+ tx-polarity = <PHY_POL_INVERT>;
+ };
compatible:
oneOf:
- enum:
+ - qcom,glymur-dp-phy
- qcom,sa8775p-edp-phy
- qcom,sc7280-edp-phy
- qcom,sc8180x-edp-phy
- description: PLL register block
clocks:
- maxItems: 2
+ minItems: 2
+ maxItems: 3
clock-names:
+ minItems: 2
items:
- const: aux
- const: cfg_ahb
+ - const: ref
"#clock-cells":
const: 1
- "#clock-cells"
- "#phy-cells"
+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,glymur-dp-phy
+ - qcom,x1e80100-dp-phy
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ minItems: 3
+ maxItems: 3
+ else:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ minItems: 2
+ maxItems: 2
+
additionalProperties: false
examples:
properties:
compatible:
- items:
- - enum:
- - qcom,sm8750-m31-eusb2-phy
+ oneOf:
+ - items:
+ - enum:
+ - qcom,glymur-m31-eusb2-phy
+ - qcom,kaanapali-m31-eusb2-phy
+ - const: qcom,sm8750-m31-eusb2-phy
+ - const: qcom,sm8750-m31-eusb2-phy
reg:
maxItems: 1
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,qcs615-qmp-usb3dp-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QMP USB3-DP PHY controller (DP, QCS615)
+
+maintainers:
+ - Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
+
+description:
+ The QMP PHY controller supports physical layer functionality for both USB3
+ and DisplayPort over USB-C. While it enables mode switching between USB3 and
+ DisplayPort, but does not support combo mode.
+
+properties:
+ compatible:
+ enum:
+ - qcom,qcs615-qmp-usb3-dp-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 4
+
+ clock-names:
+ items:
+ - const: aux
+ - const: ref
+ - const: cfg_ahb
+ - const: pipe
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: phy_phy
+ - const: dp_phy
+
+ vdda-phy-supply: true
+
+ vdda-pll-supply: true
+
+ "#clock-cells":
+ const: 1
+ description:
+ See include/dt-bindings/phy/phy-qcom-qmp.h
+
+ "#phy-cells":
+ const: 1
+ description:
+ See include/dt-bindings/phy/phy-qcom-qmp.h
+
+ qcom,tcsr-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to TCSR hardware block
+ - description: offset of the VLS CLAMP register
+ - description: offset of the PHY mode register
+ description: Clamp and PHY mode register present in the TCSR
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - vdda-phy-supply
+ - vdda-pll-supply
+ - "#clock-cells"
+ - "#phy-cells"
+ - qcom,tcsr-reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,qcs615-gcc.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+
+ phy@88e8000 {
+ compatible = "qcom,qcs615-qmp-usb3-dp-phy";
+ reg = <0x88e8000 0x2000>;
+
+ clocks = <&gcc GCC_USB2_SEC_PHY_AUX_CLK>,
+ <&gcc GCC_USB3_SEC_CLKREF_CLK>,
+ <&gcc GCC_AHB2PHY_WEST_CLK>,
+ <&gcc GCC_USB2_SEC_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "cfg_ahb",
+ "pipe";
+
+ resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
+ <&gcc GCC_USB3_DP_PHY_SEC_BCR>;
+ reset-names = "phy_phy",
+ "dp_phy";
+
+ vdda-phy-supply = <&vreg_l5a>;
+ vdda-pll-supply = <&vreg_l12a>;
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ qcom,tcsr-reg = <&tcsr 0xbff0 0xb24c>;
+ };
properties:
compatible:
enum:
+ - qcom,glymur-qmp-gen4x2-pcie-phy
- qcom,glymur-qmp-gen5x4-pcie-phy
+ - qcom,kaanapali-qmp-gen3x2-pcie-phy
- qcom,qcs615-qmp-gen3x1-pcie-phy
- qcom,qcs8300-qmp-gen4x2-pcie-phy
- qcom,sa8775p-qmp-gen4x2-pcie-phy
compatible:
contains:
enum:
+ - qcom,kaanapali-qmp-gen3x2-pcie-phy
- qcom,qcs615-qmp-gen3x1-pcie-phy
- qcom,sar2130p-qmp-gen3x2-pcie-phy
- qcom,sc8180x-qmp-pcie-phy
compatible:
contains:
enum:
+ - qcom,glymur-qmp-gen4x2-pcie-phy
- qcom,glymur-qmp-gen5x4-pcie-phy
- qcom,qcs8300-qmp-gen4x2-pcie-phy
- qcom,sa8775p-qmp-gen4x2-pcie-phy
compatible:
contains:
enum:
+ - qcom,glymur-qmp-gen4x2-pcie-phy
- qcom,glymur-qmp-gen5x4-pcie-phy
+ - qcom,kaanapali-qmp-gen3x2-pcie-phy
- qcom,sm8550-qmp-gen4x2-pcie-phy
- qcom,sm8650-qmp-gen4x2-pcie-phy
- qcom,x1e80100-qmp-gen3x2-pcie-phy
- enum:
- qcom,qcs615-qmp-ufs-phy
- const: qcom,sm6115-qmp-ufs-phy
+ - items:
+ - enum:
+ - qcom,x1e80100-qmp-ufs-phy
+ - const: qcom,sm8550-qmp-ufs-phy
- items:
- enum:
- qcom,qcs8300-qmp-ufs-phy
- qcom,kaanapali-qmp-ufs-phy
- const: qcom,sm8750-qmp-ufs-phy
- enum:
+ - qcom,milos-qmp-ufs-phy
- qcom,msm8996-qmp-ufs-phy
- qcom,msm8998-qmp-ufs-phy
- qcom,sa8775p-qmp-ufs-phy
compatible:
contains:
enum:
+ - qcom,milos-qmp-ufs-phy
- qcom,msm8998-qmp-ufs-phy
- qcom,sa8775p-qmp-ufs-phy
- qcom,sc7180-qmp-ufs-phy
properties:
compatible:
enum:
+ - qcom,glymur-qmp-usb3-uni-phy
- qcom,ipq5424-qmp-usb3-phy
- qcom,ipq6018-qmp-usb3-phy
- qcom,ipq8074-qmp-usb3-phy
vdda-pll-supply: true
+ refgen-supply: true
+
"#clock-cells":
const: 0
compatible:
contains:
enum:
+ - qcom,glymur-qmp-usb3-uni-phy
- qcom,qcs8300-qmp-usb3-uni-phy
- qcom,qdu1000-qmp-usb3-uni-phy
- qcom,sa8775p-qmp-usb3-uni-phy
compatible:
contains:
enum:
+ - qcom,glymur-qmp-usb3-uni-phy
- qcom,sa8775p-qmp-usb3-uni-phy
- qcom,sc8180x-qmp-usb3-uni-phy
- qcom,sc8280xp-qmp-usb3-uni-phy
required:
- power-domains
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,glymur-qmp-usb3-uni-phy
+ then:
+ required:
+ - refgen-supply
+ else:
+ properties:
+ refgen-supply: false
+
additionalProperties: false
examples:
properties:
compatible:
- enum:
- - qcom,sar2130p-qmp-usb3-dp-phy
- - qcom,sc7180-qmp-usb3-dp-phy
- - qcom,sc7280-qmp-usb3-dp-phy
- - qcom,sc8180x-qmp-usb3-dp-phy
- - qcom,sc8280xp-qmp-usb43dp-phy
- - qcom,sdm845-qmp-usb3-dp-phy
- - qcom,sm6350-qmp-usb3-dp-phy
- - qcom,sm8150-qmp-usb3-dp-phy
- - qcom,sm8250-qmp-usb3-dp-phy
- - qcom,sm8350-qmp-usb3-dp-phy
- - qcom,sm8450-qmp-usb3-dp-phy
- - qcom,sm8550-qmp-usb3-dp-phy
- - qcom,sm8650-qmp-usb3-dp-phy
- - qcom,sm8750-qmp-usb3-dp-phy
- - qcom,x1e80100-qmp-usb3-dp-phy
+ oneOf:
+ - items:
+ - enum:
+ - qcom,kaanapali-qmp-usb3-dp-phy
+ - const: qcom,sm8750-qmp-usb3-dp-phy
+ - enum:
+ - qcom,glymur-qmp-usb3-dp-phy
+ - qcom,sar2130p-qmp-usb3-dp-phy
+ - qcom,sc7180-qmp-usb3-dp-phy
+ - qcom,sc7280-qmp-usb3-dp-phy
+ - qcom,sc8180x-qmp-usb3-dp-phy
+ - qcom,sc8280xp-qmp-usb43dp-phy
+ - qcom,sdm845-qmp-usb3-dp-phy
+ - qcom,sm6350-qmp-usb3-dp-phy
+ - qcom,sm8150-qmp-usb3-dp-phy
+ - qcom,sm8250-qmp-usb3-dp-phy
+ - qcom,sm8350-qmp-usb3-dp-phy
+ - qcom,sm8450-qmp-usb3-dp-phy
+ - qcom,sm8550-qmp-usb3-dp-phy
+ - qcom,sm8650-qmp-usb3-dp-phy
+ - qcom,sm8750-qmp-usb3-dp-phy
+ - qcom,x1e80100-qmp-usb3-dp-phy
reg:
maxItems: 1
vdda-pll-supply: true
+ refgen-supply: true
+
"#clock-cells":
const: 1
description:
- if:
properties:
compatible:
- enum:
- - qcom,sar2130p-qmp-usb3-dp-phy
- - qcom,sc8280xp-qmp-usb43dp-phy
- - qcom,sm6350-qmp-usb3-dp-phy
- - qcom,sm8550-qmp-usb3-dp-phy
- - qcom,sm8650-qmp-usb3-dp-phy
- - qcom,sm8750-qmp-usb3-dp-phy
- - qcom,x1e80100-qmp-usb3-dp-phy
+ contains:
+ enum:
+ - qcom,glymur-qmp-usb3-dp-phy
+ - qcom,sar2130p-qmp-usb3-dp-phy
+ - qcom,sc8280xp-qmp-usb43dp-phy
+ - qcom,sm6350-qmp-usb3-dp-phy
+ - qcom,sm8550-qmp-usb3-dp-phy
+ - qcom,sm8650-qmp-usb3-dp-phy
+ - qcom,sm8750-qmp-usb3-dp-phy
+ - qcom,x1e80100-qmp-usb3-dp-phy
then:
required:
- power-domains
properties:
power-domains: false
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,glymur-qmp-usb3-dp-phy
+ then:
+ required:
+ - refgen-supply
+ else:
+ properties:
+ refgen-supply: false
+
additionalProperties: false
examples:
- qcom,pm8550b-eusb2-repeater
- qcom,pmiv0104-eusb2-repeater
- qcom,smb2360-eusb2-repeater
+ - qcom,smb2370-eusb2-repeater
reg:
maxItems: 1
minimum: 0
maximum: 7
+ qcom,squelch-detector-bp:
+ description:
+ This adjusts the voltage level for the threshold used to detect valid
+ high-speed data.
+ minimum: -6000
+ maximum: 1000
+ multipleOf: 1000
+
required:
- compatible
- reg
properties:
compatible:
- const: renesas,r9a09g047-usb3-phy
+ oneOf:
+ - const: renesas,r9a09g047-usb3-phy # RZ/G3E
+
+ - items:
+ - enum:
+ - renesas,r9a09g056-usb3-phy # RZ/V2N
+ - renesas,r9a09g057-usb3-phy # RZ/V2H(P)
+ - const: renesas,r9a09g047-usb3-phy
reg:
maxItems: 1
- const: renesas,rzg2l-usb2-phy
- items:
- - const: renesas,usb2-phy-r9a09g056 # RZ/V2N
+ - enum:
+ - renesas,usb2-phy-r9a09g047 # RZ/G3E
+ - renesas,usb2-phy-r9a09g056 # RZ/V2N
- const: renesas,usb2-phy-r9a09g057
- const: renesas,usb2-phy-r9a09g077 # RZ/T2H
Phandle to a regulator that provides power to the VBUS. This regulator
will be managed during the PHY power on/off sequence.
+ vbus-regulator:
+ $ref: /schemas/regulator/regulator.yaml#
+ description: USB VBUS internal regulator
+ type: object
+ unevaluatedProperties: false
+
renesas,no-otg-pins:
$ref: /schemas/types.yaml#/definitions/flag
description: |
dr_mode: true
+ mux-states:
+ description:
+ phandle to a mux controller node that select the source for USB VBUS.
+ maxItems: 1
+
if:
properties:
compatible:
minItems: 1
maxItems: 4
+ power-domains:
+ maxItems: 1
+
samsung,pmu-syscon:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
- samsung,exynos7870-usbdrd-phy
- samsung,exynos850-usbdrd-phy
- samsung,exynos990-usbdrd-phy
+ - samsung,exynosautov920-usb31drd-combo-ssphy
+ - samsung,exynosautov920-usbdrd-combo-hsphy
+ - samsung,exynosautov920-usbdrd-phy
clocks:
minItems: 1
settings register. For Exynos5420 this is given as 'sclk_usbphy30'
in the CMU. It's not needed for Exynos2200.
+ power-domains:
+ maxItems: 1
+
"#phy-cells":
const: 1
vddh-usbdp-supply:
description: VDDh power supply for the USB DP phy.
+ dvdd-supply:
+ description: 0.75V power supply for the USB phy.
+
+ vdd18-supply:
+ description: 1.8V power supply for the USB phy.
+
+ vdd33-supply:
+ description: 3.3V power supply for the USB phy.
+
required:
- compatible
- clocks
- samsung,exynos7870-usbdrd-phy
- samsung,exynos850-usbdrd-phy
- samsung,exynos990-usbdrd-phy
+ - samsung,exynosautov920-usb31drd-combo-ssphy
+ - samsung,exynosautov920-usbdrd-combo-hsphy
+ - samsung,exynosautov920-usbdrd-phy
then:
properties:
clocks:
reg-names:
maxItems: 1
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,exynosautov920-usb31drd-combo-ssphy
+ - samsung,exynosautov920-usbdrd-combo-hsphy
+ - samsung,exynosautov920-usbdrd-phy
+ then:
+ required:
+ - dvdd-supply
+ - vdd18-supply
+
+ else:
+ properties:
+ dvdd-supply: false
+ vdd18-supply: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,exynosautov920-usbdrd-combo-hsphy
+ - samsung,exynosautov920-usbdrd-phy
+ then:
+ required:
+ - vdd33-supply
+
+ else:
+ properties:
+ vdd33-supply: false
+
unevaluatedProperties: false
examples:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/spacemit,k1-combo-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K1 PCIe/USB3 Combo PHY
+
+maintainers:
+ - Alex Elder <elder@riscstar.com>
+
+description: >
+ Of the three PHYs on the SpacemiT K1 SoC capable of being used for
+ PCIe, one is a combo PHY that can also be configured for use by a
+ USB 3 controller. Using PCIe or USB 3 is a board design decision.
+
+ The combo PHY is also the only PCIe PHY that is able to determine
+ PCIe calibration values to use, and this must be determined before
+ the other two PCIe PHYs can be used. This calibration must be
+ performed with the combo PHY in PCIe mode, and is this is done
+ when the combo PHY is probed.
+
+ The combo PHY uses an external oscillator as a reference clock.
+ During normal operation, the PCIe or USB port driver is responsible
+ for ensuring all other clocks needed by a PHY are enabled, and all
+ resets affecting the PHY are deasserted. However, for the combo
+ PHY to perform calibration independent of whether it's later used
+ for PCIe or USB, all PCIe mode clocks and resets must be defined.
+
+properties:
+ compatible:
+ const: spacemit,k1-combo-phy
+
+ reg:
+ items:
+ - description: PHY control registers
+
+ clocks:
+ items:
+ - description: External oscillator used by the PHY PLL
+ - description: DWC PCIe Data Bus Interface (DBI) clock
+ - description: DWC PCIe application AXI-bus Master interface clock
+ - description: DWC PCIe application AXI-bus slave interface clock
+
+ clock-names:
+ items:
+ - const: refclk
+ - const: dbi
+ - const: mstr
+ - const: slv
+
+ resets:
+ items:
+ - description: PHY reset; remains deasserted after initialization
+ - description: DWC PCIe Data Bus Interface (DBI) reset
+ - description: DWC PCIe application AXI-bus Master interface reset
+ - description: DWC PCIe application AXI-bus slave interface reset
+
+ reset-names:
+ items:
+ - const: phy
+ - const: dbi
+ - const: mstr
+ - const: slv
+
+ spacemit,apmu:
+ description:
+ A phandle that refers to the APMU system controller, whose
+ regmap is used in setting the mode
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ "#phy-cells":
+ const: 1
+ description:
+ The argument value (PHY_TYPE_PCIE or PHY_TYPE_USB3) determines
+ whether the PHY operates in PCIe or USB3 mode.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - spacemit,apmu
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/spacemit,k1-syscon.h>
+ phy@c0b10000 {
+ compatible = "spacemit,k1-combo-phy";
+ reg = <0xc0b10000 0x1000>;
+ clocks = <&vctcxo_24m>,
+ <&syscon_apmu CLK_PCIE0_DBI>,
+ <&syscon_apmu CLK_PCIE0_MASTER>,
+ <&syscon_apmu CLK_PCIE0_SLAVE>;
+ clock-names = "refclk",
+ "dbi",
+ "mstr",
+ "slv";
+ resets = <&syscon_apmu RESET_PCIE0_GLOBAL>,
+ <&syscon_apmu RESET_PCIE0_DBI>,
+ <&syscon_apmu RESET_PCIE0_MASTER>,
+ <&syscon_apmu RESET_PCIE0_SLAVE>;
+ reset-names = "phy",
+ "dbi",
+ "mstr",
+ "slv";
+ spacemit,apmu = <&syscon_apmu>;
+ #phy-cells = <1>;
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/spacemit,k1-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K1 PCIe PHY
+
+maintainers:
+ - Alex Elder <elder@riscstar.com>
+
+description: >
+ Two PHYs on the SpacemiT K1 SoC used for only for PCIe. These
+ PHYs must be configured using calibration values that are
+ determined by a third "combo PHY". The combo PHY determines
+ these calibration values during probe so they can be used for
+ the two PCIe-only PHYs.
+
+ The PHY uses an external oscillator as a reference clock. During
+ normal operation, the PCIe host driver is responsible for ensuring
+ all other clocks needed by a PHY are enabled, and all resets
+ affecting the PHY are deasserted.
+
+properties:
+ compatible:
+ const: spacemit,k1-pcie-phy
+
+ reg:
+ items:
+ - description: PHY control registers
+
+ clocks:
+ items:
+ - description: External oscillator used by the PHY PLL
+
+ clock-names:
+ const: refclk
+
+ resets:
+ items:
+ - description: PHY reset; remains deasserted after initialization
+
+ reset-names:
+ const: phy
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/spacemit,k1-syscon.h>
+ phy@c0c10000 {
+ compatible = "spacemit,k1-pcie-phy";
+ reg = <0xc0c10000 0x1000>;
+ clocks = <&vctcxo_24m>;
+ clock-names = "refclk";
+ resets = <&syscon_apmu RESET_PCIE1_GLOBAL>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/spacemit,usb2-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K1 SoC USB 2.0 PHY
+
+maintainers:
+ - Ze Huang <huang.ze@linux.dev>
+
+properties:
+ compatible:
+ const: spacemit,k1-usb2-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ usb-phy@c09c0000 {
+ compatible = "spacemit,k1-usb2-phy";
+ reg = <0xc09c0000 0x200>;
+ clocks = <&syscon_apmu 15>;
+ #phy-cells = <0>;
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/ti,control-phy-otghs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI OMAP Control PHY Module
+
+maintainers:
+ - Roger Quadros <rogerq@ti.com>
+
+description:
+ The TI OMAP Control PHY module is a hardware block within the system
+ control module (SCM) of Texas Instruments OMAP SoCs. It provides
+ centralized control over power, configuration, and auxiliary features
+ for multiple on-chip PHYs. This module is essential for proper PHY
+ operation in power-constrained embedded systems.
+
+properties:
+ $nodename:
+ pattern: "^phy@[0-9a-f]+$"
+
+ compatible:
+ enum:
+ - ti,control-phy-otghs
+ - ti,control-phy-pcie
+ - ti,control-phy-pipe3
+ - ti,control-phy-usb2
+ - ti,control-phy-usb2-am437
+ - ti,control-phy-usb2-dra7
+
+ reg:
+ minItems: 1
+ maxItems: 3
+
+ reg-names:
+ minItems: 1
+ maxItems: 3
+ items:
+ enum: [otghs_control, power, pcie_pcs, control_sma]
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ti,control-phy-otghs
+ then:
+ properties:
+ reg-names:
+ const: otghs_control
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ti,control-phy-pcie
+ then:
+ properties:
+ reg:
+ minItems: 3
+
+ reg-names:
+ items:
+ - const: power
+ - const: pcie_pcs
+ - const: control_sma
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ti,control-phy-usb2
+ - ti,control-phy-usb2-dra7
+ - ti,control-phy-usb2-am437
+ - ti,control-phy-pipe3
+ then:
+ properties:
+ reg-names:
+ const: power
+
+required:
+ - reg
+ - compatible
+ - reg-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ phy@4a00233c {
+ compatible = "ti,control-phy-otghs";
+ reg = <0x4a00233c 0x4>;
+ reg-names = "otghs_control";
+ };
+...
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/ti,phy-usb3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI PIPE3 PHY Module
+
+maintainers:
+ - Roger Quadros <rogerq@ti.com>
+
+description:
+ The TI PIPE3 PHY is a high-speed SerDes (Serializer/Deserializer)
+ transceiver integrated in OMAP5, DRA7xx/AM57xx, and similar SoCs.
+ It supports multiple protocols (USB3, SATA, PCIe) using the PIPE3
+ interface standard, which defines a common physical layer for
+ high-speed serial interfaces.
+
+properties:
+ $nodename:
+ pattern: "^(pcie-phy|usb3-phy|phy)@[0-9a-f]+$"
+
+ compatible:
+ enum:
+ - ti,omap-usb3
+ - ti,phy-pipe3-pcie
+ - ti,phy-pipe3-sata
+ - ti,phy-usb3
+
+ reg:
+ minItems: 2
+ maxItems: 3
+
+ reg-names:
+ minItems: 2
+ items:
+ - const: phy_rx
+ - const: phy_tx
+ - const: pll_ctrl
+
+ "#phy-cells":
+ const: 0
+
+ clocks:
+ minItems: 2
+ maxItems: 7
+
+ clock-names:
+ minItems: 2
+ maxItems: 7
+ items:
+ enum: [wkupclk, sysclk, refclk, dpll_ref,
+ dpll_ref_m2, phy-div, div-clk]
+
+ syscon-phy-power:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+ items:
+ items:
+ - description: Phandle to the system control module
+ - description: Register offset controlling PHY power
+
+ syscon-pllreset:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+ items:
+ items:
+ - description: Phandle to the system control module
+ - description: Register offset of CTRL_CORE_SMA_SW_0
+
+ syscon-pcs:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+ items:
+ items:
+ - description: Phandle to the system control module
+ - description: Register offset for PCS delay programming
+
+ ctrl-module:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle of control module for PHY power on.
+ deprecated: true
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,phy-pipe3-sata
+ then:
+ properties:
+ syscon-pllreset: true
+ else:
+ properties:
+ syscon-pllreset: false
+
+required:
+ - reg
+ - compatible
+ - reg-names
+ - "#phy-cells"
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ /* TI PIPE3 USB3 PHY */
+ usb3-phy@4a084400 {
+ compatible = "ti,phy-usb3";
+ reg = <0x4a084400 0x80>,
+ <0x4a084800 0x64>,
+ <0x4a084c00 0x40>;
+ reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ #phy-cells = <0>;
+ clocks = <&usb_phy_cm_clk32k>,
+ <&sys_clkin>,
+ <&usb_otg_ss_refclk960m>;
+ clock-names = "wkupclk", "sysclk", "refclk";
+ ctrl-module = <&omap_control_usb>;
+ };
+
+ - |
+ /* TI PIPE3 SATA PHY */
+ phy@4a096000 {
+ compatible = "ti,phy-pipe3-sata";
+ reg = <0x4a096000 0x80>, /* phy_rx */
+ <0x4a096400 0x64>, /* phy_tx */
+ <0x4a096800 0x40>; /* pll_ctrl */
+ reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ clocks = <&sys_clkin1>, <&sata_ref_clk>;
+ clock-names = "sysclk", "refclk";
+ syscon-pllreset = <&scm_conf 0x3fc>;
+ #phy-cells = <0>;
+ };
+...
- microchip,ata6561
- ti,tcan1051
- const: ti,tcan1042
+ - items:
+ - const: ti,tcan1046
+ - const: nxp,tja1048
- enum:
- ti,tcan1042
- ti,tcan1043
+++ /dev/null
-TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
-
-OMAP CONTROL PHY
-
-Required properties:
- - compatible: Should be one of
- "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
- "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
- e.g. USB2_PHY on OMAP5.
- "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
- e.g. USB3 PHY and SATA PHY on OMAP5.
- "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
- set PCS delay value.
- e.g. PCIE PHY in DRA7x
- "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
- DRA7 platform.
- "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
- AM437 platform.
- - reg : register ranges as listed in the reg-names property
- - reg-names: "otghs_control" for control-phy-otghs
- "power", "pcie_pcs" and "control_sma" for control-phy-pcie
- "power" for all other types
-
-omap_control_usb: omap-control-usb@4a002300 {
- compatible = "ti,control-phy-otghs";
- reg = <0x4a00233c 0x4>;
- reg-names = "otghs_control";
-};
-
-TI PIPE3 PHY
-
-Required properties:
- - compatible: Should be "ti,phy-usb3", "ti,phy-pipe3-sata" or
- "ti,phy-pipe3-pcie. "ti,omap-usb3" is deprecated.
- - reg : Address and length of the register set for the device.
- - reg-names: The names of the register addresses corresponding to the registers
- filled in "reg".
- - #phy-cells: determine the number of cells that should be given in the
- phandle while referencing this phy.
- - clocks: a list of phandles and clock-specifier pairs, one for each entry in
- clock-names.
- - clock-names: should include:
- * "wkupclk" - wakeup clock.
- * "sysclk" - system clock.
- * "refclk" - reference clock.
- * "dpll_ref" - external dpll ref clk
- * "dpll_ref_m2" - external dpll ref clk
- * "phy-div" - divider for apll
- * "div-clk" - apll clock
-
-Optional properties:
- - id: If there are multiple instance of the same type, in order to
- differentiate between each instance "id" can be used (e.g., multi-lane PCIe
- PHY). If "id" is not provided, it is set to default value of '1'.
- - syscon-pllreset: Handle to system control region that contains the
- CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
- register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.
- - syscon-pcs : phandle/offset pair. Phandle to the system control module and the
- register offset to write the PCS delay value.
-
-Deprecated properties:
- - ctrl-module : phandle of the control module used by PHY driver to power on
- the PHY.
-
-Recommended properties:
- - syscon-phy-power : phandle/offset pair. Phandle to the system control
- module and the register offset to power on/off the PHY.
-
-This is usually a subnode of ocp2scp to which it is connected.
-
-usb3phy@4a084400 {
- compatible = "ti,phy-usb3";
- reg = <0x4a084400 0x80>,
- <0x4a084800 0x64>,
- <0x4a084c00 0x40>;
- reg-names = "phy_rx", "phy_tx", "pll_ctrl";
- ctrl-module = <&omap_control_usb>;
- #phy-cells = <0>;
- clocks = <&usb_phy_cm_clk32k>,
- <&sys_clkin>,
- <&usb_otg_ss_refclk960m>;
- clock-names = "wkupclk",
- "sysclk",
- "refclk";
-};
-
-sata_phy: phy@4a096000 {
- compatible = "ti,phy-pipe3-sata";
- reg = <0x4A096000 0x80>, /* phy_rx */
- <0x4A096400 0x64>, /* phy_tx */
- <0x4A096800 0x40>; /* pll_ctrl */
- reg-names = "phy_rx", "phy_tx", "pll_ctrl";
- ctrl-module = <&omap_control_sata>;
- clocks = <&sys_clkin1>, <&sata_ref_clk>;
- clock-names = "sysclk", "refclk";
- syscon-pllreset = <&scm_conf 0x3fc>;
- #phy-cells = <0>;
-};
+++ /dev/null
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/phy/transmit-amplitude.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Common PHY and network PCS transmit amplitude property
-
-description:
- Binding describing the peak-to-peak transmit amplitude for common PHYs
- and network PCSes.
-
-maintainers:
- - Marek Behún <kabel@kernel.org>
-
-properties:
- tx-p2p-microvolt:
- description:
- Transmit amplitude voltages in microvolts, peak-to-peak. If this property
- contains multiple values for various PHY modes, the
- 'tx-p2p-microvolt-names' property must be provided and contain
- corresponding mode names.
-
- tx-p2p-microvolt-names:
- description: |
- Names of the modes corresponding to voltages in the 'tx-p2p-microvolt'
- property. Required only if multiple voltages are provided.
-
- If a value of 'default' is provided, the system should use it for any PHY
- mode that is otherwise not defined here. If 'default' is not provided, the
- system should use manufacturer default value.
- minItems: 1
- maxItems: 16
- items:
- enum:
- - default
-
- # ethernet modes
- - sgmii
- - qsgmii
- - xgmii
- - 1000base-x
- - 2500base-x
- - 5gbase-r
- - rxaui
- - xaui
- - 10gbase-kr
- - usxgmii
- - 10gbase-r
- - 25gbase-r
-
- # PCIe modes
- - pcie
- - pcie1
- - pcie2
- - pcie3
- - pcie4
- - pcie5
- - pcie6
-
- # USB modes
- - usb
- - usb-ls
- - usb-fs
- - usb-hs
- - usb-ss
- - usb-ss+
- - usb-4
-
- # storage modes
- - sata
- - ufs-hs
- - ufs-hs-a
- - ufs-hs-b
-
- # display modes
- - lvds
- - dp
- - dp-rbr
- - dp-hbr
- - dp-hbr2
- - dp-hbr3
- - dp-uhbr-10
- - dp-uhbr-13.5
- - dp-uhbr-20
-
- # camera modes
- - mipi-dphy
- - mipi-dphy-univ
- - mipi-dphy-v2.5-univ
-
-dependencies:
- tx-p2p-microvolt-names: [ tx-p2p-microvolt ]
-
-additionalProperties: true
-
-examples:
- - |
- phy: phy {
- #phy-cells = <1>;
- tx-p2p-microvolt = <915000>, <1100000>, <1200000>;
- tx-p2p-microvolt-names = "2500base-x", "usb-hs", "usb-ss";
- };
# the pin numbers then,
# - Finally, the name will end with either -pin or pins.
- "^([rs]-)?(([a-z0-9]{3,}|[a-oq-z][a-z0-9]*?)?-)+?(p[a-ilm][0-9]*?-)??pins?$":
+ "^([rs]-)?(([a-z0-9]{3,}|[a-oq-z0-9][a-z0-9]*?)?-)+?(p[a-ilm][0-9]*?-)??pins?$":
type: object
properties:
interrupts:
description:
Specifies the interrupt lines to be used by the controller.
- Each interrupt line is shared by upto 4 GPIO lines.
+ Each interrupt line is shared by up to 4 GPIO lines.
maxItems: 8
interrupt-controller: true
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/microchip,mpfs-pinctrl-mssio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Polarfire SoC MSSIO pinctrl
+
+maintainers:
+ - Conor Dooley <conor.dooley@microchip.com>
+
+properties:
+ compatible:
+ oneOf:
+ - const: microchip,mpfs-pinctrl-mssio
+ - items:
+ - const: microchip,pic64gx-pinctrl-mssio
+ - const: microchip,mpfs-pinctrl-mssio
+
+ reg:
+ maxItems: 1
+
+ pinctrl-use-default: true
+
+patternProperties:
+ '-cfg$':
+ type: object
+ additionalProperties: false
+
+ patternProperties:
+ '-pins$':
+ type: object
+ additionalProperties: false
+
+ allOf:
+ - $ref: pincfg-node.yaml#
+ - $ref: pinmux-node.yaml#
+
+ properties:
+ pins:
+ description:
+ The list of IOs that properties in the pincfg node apply to.
+
+ function:
+ description:
+ A string containing the name of the function to mux for these
+ pins. The "reserved" function tristates a pin.
+ enum: [ sd, emmc, qspi, spi, usb, uart, i2c, can, mdio, misc
+ reserved, gpio, fabric-test, tied-low, tied-high, tristate ]
+
+ bias-bus-hold: true
+ bias-disable: true
+ bias-pull-down: true
+ bias-pull-up: true
+ input-schmitt-enable: true
+ low-power-enable: true
+
+ drive-strength:
+ enum: [ 2, 4, 6, 8, 10, 12, 16, 20 ]
+
+ power-source:
+ description:
+ Which bank voltage to use. This cannot differ for pins in a
+ given bank, the whole bank uses the same voltage.
+ enum: [ 1200000, 1500000, 1800000, 2500000, 3300000 ]
+
+ microchip,clamp-diode:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Reflects the "Clamp Diode" setting in the MSS Configurator for
+ this pin. This setting controls whether or not input voltage
+ clamping should be enabled.
+
+ microchip,ibufmd:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+ description:
+ Reflects the "IBUFMD" bits in the MSS Configurator output files
+ for this pin.
+
+ required:
+ - pins
+ - function
+ - power-source
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ pinctrl@204 {
+ compatible = "microchip,mpfs-pinctrl-mssio";
+ reg = <0x204 0x7c>;
+
+ ikrd-spi1-cfg {
+ spi1-pins {
+ pins = <30>, <31>, <32>, <33>;
+ function = "spi";
+ bias-pull-up;
+ drive-strength = <8>;
+ power-source = <3300000>;
+ microchip,ibufmd = <0x1>;
+ };
+ };
+ };
+...
pattern: '^gpio@[0-9a-f]+$'
compatible:
- enum:
- - microchip,sparx5-sgpio
- - mscc,ocelot-sgpio
- - mscc,luton-sgpio
+ oneOf:
+ - enum:
+ - microchip,sparx5-sgpio
+ - mscc,ocelot-sgpio
+ - mscc,luton-sgpio
+ - items:
+ - enum:
+ - microchip,lan9691-sgpio
+ - const: microchip,sparx5-sgpio
'#address-cells':
const: 1
type: object
properties:
compatible:
- const: microchip,sparx5-sgpio-bank
+ oneOf:
+ - items:
+ - enum:
+ - microchip,lan9691-sgpio-bank
+ - const: microchip,sparx5-sgpio-bank
+ - const: microchip,sparx5-sgpio-bank
reg:
description: |
compatible:
oneOf:
- enum:
+ - microchip,lan96455f-pinctrl
- microchip,lan966x-pinctrl
- microchip,lan9691-pinctrl
- microchip,sparx5-pinctrl
- microchip,lan9693-pinctrl
- microchip,lan9692-pinctrl
- const: microchip,lan9691-pinctrl
+ - items:
+ - enum:
+ - microchip,lan96457f-pinctrl
+ - microchip,lan96459f-pinctrl
+ - const: microchip,lan96455f-pinctrl
reg:
items:
- Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
description:
- Top Level Mode Multiplexer pin controller in Qualcomm Glymur SoC.
+ Top Level Mode Multiplexer pin controller in Qualcomm Glymur and Mahua SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
- const: qcom,glymur-tlmm
+ enum:
+ - qcom,glymur-tlmm
+ - qcom,mahua-tlmm
reg:
maxItems: 1
gpio-ranges:
maxItems: 1
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+ description:
+ The first cell contains the global GPIO port index, constructed using the
+ RZT2H_GPIO() helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
+ and the second cell is used to specify the flag.
+ E.g. "interrupts = <RZT2H_GPIO(8, 6) IRQ_TYPE_EDGE_FALLING>;" if P08_6 is
+ being used as an interrupt.
+
clocks:
maxItems: 1
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 288>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
power-domains = <&cpg>;
serial0-pins {
- enum:
- google,gs101-wakeup-eint
- samsung,exynos2200-wakeup-eint
+ - samsung,exynos9610-wakeup-eint
- samsung,exynos9810-wakeup-eint
- samsung,exynos990-wakeup-eint
- samsung,exynosautov9-wakeup-eint
- samsung,exynos850-pinctrl
- samsung,exynos8890-pinctrl
- samsung,exynos8895-pinctrl
+ - samsung,exynos9610-pinctrl
- samsung,exynos9810-pinctrl
- samsung,exynos990-pinctrl
- samsung,exynosautov9-pinctrl
properties:
compatible:
- const: spacemit,k1-pinctrl
+ enum:
+ - spacemit,k1-pinctrl
+ - spacemit,k3-pinctrl
reg:
items:
resets:
maxItems: 1
+ spacemit,apbc:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Phandle to syscon that access the protected register
+
patternProperties:
'-cfg$':
type: object
enum: [ 0, 1 ]
drive-strength:
- description: |
- typical current when output high level.
- 1.8V output: 11, 21, 32, 42 (mA)
- 3.3V output: 7, 10, 13, 16, 19, 23, 26, 29 (mA)
+ description:
+ typical current (in mA) when the output at high level.
+ anyOf:
+ - enum: [ 11, 21, 32, 42 ]
+ description: For K1 SoC, 1.8V voltage output
+
+ - enum: [ 7, 10, 13, 16, 19, 23, 26, 29 ]
+ description: For K1 SoC, 3.3V voltage output
+
+ - enum: [ 2, 4, 6, 7, 9, 11, 13, 14, 21, 23, 25, 26, 28, 30, 31, 33 ]
+ description: For K3 SoC, 1.8V voltage output
+
+ - enum: [ 3, 5, 7, 9, 11, 13, 15, 17, 25, 27, 29, 31, 33, 35, 37, 38 ]
+ description: For K3 SoC, 3.3V voltage output
input-schmitt:
description: |
clocks = <&syscon_apbc 42>,
<&syscon_apbc 94>;
clock-names = "func", "bus";
+ spacemit,apbc = <&syscon_apbc>;
uart0_2_cfg: uart0-2-cfg {
uart0-2-pins {
reg:
maxItems: 1
+ "#address-cells":
+ const: 0
+
interrupts:
maxItems: 1
title: Mediatek Power Domains Controller
maintainers:
- - MandyJH Liu <mandyjh.liu@mediatek.com>
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
- Matthias Brugger <mbrugger@suse.com>
description: |
compatible:
const: syscon-poweroff
+ reg:
+ maxItems: 1
+
mask:
$ref: /schemas/types.yaml#/definitions/uint32
description: Update only the register bits defined by the mask (32 bit).
required:
- compatible
- - offset
+
+anyOf:
+ - required: [offset]
+ - required: [reg]
additionalProperties: false
required:
- value
- oneOf:
+ anyOf:
- required: [offset]
- required: [reg]
description: battery design capacity
trickle-charge-current-microamp:
- description: current for trickle-charge phase
+ description: current for trickle-charge phase.
+ Please note that the trickle-charging here, refers "wake-up" or
+ "pre-pre" -charging, for very empty batteries. Similar term is also
+ used for "maintenance" or "top-off" -charging of batteries (like
+ NiMh bq24400) - that is different and not controlled by this
+ property.
+
+ tricklecharge-upper-limit-microvolt:
+ description: limit when to change to precharge from trickle charge
+ Trickle-charging here refers "wake-up" or "pre-pre" -charging.
precharge-current-microamp:
description: current for pre-charge phase
- description: alert when battery temperature is lower than this value
- description: alert when battery temperature is higher than this value
+ # The volt-drop* -properties describe voltage-drop for a battery, described
+ # as VDROP in:
+ # https://patentimages.storage.googleapis.com/6c/f5/17/c1d901c220f6a9/US20150032394A1.pdf
+ volt-drop-thresh-microvolt:
+ description: Threshold for starting the VDR correction
+ maximum: 48000000
+
+ volt-drop-soc-bp:
+ description: Table of capacity values matching the values in VDR tables.
+ The value should be given as basis points, 1/100 of a percent.
+
+ volt-drop-temperatures-millicelsius:
+ description: An array containing the temperature in milli celsius, for each
+ of the VDR lookup table.
+
required:
- compatible
- description: battery capacity percent
maximum: 100
+ '^volt-drop-[0-9]-microvolt':
+ description: Table of the voltage drop rate (VDR) values. Each entry in the
+ table should match a capacity value in the volt-drop-soc table.
+ Furthermore, the values should be obtained for the temperature given in
+ volt-drop-temperatures-millicelsius table at index matching the
+ number in this table's name.
+
additionalProperties: false
examples:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/supply/google,goldfish-battery.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Android Goldfish Battery
+
+maintainers:
+ - Kuan-Wei Chiu <visitorckw@gmail.com>
+
+allOf:
+ - $ref: power-supply.yaml#
+
+description:
+ Android goldfish battery device generated by Android emulator.
+
+properties:
+ compatible:
+ const: google,goldfish-battery
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ battery@9020000 {
+ compatible = "google,goldfish-battery";
+ reg = <0x9020000 0x1000>;
+ interrupts = <3>;
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/powerpc/fsl/fsl,mpc83xx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale PowerQUICC II Pro (MPC83xx) platforms
+
+maintainers:
+ - J. Neuschäfer <j.ne@posteo.net>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: MPC83xx Reference Design Boards
+ items:
+ - enum:
+ - fsl,mpc8308rdb
+ - fsl,mpc8315erdb
+ - fsl,mpc8360rdk
+ - fsl,mpc8377rdb
+ - fsl,mpc8377wlan
+ - fsl,mpc8378rdb
+ - fsl,mpc8379rdb
+
+ - description: MPC8313E Reference Design Board
+ items:
+ - const: MPC8313ERDB
+ - const: MPC831xRDB
+ - const: MPC83xxRDB
+
+ - description: MPC8323E Reference Design Board
+ items:
+ - const: MPC8323ERDB
+ - const: MPC832xRDB
+ - const: MPC83xxRDB
+
+ - description: MPC8349E-mITX(-GP) Reference Design Platform
+ items:
+ - enum:
+ - MPC8349EMITX
+ - MPC8349EMITXGP
+ - const: MPC834xMITX
+ - const: MPC83xxMITX
+
+ - description: Keymile KMETER1 board
+ const: keymile,KMETER1
+
+ - description: MPC8308 P1M board
+ const: denx,mpc8308_p1m
+
+patternProperties:
+ "^soc@.*$":
+ type: object
+ properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - fsl,mpc8315-immr
+ - fsl,mpc8308-immr
+ - const: simple-bus
+ - items:
+ - const: fsl,mpc8360-immr
+ - const: fsl,immr
+ - const: fsl,soc
+ - const: simple-bus
+ - const: simple-bus
+
+additionalProperties: true
+
+examples:
+ - |
+ / {
+ compatible = "fsl,mpc8315erdb";
+ model = "MPC8315E-RDB";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ soc@e0000000 {
+ compatible = "fsl,mpc8315-immr", "simple-bus";
+ reg = <0xe0000000 0x00000200>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ ranges = <0 0xe0000000 0x00100000>;
+ bus-frequency = <0>;
+ };
+ };
+
+...
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ptp/amazon,vmclock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Virtual Machine Clock
+
+maintainers:
+ - David Woodhouse <dwmw2@infradead.org>
+
+description:
+ The vmclock device provides a precise clock source and allows for
+ accurate timekeeping across live migration and snapshot/restore
+ operations. The full specification of the shared data structure is
+ available at https://uapi-group.org/specifications/specs/vmclock/
+
+properties:
+ compatible:
+ const: amazon,vmclock
+
+ reg:
+ description:
+ Specifies the shared memory region containing the vmclock_abi structure.
+ maxItems: 1
+
+ interrupts:
+ description:
+ Interrupt used to notify when the contents of the vmclock_abi structure
+ have been updated.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ ptp@80000000 {
+ compatible = "amazon,vmclock";
+ reg = <0x80000000 0x1000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>;
+ };
required:
- compatible
- reg
+ - clocks
- '#pwm-cells'
allOf:
examples:
- |
+ #include <dt-bindings/clock/lpc32xx-clock.h>
+
pwm@4005c000 {
compatible = "nxp,lpc3220-pwm";
reg = <0x4005c000 0x4>;
+ clocks = <&clk LPC32XX_CLK_PWM1>;
#pwm-cells = <3>;
};
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/adi,max77675.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX77675 PMIC Regulator
+
+maintainers:
+ - Joan Na <joan.na@analog.com>
+
+description:
+ The MAX77675 is a Power Management IC providing four switching buck
+ regulators (SBB0–SBB3) accessible via I2C. It supports configuration
+ of output voltages and enable controls for each regulator.
+
+allOf:
+ - $ref: /schemas/input/input.yaml
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+
+properties:
+ compatible:
+ const: adi,max77675
+
+ reg:
+ maxItems: 1
+
+ reset-time-sec:
+ description: Manual reset time in seconds
+ enum: [4, 8, 12, 16]
+ default: 4
+
+ bias-disable:
+ type: boolean
+ description: Disable internal pull-up for EN pin
+
+ input-debounce:
+ description: Debounce time for the enable pin, in microseconds
+ items:
+ - enum: [100, 30000]
+ default: 100
+
+ adi,en-mode:
+ description: |
+ Enable mode configuration.
+ The debounce time set by 'input-debounce' applies to
+ both push-button and slide-switch modes.
+ "push-button" - A long press triggers power-on or power-down
+ "slide-switch" - Low : powers on, High : powers down
+ "logic" - Low : powers on, High : powers down (no debounce time)
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [push-button, slide-switch, logic]
+ default: slide-switch
+
+ adi,voltage-change-latency-us:
+ description:
+ Specifies the delay (in microseconds) between an output voltage change
+ request and the start of the SBB voltage ramp.
+ enum: [10, 100]
+ default: 100
+
+ adi,drv-sbb-strength:
+ description: |
+ SIMO Buck-Boost Drive Strength Trim.
+ Controls the drive strength of the SIMO regulator's power MOSFETs.
+ This setting affects switching speed, impacting power efficiency and EMI.
+ "max" – Maximum drive strength (~0.6 ns transition time)
+ "high" – High drive strength (~1.2 ns transition time)
+ "low" – Low drive strength (~1.8 ns transition time)
+ "min" – Minimum drive strength (~8 ns transition time)
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [max, high, low, min]
+ default: max
+
+ adi,dvs-slew-rate-mv-per-us:
+ description:
+ Dynamic rising slew rate for output voltage transitions, in mV/μs.
+ This setting is only used when 'adi,fixed-slew-rate' is not present.
+ enum: [5, 10]
+ default: 5
+
+ adi,bias-low-power-request:
+ type: boolean
+ description: Request low-power bias mode
+
+ adi,simo-ldo-always-on:
+ type: boolean
+ description: Set internal LDO to always supply 1.8V
+
+ regulators:
+ type: object
+ description: Regulator child nodes
+ patternProperties:
+ "^sbb[0-3]$":
+ type: object
+ $ref: regulator.yaml#
+ properties:
+ adi,fps-slot:
+ description: |
+ FPS (Flexible Power Sequencer) slot selection.
+ The Flexible Power Sequencer allows resources to power up under
+ hardware or software control. Additionally, each resource can
+ power up independently or among a group of other regulators with
+ adjustable power-up and power-down slots.
+ "slot0" - Assign to FPS Slot 0
+ "slot1" - Assign to FPS Slot 1
+ "slot2" - Assign to FPS Slot 2
+ "slot3" - Assign to FPS Slot 3
+ "default" - Use the default FPS slot value stored in register
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [slot0, slot1, slot2, slot3, default]
+ default: default
+
+ adi,fixed-slew-rate:
+ type: boolean
+ description:
+ When this property is present, the device uses a constant 2 mV/μs
+ slew rate and ignores any dynamic slew rate configuration.
+ When absent, the device uses the dynamic slew rate specified
+ by 'adi,dvs-slew-rate-mv-per-us'
+
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - regulators
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ max77675: pmic@44 {
+ compatible = "adi,max77675";
+ reg = <0x44>;
+
+ reset-time-sec = <4>;
+ input-debounce = <100>;
+
+ adi,en-mode = "slide-switch";
+ adi,voltage-change-latency-us = <100>;
+ adi,drv-sbb-strength = "max";
+ adi,dvs-slew-rate-mv-per-us = <5>;
+
+ regulators {
+ sbb0: sbb0 {
+ regulator-name = "sbb0";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <5500000>;
+ adi,fps-slot = "default";
+ adi,fixed-slew-rate;
+ };
+
+ sbb1: sbb1 {
+ regulator-name = "sbb1";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <5500000>;
+ adi,fps-slot = "default";
+ adi,fixed-slew-rate;
+ };
+
+ sbb2: sbb2 {
+ regulator-name = "sbb2";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <5500000>;
+ adi,fps-slot = "default";
+ adi,fixed-slew-rate;
+ };
+
+ sbb3: sbb3 {
+ regulator-name = "sbb3";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <5500000>;
+ adi,fps-slot = "default";
+ adi,fixed-slew-rate;
+ };
+ };
+ };
+ };
+
unevaluatedProperties: false
- "^ldo-v(dig18|emc33|ibr|mc|mch|mipi|rtc|sim1|sim2|sram|usb10)$":
+ "^ldo-v(dig18|emc33|ibr|io28|mc|mch|mipi|rtc|sim1|sim2|sram|usb10)$":
type: object
$ref: regulator.yaml#
properties:
regulator-name:
- pattern: "^v(dig18|emc33|ibr|mc|mch|mipi|rtc|sim1|sim2|sram|usb)$"
+ pattern: "^v(dig18|emc33|ibr|io28|mc|mch|mipi|rtc|sim1|sim2|sram|usb)$"
unevaluatedProperties: false
regulator-max-microvolt = <1700000>;
};
mt6359_vrfck_1_ldo_reg: ldo_vrfck_1 {
- regulator-name = "vrfck";
+ regulator-name = "vrfck_1";
regulator-min-microvolt = <1240000>;
regulator-max-microvolt = <1600000>;
};
regulator-max-microvolt = <3300000>;
};
mt6359_vemc_1_ldo_reg: ldo_vemc_1 {
- regulator-name = "vemc";
+ regulator-name = "vemc_1";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3300000>;
};
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/qcom,wcn3990-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. WCN3990 PMU Regulators
+
+maintainers:
+ - Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
+
+description:
+ The WCN3990 package contains discrete modules for WLAN and Bluetooth. They
+ are powered by the Power Management Unit (PMU) that takes inputs from the
+ host and provides LDO outputs. This document describes this module.
+
+properties:
+ compatible:
+ enum:
+ - qcom,wcn3950-pmu
+ - qcom,wcn3988-pmu
+ - qcom,wcn3990-pmu
+ - qcom,wcn3991-pmu
+ - qcom,wcn3998-pmu
+
+ vddio-supply:
+ description: VDD_IO supply regulator handle
+
+ vddxo-supply:
+ description: VDD_XTAL supply regulator handle
+
+ vddrf-supply:
+ description: VDD_RF supply regulator handle
+
+ vddch0-supply:
+ description: chain 0 supply regulator handle
+
+ vddch1-supply:
+ description: chain 1 supply regulator handle
+
+ swctrl-gpios:
+ maxItems: 1
+ description: GPIO line indicating the state of the clock supply to the BT module
+
+ clocks:
+ maxItems: 1
+ description: Reference clock handle
+
+ regulators:
+ type: object
+ description:
+ LDO outputs of the PMU
+
+ patternProperties:
+ "^ldo[0-9]$":
+ $ref: regulator.yaml#
+ type: object
+ unevaluatedProperties: false
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - regulators
+ - vddio-supply
+ - vddxo-supply
+ - vddrf-supply
+ - vddch0-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ pmu {
+ compatible = "qcom,wcn3990-pmu";
+
+ vddio-supply = <&vreg_io>;
+ vddxo-supply = <&vreg_xo>;
+ vddrf-supply = <&vreg_rf>;
+ vddch0-supply = <&vreg_ch0>;
+
+ regulators {
+ vreg_pmu_io: ldo0 {
+ regulator-name = "vreg_pmu_io";
+ };
+
+ vreg_pmu_xo: ldo1 {
+ regulator-name = "vreg_pmu_xo";
+ };
+
+ vreg_pmu_rf: ldo2 {
+ regulator-name = "vreg_pmu_rf";
+ };
+
+ vreg_pmu_ch0: ldo3 {
+ regulator-name = "vreg_pmu_ch0";
+ };
+ };
+ };
reg:
maxItems: 1
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+
additionalProperties: false
required:
offset from voltage set to regulator.
regulator-uv-protection-microvolt:
- description: Set over under voltage protection limit. This is a limit where
+ description: Set under voltage protection limit. This is a limit where
hardware performs emergency shutdown. Zero can be passed to disable
protection and value '1' indicates that protection should be enabled but
limit setting can be omitted. Limit is given as microvolt offset from
is given as microvolt offset from voltage set to regulator.
regulator-uv-warn-microvolt:
- description: Set over under voltage warning limit. This is a limit where
+ description: Set under voltage warning limit. This is a limit where
hardware is assumed still to be functional but approaching limit where
it gets damaged. Recovery actions should be initiated. Zero can be passed
to disable detection and value '1' indicates that detection should
suspend. This property is now deprecated, instead setting voltage
for suspend mode via the API which regulator driver provides is
recommended.
+ deprecated: true
regulator-changeable-in-suspend:
description: whether the default voltage and the regulator on/off
supply of 2.5V to 5.5V. It can provide up to 3.5A continuous current
capability at over 80% high efficiency.
+ The RT8092 is similar type buck converter. Compared to RT5739, it can offer
+ up to 4A output current and more output voltage range to meet the application
+ on most mobile products.
+
allOf:
- $ref: regulator.yaml#
enum:
- richtek,rt5733
- richtek,rt5739
+ - richtek,rt8092
reg:
maxItems: 1
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/rohm,bd72720-regulator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROHM BD72720 Power Management Integrated Circuit regulators
+
+maintainers:
+ - Matti Vaittinen <mazziesaccount@gmail.com>
+
+description: |
+ This module is part of the ROHM BD72720 MFD device. For more details
+ see Documentation/devicetree/bindings/mfd/rohm,bd72720-pmic.yaml.
+
+ The regulator controller is represented as a sub-node of the PMIC node
+ on the device tree.
+
+ Regulator nodes should be named to BUCK_<number> and LDO_<number>.
+ The valid names for BD72720 regulator nodes are
+ buck1, buck2, buck3, buck4, buck5, buck6, buck7, buck8, buck9, buck10
+ ldo1, ldo2, ldo3, ldo4, ldo5, ldo6, ldo7, ldo8, ldo9, ldo10, ldo11
+
+patternProperties:
+ "^ldo([1-9]|1[0-1])$":
+ type: object
+ description:
+ Properties for single LDO regulator.
+ $ref: regulator.yaml#
+
+ properties:
+ regulator-name:
+ pattern: "^ldo([1-9]|1[0-1])$"
+
+ rohm,dvs-run-voltage:
+ description:
+ PMIC default "RUN" state voltage in uV. See below table for
+ LDOs which support this. 0 means disabled.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3300000
+
+ rohm,dvs-idle-voltage:
+ description:
+ PMIC default "IDLE" state voltage in uV. See below table for
+ LDOs which support this. 0 means disabled.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3300000
+
+ rohm,dvs-suspend-voltage:
+ description:
+ PMIC default "SUSPEND" state voltage in uV. See below table for
+ LDOs which support this. 0 means disabled.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3300000
+
+ rohm,dvs-lpsr-voltage:
+ description:
+ PMIC default "deep-idle" state voltage in uV. See below table for
+ LDOs which support this. 0 means disabled.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3300000
+
+ # Supported default DVS states:
+ # ldo | run | idle | suspend | lpsr
+ # --------------------------------------------------------------
+ # 1, 2, 3, and 4 | supported | supported | supported | supported
+ # --------------------------------------------------------------
+ # 5 - 11 | supported (*)
+ # --------------------------------------------------------------
+ #
+ # (*) All states use same voltage but have own enable / disable
+ # settings. Voltage 0 can be specified for a state to make
+ # regulator disabled on that state.
+
+ unevaluatedProperties: false
+
+ "^buck([1-9]|10)$":
+ type: object
+ description:
+ Properties for single BUCK regulator.
+ $ref: regulator.yaml#
+
+ properties:
+ regulator-name:
+ pattern: "^buck([1-9]|10)$"
+
+ rohm,ldon-head-microvolt:
+ description:
+ Set this on boards where BUCK10 is used to supply LDOs 1-4. The bucki
+ voltage will be changed by the PMIC to follow the LDO output voltages
+ with the offset voltage given here. This will improve the LDO efficiency.
+ minimum: 50000
+ maximum: 300000
+
+ rohm,dvs-run-voltage:
+ description:
+ PMIC default "RUN" state voltage in uV. See below table for
+ bucks which support this. 0 means disabled.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3300000
+
+ rohm,dvs-idle-voltage:
+ description:
+ PMIC default "IDLE" state voltage in uV. See below table for
+ bucks which support this. 0 means disabled.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3300000
+
+ rohm,dvs-suspend-voltage:
+ description:
+ PMIC default "SUSPEND" state voltage in uV. See below table for
+ bucks which support this. 0 means disabled.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3300000
+
+ rohm,dvs-lpsr-voltage:
+ description:
+ PMIC default "deep-idle" state voltage in uV. See below table for
+ bucks which support this. 0 means disabled.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3300000
+
+ # Supported default DVS states:
+ # buck | run | idle | suspend | lpsr
+ # --------------------------------------------------------------
+ # 1, 2, 3, and 4 | supported | supported | supported | supported
+ # --------------------------------------------------------------
+ # 5 - 10 | supported (*)
+ # --------------------------------------------------------------
+ #
+ # (*) All states use same voltage but have own enable / disable
+ # settings. Voltage 0 can be specified for a state to make
+ # regulator disabled on that state.
+
+ required:
+ - regulator-name
+
+ unevaluatedProperties: false
+
+additionalProperties: false
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/samsung,s2mpg10-regulator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S2MPG10 Power Management IC regulators
+
+maintainers:
+ - André Draszik <andre.draszik@linaro.org>
+
+description: |
+ This is part of the device tree bindings for the S2MG10 Power Management IC
+ (PMIC).
+
+ The S2MPG10 PMIC provides 10 buck and 31 LDO regulators.
+
+ See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for
+ additional information and example.
+
+properties:
+ # 1 LDO with possible (but limited) external control
+ ldo20m:
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+ description:
+ Properties for a single LDO regulator.
+
+ allOf:
+ - $ref: "#/$defs/s2mpg10-ext-control"
+
+ properties:
+ regulator-ramp-delay: false
+
+ samsung,ext-control:
+ minimum: 11
+
+patternProperties:
+ # 10 bucks
+ "^buck([1-9]|10)m$":
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+ description:
+ Properties for a single buck regulator.
+
+ allOf:
+ - $ref: "#/$defs/s2mpg10-ext-control"
+
+ properties:
+ regulator-ramp-delay:
+ enum: [6250, 12500, 25000]
+ default: 6250
+
+ samsung,ext-control:
+ maximum: 10
+
+ # 12 standard LDOs
+ "^ldo(2[1-9]?|3[0-1])m$":
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+ description:
+ Properties for single LDO regulator.
+
+ properties:
+ regulator-ramp-delay: false
+
+ # 12 LDOs with possible external control
+ "^ldo([3-689]|1[046-9])m$":
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+ description:
+ Properties for a single LDO regulator.
+
+ allOf:
+ - $ref: "#/$defs/s2mpg10-ext-control"
+
+ properties:
+ regulator-ramp-delay: false
+
+ samsung,ext-control:
+ maximum: 10
+
+ # 6 LDOs with ramp support, 5 out of those with possible external control
+ "^ldo(1[1235]?|7)m$":
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+ description:
+ Properties for a single LDO regulator.
+
+ allOf:
+ - $ref: "#/$defs/s2mpg10-ext-control"
+
+ properties:
+ regulator-ramp-delay:
+ enum: [6250, 12500]
+ default: 6250
+
+ samsung,ext-control:
+ maximum: 10
+
+$defs:
+ s2mpg10-ext-control:
+ properties:
+ samsung,ext-control:
+ description: |
+ These rails can be controlled via one of several possible external
+ (hardware) signals. If so, this property configures the signal the PMIC
+ should monitor. For S2MPG10 rails where external control is possible other
+ than ldo20m, the following values generally corresponding to the
+ respective on-chip pin are valid:
+ - 0 # S2MPG10_EXTCTRL_PWREN - PWREN pin
+ - 1 # S2MPG10_EXTCTRL_PWREN_MIF - PWREN_MIF pin
+ - 2 # S2MPG10_EXTCTRL_AP_ACTIVE_N - ~AP_ACTIVE_N pin
+ - 3 # S2MPG10_EXTCTRL_CPUCL1_EN - CPUCL1_EN pin
+ - 4 # S2MPG10_EXTCTRL_CPUCL1_EN2 - CPUCL1_EN & PWREN pins
+ - 5 # S2MPG10_EXTCTRL_CPUCL2_EN - CPUCL2_EN pin
+ - 6 # S2MPG10_EXTCTRL_CPUCL2_EN2 - CPUCL2_E2 & PWREN pins
+ - 7 # S2MPG10_EXTCTRL_TPU_EN - TPU_EN pin
+ - 8 # S2MPG10_EXTCTRL_TPU_EN2 - TPU_EN & ~AP_ACTIVE_N pins
+ - 9 # S2MPG10_EXTCTRL_TCXO_ON - TCXO_ON pin
+ - 10 # S2MPG10_EXTCTRL_TCXO_ON2 - TCXO_ON & ~AP_ACTIVE_N pins
+
+ For S2MPG10 ldo20m, the following values are valid
+ - 11 # S2MPG10_EXTCTRL_LDO20M_EN2 - VLDO20M_EN & LDO20M_SFR
+ - 12 # S2MPG10_EXTCTRL_LDO20M_EN - VLDO20M_EN pin
+
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 12
+
+ enable-gpios:
+ description:
+ For rails where external control is done via a GPIO, this optional
+ property describes the GPIO line used.
+
+ dependentRequired:
+ enable-gpios: [ "samsung,ext-control" ]
+
+allOf:
+ # Bucks 8, 9, and LDO 1 can not be controlled externally - above definition
+ # allows it and we deny it here. This approach reduces repetition.
+ - if:
+ anyOf:
+ - required: [buck8m]
+ - required: [buck9m]
+ - required: [ldo1m]
+ then:
+ patternProperties:
+ "^(buck[8-9]|ldo1)m$":
+ properties:
+ samsung,ext-control: false
+
+additionalProperties: false
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/samsung,s2mpg11-regulator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S2MPG11 Power Management IC regulators
+
+maintainers:
+ - André Draszik <andre.draszik@linaro.org>
+
+description: |
+ This is part of the device tree bindings for the S2MG11 Power Management IC
+ (PMIC).
+
+ The S2MPG11 PMIC provides 12 buck, 1 buck-boost, and 15 LDO regulators.
+
+ See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for
+ additional information and example.
+
+properties:
+ buckboost:
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+ description:
+ Properties for the buck-boost regulator.
+
+ properties:
+ regulator-ramp-delay: false
+
+patternProperties:
+ # 12 bucks
+ "^buck(([1-9]|10)s|[ad])$":
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+ description:
+ Properties for a single buck regulator.
+
+ allOf:
+ - $ref: "#/$defs/s2mpg11-ext-control"
+
+ properties:
+ regulator-ramp-delay:
+ enum: [6250, 12500, 25000]
+ default: 6250
+
+ # 11 standard LDOs
+ "^ldo([3-79]|1[01245])s$":
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+ description:
+ Properties for a single LDO regulator.
+
+ properties:
+ regulator-ramp-delay: false
+
+ # 2 LDOs with possible external control
+ "^ldo(8|13)s$":
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+ description:
+ Properties for single LDO regulator.
+
+ allOf:
+ - $ref: "#/$defs/s2mpg11-ext-control"
+
+ properties:
+ regulator-ramp-delay: false
+
+ # 2 LDOs with ramp support and possible external control
+ "^ldo[12]s$":
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+ description:
+ Properties for a single LDO regulator.
+
+ allOf:
+ - $ref: "#/$defs/s2mpg11-ext-control"
+
+ properties:
+ regulator-ramp-delay:
+ enum: [6250, 12500]
+ default: 6250
+
+$defs:
+ s2mpg11-ext-control:
+ properties:
+ samsung,ext-control:
+ description: |
+ These rails can be controlled via one of several possible external
+ (hardware) signals. If so, this property configures the signal the PMIC
+ should monitor. The following values generally corresponding to the
+ respective on-chip pin are valid:
+ - 0 # S2MPG11_EXTCTRL_PWREN - PWREN pin
+ - 1 # S2MPG11_EXTCTRL_PWREN_MIF - PWREN_MIF pin
+ - 2 # S2MPG11_EXTCTRL_AP_ACTIVE_N - ~AP_ACTIVE_N pin
+ - 3 # S2MPG11_EXTCTRL_G3D_EN - G3D_EN pin
+ - 4 # S2MPG11_EXTCTRL_G3D_EN2 - G3D_EN & ~AP_ACTIVE_N pins
+ - 5 # S2MPG11_EXTCTRL_AOC_VDD - AOC_VDD pin
+ - 6 # S2MPG11_EXTCTRL_AOC_RET - AOC_RET pin
+ - 7 # S2MPG11_EXTCTRL_UFS_EN - UFS_EN pin
+ - 8 # S2MPG11_EXTCTRL_LDO13S_EN - VLDO13S_EN pin
+
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 8
+
+ enable-gpios:
+ description:
+ For rails where external control is done via a GPIO, this optional
+ property describes the GPIO line used.
+
+ dependentRequired:
+ enable-gpios: [ "samsung,ext-control" ]
+
+allOf:
+ # Bucks 4, 6, 7 and 10 can not be controlled externally - above definition
+ # allows it and we deny it here. This approach reduces repetition.
+ - if:
+ anyOf:
+ - required: [buck4s]
+ - required: [buck6s]
+ - required: [buck7s]
+ - required: [buck10s]
+ then:
+ patternProperties:
+ "^buck([467]|10)s$":
+ properties:
+ samsung,ext-control: false
+
+additionalProperties: false
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/ti,tps65185.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI TPS65185 Power Management Integrated Circuit
+
+maintainers:
+ - Andreas Kemnade <andreas@kemnade.info>
+
+description:
+ TPS65185 is a Power Management IC to provide Power for EPDs with one 3.3V
+ switch, 2 symmetric LDOs behind 2 DC/DC converters, and one unsymmetric
+ regulator for a compensation voltage.
+
+properties:
+ compatible:
+ const: ti,tps65185
+
+ reg:
+ maxItems: 1
+
+ enable-gpios:
+ description:
+ PWRUP pin
+ maxItems: 1
+
+ pwr-good-gpios:
+ maxItems: 1
+
+ vcom-ctrl-gpios:
+ maxItems: 1
+
+ wakeup-gpios:
+ maxItems: 1
+
+ vin-supply: true
+
+ interrupts:
+ maxItems: 1
+
+ regulators:
+ type: object
+ additionalProperties: false
+ patternProperties:
+ "^(vcom|vposneg|v3p3)$":
+ unevaluatedProperties: false
+ type: object
+ $ref: /schemas/regulator/regulator.yaml
+
+required:
+ - compatible
+ - reg
+ - pwr-good-gpios
+ - vin-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic@18 {
+ compatible = "ti,tps65185";
+ reg = <0x18>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tps65185_gpio>;
+ pwr-good-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+ vcom-ctrl-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
+ wakeup-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&epdc_pmic_supply>;
+ interrupts-extended = <&gpio2 0 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ vcom {
+ regulator-name = "vcom";
+ };
+
+ vposneg {
+ regulator-name = "vposneg";
+ regulator-min-microvolt = <15000000>;
+ regulator-max-microvolt = <15000000>;
+ };
+
+ v3p3 {
+ regulator-name = "v3p3";
+ };
+ };
+ };
+ };
- fsl,imx8qxp-cm4
- fsl,imx8ulp-cm33
- fsl,imx93-cm33
+ - fsl,imx95-cm7
clocks:
maxItems: 1
title: Mediatek SCP
maintainers:
- - Tinghan Shen <tinghan.shen@mediatek.com>
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
description:
This binding provides support for ARM Cortex M4 Co-processor found on some
reg:
maxItems: 1
+ cx-supply: true
+
px-supply:
description: Phandle to the PX regulator
items:
- const: lcx
- const: lmx
+ else:
+ properties:
+ cx-supply: false
- if:
properties:
- const: stop-ack
- const: shutdown-ack
+ iommus:
+ maxItems: 1
+
power-domains:
minItems: 1
maxItems: 3
enum:
- qcom,sm8550-adsp-pas
- qcom,sm8650-adsp-pas
- - qcom,sm8750-adsp-pas
- qcom,x1e80100-adsp-pas
then:
properties:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/remoteproc/ti,hsm-m4fss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI K3 HSM M4F processor subsystems
+
+maintainers:
+ - Beleswar Padhi <b-padhi@ti.com>
+
+description: |
+ Some K3 family SoCs have a HSM (High Security Module) M4F core in the
+ Wakeup Voltage Domain which could be used to run secure services like
+ Authentication. Some of those are J721S2, J784S4, J722S, AM62X.
+
+$ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ti,hsm-m4fss
+
+ reg:
+ items:
+ - description: SRAM0_0 internal memory region
+ - description: SRAM0_1 internal memory region
+ - description: SRAM1 internal memory region
+
+ reg-names:
+ items:
+ - const: sram0_0
+ - const: sram0_1
+ - const: sram1
+
+ resets:
+ maxItems: 1
+
+ firmware-name:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - resets
+ - firmware-name
+ - ti,sci
+ - ti,sci-dev-id
+ - ti,sci-proc-ids
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ remoteproc@43c00000 {
+ compatible = "ti,hsm-m4fss";
+ reg = <0x00 0x43c00000 0x00 0x20000>,
+ <0x00 0x43c20000 0x00 0x10000>,
+ <0x00 0x43c30000 0x00 0x10000>;
+ reg-names = "sram0_0", "sram0_1", "sram1";
+ resets = <&k3_reset 225 1>;
+ firmware-name = "hsm.bin";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <225>;
+ ti,sci-proc-ids = <0x80 0xff>;
+ };
+ };
- kick-gpios: Should specify the gpio device needed for the virtio IPC
stack. This will be used to interrupt the remote processor.
The gpio device to be used is as per the bindings in,
- Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt
+ Documentation/devicetree/bindings/gpio/ti,keystone-dsp-gpio.yaml
SoC-specific Required properties:
---------------------------------
- sifive,u7
- sifive,u74
- sifive,u74-mc
+ - spacemit,x100
- spacemit,x60
- thead,c906
- thead,c908
ratified states, with the exception of the I, Zicntr & Zihpm extensions.
See the "i" property for more information.
-select:
- properties:
- compatible:
- contains:
- const: riscv
-
properties:
riscv,isa:
description:
The standard C extension for compressed instructions, as ratified in
the 20191213 version of the unprivileged ISA specification.
+ - const: b
+ description:
+ The standard B extension for bit manipulation instructions, as
+ ratified in the 20240411 version of the unprivileged ISA
+ specification. The B standard extension comprises instructions
+ provided by the Zba, Zbb, and Zbs extensions.
+
- const: v
description:
The standard V extension for vector operations, as ratified
- const: h
description:
- The standard H extension for hypervisors as ratified in the 20191213
- version of the privileged ISA specification.
+ The standard H extension for hypervisors as ratified in the RISC-V
+ Instruction Set Manual, Volume II Privileged Architecture,
+ Document Version 20211203.
# multi-letter extensions, sorted alphanumerically
+ - const: sha
+ description: |
+ The standard Sha extension for augmented hypervisor extension as
+ ratified in RVA23 Profiles Version 1.0, with commit 0273f3c921b6
+ ("rva23/rvb23 ratified").
+
+ Sha captures the full set of features that are mandated to be
+ supported along with the H extension. Sha comprises the following
+ extensions: H, Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala,
+ Shvstvecd, and Ssstateen.
+
+ - const: shcounterenw
+ description: |
+ The standard Shcounterenw extension for support writable enables
+ in hcounteren for any supported counter, as ratified in RISC-V
+ Profiles Version 1.0, with commit b1d806605f87 ("Updated to
+ ratified state.")
+
+ - const: shgatpa
+ description: |
+ The standard Shgatpa extension indicates that for each supported
+ virtual memory scheme SvNN supported in satp, the corresponding
+ hgatp SvNNx4 mode must be supported. The hgatp mode Bare must
+ also be supported. It is ratified in RISC-V Profiles Version 1.0,
+ with commit b1d806605f87 ("Updated to ratified state.")
+
+ - const: shtvala
+ description: |
+ The standard Shtvala extension for htval be written with the
+ faulting guest physical address in all circumstances permitted by
+ the ISA. It is ratified in RISC-V Profiles Version 1.0, with
+ commit b1d806605f87 ("Updated to ratified state.")
+
+ - const: shvsatpa
+ description: |
+ The standard Shvsatpa extension for vsatp supporting all translation
+ modes supported in satp, as ratified in RISC-V Profiles Version 1.0,
+ with commit b1d806605f87 ("Updated to ratified state.")
+
+ - const: shvstvala
+ description: |
+ The standard Shvstvala extension for vstval provides all needed
+ values as ratified in RISC-V Profiles Version 1.0, with commit
+ b1d806605f87 ("Updated to ratified state.")
+
+ - const: shvstvecd
+ description: |
+ The standard Shvstvecd extension for vstvec supporting Direct mode,
+ as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
+ ("Updated to ratified state.")
+
- const: smaia
description: |
The standard Smaia supervisor-level extension for the advanced
behavioural changes to interrupts as frozen at commit ccbddab
("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
+ - const: ssccptr
+ description: |
+ The standard Ssccptr extension for main memory (cacheability and
+ coherence) hardware page-table reads, as ratified in RISC-V
+ Profiles Version 1.0, with commit b1d806605f87 ("Updated to
+ ratified state.")
+
- const: sscofpmf
description: |
The standard Sscofpmf supervisor-level extension for count overflow
and mode-based filtering as ratified at commit 01d1df0 ("Add ability
to manually trigger workflow. (#2)") of riscv-count-overflow.
+ - const: sscounterenw
+ description: |
+ The standard Sscounterenw extension for support writable enables
+ in scounteren for any supported counter, as ratified in RISC-V
+ Profiles Version 1.0, with commit b1d806605f87 ("Updated to
+ ratified state.")
+
- const: ssnpm
description: |
The standard Ssnpm extension for next-mode pointer masking as
ratified at commit d70011dde6c2 ("Update to ratified state")
of riscv-j-extension.
+ - const: ssstateen
+ description: |
+ The standard Ssstateen extension for supervisor-mode view of the
+ state-enable extension, as ratified in RISC-V Profiles Version 1.0,
+ with commit b1d806605f87 ("Updated to ratified state.")
+
- const: sstc
description: |
The standard Sstc supervisor-level extension for time compare as
ratified at commit 3f9ed34 ("Add ability to manually trigger
workflow. (#2)") of riscv-time-compare.
+ - const: sstvala
+ description: |
+ The standard Sstvala extension for stval provides all needed values
+ as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
+ ("Updated to ratified state.")
+
+ - const: sstvecd
+ description: |
+ The standard Sstvecd extension for stvec supports Direct mode as
+ ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
+ ("Updated to ratified state.")
+
+ - const: ssu64xl
+ description: |
+ The standard Ssu64xl extension for UXLEN=64 must be supported, as
+ ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
+ ("Updated to ratified state.")
+
- const: svade
description: |
The standard Svade supervisor-level extension for SW-managed PTE A/D
- const: svinval
description:
The standard Svinval supervisor-level extension for fine-grained
- address-translation cache invalidation as ratified in the 20191213
- version of the privileged ISA specification.
+ address-translation cache invalidation as ratified in the RISC-V
+ Instruction Set Manual, Volume II Privileged Architecture,
+ Document Version 20211203.
- const: svnapot
description:
The standard Svnapot supervisor-level extensions for napot
- translation contiguity as ratified in the 20191213 version of the
- privileged ISA specification.
+ translation contiguity as ratified in the RISC-V Instruction Set
+ Manual, Volume II Privileged Architecture, Document Version
+ 20211203.
- const: svpbmt
description:
The standard Svpbmt supervisor-level extensions for page-based
- memory types as ratified in the 20191213 version of the privileged
- ISA specification.
+ memory types as ratified in the RISC-V Instruction Set Manual,
+ Volume II Privileged Architecture, Document Version 20211203.
- const: svrsw60t59b
description:
as ratified at commit 4a69197e5617 ("Update to ratified state") of
riscv-svvptc.
+ - const: za64rs
+ description:
+ The standard Za64rs extension for reservation set size of at most
+ 64 bytes, as ratified in RISC-V Profiles Version 1.0, with commit
+ b1d806605f87 ("Updated to ratified state.")
+
- const: zaamo
description: |
The standard Zaamo extension for atomic memory operations as
in commit 64074bc ("Update version numbers for Zfh/Zfinx") of
riscv-isa-manual.
+ - const: ziccamoa
+ description:
+ The standard Ziccamoa extension for main memory (cacheability and
+ coherence) must support all atomics in A, as ratified in RISC-V
+ Profiles Version 1.0, with commit b1d806605f87 ("Updated to
+ ratified state.")
+
+ - const: ziccif
+ description:
+ The standard Ziccif extension for main memory (cacheability and
+ coherence) instruction fetch atomicity, as ratified in RISC-V
+ Profiles Version 1.0, with commit b1d806605f87 ("Updated to
+ ratified state.")
+
+ - const: zicclsm
+ description:
+ The standard Zicclsm extension for main memory (cacheability and
+ coherence) must support misaligned loads and stores, as ratified
+ in RISC-V Profiles Version 1.0, with commit b1d806605f87 ("Updated
+ to ratified state.")
+
- const: ziccrse
description:
The standard Ziccrse extension which provides forward progress
The standard Zicboz extension for cache-block zeroing as ratified
in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
+ - const: zicfilp
+ description: |
+ The standard Zicfilp extension for enforcing forward edge
+ control-flow integrity as ratified in commit 3f8e450 ("merge
+ pull request #227 from ved-rivos/0709") of riscv-cfi
+ github repo.
+
+ - const: zicfiss
+ description: |
+ The standard Zicfiss extension for enforcing backward edge
+ control-flow integrity as ratified in commit 3f8e450 ("merge
+ pull request #227 from ved-rivos/0709") of riscv-cfi
+ github repo.
+
- const: zicntr
description:
The standard Zicntr extension for base counters and timers, as
then:
contains:
const: f
+ # B comprises Zba, Zbb, and Zbs
+ - if:
+ contains:
+ const: b
+ then:
+ allOf:
+ - contains:
+ const: zba
+ - contains:
+ const: zbb
+ - contains:
+ const: zbs
+ # Zba, Zbb, Zbs together require B
+ - if:
+ allOf:
+ - contains:
+ const: zba
+ - contains:
+ const: zbb
+ - contains:
+ const: zbs
+ then:
+ contains:
+ const: b
+ # Za64rs and Ziccrse depend on Zalrsc or A
+ - if:
+ contains:
+ anyOf:
+ - const: za64rs
+ - const: ziccrse
+ then:
+ oneOf:
+ - contains:
+ const: zalrsc
+ - contains:
+ const: a
# Zcb depends on Zca
- if:
contains:
then:
contains:
const: f
+ # Ziccamoa depends on Zaamo or A
+ - if:
+ contains:
+ const: ziccamoa
+ then:
+ oneOf:
+ - contains:
+ const: zaamo
+ - contains:
+ const: a
# Zvfbfmin depends on V or Zve32f
- if:
contains:
title: SpacemiT SoC-based boards
maintainers:
+ - Guodong Xu <guodong@riscstar.com>
- Yangyu Chen <cyy@cyyself.name>
- Yixun Lan <dlan@gentoo.org>
- xunlong,orangepi-r2s
- xunlong,orangepi-rv2
- const: spacemit,k1
+ - items:
+ - enum:
+ - spacemit,k3-pico-itx
+ - const: spacemit,k3
additionalProperties: true
- starfive,visionfive-2-lite
- starfive,visionfive-2-lite-emmc
- const: starfive,jh7110s
+ - const: starfive,jh7110
additionalProperties: true
properties:
compatible:
- enum:
- - samsung,exynos5250-trng
- - samsung,exynos850-trng
+ oneOf:
+ - enum:
+ - samsung,exynos5250-trng
+ - samsung,exynos850-trng
+ - items:
+ - const: google,gs101-trng
+ - const: samsung,exynos850-trng
clocks:
minItems: 1
minItems: 1
maxItems: 2
+ power-domains:
+ maxItems: 1
+
reg:
maxItems: 1
+++ /dev/null
-Motorola CPCAP PMIC RTC
------------------------
-
-This module is part of the CPCAP. For more details about the whole
-chip see Documentation/devicetree/bindings/mfd/motorola-cpcap.txt.
-
-Requires node properties:
-- compatible: should contain "motorola,cpcap-rtc"
-- interrupts: An interrupt specifier for alarm and 1 Hz irq
-
-Example:
-
-&cpcap {
- cpcap_rtc: rtc {
- compatible = "motorola,cpcap-rtc";
- interrupts = <39 IRQ_TYPE_NONE>, <26 IRQ_TYPE_NONE>;
- };
-};
- loongson,ls1b-rtc
- loongson,ls1c-rtc
- loongson,ls7a-rtc
+ - loongson,ls2k0300-rtc
- loongson,ls2k1000-rtc
- items:
- enum:
unevaluatedProperties: false
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - loongson,ls1c-rtc
+ - loongson,ls2k0300-rtc
+
+then:
+ properties:
+ interrupts: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/motorola,cpcap-rtc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Motorola CPCAP PMIC RTC
+
+maintainers:
+ - Svyatoslav Ryhel <clamor95@gmail.com>
+
+description:
+ This module is part of the Motorola CPCAP MFD device. For more details
+ see Documentation/devicetree/bindings/mfd/motorola,cpcap.yaml. The
+ RTC is represented as a sub-node of the PMIC node on the device tree.
+
+properties:
+ compatible:
+ const: motorola,cpcap-rtc
+
+ interrupts:
+ items:
+ - description: alarm interrupt
+ - description: 1 Hz interrupt
+
+required:
+ - compatible
+ - interrupts
+
+additionalProperties: false
+
+...
items:
- enum:
- renesas,r9a08g045-rtca3 # RZ/G3S
+ - renesas,r9a09g056-rtca3 # RZ/V2N
- renesas,r9a09g057-rtca3 # RZ/V2H
- const: renesas,rz-rtca3
properties:
compatible:
contains:
- const: renesas,r9a09g057-rtca3
+ enum:
+ - renesas,r9a09g056-rtca3
+ - renesas,r9a09g057-rtca3
then:
properties:
resets:
- enum:
- mrvl,mmp-uart
- spacemit,k1-uart
+ - spacemit,k3-uart
- const: intel,xscale-uart
- items:
- enum:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/google,goldfish-tty.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google Goldfish TTY
+
+maintainers:
+ - Kuan-Wei Chiu <visitorckw@gmail.com>
+
+allOf:
+ - $ref: /schemas/serial/serial.yaml#
+
+description:
+ Android goldfish TTY device generated by Android emulator.
+
+properties:
+ compatible:
+ const: google,goldfish-tty
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ serial@1f004000 {
+ compatible = "google,goldfish-tty";
+ reg = <0x1f004000 0x1000>;
+ interrupts = <12>;
+ };
- Geert Uytterhoeven <geert+renesas@glider.be>
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
-allOf:
- - $ref: serial.yaml#
-
properties:
compatible:
oneOf:
+ - enum:
+ - renesas,r9a09g047-rsci # RZ/G3E
+ - renesas,r9a09g077-rsci # RZ/T2H
+
- items:
- - const: renesas,r9a09g087-rsci # RZ/N2H
- - const: renesas,r9a09g077-rsci # RZ/T2H
+ - enum:
+ - renesas,r9a09g056-rsci # RZ/V2N
+ - renesas,r9a09g057-rsci # RZ/V2H(P)
+ - const: renesas,r9a09g047-rsci
- items:
+ - const: renesas,r9a09g087-rsci # RZ/N2H
- const: renesas,r9a09g077-rsci # RZ/T2H
reg:
maxItems: 1
interrupts:
+ minItems: 4
items:
- description: Error interrupt
- description: Receive buffer full interrupt
- description: Transmit buffer empty interrupt
- description: Transmit end interrupt
+ - description: Active edge detection interrupt
+ - description: Break field detection interrupt
interrupt-names:
+ minItems: 4
items:
- const: eri
- const: rxi
- const: txi
- const: tei
+ - const: aed
+ - const: bfd
clocks:
minItems: 2
- maxItems: 3
+ maxItems: 6
clock-names:
- minItems: 2
+ oneOf:
+ - items:
+ - const: operation
+ - const: bus
+ - const: sck # optional external clock input
+
+ minItems: 2
+
+ - items:
+ - const: pclk
+ - const: tclk
+ - const: tclk_div4
+ - const: tclk_div16
+ - const: tclk_div64
+ - const: sck # optional external clock input
+
+ minItems: 5
+
+ resets:
items:
- - const: operation
- - const: bus
- - const: sck # optional external clock input
+ - description: Input for resetting the APB clock
+ - description: Input for resetting TCLK
+
+ reset-names:
+ items:
+ - const: presetn
+ - const: tresetn
power-domains:
maxItems: 1
- clock-names
- power-domains
+allOf:
+ - $ref: serial.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g077-rsci
+ then:
+ properties:
+ interrupts:
+ maxItems: 4
+
+ interrupt-names:
+ maxItems: 4
+
+ clocks:
+ minItems: 2
+ maxItems: 3
+
+ clock-names:
+ minItems: 2
+ maxItems: 3
+
+ resets: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g047-rsci
+ then:
+ properties:
+ interrupts:
+ minItems: 6
+
+ interrupt-names:
+ minItems: 6
+
+ clocks:
+ minItems: 5
+ maxItems: 6
+
+ clock-names:
+ minItems: 5
+ maxItems: 6
+
+ required:
+ - resets
+ - reset-names
+
unevaluatedProperties: false
examples:
properties:
compatible:
oneOf:
+ - enum:
+ - renesas,scif-r7s9210 # RZ/A2
+ - renesas,scif-r9a07g044 # RZ/G2{L,LC}
+ - renesas,scif-r9a09g057 # RZ/V2H(P)
+
- items:
- enum:
- renesas,scif-r7s72100 # RZ/A1H
- const: renesas,scif # generic SCIF compatible UART
- - items:
- - enum:
- - renesas,scif-r7s9210 # RZ/A2
-
- items:
- enum:
- renesas,scif-r8a7778 # R-Car M1
- const: renesas,rcar-gen5-scif # R-Car Gen5
- const: renesas,scif # generic SCIF compatible UART
- - items:
- - enum:
- - renesas,scif-r9a07g044 # RZ/G2{L,LC}
-
- items:
- enum:
- renesas,scif-r9a07g043 # RZ/G2UL and RZ/Five
- renesas,scif-r9a07g054 # RZ/V2L
- renesas,scif-r9a08g045 # RZ/G3S
+ - renesas,scif-r9a08g046 # RZ/G3L
- const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback
- - const: renesas,scif-r9a09g057 # RZ/V2H(P)
-
- items:
- enum:
- renesas,scif-r9a09g047 # RZ/G3E
compatible:
oneOf:
- description: Cyclone5/Arria5/Arria10
- const: altr,sys-mgr
+ items:
+ - const: altr,sys-mgr
+ - const: syscon
- description: Stratix10 SoC
items:
- const: altr,sys-mgr-s10
examples:
- |
sysmgr@ffd08000 {
- compatible = "altr,sys-mgr";
+ compatible = "altr,sys-mgr", "syscon";
reg = <0xffd08000 0x1000>;
cpu1-start-addr = <0xffd080c4>;
};
maxItems: 1
description: DVFSRC common register address and length.
+ clocks:
+ items:
+ - description: Clock that drives the DVFSRC MCU
+
regulators:
type: object
$ref: /schemas/regulator/mediatek,mt6873-dvfsrc-regulator.yaml#
examples:
- |
+ #include <dt-bindings/clock/mt8195-clk.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
system-controller@10012000 {
compatible = "mediatek,mt8195-dvfsrc";
reg = <0 0x10012000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_DVFSRC>;
regulators {
compatible = "mediatek,mt8195-dvfsrc-regulator";
type: object
$ref: /schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml
+ pinctrl@204:
+ type: object
+ $ref: /schemas/pinctrl/microchip,mpfs-pinctrl-mssio.yaml
+
required:
- compatible
- reg
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/renesas/renesas,rzn1-gpioirqmux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/N1 SoCs GPIO Interrupt Multiplexer
+
+description: |
+ The Renesas RZ/N1 GPIO Interrupt Multiplexer multiplexes GPIO interrupt
+ lines to the interrupt controller available in the SoC.
+
+ It selects up to 8 of the 96 GPIO interrupt lines available and connect them
+ to 8 output interrupt lines.
+
+maintainers:
+ - Herve Codina <herve.codina@bootlin.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a06g032-gpioirqmux
+ - const: renesas,rzn1-gpioirqmux
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 0
+
+ "#interrupt-cells":
+ const: 1
+
+ interrupt-map-mask:
+ items:
+ - const: 0x7f
+
+ interrupt-map:
+ description: |
+ Specifies the mapping from external GPIO interrupt lines to the output
+ interrupts. The array has up to 8 items defining the mapping related to
+ the output line 0 (GIC 103) up to the output line 7 (GIC 110).
+
+ The child interrupt number set in arrays items is computed using the
+ following formula:
+ gpio_bank * 32 + gpio_number
+ with:
+ - gpio_bank: The GPIO bank number
+ - 0 for GPIO0A,
+ - 1 for GPIO1A,
+ - 2 for GPIO2A
+ - gpio_number: Number of the gpio in the bank (0..31)
+ minItems: 1
+ maxItems: 8
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#interrupt-cells"
+ - interrupt-map-mask
+ - interrupt-map
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ gic: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <3>;
+ };
+
+ interrupt-controller@51000480 {
+ compatible = "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioirqmux";
+ reg = <0x51000480 0x20>;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x7f>;
+ interrupt-map =
+ <32 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* line 0, GPIO1A.0 */
+ <89 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* line 1, GPIO2A.25 */
+ <9 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; /* line 3, GPIO0A.9 */
+ };
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
-# Custom select to avoid matching all nodes with 'syscon'
-select:
- properties:
- compatible:
- contains:
- enum:
- - google,gs101-pmu
- - samsung,exynos3250-pmu
- - samsung,exynos4210-pmu
- - samsung,exynos4212-pmu
- - samsung,exynos4412-pmu
- - samsung,exynos5250-pmu
- - samsung,exynos5260-pmu
- - samsung,exynos5410-pmu
- - samsung,exynos5420-pmu
- - samsung,exynos5433-pmu
- - samsung,exynos7-pmu
- - samsung,exynos850-pmu
- - samsung-s5pv210-pmu
- required:
- - compatible
-
properties:
compatible:
oneOf:
+ - enum:
+ - google,gs101-pmu
- items:
- enum:
- - google,gs101-pmu
- samsung,exynos3250-pmu
- samsung,exynos4210-pmu
- samsung,exynos4212-pmu
- const: syscon
- items:
- enum:
+ - axis,artpec9-pmu
- samsung,exynos2200-pmu
- samsung,exynos7870-pmu
- samsung,exynos7885-pmu
- items:
- enum:
- google,gs101-apm-sysreg
+ - google,gs101-dpu-sysreg
- google,gs101-hsi0-sysreg
- google,gs101-hsi2-sysreg
- google,gs101-misc-sysreg
compatible:
contains:
enum:
+ - google,gs101-dpu-sysreg
- google,gs101-hsi0-sysreg
- google,gs101-hsi2-sysreg
- google,gs101-misc-sysreg
$id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-syscon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: SpacemiT K1 SoC System Controller
+title: SpacemiT K1/K3 SoC System Controller
maintainers:
- Haylen Chu <heylenay@4d2.org>
description:
- System controllers found on SpacemiT K1 SoC, which are capable of
+ System controllers found on SpacemiT K1/K3 SoC, which are capable of
clock, reset and power-management functions.
properties:
- spacemit,k1-syscon-rcpu
- spacemit,k1-syscon-rcpu2
- spacemit,k1-syscon-apbc2
+ - spacemit,k3-syscon-apbc
+ - spacemit,k3-syscon-apmu
+ - spacemit,k3-syscon-dciu
+ - spacemit,k3-syscon-mpmu
reg:
maxItems: 1
"#clock-cells":
const: 1
description:
- See <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
+ For K1 SoC, check <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
+ For K3 SoC, check <dt-bindings/clock/spacemit,k3-clocks.h> for valid indices.
"#power-domain-cells":
const: 1
"#reset-cells":
const: 1
+ description: |
+ ID of the reset controller line. Valid IDs are defined in corresponding
+ files:
+
+ For SpacemiT K1, see include/dt-bindings/clock/spacemit,k1-syscon.h
+ For SpacemiT K3, see include/dt-bindings/reset/spacemit,k3-resets.h
required:
- compatible
enum:
- spacemit,k1-syscon-apmu
- spacemit,k1-syscon-mpmu
+ - spacemit,k3-syscon-apmu
+ - spacemit,k3-syscon-mpmu
then:
required:
- "#power-domain-cells"
- spacemit,k1-syscon-apbc
- spacemit,k1-syscon-apmu
- spacemit,k1-syscon-mpmu
+ - spacemit,k3-syscon-apbc
+ - spacemit,k3-syscon-apmu
+ - spacemit,k3-syscon-mpmu
then:
required:
- clocks
reg:
maxItems: 1
- avdd-supply:
+ AVDD-supply:
description: Analog power supply
- dvdd-supply:
+ DVDD-supply:
description: Digital power supply
reset-gpios:
properties:
dsd-path: false
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
reg:
maxItems: 1
- avdd-supply:
+ AVDD-supply:
description: A 1.8V supply that powers up the AVDD pin.
- dvdd-supply:
+ DVDD-supply:
description: A 1.2V supply that powers up the DVDD pin.
reset-gpios:
- compatible
- reg
-additionalProperties: false
+allOf:
+ - $ref: dai-common.yaml#
+
+unevaluatedProperties: false
examples:
- |
sound quallity, which is a new high efficiency, low
noise, constant large volume, 6th Smart K audio amplifier.
-allOf:
- - $ref: dai-common.yaml#
-
properties:
compatible:
- const: awinic,aw87390
+ oneOf:
+ - enum:
+ - awinic,aw87390
+ - items:
+ - enum:
+ - anbernic,rgds-amp
+ - const: awinic,aw87391
reg:
maxItems: 1
- compatible
- reg
- "#sound-dai-cells"
- - awinic,audio-channel
unevaluatedProperties: false
+allOf:
+ - $ref: dai-common.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - awinic,aw87390
+ then:
+ required:
+ - awinic,audio-channel
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - anbernic,rgds-amp
+ then:
+ properties:
+ vdd-supply: true
+
examples:
- |
i2c {
reset-gpios:
maxItems: 1
+ dvdd-supply: true
+
awinic,audio-channel:
description:
It is used to distinguish multiple PA devices, so that different
then:
properties:
reset-gpios: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: awinic,aw88261
+ then:
+ required:
+ - dvdd-supply
+ else:
+ properties:
+ dvdd-supply: false
unevaluatedProperties: false
tdm-slots:
$ref: /schemas/types.yaml#/definitions/uint32
description:
- number of channels over one serializer
- the property is ignored in DIT mode
+ Number of channels over one serializer. This property
+ specifies the TX playback TDM slot count, along with default RX slot count
+ if tdm-slots-rx is not specified.
+ The property is ignored in DIT mode.
minimum: 2
maximum: 32
+ tdm-slots-rx:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Number of RX capture channels over one serializer. If specified,
+ allows independent RX TDM slot count separate from TX. Requires
+ ti,async-mode to be enabled for independent TX/RX clock rates.
+ The property is ignored in DIT mode.
+ minimum: 2
+ maximum: 32
+
+ ti,async-mode:
+ description:
+ Specify to allow independent TX & RX clocking,
+ to enable audio playback & record with different sampling rate,
+ and different number of bits per frame.
+ if property is omitted, TX and RX will share same bit clock and frame clock signals,
+ thus RX need to use same bits per frame and sampling rate as TX in synchronous mode.
+ the property is ignored in DIT mode (as DIT is TX-only)
+ type: boolean
+
serial-dir:
description:
A list of serializer configuration
auxclk-fs-ratio:
$ref: /schemas/types.yaml#/definitions/uint32
- description: ratio of AUCLK and FS rate if applicable
+ description:
+ Ratio of AUCLK and FS rate if applicable. This property specifies
+ the TX ratio, along with default RX ratio if auxclk-fs-ratio-rx
+ is not specified.
+ When not specified, the inputted system clock frequency via set_sysclk
+ callback by the machine driver is used for divider calculation.
+
+ auxclk-fs-ratio-rx:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Ratio of AUCLK and FS rate for RX. If specified, allows
+ for a different RX ratio. Requires ti,async-mode to be
+ enabled when the ratio differs from auxclk-fs-ratio.
+ When not specified, it defaults to the value of auxclk-fs-ratio.
+ The property is ignored in DIT mode.
gpio-controller: true
- $ref: dai-common.yaml#
- if:
properties:
- opmode:
+ op-mode:
enum:
- 0
-
then:
required:
- tdm-slots
+ - if:
+ properties:
+ op-mode:
+ const: 1
+ then:
+ properties:
+ tdm-slots: false
+ tdm-slots-rx: false
+ ti,async-mode: false
+ auxclk-fs-ratio-rx: false
+
+ - if:
+ required:
+ - tdm-slots-rx
+ then:
+ required:
+ - ti,async-mode
+
+ - if:
+ required:
+ - auxclk-fs-ratio-rx
+ then:
+ required:
+ - ti,async-mode
+
unevaluatedProperties: false
examples:
interrupt-names = "tx", "rx";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
+ ti,async-mode;
dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
dma-names = "tx", "rx";
serial-dir = <
"#sound-dai-cells":
const: 0
+ vdda-supply:
+ description:
+ Analogue power supply.
+
+ vddd-supply:
+ description:
+ Interface power supply.
+
required:
- compatible
- reg
- "#sound-dai-cells"
+ - vddd-supply
+ - vdda-supply
additionalProperties: false
compatible = "everest,es8389";
reg = <0x10>;
#sound-dai-cells = <0>;
+ vddd-supply = <&vdd3v3>;
+ vdda-supply = <&vdd3v3>;
};
};
properties:
compatible:
- const: fsl,imx8qm-audmix
+ enum:
+ - fsl,imx8qm-audmix
+ - fsl,imx952-audmix
reg:
maxItems: 1
- reg
- clocks
- clock-names
- - power-domains
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8qm-audmix
+ then:
+ required:
+ - power-domains
unevaluatedProperties: false
- fsl,imx53-asrc
- fsl,imx8qm-asrc
- fsl,imx8qxp-asrc
+ - fsl,imx952-asrc
- items:
- enum:
- fsl,imx6sx-asrc
allOf:
- $ref: dai-common.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx6sx-mqs
+ - fsl,imx93-mqs
+ then:
+ required:
+ - gpr
- if:
properties:
compatible:
clock-names:
items:
- const: mclk
- required:
- - gpr
unevaluatedProperties: false
properties:
compatible:
- enum:
- - fsl,imx7ulp-rpmsg-audio
- - fsl,imx8mn-rpmsg-audio
- - fsl,imx8mm-rpmsg-audio
- - fsl,imx8mp-rpmsg-audio
- - fsl,imx8ulp-rpmsg-audio
- - fsl,imx93-rpmsg-audio
- - fsl,imx95-rpmsg-audio
+ oneOf:
+ - enum:
+ - fsl,imx7ulp-rpmsg-audio
+ - fsl,imx8mn-rpmsg-audio
+ - fsl,imx8mm-rpmsg-audio
+ - fsl,imx8mp-rpmsg-audio
+ - fsl,imx8ulp-rpmsg-audio
+ - fsl,imx93-rpmsg-audio
+ - fsl,imx95-rpmsg-audio
+ - items:
+ - enum:
+ - fsl,imx94-rpmsg-audio
+ - fsl,imx952-rpmsg-audio
+ - const: fsl,imx95-rpmsg-audio
clocks:
items:
- description: dataline mask for 'rx'
- description: dataline mask for 'tx'
+ fsl,sai-amix-mode:
+ $ref: /schemas/types.yaml#/definitions/string
+ description:
+ The audmix module is bypassed from hardware or not.
+ enum: [none, bypass, audmix]
+ default: none
+
fsl,sai-mclk-direction-output:
description: SAI will output the SAI MCLK clock.
type: boolean
properties:
fsl,sai-synchronous-rx: false
+ - if:
+ required:
+ - fsl,sai-amix-mode
+ then:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx952-sai
+
required:
- compatible
- reg
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/google,goldfish-audio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Android Goldfish Audio
+
+maintainers:
+ - Kuan-Wei Chiu <visitorckw@gmail.com>
+
+description:
+ Android goldfish audio device generated by Android emulator.
+
+properties:
+ compatible:
+ const: google,goldfish-audio
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ sound@9030000 {
+ compatible = "google,goldfish-audio";
+ reg = <0x9030000 0x100>;
+ interrupts = <4>;
+ };
- description: AFE clock
- description: ADDA DAC clock
- description: ADDA DAC pre-distortion clock
- - description: audio infra sys clock
- - description: audio infra 26M clock
+ - description: ADDA ADC clock
+ - description: ADDA6 ADC clock
+ - description: Audio low-jitter 22.5792m clock
+ - description: Audio low-jitter 24.576m clock
+ - description: Audio PLL1 tuner clock
+ - description: Audio PLL2 tuner clock
+ - description: Audio Time-Division Multiplexing interface clock
+ - description: ADDA ADC Sine Generator clock
+ - description: audio Non-LE clock
+ - description: Audio DAC High-Resolution clock
+ - description: Audio High-Resolution ADC clock
+ - description: Audio High-Resolution ADC SineGen clock
+ - description: Audio ADDA6 High-Resolution ADC clock
+ - description: Tertiary ADDA DAC clock
+ - description: Tertiary ADDA DAC pre-distortion clock
+ - description: Tertiary ADDA DAC Sine Generator clock
+ - description: Tertiary ADDA DAC High-Resolution clock
+ - description: Audio infra sys clock
+ - description: Audio infra 26M clock
+ - description: Mux for audio clock
+ - description: Mux for audio internal bus clock
+ - description: Mux main divider by 4
+ - description: Primary audio mux
+ - description: Primary audio PLL
+ - description: Secondary audio mux
+ - description: Secondary audio PLL
+ - description: Primary audio en-generator clock
+ - description: Primary PLL divider by 4 for IEC
+ - description: Secondary audio en-generator clock
+ - description: Secondary PLL divider by 4 for IEC
+ - description: Mux selector for I2S port 0
+ - description: Mux selector for I2S port 1
+ - description: Mux selector for I2S port 2
+ - description: Mux selector for I2S port 3
+ - description: Mux selector for I2S port 4
+ - description: Mux selector for I2S port 5
+ - description: Mux selector for I2S port 6
+ - description: Mux selector for I2S port 7
+ - description: Mux selector for I2S port 8
+ - description: Mux selector for I2S port 9
+ - description: APLL1 and APLL2 divider for I2S port 0
+ - description: APLL1 and APLL2 divider for I2S port 1
+ - description: APLL1 and APLL2 divider for I2S port 2
+ - description: APLL1 and APLL2 divider for I2S port 3
+ - description: APLL1 and APLL2 divider for I2S port 4
+ - description: APLL1 and APLL2 divider for IEC
+ - description: APLL1 and APLL2 divider for I2S port 5
+ - description: APLL1 and APLL2 divider for I2S port 6
+ - description: APLL1 and APLL2 divider for I2S port 7
+ - description: APLL1 and APLL2 divider for I2S port 8
+ - description: APLL1 and APLL2 divider for I2S port 9
+ - description: Top mux for audio subsystem
+ - description: 26MHz clock for audio subsystem
clock-names:
items:
- const: aud_afe_clk
- const: aud_dac_clk
- const: aud_dac_predis_clk
+ - const: aud_adc_clk
+ - const: aud_adda6_adc_clk
+ - const: aud_apll22m_clk
+ - const: aud_apll24m_clk
+ - const: aud_apll1_tuner_clk
+ - const: aud_apll2_tuner_clk
+ - const: aud_tdm_clk
+ - const: aud_tml_clk
+ - const: aud_nle
+ - const: aud_dac_hires_clk
+ - const: aud_adc_hires_clk
+ - const: aud_adc_hires_tml
+ - const: aud_adda6_adc_hires_clk
+ - const: aud_3rd_dac_clk
+ - const: aud_3rd_dac_predis_clk
+ - const: aud_3rd_dac_tml
+ - const: aud_3rd_dac_hires_clk
- const: aud_infra_clk
- const: aud_infra_26m_clk
+ - const: top_mux_audio
+ - const: top_mux_audio_int
+ - const: top_mainpll_d4_d4
+ - const: top_mux_aud_1
+ - const: top_apll1_ck
+ - const: top_mux_aud_2
+ - const: top_apll2_ck
+ - const: top_mux_aud_eng1
+ - const: top_apll1_d4
+ - const: top_mux_aud_eng2
+ - const: top_apll2_d4
+ - const: top_i2s0_m_sel
+ - const: top_i2s1_m_sel
+ - const: top_i2s2_m_sel
+ - const: top_i2s3_m_sel
+ - const: top_i2s4_m_sel
+ - const: top_i2s5_m_sel
+ - const: top_i2s6_m_sel
+ - const: top_i2s7_m_sel
+ - const: top_i2s8_m_sel
+ - const: top_i2s9_m_sel
+ - const: top_apll12_div0
+ - const: top_apll12_div1
+ - const: top_apll12_div2
+ - const: top_apll12_div3
+ - const: top_apll12_div4
+ - const: top_apll12_divb
+ - const: top_apll12_div5
+ - const: top_apll12_div6
+ - const: top_apll12_div7
+ - const: top_apll12_div8
+ - const: top_apll12_div9
+ - const: top_mux_audio_h
+ - const: top_clk26m_clk
required:
- compatible
afe: mt8192-afe-pcm {
compatible = "mediatek,mt8192-audio";
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&audsys CLK_AUD_AFE>, <&audsys CLK_AUD_DAC>,
+ <&audsys CLK_AUD_DAC_PREDIS>, <&audsys CLK_AUD_ADC>,
+ <&audsys CLK_AUD_ADDA6_ADC>, <&audsys CLK_AUD_22M>,
+ <&audsys CLK_AUD_24M>, <&audsys CLK_AUD_APLL_TUNER>,
+ <&audsys CLK_AUD_APLL2_TUNER>, <&audsys CLK_AUD_TDM>,
+ <&audsys CLK_AUD_TML>, <&audsys CLK_AUD_NLE>,
+ <&audsys CLK_AUD_DAC_HIRES>, <&audsys CLK_AUD_ADC_HIRES>,
+ <&audsys CLK_AUD_ADC_HIRES_TML>, <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
+ <&audsys CLK_AUD_3RD_DAC>, <&audsys CLK_AUD_3RD_DAC_PREDIS>,
+ <&audsys CLK_AUD_3RD_DAC_TML>, <&audsys CLK_AUD_3RD_DAC_HIRES>,
+ <&infracfg CLK_INFRA_AUDIO>, <&infracfg CLK_INFRA_AUDIO_26M_B>,
+ <&topckgen CLK_TOP_AUDIO_SEL>, <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+ <&topckgen CLK_TOP_MAINPLL_D4_D4>, <&topckgen CLK_TOP_AUD_1_SEL>,
+ <&topckgen CLK_TOP_APLL1>, <&topckgen CLK_TOP_AUD_2_SEL>,
+ <&topckgen CLK_TOP_APLL2>, <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
+ <&topckgen CLK_TOP_APLL1_D4>, <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
+ <&topckgen CLK_TOP_APLL2_D4>, <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, <&topckgen CLK_TOP_APLL12_DIV0>,
+ <&topckgen CLK_TOP_APLL12_DIV1>, <&topckgen CLK_TOP_APLL12_DIV2>,
+ <&topckgen CLK_TOP_APLL12_DIV3>, <&topckgen CLK_TOP_APLL12_DIV4>,
+ <&topckgen CLK_TOP_APLL12_DIVB>, <&topckgen CLK_TOP_APLL12_DIV5>,
+ <&topckgen CLK_TOP_APLL12_DIV6>, <&topckgen CLK_TOP_APLL12_DIV7>,
+ <&topckgen CLK_TOP_APLL12_DIV8>, <&topckgen CLK_TOP_APLL12_DIV9>,
+ <&topckgen CLK_TOP_AUDIO_H_SEL>, <&clk26m>;
+ clock-names = "aud_afe_clk", "aud_dac_clk",
+ "aud_dac_predis_clk", "aud_adc_clk",
+ "aud_adda6_adc_clk", "aud_apll22m_clk",
+ "aud_apll24m_clk", "aud_apll1_tuner_clk",
+ "aud_apll2_tuner_clk", "aud_tdm_clk",
+ "aud_tml_clk", "aud_nle",
+ "aud_dac_hires_clk", "aud_adc_hires_clk",
+ "aud_adc_hires_tml", "aud_adda6_adc_hires_clk",
+ "aud_3rd_dac_clk", "aud_3rd_dac_predis_clk",
+ "aud_3rd_dac_tml", "aud_3rd_dac_hires_clk",
+ "aud_infra_clk", "aud_infra_26m_clk",
+ "top_mux_audio", "top_mux_audio_int",
+ "top_mainpll_d4_d4", "top_mux_aud_1",
+ "top_apll1_ck", "top_mux_aud_2",
+ "top_apll2_ck", "top_mux_aud_eng1",
+ "top_apll1_d4", "top_mux_aud_eng2",
+ "top_apll2_d4", "top_i2s0_m_sel",
+ "top_i2s1_m_sel", "top_i2s2_m_sel",
+ "top_i2s3_m_sel", "top_i2s4_m_sel",
+ "top_i2s5_m_sel", "top_i2s6_m_sel",
+ "top_i2s7_m_sel", "top_i2s8_m_sel",
+ "top_i2s9_m_sel", "top_apll12_div0",
+ "top_apll12_div1", "top_apll12_div2",
+ "top_apll12_div3", "top_apll12_div4",
+ "top_apll12_divb", "top_apll12_div5",
+ "top_apll12_div6", "top_apll12_div7",
+ "top_apll12_div8", "top_apll12_div9",
+ "top_mux_audio_h", "top_clk26m_clk";
+ memory-region = <&afe_dma_mem>;
+ power-domains = <&scpsys MT8192_POWER_DOMAIN_AUDIO>;
resets = <&watchdog MT8192_TOPRGU_AUDIO_SW_RST>;
reset-names = "audiosys";
mediatek,apmixedsys = <&apmixedsys>;
mediatek,infracfg = <&infracfg>;
mediatek,topckgen = <&topckgen>;
- power-domains = <&scpsys MT8192_POWER_DOMAIN_AUDIO>;
- clocks = <&audsys CLK_AUD_AFE>,
- <&audsys CLK_AUD_DAC>,
- <&audsys CLK_AUD_DAC_PREDIS>,
- <&infracfg CLK_INFRA_AUDIO>,
- <&infracfg CLK_INFRA_AUDIO_26M_B>;
- clock-names = "aud_afe_clk",
- "aud_dac_clk",
- "aud_dac_predis_clk",
- "aud_infra_clk",
- "aud_infra_26m_clk";
- memory-region = <&afe_dma_mem>;
};
...
enum:
- nvidia,tegra210-audio-graph-card
- nvidia,tegra186-audio-graph-card
+ - nvidia,tegra238-audio-graph-card
- nvidia,tegra264-audio-graph-card
clocks:
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/realtek,rt5575.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ALC5575 audio CODEC
+
+maintainers:
+ - Oder Chiou <oder_chiou@realtek.com>
+
+description:
+ The device supports both I2C and SPI. I2C is mandatory, while SPI is
+ optional depending on the hardware configuration. SPI is used for
+ firmware loading if present.
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ const: realtek,rt5575
+
+ reg:
+ maxItems: 1
+
+ spi-parent:
+ description:
+ Optional phandle reference to the SPI controller used for firmware
+ loading. The argument specifies the chip select.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ # I2C-only node
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ codec@57 {
+ compatible = "realtek,rt5575";
+ reg = <0x57>;
+ };
+ };
+
+ # I2C + optional SPI node
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ codec@57 {
+ compatible = "realtek,rt5575";
+ reg = <0x57>;
+ spi-parent = <&spi0 0>; /* chip-select 0 */
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/realtek,rt5651.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Realtek RT5651 audio CODEC
+
+maintainers:
+ - Bard Liao <bardliao@realtek.com>
+
+description: >
+ This device supports I2C only.
+
+ Pins on the device (for linking into audio routes) for RT5651:
+
+ * DMIC L1
+ * DMIC R1
+ * IN1P
+ * IN2P
+ * IN2N
+ * IN3P
+ * HPOL
+ * HPOR
+ * LOUTL
+ * LOUTR
+ * PDML
+ * PDMR
+
+allOf:
+ - $ref: /schemas/sound/dai-common.yaml#
+
+properties:
+ compatible:
+ const: realtek,rt5651
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: mclk
+
+ '#sound-dai-cells':
+ const: 0
+
+ realtek,in2-differential:
+ type: boolean
+ description: Indicate MIC2 input are differential, rather than single-ended.
+
+ realtek,dmic-en:
+ type: boolean
+ description: Indicates DMIC is used.
+
+ realtek,jack-detect-source:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Select jack-detect input pin.
+ enum: [1, 2, 3]
+
+ realtek,jack-detect-not-inverted:
+ type: boolean
+ description:
+ Normal jack-detect switches give an inverted (active-low) signal. Set this
+ bool in the rare case you've a jack-detect switch which is not inverted.
+
+ realtek,over-current-threshold-microamp:
+ description: Micbias over-current detection threshold in µA.
+ enum: [600, 1500, 2000]
+
+ realtek,over-current-scale-factor:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: >
+ Micbias over-current detection scale factor:
+
+ 0: scale current by 0.5
+ 1: scale current by 0.75
+ 2: scale current by 1.0
+ 3: scale current by 1.5
+ enum: [0, 1, 2, 3]
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ codec@1a {
+ compatible = "realtek,rt5651";
+ reg = <0x1a>;
+ realtek,dmic-en;
+ realtek,in2-differential;
+ };
+ };
- renesas,r9a07g044-ssi # RZ/G2{L,LC}
- renesas,r9a07g054-ssi # RZ/V2L
- renesas,r9a08g045-ssi # RZ/G3S
+ - renesas,r9a08g046-ssi # RZ/G3L
- const: renesas,rz-ssi
reg:
class-D audio power amplifier and delivering 4x75W into 4OHm at 10%
THD+N from a 25V supply in automotive applications.
+ The RTQ9154 is the family series of RTQ9128. The major change is to modify
+ the package size. Beside this, whole functions are almost all the same.
+
allOf:
- $ref: dai-common.yaml#
properties:
compatible:
- enum:
- - richtek,rtq9128
+ oneOf:
+ - enum:
+ - richtek,rtq9128
+ - items:
+ - enum:
+ - richtek,rtq9154
+ - const: richtek,rtq9128
reg:
maxItems: 1
- const: rockchip,rk3066-spdif
- items:
- enum:
+ - rockchip,rk3576-spdif
- rockchip,rk3588-spdif
- const: rockchip,rk3568-spdif
+++ /dev/null
-RT5651 audio CODEC
-
-This device supports I2C only.
-
-Required properties:
-
-- compatible : "realtek,rt5651".
-
-- reg : The I2C address of the device.
-
-Optional properties:
-
-- realtek,in2-differential
- Boolean. Indicate MIC2 input are differential, rather than single-ended.
-
-- realtek,dmic-en
- Boolean. true if dmic is used.
-
-- realtek,jack-detect-source
- u32. Valid values:
- 1: Use JD1_1 pin for jack-detect
- 2: Use JD1_2 pin for jack-detect
- 3: Use JD2 pin for jack-detect
-
-- realtek,jack-detect-not-inverted
- bool. Normal jack-detect switches give an inverted (active-low) signal,
- set this bool in the rare case you've a jack-detect switch which is not
- inverted.
-
-- realtek,over-current-threshold-microamp
- u32, micbias over-current detection threshold in µA, valid values are
- 600, 1500 and 2000µA.
-
-- realtek,over-current-scale-factor
- u32, micbias over-current detection scale-factor, valid values are:
- 0: Scale current by 0.5
- 1: Scale current by 0.75
- 2: Scale current by 1.0
- 3: Scale current by 1.5
-
-Pins on the device (for linking into audio routes) for RT5651:
-
- * DMIC L1
- * DMIC R1
- * IN1P
- * IN2P
- * IN2N
- * IN3P
- * HPOL
- * HPOR
- * LOUTL
- * LOUTR
- * PDML
- * PDMR
-
-Example:
-
-rt5651: codec@1a {
- compatible = "realtek,rt5651";
- reg = <0x1a>;
- realtek,dmic-en = "true";
- realtek,in2-diff = "false";
-};
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/sophgo,cv1800b-codecs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo CV1800B Internal ADC/DAC Codec
+
+maintainers:
+ - Anton D. Stavinskii <stavinsky@gmail.com>
+
+description:
+ Internal ADC and DAC audio codecs integrated in the Sophgo CV1800B SoC.
+ Codecs expose a single DAI and are intended to be connected
+ to an I2S/TDM controller via an ASoC machine driver.
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - sophgo,cv1800b-sound-adc
+ - sophgo,cv1800b-sound-dac
+
+ reg:
+ maxItems: 1
+
+ "#sound-dai-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - "#sound-dai-cells"
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ audio-codec@300a100 {
+ compatible = "sophgo,cv1800b-sound-adc";
+ reg = <0x0300a100 0x100>;
+ #sound-dai-cells = <0>;
+ };
+...
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/sophgo,cv1800b-i2s.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo CV1800B I2S/TDM controller
+
+maintainers:
+ - Anton D. Stavinskii <stavinsky@gmail.com>
+
+description: I2S/TDM controller found in CV1800B / Sophgo SG2002/SG2000 SoCs.
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ const: sophgo,cv1800b-i2s
+
+ reg:
+ maxItems: 1
+
+ "#sound-dai-cells":
+ const: 0
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: i2s
+ - const: mclk
+
+ dmas:
+ minItems: 1
+ maxItems: 2
+
+ dma-names:
+ minItems: 1
+ items:
+ - enum: [rx, tx]
+ - const: tx
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#sound-dai-cells"
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/sophgo,cv1800.h>
+
+ i2s@4110000 {
+ compatible = "sophgo,cv1800b-i2s";
+ reg = <0x04110000 0x10000>;
+ clocks = <&clk CLK_APB_I2S1>, <&clk CLK_SDMA_AUD1>;
+ clock-names = "i2s", "mclk";
+ dmas = <&dmamux 2 1>, <&dmamux 3 1>;
+ dma-names = "rx", "tx";
+ #sound-dai-cells = <0>;
+ };
+...
properties:
compatible:
contains:
- const: st,stm32mph7-sai
+ const: st,stm32h7-sai
then:
properties:
clocks:
+++ /dev/null
-Texas Instruments - tas2552 Codec module
-
-The tas2552 serial control bus communicates through I2C protocols
-
-Required properties:
- - compatible - One of:
- "ti,tas2552" - TAS2552
- - reg - I2C slave address: it can be 0x40 if ADDR pin is 0
- or 0x41 if ADDR pin is 1.
- - supply-*: Required supply regulators are:
- "vbat" battery voltage
- "iovdd" I/O Voltage
- "avdd" Analog DAC Voltage
-
-Optional properties:
- - enable-gpio - gpio pin to enable/disable the device
-
-tas2552 can receive its reference clock via MCLK, BCLK, IVCLKIN pin or use the
-internal 1.8MHz. This CLKIN is used by the PLL. In addition to PLL, the PDM
-reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK.
-For system integration the dt-bindings/sound/tas2552.h header file provides
-defined values to select and configure the PLL and PDM reference clocks.
-
-Example:
-
-tas2552: tas2552@41 {
- compatible = "ti,tas2552";
- reg = <0x41>;
- vbat-supply = <®_vbat>;
- iovdd-supply = <®_iovdd>;
- avdd-supply = <®_avdd>;
- enable-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
-};
-
-For more product information please see the link below:
-https://www.ti.com/product/TAS2552
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/ti,tas2552.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments TAS2552 Codec
+
+maintainers:
+ - Shenghao Ding <shenghao-ding@ti.com>
+ - Kevin Lu <kevin-lu@ti.com>
+ - Baojun Xu <baojun.xu@ti.com>
+
+description: >
+ The TAS2552 can receive its reference clock via MCLK, BCLK, IVCLKIN pin or
+ use the internal 1.8MHz. This CLKIN is used by the PLL. In addition to PLL,
+ the PDM reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK.
+
+ For system integration the dt-bindings/sound/tas2552.h header file provides
+ defined values to select and configure the PLL and PDM reference clocks.
+
+properties:
+ compatible:
+ const: ti,tas2552
+
+ reg:
+ maxItems: 1
+
+ vbat-supply: true
+ iovdd-supply: true
+ avdd-supply: true
+
+ enable-gpio:
+ maxItems: 1
+ description: gpio pin to enable/disable the device
+
+ '#sound-dai-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - vbat-supply
+ - iovdd-supply
+ - avdd-supply
+
+allOf:
+ - $ref: dai-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ audio-codec@41 {
+ compatible = "ti,tas2552";
+ reg = <0x41>;
+ #sound-dai-cells = <0>;
+ vbat-supply = <®_vbat>;
+ iovdd-supply = <®_iovdd>;
+ avdd-supply = <®_avdd>;
+ enable-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
+ };
+ };
areg-supply:
description: |
- Regulator with AVDD at 3.3V. If not defined then the internal regulator
- is enabled.
+ External supply of 1.8V. If not defined then the internal regulator is
+ enabled instead.
+
+ avdd-supply: true
+ iovdd-supply: true
ti,mic-bias-source:
description: |
- items:
- enum:
- qcom,soundwire-v2.1.0
+ - qcom,soundwire-v2.2.0
- const: qcom,soundwire-v2.0.0
reg:
unevaluatedProperties: false
+patternProperties:
+ "^.*@[0-9a-f]+":
+ type: object
+
+ properties:
+ spi-rx-bus-width:
+ maxItems: 8
+ items:
+ enum: [0, 1]
+
+ spi-tx-bus-width:
+ maxItems: 8
+ items:
+ enum: [0, 1]
+
examples:
- |
spi@44a00000 {
maximum: 4
spi-rx-bus-width:
- const: 1
+ items:
+ - const: 1
spi-tx-bus-width:
- const: 1
+ items:
+ - const: 1
required:
- compatible
title: Allwinner A31 SPI Controller
-allOf:
- - $ref: spi-controller.yaml
-
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
maximum: 4
spi-rx-bus-width:
- const: 1
+ items:
+ enum: [0, 1, 2, 4]
spi-tx-bus-width:
- const: 1
+ items:
+ enum: [0, 1, 2, 4]
required:
- compatible
- clocks
- clock-names
+allOf:
+ - $ref: spi-controller.yaml
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - allwinner,sun50i-r329-spi
+ - allwinner,sun55i-a523-spi
+ then:
+ patternProperties:
+ "^.*@[0-9a-f]+":
+ properties:
+ spi-rx-bus-width:
+ items:
+ enum: [0, 1]
+
+ spi-tx-bus-width:
+ items:
+ enum: [0, 1]
+
unevaluatedProperties: false
examples:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/andestech,ae350-spi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Andes ATCSPI200 SPI controller
+
+maintainers:
+ - CL Wang <cl634@andestech.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - andestech,qilai-spi
+ - const: andestech,ae350-spi
+ - const: andestech,ae350-spi
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ num-cs:
+ description: Number of chip selects supported
+ maxItems: 1
+
+ dmas:
+ items:
+ - description: Transmit FIFO DMA channel
+ - description: Receive FIFO DMA channel
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+
+patternProperties:
+ "@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ spi-rx-bus-width:
+ items:
+ - enum: [1, 4]
+
+ spi-tx-bus-width:
+ items:
+ - enum: [1, 4]
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - dmas
+ - dma-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi@f0b00000 {
+ compatible = "andestech,ae350-spi";
+ reg = <0xf0b00000 0x100>;
+ clocks = <&clk_spi>;
+ dmas = <&dma0 0>, <&dma0 1>;
+ dma-names = "tx", "rx";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-cpol;
+ spi-cpha;
+ };
+ };
- const: atmel,at91rm9200-spi
- items:
- enum:
+ - microchip,lan9691-spi
- microchip,sam9x60-spi
- microchip,sam9x7-spi
- microchip,sama7d65-spi
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/axiado,ax3000-spi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Axiado AX3000 SoC SPI controller
+
+maintainers:
+ - Vladimir Moravcevic <vmoravcevic@axiado.com>
+ - Tzu-Hao Wei <twei@axiado.com>
+ - Swark Yang <syang@axiado.com>
+ - Prasad Bolisetty <pbolisetty@axiado.com>
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - axiado,ax3000-spi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: ref
+ - const: pclk
+
+ clocks:
+ maxItems: 2
+
+ num-cs:
+ description: |
+ Number of chip selects used.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 4
+ default: 4
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clock-names
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ spi@80510000 {
+ compatible = "axiado,ax3000-spi";
+ reg = <0x00 0x80510000 0x00 0x1000>;
+ clock-names = "ref", "pclk";
+ clocks = <&spi_clk>, <&apb_pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ num-cs = <4>;
+ };
+ };
+...
cdns,fifo-depth:
enum: [ 128, 256 ]
default: 128
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,rzn1-qspi
+ then:
+ properties:
+ cdns,trigger-address: false
+ cdns,fifo-depth: false
+ cdns,fifo-width: false
+ else:
+ required:
+ - cdns,trigger-address
+ - cdns,fifo-depth
properties:
compatible:
# controllers are meant to be used with flashes of all kinds,
# ie. also NAND flashes, not only NOR flashes.
- const: cdns,qspi-nor
+ - items:
+ - const: renesas,r9a06g032-qspi
+ - const: renesas,rzn1-qspi
- const: cdns,qspi-nor
deprecated: true
- reg
- interrupts
- clocks
- - cdns,fifo-width
- - cdns,trigger-address
- '#address-cells'
- '#size-cells'
examples:
- |
- qspi: spi@ff705000 {
+ spi@ff705000 {
compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
#address-cells = <1>;
#size-cells = <0>;
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/faraday,ftssp010.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Faraday FTSSP010 SPI Controller
+
+maintainers:
+ - Linus Walleij <linusw@kernel.org>
+
+properties:
+ compatible:
+ const: faraday,ftssp010
+
+ interrupts:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+ cs-gpios: true
+
+required:
+ - compatible
+ - interrupts
+ - reg
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ spi@4a000000 {
+ compatible = "faraday,ftssp010";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4a000000 0x1000>;
+ interrupts = <0>;
+ };
properties:
spi-rx-bus-width:
- enum: [1, 2, 4]
+ items:
+ - enum: [1, 2, 4]
spi-tx-bus-width:
- enum: [1, 2, 4]
+ items:
+ - enum: [1, 2, 4]
required:
- compatible
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/nxp,imx94-xspi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP External Serial Peripheral Interface (xSPI)
+
+maintainers:
+ - Haibo Chen <haibo.chen@nxp.com>
+ - Han Xu <han.xu@nxp.com>
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - nxp,imx94-xspi
+ - items:
+ - enum:
+ - nxp,imx952-xspi
+ - const: nxp,imx94-xspi
+
+ reg:
+ items:
+ - description: registers address space
+ - description: memory mapped address space
+
+ reg-names:
+ items:
+ - const: base
+ - const: mmap
+
+ interrupts:
+ items:
+ - description: interrupt for EENV0
+ - description: interrupt for EENV1
+ - description: interrupt for EENV2
+ - description: interrupt for EENV3
+ - description: interrupt for EENV4
+
+ clocks:
+ items:
+ - description: SPI serial clock
+
+ clock-names:
+ items:
+ - const: per
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - clocks
+ - clock-names
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ spi@42b90000 {
+ compatible = "nxp,imx94-xspi";
+ reg = <0x0 0x42b90000 0x0 0x50000>, <0x0 0x28000000 0x0 0x08000000>;
+ reg-names = "base", "mmap";
+ interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_1>;
+ clock-names = "per";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <200000000>;
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <8>;
+ };
+ };
+ };
clocks:
maxItems: 1
+ dmas:
+ maxItems: 1
+
+ dma-names:
+ const: rx-tx
+
allOf:
- $ref: spi-controller.yaml#
compatible = "nxp,lpc3220-spi";
reg = <0x20088000 0x1000>;
clocks = <&clk LPC32XX_CLK_SPI1>;
+ dmas = <&dmamux 11 1 0>;
+ dma-names = "rx-tx";
#address-cells = <1>;
#size-cells = <0>;
};
- const: presetn
- const: tresetn
+ dmas:
+ maxItems: 2
+
+ dma-names:
+ items:
+ - const: rx
+ - const: tx
+
power-domains:
maxItems: 1
properties:
reg:
minItems: 2
- - if:
- properties:
- compatible:
- contains:
- enum:
- - baikal,bt1-sys-ssi
- then:
- properties:
- mux-controls:
- maxItems: 1
- required:
- - mux-controls
- else:
- required:
- - interrupts
- if:
properties:
compatible:
const: intel,mountevans-imc-ssi
- description: AMD Pensando Elba SoC SPI Controller
const: amd,pensando-elba-spi
- - description: Baikal-T1 SPI Controller
- const: baikal,bt1-ssi
- - description: Baikal-T1 System Boot SPI Controller
- const: baikal,bt1-sys-ssi
- description: Canaan Kendryte K210 SoS SPI Controller
const: canaan,k210-spi
- description: Renesas RZ/N1 SPI Controller
- "#address-cells"
- "#size-cells"
- clocks
+ - interrupts
examples:
- |
rx-sample-delay-ns = <7>;
};
};
- - |
- spi@1f040100 {
- compatible = "baikal,bt1-sys-ssi";
- reg = <0x1f040100 0x900>,
- <0x1c000000 0x1000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- mux-controls = <&boot_mux>;
- clocks = <&ccu_sys>;
- clock-names = "ssi_clk";
- };
...
description:
Bus width to the SPI bus used for read transfers.
If 0 is provided, then no RX will be possible on this device.
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [0, 1, 2, 4, 8]
- default: 1
+
+ Some SPI peripherals and controllers may have multiple data lanes for
+ receiving two or more words at the same time. If this is the case, each
+ index in the array represents the lane on both the SPI peripheral and
+ controller. Additional mapping properties may be needed if a lane is
+ skipped on either side.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ enum: [0, 1, 2, 4, 8]
+ default: [1]
+
+ spi-rx-lane-map:
+ description: Mapping of peripheral SDO lanes to controller SDI lanes.
+ Each index in the array represents a peripheral SDO lane, and the value
+ at that index represents the corresponding controller SDI lane.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ default: [0, 1, 2, 3, 4, 5, 6, 7]
spi-rx-delay-us:
description:
description:
Bus width to the SPI bus used for write transfers.
If 0 is provided, then no TX will be possible on this device.
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [0, 1, 2, 4, 8]
- default: 1
+
+ Some SPI peripherals and controllers may have multiple data lanes for
+ transmitting two or more words at the same time. If this is the case, each
+ index in the array represents the lane on both the SPI peripheral and
+ controller. Additional mapping properties may be needed if a lane is
+ skipped on either side.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ enum: [0, 1, 2, 4, 8]
+ default: [1]
+
+ spi-tx-lane-map:
+ description: Mapping of peripheral SDI lanes to controller SDO lanes.
+ Each index in the array represents a peripheral SDI lane, and the value
+ at that index represents the corresponding controller SDO lane.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ default: [0, 1, 2, 3, 4, 5, 6, 7]
spi-tx-delay-us:
description:
required:
- compatible
- reg
- - interrupts
unevaluatedProperties: false
The region should be defined as child node of the AHB SRAM node
as per the generic bindings in Documentation/devicetree/bindings/sram/sram.yaml
+ power-domains:
+ maxItems: 1
+
access-controllers:
minItems: 1
maxItems: 2
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spmi/mediatek,mt8196-spmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MT8196 SPMI 2.0 Controller
+
+maintainers:
+ - Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+
+description:
+ The MediaTek MT8196 SoC features a SPMI version 2.0 compliant controller,
+ with internal wrapping arbitration logic to allow for multiple on-chip
+ devices to control up to two SPMI buses.
+ The main arbiter also acts as an interrupt controller, arbitering also
+ the interrupts coming from SPMI-connected devices into each of the nested
+ interrupt controllers from any of the present SPMI buses.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - mediatek,mt8196-spmi
+ - items:
+ - enum:
+ - mediatek,mt6991-spmi
+ - const: mediatek,mt8196-spmi
+
+ ranges: true
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+patternProperties:
+ "^spmi@[a-f0-9]+$":
+ type: object
+ $ref: /schemas/spmi/spmi.yaml
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ items:
+ - description: controller interface registers
+ - description: spmi master controller registers
+
+ reg-names:
+ items:
+ - const: pmif
+ - const: spmimst
+
+ clocks:
+ items:
+ - description: controller interface system clock
+ - description: controller interface timer clock
+ - description: spmi controller master clock
+
+ clock-names:
+ items:
+ - const: pmif_sys_ck
+ - const: pmif_tmr_ck
+ - const: spmimst_clk_mux
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ const: rcs
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 3
+ description: |
+ cell 1: slave ID for the requested interrupt (0-15)
+ cell 2: the requested peripheral interrupt (0-7)
+ cell 3: interrupt flags indicating level-sense information,
+ as defined in dt-bindings/interrupt-controller/irq.h
+ required:
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - interrupt-controller
+ - "#interrupt-cells"
+
+required:
+ - compatible
+ - ranges
+ - '#address-cells'
+ - '#size-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ spmi-arbiter@1c018000 {
+ compatible = "mediatek,mt8196-spmi";
+ ranges = <0 0 0x1c018000 0x4900>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ spmi@0 {
+ reg = <0 0x900>, <0x4800 0x100>;
+ reg-names = "pmif", "spmimst";
+ interrupts-extended = <&pio 292 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rcs";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ clocks = <&pmif_sys>, <&pmif_tmr>, <&spmi_mst>;
+ clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";
+ };
+
+ spmi@2000 {
+ reg = <0x2000 0x900>, <0x4000 0x100>;
+ reg-names = "pmif", "spmimst";
+ interrupts-extended = <&pio 291 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rcs";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ clocks = <&pmif_sys>, <&pmif_tmr>, <&spmi_mst>;
+ clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";
+ };
+ };
+ };
+...
- enum:
- mediatek,mt8186-spmi
- mediatek,mt8188-spmi
+ - mediatek,mt8189-spmi
- const: mediatek,mt8195-spmi
reg:
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spmi/qcom,glymur-spmi-pmic-arb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Glymur SPMI Controller (PMIC Arbiter v8)
+
+maintainers:
+ - David Collins <david.collins@oss.qualcomm.com>
+
+description: |
+ The Glymur SPMI PMIC Arbiter implements HW version 8 and it's an SPMI
+ controller with wrapping arbitration logic to allow for multiple on-chip
+ devices to control up to 4 SPMI separate buses.
+
+ The PMIC Arbiter can also act as an interrupt controller, providing interrupts
+ to slave devices.
+
+allOf:
+ - $ref: /schemas/spmi/qcom,spmi-pmic-arb-common.yaml
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - qcom,kaanapali-spmi-pmic-arb
+ - const: qcom,glymur-spmi-pmic-arb
+ - enum:
+ - qcom,glymur-spmi-pmic-arb
+
+ reg:
+ items:
+ - description: core registers
+ - description: tx-channel per virtual slave registers
+ - description: rx-channel (called observer) per virtual slave registers
+ - description: channel to PMIC peripheral mapping registers
+
+ reg-names:
+ items:
+ - const: core
+ - const: chnls
+ - const: obsrvr
+ - const: chnl_map
+
+ ranges: true
+
+ '#address-cells':
+ const: 2
+
+ '#size-cells':
+ const: 2
+
+patternProperties:
+ "^spmi@[a-f0-9]+$":
+ type: object
+ $ref: /schemas/spmi/spmi.yaml
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ items:
+ - description: configuration registers
+ - description: interrupt controller registers
+ - description: channel owner EE mapping registers
+
+ reg-names:
+ items:
+ - const: cnfg
+ - const: intr
+ - const: chnl_owner
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ const: periph_irq
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 4
+ description: |
+ cell 1: slave ID for the requested interrupt (0-15)
+ cell 2: peripheral ID for requested interrupt (0-255)
+ cell 3: the requested peripheral interrupt (0-7)
+ cell 4: interrupt flags indicating level-sense information,
+ as defined in dt-bindings/interrupt-controller/irq.h
+
+required:
+ - compatible
+ - reg-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ arbiter@c400000 {
+ compatible = "qcom,glymur-spmi-pmic-arb";
+ reg = <0x0 0xc400000 0x0 0x3000>,
+ <0x0 0xc900000 0x0 0x400000>,
+ <0x0 0xc4c0000 0x0 0x400000>,
+ <0x0 0xc403000 0x0 0x8000>;
+ reg-names = "core", "chnls", "obsrvr", "chnl_map";
+
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ spmi@c426000 {
+ reg = <0x0 0xc426000 0x0 0x4000>,
+ <0x0 0xc8c0000 0x0 0x10000>,
+ <0x0 0xc42a000 0x0 0x8000>;
+ reg-names = "cnfg", "intr", "chnl_owner";
+
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "periph_irq";
+ interrupt-controller;
+ #interrupt-cells = <4>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+
+ spmi@c437000 {
+ reg = <0x0 0xc437000 0x0 0x4000>,
+ <0x0 0xc8d0000 0x0 0x10000>,
+ <0x0 0xc43b000 0x0 0x8000>;
+ reg-names = "cnfg", "intr", "chnl_owner";
+
+ interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "periph_irq";
+ interrupt-controller;
+ #interrupt-cells = <4>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+ };
+ };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spmi/qcom,spmi-pmic-arb-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SPMI Controller (common)
+
+maintainers:
+ - David Collins <david.collins@oss.qualcomm.com>
+
+description: |
+ This defines some common properties used to define Qualcomm SPMI controllers
+ for PMIC arbiter.
+
+properties:
+ qcom,ee:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 5
+ description:
+ indicates the active Execution Environment identifier
+
+ qcom,channel:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 5
+ description:
+ which of the PMIC Arb provided channels to use for accesses
+
+required:
+ - qcom,ee
+ - qcom,channel
+
+additionalProperties: true
allOf:
- $ref: spmi.yaml
+ - $ref: qcom,spmi-pmic-arb-common.yaml
properties:
compatible:
'#size-cells': true
- qcom,ee:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 0
- maximum: 5
- description: >
- indicates the active Execution Environment identifier
-
- qcom,channel:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 0
- maximum: 5
- description: >
- which of the PMIC Arb provided channels to use for accesses
-
qcom,bus-id:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
required:
- compatible
- reg-names
- - qcom,ee
- - qcom,channel
unevaluatedProperties: false
The PMIC Arbiter can also act as an interrupt controller, providing interrupts
to slave devices.
+allOf:
+ - $ref: qcom,spmi-pmic-arb-common.yaml
+
properties:
compatible:
oneOf:
'#size-cells':
const: 2
- qcom,ee:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 0
- maximum: 5
- description: >
- indicates the active Execution Environment identifier
-
- qcom,channel:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 0
- maximum: 5
- description: >
- which of the PMIC Arb provided channels to use for accesses
-
patternProperties:
"^spmi@[a-f0-9]+$":
type: object
required:
- compatible
- reg-names
- - qcom,ee
- - qcom,channel
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
- nvidia,tegra186-sysram
- nvidia,tegra194-sysram
- nvidia,tegra234-sysram
+ - qcom,kaanapali-imem
- qcom,rpm-msg-ram
- rockchip,rk3288-pmu-sram
- arm,juno-scp-shmem
- arm,scmi-shmem
- arm,scp-shmem
+ - qcom,pil-reloc-info
- renesas,smp-sram
- rockchip,rk3066-smp-sram
- samsung,exynos4210-sysram
"dt-bindings: <binding dir>: ..."
- Few subsystems, like ASoC, media, regulators and SPI, expect reverse order
- of the prefixes::
+ Few subsystems, like ASoC, media, regulators, SCSI, SPI and UFS, expect
+ reverse order of the prefixes, based on subsystem name::
"<binding dir>: dt-bindings: ..."
properties:
compatible:
enum:
+ - mediatek,mt7987-lvts-ap
- mediatek,mt7988-lvts-ap
- mediatek,mt8186-lvts
- mediatek,mt8188-lvts-ap
- mediatek,mt8192-lvts-mcu
- mediatek,mt8195-lvts-ap
- mediatek,mt8195-lvts-mcu
+ - mediatek,mt8196-lvts-ap
+ - mediatek,mt8196-lvts-mcu
reg:
maxItems: 1
properties:
compatible:
oneOf:
- - const: renesas,r9a09g047-tsu # RZ/G3E
+ - enum:
+ - renesas,r9a09g047-tsu # RZ/G3E
+ - renesas,r9a09g077-tsu # RZ/T2H
- items:
- - const: renesas,r9a09g057-tsu # RZ/V2H
+ - enum:
+ - renesas,r9a09g056-tsu # RZ/V2N
+ - renesas,r9a09g057-tsu # RZ/V2H
- const: renesas,r9a09g047-tsu # RZ/G3E
+ - items:
+ - const: renesas,r9a09g087-tsu # RZ/N2H
+ - const: renesas,r9a09g077-tsu # RZ/T2H
reg:
maxItems: 1
- compatible
- reg
- clocks
- - resets
- power-domains
- interrupts
- interrupt-names
- "#thermal-sensor-cells"
- - renesas,tsu-trim
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g047-tsu
+ then:
+ required:
+ - resets
+ - renesas,tsu-trim
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g077-tsu
+ then:
+ properties:
+ resets: false
+ renesas,tsu-trim: false
additionalProperties: false
- eswin,eic7700-clint # ESWIN EIC7700
- sifive,fu540-c000-clint # SiFive FU540
- spacemit,k1-clint # SpacemiT K1
+ - spacemit,k3-clint # SpacemiT K3
- starfive,jh7100-clint # StarFive JH7100
- starfive,jh7110-clint # StarFive JH7110
- starfive,jh8100-clint # StarFive JH8100
- infineon,slb9673
- nuvoton,npct75x
- st,st33ktpm2xi2c
+ - st,st33tphf2ei2c
- const: tcg,tpm-tis-i2c
- description: TPM 1.2 and 2.0 chips with vendor-specific I²C interface
- delta,ahe50dc-fan
# Delta Electronics DPS-650-AB power supply
- delta,dps650ab
+ # Delta Electronics DPS-800-AB power supply
+ - delta,dps800
# Delta Electronics DPS920AB 920W 54V Power Supply
- delta,dps920ab
# 1/4 Brick DC/DC Regulated Power Module
- fsl,mma8450
# MPR121: Proximity Capacitive Touch Sensor Controller
- fsl,mpr121
+ # HiTRON AC/DC CompactPCI Power Supply
+ - hitron,hac300s
# Honeywell Humidicon HIH-6130 humidity/temperature sensor
- honeywell,hi6130
# IBM Common Form Factor Power Supply Versions (all versions)
- ibm,cffps2
# IBM On-Chip Controller hwmon device
- ibm,p8-occ-hwmon
+ # Infineon Digital Multi-phase Controller
+ - infineon,ir35221
# Infineon IR36021 digital POL buck controller
- infineon,ir36021
# Infineon IRPS5401 Voltage Regulator (PMIC)
- infineon,irps5401
+ # Infineon Digital Dual Output 6+1 VR12.5 & VR13 CPU Controller
+ - infineon,pxe1610
# Infineon Hot-swap controller xdp710
- infineon,xdp710
# Infineon Multi-phase Digital VR Controller xdpe11280
- meas,tsys01
# MEMSIC magnetometer
- memsic,mmc35240
+ # MEMSIC 3-axis magnetometer
+ - memsic,mmc5603
+ # MEMSIC 3-axis magnetometer (Support I3C HDR)
+ - memsic,mmc5633
# MEMSIC 3-axis accelerometer
- memsic,mxc4005
# MEMSIC 2-axis 8-bit digital accelerometer
- mps,mp5023
# Monolithic Power Systems Inc. multi-phase hot-swap controller mp5920
- mps,mp5920
+ # Monolithic Power Systems Inc. multi-phase hot-swap controller mp5926
+ - mps,mp5926
# Monolithic Power Systems Inc. multi-phase hot-swap controller mp5990
- mps,mp5990
# Monolithic Power Systems Inc. multi-phase hot-swap controller mp5998
- smsc,emc6d103
# Temperature sensor with integrated fan control
- smsc,emc6d103s
+ # Socionext Uniphier SMP control registers
+ - socionext,uniphier-smpctrl
# SparkFun Qwiic Joystick (COM-15168) with i2c interface
- sparkfun,qwiic-joystick
+ # STMicroelectronics Hot-swap controller stef48h28
+ - st,stef48h28
# Sierra Wireless mangOH Green SPI IoT interface
- swir,mangoh-iotport-spi
# Synaptics I2C touchpad
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/qcom,sa8255p-ufshc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SA8255P UFS Host Controller
+
+maintainers:
+ - Ram Kumar Dwivedi <ram.dwivedi@oss.qualcomm.com>
+
+properties:
+ compatible:
+ const: qcom,sa8255p-ufshc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+ dma-coherent: true
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - iommus
+ - dma-coherent
+
+allOf:
+ - $ref: ufs-common.yaml
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ ufshc@1d84000 {
+ compatible = "qcom,sa8255p-ufshc";
+ reg = <0x01d84000 0x3000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ lanes-per-direction = <2>;
+
+ iommus = <&apps_smmu 0x100 0x0>;
+ power-domains = <&scmi3_pd 0>;
+ dma-coherent;
+ };
Supported number of devices and endpoints vary depending on hardware
revisions. AST2400 and AST2500 Virtual Hub supports 5 downstream devices
- and 15 generic endpoints, while AST2600 Virtual Hub supports 7 downstream
- devices and 21 generic endpoints.
+ and 15 generic endpoints, while AST2600 and AST2700 Virtual Hub supports
+ 7 downstream devices and 21 generic endpoints.
properties:
compatible:
- aspeed,ast2400-usb-vhub
- aspeed,ast2500-usb-vhub
- aspeed,ast2600-usb-vhub
+ - aspeed,ast2700-usb-vhub
reg:
maxItems: 1
clocks:
maxItems: 1
+ resets:
+ maxItems: 1
+
interrupts:
maxItems: 1
- aspeed,vhub-downstream-ports
- aspeed,vhub-generic-endpoints
+if:
+ properties:
+ compatible:
+ contains:
+ const: aspeed,ast2700-usb-vhub
+
+then:
+ required:
+ - resets
+
+else:
+ properties:
+ resets: false
+
additionalProperties: false
examples:
minItems: 1
maxItems: 2
+ dma-coherent: true
+
interrupts:
maxItems: 1
reg:
maxItems: 1
+ dma-coherent: true
+
interrupts:
maxItems: 1
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (c) 2025, Google LLC
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/google,lga-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google Tensor Series G5 (Laguna) DWC3 USB SoC Controller
+
+maintainers:
+ - Roy Luo <royluo@google.com>
+
+description:
+ Describes the DWC3 USB controller block implemented on Google Tensor SoCs,
+ starting with the G5 generation (laguna). Based on Synopsys DWC3 IP, the
+ controller features Dual-Role Device single port with hibernation add-on.
+
+properties:
+ compatible:
+ const: google,lga-dwc3
+
+ reg:
+ items:
+ - description: Core DWC3 IP registers.
+
+ interrupts:
+ items:
+ - description: Core DWC3 interrupt.
+ - description: High speed power management event for remote wakeup.
+ - description: Super speed power management event for remote wakeup.
+
+ interrupt-names:
+ items:
+ - const: core
+ - const: hs_pme
+ - const: ss_pme
+
+ clocks:
+ items:
+ - description: Non-sticky module clock.
+ - description: Sticky module clock.
+
+ clock-names:
+ items:
+ - const: non_sticky
+ - const: sticky
+
+ resets:
+ items:
+ - description: Non-sticky module reset.
+ - description: Sticky module reset.
+ - description: DRD bus reset.
+ - description: Top-level reset.
+
+ reset-names:
+ items:
+ - const: non_sticky
+ - const: sticky
+ - const: drd_bus
+ - const: top
+
+ power-domains:
+ items:
+ - description: Power switchable domain, the child of top domain.
+ Turning it on puts the controller into full power state,
+ turning it off puts the controller into power gated state.
+ - description: Top domain, the parent of power switchable domain.
+ Turning it on puts the controller into power gated state,
+ turning it off completely shuts off the controller.
+
+ power-domain-names:
+ items:
+ - const: psw
+ - const: top
+
+ iommus:
+ maxItems: 1
+
+ google,usb-cfg-csr:
+ description:
+ A phandle to a syscon node used to access the USB configuration
+ registers. These registers are the top-level wrapper of the USB
+ subsystem and provide control and status for the integrated USB
+ controller and USB PHY.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to the syscon node.
+ - description: USB host controller configuration register offset.
+ - description: USB custom interrrupts control register offset.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - power-domains
+ - power-domain-names
+ - google,usb-cfg-csr
+
+allOf:
+ - $ref: snps,dwc3-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ usb@c400000 {
+ compatible = "google,lga-dwc3";
+ reg = <0 0x0c400000 0 0xd060>;
+ interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "core", "hs_pme", "ss_pme";
+ clocks = <&hsion_usbc_non_sticky_clk>, <&hsion_usbc_sticky_clk>;
+ clock-names = "non_sticky", "sticky";
+ resets = <&hsion_resets_usbc_non_sticky>, <&hsion_resets_usbc_sticky>,
+ <&hsion_resets_usb_drd_bus>, <&hsion_resets_usb_top>;
+ reset-names = "non_sticky", "sticky", "drd_bus", "top";
+ power-domains = <&hsio_n_usb_psw>, <&hsio_n_usb>;
+ power-domain-names = "psw", "top";
+ phys = <&usb_phy 0>;
+ phy-names = "usb2-phy";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,gfladj-refclk-lpm-sel-quirk;
+ snps,incr-burst-type-adjustment = <4>;
+ google,usb-cfg-csr = <&usb_cfg_csr 0x0 0x20>;
+ };
+ };
+...
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
- i2c2 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/microchip,lan9691-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip LAN969x SuperSpeed DWC3 USB SoC controller
+
+maintainers:
+ - Robert Marko <robert.marko@sartura.hr>
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - microchip,lan9691-dwc3
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - microchip,lan9691-dwc3
+ - const: snps,dwc3
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Gated USB DRD clock
+ - description: Controller reference clock
+
+ clock-names:
+ items:
+ - const: bus_early
+ - const: ref
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+allOf:
+ - $ref: snps,dwc3.yaml#
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ usb@300000 {
+ compatible = "microchip,lan9691-dwc3", "snps,dwc3";
+ reg = <0x300000 0x80000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 12>, <&clks 11>;
+ clock-names = "bus_early", "ref";
+ };
- renesas,usbhs-r9a07g044 # RZ/G2{L,LC}
- renesas,usbhs-r9a07g054 # RZ/V2L
- renesas,usbhs-r9a08g045 # RZ/G3S
+ - renesas,usbhs-r9a09g047 # RZ/G3E
- renesas,usbhs-r9a09g056 # RZ/V2N
- renesas,usbhs-r9a09g057 # RZ/V2H(P)
- const: renesas,rzg2l-usbhs
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/socionext,uniphier-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext Uniphier SuperSpeed DWC3 USB SoC controller
+
+maintainers:
+ - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+ - Masami Hiramatsu <mhiramat@kernel.org>
+
+select:
+ properties:
+ compatible:
+ contains:
+ const: socionext,uniphier-dwc3
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - const: socionext,uniphier-dwc3
+ - const: snps,dwc3
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ items:
+ - description: Host or single combined interrupt
+ - description: Peripheral interrupt
+
+ interrupt-names:
+ minItems: 1
+ items:
+ - enum:
+ - dwc_usb3
+ - host
+ - const: peripheral
+
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: ref
+ - const: bus_early
+ - const: suspend
+
+ phys:
+ description: 1 to 4 HighSpeed PHYs followed by 1 or 2 SuperSpeed PHYs
+ minItems: 1
+ maxItems: 6
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - phys
+
+unevaluatedProperties: false
+
+allOf:
+ - $ref: snps,dwc3.yaml#
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ usb@65a00000 {
+ compatible = "socionext,uniphier-dwc3", "snps,dwc3";
+ reg = <0x65a00000 0xcd00>;
+ interrupt-names = "dwc_usb3";
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "ref", "bus_early", "suspend";
+ clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
+ resets = <&usb0_rst 15>;
+ phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
+ <&usb0_ssphy0>, <&usb0_ssphy1>;
+ dr_mode = "host";
+ };
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/wch,ch334.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: WCH CH334/CH335 USB 2.0 Hub Controller
+
+maintainers:
+ - Chaoyi Chen <kernel@airkyi.com>
+
+allOf:
+ - $ref: usb-hub.yaml#
+
+properties:
+ compatible:
+ enum:
+ - usb1a86,8091
+
+ reg: true
+
+ reset-gpios:
+ description: GPIO controlling the RESET# pin.
+
+ vdd33-supply:
+ description:
+ The regulator that provides 3.3V core power to the hub.
+
+ v5-supply:
+ description:
+ The regulator that provides 3.3V or 5V power to the hub.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ patternProperties:
+ '^port@':
+ $ref: /schemas/graph.yaml#/properties/port
+
+ properties:
+ reg:
+ minimum: 1
+ maximum: 4
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ usb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hub: hub@1 {
+ compatible = "usb1a86,8091";
+ reg = <1>;
+ reset-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ v5-supply = <&vcc_3v3>;
+ vdd33-supply = <&vcc_3v3>;
+ };
+ };
description: Aldec, Inc.
"^alfa-network,.*":
description: ALFA Network Inc.
+ "^algoltek,.*":
+ description: AlgolTek, Inc.
"^allegro,.*":
description: Allegro DVT
"^allegromicro,.*":
description: Arctic Sand
"^arcx,.*":
description: arcx Inc. / Archronix Inc.
+ "^arduino,.*":
+ description: Arduino SRL
"^argon40,.*":
description: Argon 40 Technologies Limited
"^ariaboard,.*":
description: Exegin Technologies Limited
"^ezchip,.*":
description: EZchip Semiconductor
+ "^ezurio,.*":
+ description: Ezurio LLC
"^facebook,.*":
description: Facebook
"^fairchild,.*":
description: Hitachi Ltd.
"^hitex,.*":
description: Hitex Development Tools
+ "^hitron,.*":
+ description: HiTRON Electronics Corporation
"^holt,.*":
description: Holt Integrated Circuits, Inc.
"^holtek,.*":
description: IEI Integration Corp.
"^ifi,.*":
description: Ingenieurburo Fur Ic-Technologie (I/F/I)
+ "^ifm,.*":
+ description: ifm electronic gmbh
"^ilitek,.*":
description: ILI Technology Corporation (ILITEK)
"^imagis,.*":
description: Mustek Limited
"^mediatek,.*":
description: MediaTek Inc.
+ "^medion,.*":
+ description: Medion AG
"^megachips,.*":
description: MegaChips
"^mele,.*":
description: Revolution Robotics, Inc. (Revotics)
"^rex,.*":
description: iMX6 Rex Project
+ "^rfdigital,.*":
+ description: RF Digital Corporation
"^richtek,.*":
description: Richtek Technology Corporation
"^ricoh,.*":
description: Theobroma Systems Design und Consulting GmbH
"^turing,.*":
description: Turing Machines, Inc.
+ "^tuxedo,.*":
+ description: TUXEDO Computers GmbH
"^tyan,.*":
description: Tyan Computer Corporation
"^tyhx,.*":
+++ /dev/null
-* Freescale mpc8xxx watchdog driver (For 83xx, 86xx and 8xx)
-
-Required properties:
-- compatible: Shall contain one of the following:
- "mpc83xx_wdt" for an mpc83xx
- "fsl,mpc8610-wdt" for an mpc86xx
- "fsl,mpc823-wdt" for an mpc8xx
-- reg: base physical address and length of the area hosting the
- watchdog registers.
- On the 83xx, "Watchdog Timer Registers" area: <0x200 0x100>
- On the 86xx, "Watchdog Timer Registers" area: <0xe4000 0x100>
- On the 8xx, "General System Interface Unit" area: <0x0 0x10>
-
-Optional properties:
-- reg: additional physical address and length (4) of location of the
- Reset Status Register (called RSTRSCR on the mpc86xx)
- On the 83xx, it is located at offset 0x910
- On the 86xx, it is located at offset 0xe0094
- On the 8xx, it is located at offset 0x288
-
-Example:
- WDT: watchdog@0 {
- compatible = "fsl,mpc823-wdt";
- reg = <0x0 0x10 0x288 0x4>;
- };
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/mpc8xxx-wdt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale MPC8xxx watchdog timer (For 83xx, 86xx and 8xx)
+
+maintainers:
+ - J. Neuschäfer <j.ne@posteo.net>
+
+properties:
+ compatible:
+ enum:
+ - mpc83xx_wdt # for an mpc83xx
+ - fsl,mpc8610-wdt # for an mpc86xx
+ - fsl,mpc823-wdt # for an mpc8xx
+
+ device_type:
+ const: watchdog
+
+ reg:
+ minItems: 1
+ items:
+ - description: |
+ Base physical address and length of the area hosting the watchdog
+ registers.
+
+ On the 83xx, "Watchdog Timer Registers" area: <0x200 0x100>
+ On the 86xx, "Watchdog Timer Registers" area: <0xe4000 0x100>
+ On the 8xx, "General System Interface Unit" area: <0x0 0x10>
+
+ - description: |
+ Additional optional physical address and length (4) of location of
+ the Reset Status Register (called RSTRSCR on the mpc86xx)
+
+ On the 83xx, it is located at offset 0x910
+ On the 86xx, it is located at offset 0xe0094
+ On the 8xx, it is located at offset 0x288
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: watchdog.yaml#
+
+additionalProperties: false
+
+examples:
+ - |
+ watchdog@0 {
+ compatible = "fsl,mpc823-wdt";
+ reg = <0x0 0x10 0x288 0x4>;
+ };
+
+ - |
+ watchdog@200 {
+ compatible = "mpc83xx_wdt";
+ reg = <0x200 0x100>;
+ device_type = "watchdog";
+ };
+
+...
oneOf:
- items:
- enum:
+ - qcom,apss-wdt-glymur
- qcom,kpss-wdt-ipq4019
- qcom,apss-wdt-ipq5018
- qcom,apss-wdt-ipq5332
- qcom,apss-wdt-sm6350
- qcom,apss-wdt-sm8150
- qcom,apss-wdt-sm8250
+ - qcom,apss-wdt-x1e80100
- const: qcom,kpss-wdt
- const: qcom,kpss-wdt
deprecated: true
oneOf:
- enum:
- google,gs101-wdt # for Google gs101
- - samsung,s3c2410-wdt # for S3C2410
- samsung,s3c6410-wdt # for S3C6410, S5PV210 and Exynos4
- samsung,exynos5250-wdt # for Exynos5250
- samsung,exynos5420-wdt # for Exynos5420
samsung,cluster-index:
$ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
description:
Index of CPU cluster on which watchdog is running (in case of Exynos850,
Exynos990 or Google gs101).
contains:
enum:
- google,gs101-wdt
- - samsung,exynos5250-wdt
- - samsung,exynos5420-wdt
- - samsung,exynos7-wdt
- samsung,exynos850-wdt
- - samsung,exynos990-wdt
- samsung,exynosautov9-wdt
- samsung,exynosautov920-wdt
then:
+ properties:
+ clocks:
+ items:
+ - description: Bus clock, used for register interface
+ - description: Source clock (driving watchdog counter)
+ clock-names:
+ items:
+ - const: watchdog
+ - const: watchdog_src
+ samsung,cluster-index:
+ enum: [0, 1]
required:
+ - samsung,cluster-index
- samsung,syscon-phandle
+
- if:
properties:
compatible:
contains:
enum:
- - google,gs101-wdt
- - samsung,exynos850-wdt
- samsung,exynos990-wdt
- - samsung,exynosautov9-wdt
- - samsung,exynosautov920-wdt
then:
properties:
clocks:
items:
- const: watchdog
- const: watchdog_src
- samsung,cluster-index:
- enum: [0, 1, 2]
required:
- samsung,cluster-index
- else:
+ - samsung,syscon-phandle
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,exynos5250-wdt
+ - samsung,exynos5420-wdt
+ - samsung,exynos7-wdt
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Bus clock, which is also a source clock
+ clock-names:
+ items:
+ - const: watchdog
+ samsung,cluster-index: false
+ required:
+ - samsung,syscon-phandle
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,s3c6410-wdt
+ then:
properties:
clocks:
items:
items:
- const: watchdog
samsung,cluster-index: false
+ samsung,syscon-phandle: false
unevaluatedProperties: false
clocks:
maxItems: 1
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- reg
make dt_binding_check
+Or to validate a single schema and its example::
+
+ make sram/sram.yaml
+
In order to perform validation of DT source files, use the ``dtbs_check`` target::
make dtbs_check
make dt_binding_check dtbs_check
-It is also possible to run checks with a subset of matching schema files by
-setting the ``DT_SCHEMA_FILES`` variable to 1 or more specific schema files or
-patterns (partial match of a fixed string). Each file or pattern should be
-separated by ':'.
+It is also possible to combine running the above commands with a subset of
+matching schema files by setting the ``DT_SCHEMA_FILES`` variable to 1 or more
+specific schema files or patterns (partial match of a fixed string). Each file
+or pattern should be separated by ':'.
::
#define CLKID_HDCP22_SKPCLK_SEL 222
#define CLKID_HDCP22_SKPCLK_DIV 223
#define CLKID_HDCP22_SKPCLK 224
+#define CLKID_CTS_ENCL_SEL 225
+#define CLKID_CTS_ENCL 226
+#define CLKID_CDAC_SEL 227
+#define CLKID_CDAC_DIV 228
+#define CLKID_CDAC 229
+#define CLKID_DEMOD_CORE_SEL 230
+#define CLKID_DEMOD_CORE_DIV 231
+#define CLKID_DEMOD_CORE 232
+#define CLKID_ADC_EXTCLK_IN_SEL 233
+#define CLKID_ADC_EXTCLK_IN_DIV 234
+#define CLKID_ADC_EXTCLK_IN 235
#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H */
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
+ */
+
+#ifndef __T7_PERIPHERALS_CLKC_H
+#define __T7_PERIPHERALS_CLKC_H
+
+#define CLKID_RTC_DUALDIV_IN 0
+#define CLKID_RTC_DUALDIV_DIV 1
+#define CLKID_RTC_DUALDIV_SEL 2
+#define CLKID_RTC_DUALDIV 3
+#define CLKID_RTC 4
+#define CLKID_CECA_DUALDIV_IN 5
+#define CLKID_CECA_DUALDIV_DIV 6
+#define CLKID_CECA_DUALDIV_SEL 7
+#define CLKID_CECA_DUALDIV 8
+#define CLKID_CECA 9
+#define CLKID_CECB_DUALDIV_IN 10
+#define CLKID_CECB_DUALDIV_DIV 11
+#define CLKID_CECB_DUALDIV_SEL 12
+#define CLKID_CECB_DUALDIV 13
+#define CLKID_CECB 14
+#define CLKID_SC_SEL 15
+#define CLKID_SC_DIV 16
+#define CLKID_SC 17
+#define CLKID_DSPA_0_SEL 18
+#define CLKID_DSPA_0_DIV 19
+#define CLKID_DSPA_0 20
+#define CLKID_DSPA_1_SEL 21
+#define CLKID_DSPA_1_DIV 22
+#define CLKID_DSPA_1 23
+#define CLKID_DSPA 24
+#define CLKID_DSPB_0_SEL 25
+#define CLKID_DSPB_0_DIV 26
+#define CLKID_DSPB_0 27
+#define CLKID_DSPB_1_SEL 28
+#define CLKID_DSPB_1_DIV 29
+#define CLKID_DSPB_1 30
+#define CLKID_DSPB 31
+#define CLKID_24M 32
+#define CLKID_24M_DIV2 33
+#define CLKID_12M 34
+#define CLKID_25M_DIV 35
+#define CLKID_25M 36
+#define CLKID_ANAKIN_0_SEL 37
+#define CLKID_ANAKIN_0_DIV 38
+#define CLKID_ANAKIN_0 39
+#define CLKID_ANAKIN_1_SEL 40
+#define CLKID_ANAKIN_1_DIV 41
+#define CLKID_ANAKIN_1 42
+#define CLKID_ANAKIN_01_SEL 43
+#define CLKID_ANAKIN 44
+#define CLKID_TS_DIV 45
+#define CLKID_TS 46
+#define CLKID_MIPI_CSI_PHY_0_SEL 47
+#define CLKID_MIPI_CSI_PHY_0_DIV 48
+#define CLKID_MIPI_CSI_PHY_0 49
+#define CLKID_MIPI_CSI_PHY_1_SEL 50
+#define CLKID_MIPI_CSI_PHY_1_DIV 51
+#define CLKID_MIPI_CSI_PHY_1 52
+#define CLKID_MIPI_CSI_PHY 53
+#define CLKID_MIPI_ISP_SEL 54
+#define CLKID_MIPI_ISP_DIV 55
+#define CLKID_MIPI_ISP 56
+#define CLKID_MALI_0_SEL 57
+#define CLKID_MALI_0_DIV 58
+#define CLKID_MALI_0 59
+#define CLKID_MALI_1_SEL 60
+#define CLKID_MALI_1_DIV 61
+#define CLKID_MALI_1 62
+#define CLKID_MALI 63
+#define CLKID_ETH_RMII_SEL 64
+#define CLKID_ETH_RMII_DIV 65
+#define CLKID_ETH_RMII 66
+#define CLKID_FCLK_DIV2_DIV8 67
+#define CLKID_ETH_125M 68
+#define CLKID_SD_EMMC_A_SEL 69
+#define CLKID_SD_EMMC_A_DIV 70
+#define CLKID_SD_EMMC_A 71
+#define CLKID_SD_EMMC_B_SEL 72
+#define CLKID_SD_EMMC_B_DIV 73
+#define CLKID_SD_EMMC_B 74
+#define CLKID_SD_EMMC_C_SEL 75
+#define CLKID_SD_EMMC_C_DIV 76
+#define CLKID_SD_EMMC_C 77
+#define CLKID_SPICC0_SEL 78
+#define CLKID_SPICC0_DIV 79
+#define CLKID_SPICC0 80
+#define CLKID_SPICC1_SEL 81
+#define CLKID_SPICC1_DIV 82
+#define CLKID_SPICC1 83
+#define CLKID_SPICC2_SEL 84
+#define CLKID_SPICC2_DIV 85
+#define CLKID_SPICC2 86
+#define CLKID_SPICC3_SEL 87
+#define CLKID_SPICC3_DIV 88
+#define CLKID_SPICC3 89
+#define CLKID_SPICC4_SEL 90
+#define CLKID_SPICC4_DIV 91
+#define CLKID_SPICC4 92
+#define CLKID_SPICC5_SEL 93
+#define CLKID_SPICC5_DIV 94
+#define CLKID_SPICC5 95
+#define CLKID_SARADC_SEL 96
+#define CLKID_SARADC_DIV 97
+#define CLKID_SARADC 98
+#define CLKID_PWM_A_SEL 99
+#define CLKID_PWM_A_DIV 100
+#define CLKID_PWM_A 101
+#define CLKID_PWM_B_SEL 102
+#define CLKID_PWM_B_DIV 103
+#define CLKID_PWM_B 104
+#define CLKID_PWM_C_SEL 105
+#define CLKID_PWM_C_DIV 106
+#define CLKID_PWM_C 107
+#define CLKID_PWM_D_SEL 108
+#define CLKID_PWM_D_DIV 109
+#define CLKID_PWM_D 110
+#define CLKID_PWM_E_SEL 111
+#define CLKID_PWM_E_DIV 112
+#define CLKID_PWM_E 113
+#define CLKID_PWM_F_SEL 114
+#define CLKID_PWM_F_DIV 115
+#define CLKID_PWM_F 116
+#define CLKID_PWM_AO_A_SEL 117
+#define CLKID_PWM_AO_A_DIV 118
+#define CLKID_PWM_AO_A 119
+#define CLKID_PWM_AO_B_SEL 120
+#define CLKID_PWM_AO_B_DIV 121
+#define CLKID_PWM_AO_B 122
+#define CLKID_PWM_AO_C_SEL 123
+#define CLKID_PWM_AO_C_DIV 124
+#define CLKID_PWM_AO_C 125
+#define CLKID_PWM_AO_D_SEL 126
+#define CLKID_PWM_AO_D_DIV 127
+#define CLKID_PWM_AO_D 128
+#define CLKID_PWM_AO_E_SEL 129
+#define CLKID_PWM_AO_E_DIV 130
+#define CLKID_PWM_AO_E 131
+#define CLKID_PWM_AO_F_SEL 132
+#define CLKID_PWM_AO_F_DIV 133
+#define CLKID_PWM_AO_F 134
+#define CLKID_PWM_AO_G_SEL 135
+#define CLKID_PWM_AO_G_DIV 136
+#define CLKID_PWM_AO_G 137
+#define CLKID_PWM_AO_H_SEL 138
+#define CLKID_PWM_AO_H_DIV 139
+#define CLKID_PWM_AO_H 140
+#define CLKID_SYS_DDR 141
+#define CLKID_SYS_DOS 142
+#define CLKID_SYS_MIPI_DSI_A 143
+#define CLKID_SYS_MIPI_DSI_B 144
+#define CLKID_SYS_ETHPHY 145
+#define CLKID_SYS_MALI 146
+#define CLKID_SYS_AOCPU 147
+#define CLKID_SYS_AUCPU 148
+#define CLKID_SYS_CEC 149
+#define CLKID_SYS_GDC 150
+#define CLKID_SYS_DESWARP 151
+#define CLKID_SYS_AMPIPE_NAND 152
+#define CLKID_SYS_AMPIPE_ETH 153
+#define CLKID_SYS_AM2AXI0 154
+#define CLKID_SYS_AM2AXI1 155
+#define CLKID_SYS_AM2AXI2 156
+#define CLKID_SYS_SD_EMMC_A 157
+#define CLKID_SYS_SD_EMMC_B 158
+#define CLKID_SYS_SD_EMMC_C 159
+#define CLKID_SYS_SMARTCARD 160
+#define CLKID_SYS_ACODEC 161
+#define CLKID_SYS_SPIFC 162
+#define CLKID_SYS_MSR_CLK 163
+#define CLKID_SYS_IR_CTRL 164
+#define CLKID_SYS_AUDIO 165
+#define CLKID_SYS_ETH 166
+#define CLKID_SYS_UART_A 167
+#define CLKID_SYS_UART_B 168
+#define CLKID_SYS_UART_C 169
+#define CLKID_SYS_UART_D 170
+#define CLKID_SYS_UART_E 171
+#define CLKID_SYS_UART_F 172
+#define CLKID_SYS_AIFIFO 173
+#define CLKID_SYS_SPICC2 174
+#define CLKID_SYS_SPICC3 175
+#define CLKID_SYS_SPICC4 176
+#define CLKID_SYS_TS_A73 177
+#define CLKID_SYS_TS_A53 178
+#define CLKID_SYS_SPICC5 179
+#define CLKID_SYS_G2D 180
+#define CLKID_SYS_SPICC0 181
+#define CLKID_SYS_SPICC1 182
+#define CLKID_SYS_PCIE 183
+#define CLKID_SYS_USB 184
+#define CLKID_SYS_PCIE_PHY 185
+#define CLKID_SYS_I2C_AO_A 186
+#define CLKID_SYS_I2C_AO_B 187
+#define CLKID_SYS_I2C_M_A 188
+#define CLKID_SYS_I2C_M_B 189
+#define CLKID_SYS_I2C_M_C 190
+#define CLKID_SYS_I2C_M_D 191
+#define CLKID_SYS_I2C_M_E 192
+#define CLKID_SYS_I2C_M_F 193
+#define CLKID_SYS_HDMITX_APB 194
+#define CLKID_SYS_I2C_S_A 195
+#define CLKID_SYS_HDMIRX_PCLK 196
+#define CLKID_SYS_MMC_APB 197
+#define CLKID_SYS_MIPI_ISP_PCLK 198
+#define CLKID_SYS_RSA 199
+#define CLKID_SYS_PCLK_SYS_APB 200
+#define CLKID_SYS_A73PCLK_APB 201
+#define CLKID_SYS_DSPA 202
+#define CLKID_SYS_DSPB 203
+#define CLKID_SYS_VPU_INTR 204
+#define CLKID_SYS_SAR_ADC 205
+#define CLKID_SYS_GIC 206
+#define CLKID_SYS_TS_GPU 207
+#define CLKID_SYS_TS_NNA 208
+#define CLKID_SYS_TS_VPU 209
+#define CLKID_SYS_TS_HEVC 210
+#define CLKID_SYS_PWM_AB 211
+#define CLKID_SYS_PWM_CD 212
+#define CLKID_SYS_PWM_EF 213
+#define CLKID_SYS_PWM_AO_AB 214
+#define CLKID_SYS_PWM_AO_CD 215
+#define CLKID_SYS_PWM_AO_EF 216
+#define CLKID_SYS_PWM_AO_GH 217
+
+#endif /* __T7_PERIPHERALS_CLKC_H */
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
+ */
+
+#ifndef __T7_PLL_CLKC_H
+#define __T7_PLL_CLKC_H
+
+/* GP0 */
+#define CLKID_GP0_PLL_DCO 0
+#define CLKID_GP0_PLL 1
+
+/* GP1 */
+#define CLKID_GP1_PLL_DCO 0
+#define CLKID_GP1_PLL 1
+
+/* HIFI */
+#define CLKID_HIFI_PLL_DCO 0
+#define CLKID_HIFI_PLL 1
+
+/* PCIE */
+#define CLKID_PCIE_PLL_DCO 0
+#define CLKID_PCIE_PLL_DCO_DIV2 1
+#define CLKID_PCIE_PLL_OD 2
+#define CLKID_PCIE_PLL 3
+
+/* MPLL */
+#define CLKID_MPLL_PREDIV 0
+#define CLKID_MPLL0_DIV 1
+#define CLKID_MPLL0 2
+#define CLKID_MPLL1_DIV 3
+#define CLKID_MPLL1 4
+#define CLKID_MPLL2_DIV 5
+#define CLKID_MPLL2 6
+#define CLKID_MPLL3_DIV 7
+#define CLKID_MPLL3 8
+
+/* HDMI */
+#define CLKID_HDMI_PLL_DCO 0
+#define CLKID_HDMI_PLL_OD 1
+#define CLKID_HDMI_PLL 2
+
+/* MCLK */
+#define CLKID_MCLK_PLL_DCO 0
+#define CLKID_MCLK_PRE 1
+#define CLKID_MCLK_PLL 2
+#define CLKID_MCLK_0_SEL 3
+#define CLKID_MCLK_0_DIV2 4
+#define CLKID_MCLK_0_PRE 5
+#define CLKID_MCLK_0 6
+#define CLKID_MCLK_1_SEL 7
+#define CLKID_MCLK_1_DIV2 8
+#define CLKID_MCLK_1_PRE 9
+#define CLKID_MCLK_1 10
+
+#endif /* __T7_PLL_CLKC_H */
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
+ */
+
+#ifndef __T7_SCMI_CLKC_H
+#define __T7_SCMI_CLKC_H
+
+#define CLKID_DDR_PLL_OSC 0
+#define CLKID_AUD_PLL_OSC 1
+#define CLKID_TOP_PLL_OSC 2
+#define CLKID_TCON_PLL_OSC 3
+#define CLKID_USB_PLL0_OSC 4
+#define CLKID_USB_PLL1_OSC 5
+#define CLKID_MCLK_PLL_OSC 6
+#define CLKID_PCIE_OSC 7
+#define CLKID_ETH_PLL_OSC 8
+#define CLKID_PCIE_REFCLK_PLL_OSC 9
+#define CLKID_EARC_OSC 10
+#define CLKID_SYS1_PLL_OSC 11
+#define CLKID_HDMI_PLL_OSC 12
+#define CLKID_SYS_CLK 13
+#define CLKID_AXI_CLK 14
+#define CLKID_FIXED_PLL_DCO 15
+#define CLKID_FIXED_PLL 16
+#define CLKID_FCLK_DIV2_DIV 17
+#define CLKID_FCLK_DIV2 18
+#define CLKID_FCLK_DIV2P5_DIV 19
+#define CLKID_FCLK_DIV2P5 20
+#define CLKID_FCLK_DIV3_DIV 21
+#define CLKID_FCLK_DIV3 22
+#define CLKID_FCLK_DIV4_DIV 23
+#define CLKID_FCLK_DIV4 24
+#define CLKID_FCLK_DIV5_DIV 25
+#define CLKID_FCLK_DIV5 26
+#define CLKID_FCLK_DIV7_DIV 27
+#define CLKID_FCLK_DIV7 28
+#define CLKID_FCLK_50M_DIV 29
+#define CLKID_FCLK_50M 30
+#define CLKID_CPU_CLK 31
+#define CLKID_A73_CLK 32
+#define CLKID_CPU_CLK_DIV16_DIV 33
+#define CLKID_CPU_CLK_DIV16 34
+#define CLKID_A73_CLK_DIV16_DIV 35
+#define CLKID_A73_CLK_DIV16 36
+
+#endif /* __T7_SCMI_CLKC_H */
#define ASPEED_RESET_AHB 8
#define ASPEED_RESET_CRT1 9
#define ASPEED_RESET_HACE 10
+#define ASPEED_RESET_VIDEO 11
#endif
#define CLK_APM_PLL_DIV4_APM 70
#define CLK_APM_PLL_DIV16_APM 71
+/* CMU_DPU */
+#define CLK_MOUT_DPU_BUS_USER 1
+#define CLK_DOUT_DPU_BUSP 2
+#define CLK_GOUT_DPU_PCLK 3
+#define CLK_GOUT_DPU_CLK_DPU_OSCCLK_CLK 4
+#define CLK_GOUT_DPU_AD_APB_DPU_DMA_PCLKM 5
+#define CLK_GOUT_DPU_DPUF_ACLK_DMA 6
+#define CLK_GOUT_DPU_DPUF_ACLK_DPP 7
+#define CLK_GOUT_DPU_D_TZPC_DPU_PCLK 8
+#define CLK_GOUT_DPU_GPC_DPU_PCLK 9
+#define CLK_GOUT_DPU_LHM_AXI_P_DPU_I_CLK 10
+#define CLK_GOUT_DPU_LHS_AXI_D0_DPU_I_CLK 11
+#define CLK_GOUT_DPU_LHS_AXI_D1_DPU_I_CLK 12
+#define CLK_GOUT_DPU_LHS_AXI_D2_DPU_I_CLK 13
+#define CLK_GOUT_DPU_PPMU_DPUD0_ACLK 14
+#define CLK_GOUT_DPU_PPMU_DPUD0_PCLK 15
+#define CLK_GOUT_DPU_PPMU_DPUD1_ACLK 16
+#define CLK_GOUT_DPU_PPMU_DPUD1_PCLK 17
+#define CLK_GOUT_DPU_PPMU_DPUD2_ACLK 18
+#define CLK_GOUT_DPU_PPMU_DPUD2_PCLK 19
+#define CLK_GOUT_DPU_CLK_DPU_BUSD_CLK 20
+#define CLK_GOUT_DPU_CLK_DPU_BUSP_CLK 21
+#define CLK_GOUT_DPU_SSMT_DPU0_ACLK 22
+#define CLK_GOUT_DPU_SSMT_DPU0_PCLK 23
+#define CLK_GOUT_DPU_SSMT_DPU1_ACLK 24
+#define CLK_GOUT_DPU_SSMT_DPU1_PCLK 25
+#define CLK_GOUT_DPU_SSMT_DPU2_ACLK 26
+#define CLK_GOUT_DPU_SSMT_DPU2_PCLK 27
+#define CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S1 28
+#define CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S2 29
+#define CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S1 30
+#define CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S2 31
+#define CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S1 32
+#define CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S2 33
+#define CLK_GOUT_DPU_SYSREG_DPU_PCLK 34
+
/* CMU_HSI0 */
#define CLK_FOUT_USB_PLL 1
#define CLK_MOUT_PLL_USB 2
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef DT_CLOCK_OXSEMI_OX810SE_H
-#define DT_CLOCK_OXSEMI_OX810SE_H
-
-#define CLK_810_LEON 0
-#define CLK_810_DMA_SGDMA 1
-#define CLK_810_CIPHER 2
-#define CLK_810_SATA 3
-#define CLK_810_AUDIO 4
-#define CLK_810_USBMPH 5
-#define CLK_810_ETHA 6
-#define CLK_810_PCIEA 7
-#define CLK_810_NAND 8
-
-#endif /* DT_CLOCK_OXSEMI_OX810SE_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef DT_CLOCK_OXSEMI_OX820_H
-#define DT_CLOCK_OXSEMI_OX820_H
-
-/* PLLs */
-#define CLK_820_PLLA 0
-#define CLK_820_PLLB 1
-
-/* Gate Clocks */
-#define CLK_820_LEON 2
-#define CLK_820_DMA_SGDMA 3
-#define CLK_820_CIPHER 4
-#define CLK_820_SD 5
-#define CLK_820_SATA 6
-#define CLK_820_AUDIO 7
-#define CLK_820_USBMPH 8
-#define CLK_820_ETHA 9
-#define CLK_820_PCIEA 10
-#define CLK_820_NAND 11
-#define CLK_820_PCIEB 12
-#define CLK_820_ETHB 13
-#define CLK_820_REF600 14
-#define CLK_820_USBDEV 15
-
-#endif /* DT_CLOCK_OXSEMI_OX820_H */
#define MSM8937_GCC_MDSS_PCLK1_CLK 179
#define MSM8937_GCC_OXILI_AON_CLK 180
#define MSM8937_GCC_OXILI_TIMER_CLK 181
+#define MSM8940_GCC_IPA_TBU_CLK 182
/* GCC block resets */
#define GCC_CAMSS_MICRO_BCR 0
#define GCC_QUSB2_PHY_BCR 2
#define GCC_USB_HS_BCR 3
#define GCC_USB2_HS_PHY_ONLY_BCR 4
+#define GCC_MDSS_BCR 5
/* GDSCs */
#define CPP_GDSC 0
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_CAM_BIST_MCLK_CC_KAANAPALI_H
+#define _DT_BINDINGS_CLK_QCOM_CAM_BIST_MCLK_CC_KAANAPALI_H
+
+/* CAM_BIST_MCLK_CC clocks */
+#define CAM_BIST_MCLK_CC_DEBUG_CLK 0
+#define CAM_BIST_MCLK_CC_DEBUG_DIV_CLK_SRC 1
+#define CAM_BIST_MCLK_CC_MCLK0_CLK 2
+#define CAM_BIST_MCLK_CC_MCLK0_CLK_SRC 3
+#define CAM_BIST_MCLK_CC_MCLK1_CLK 4
+#define CAM_BIST_MCLK_CC_MCLK1_CLK_SRC 5
+#define CAM_BIST_MCLK_CC_MCLK2_CLK 6
+#define CAM_BIST_MCLK_CC_MCLK2_CLK_SRC 7
+#define CAM_BIST_MCLK_CC_MCLK3_CLK 8
+#define CAM_BIST_MCLK_CC_MCLK3_CLK_SRC 9
+#define CAM_BIST_MCLK_CC_MCLK4_CLK 10
+#define CAM_BIST_MCLK_CC_MCLK4_CLK_SRC 11
+#define CAM_BIST_MCLK_CC_MCLK5_CLK 12
+#define CAM_BIST_MCLK_CC_MCLK5_CLK_SRC 13
+#define CAM_BIST_MCLK_CC_MCLK6_CLK 14
+#define CAM_BIST_MCLK_CC_MCLK6_CLK_SRC 15
+#define CAM_BIST_MCLK_CC_MCLK7_CLK 16
+#define CAM_BIST_MCLK_CC_MCLK7_CLK_SRC 17
+#define CAM_BIST_MCLK_CC_PLL0 18
+#define CAM_BIST_MCLK_CC_PLL_TEST_CLK 19
+#define CAM_BIST_MCLK_CC_PLL_TEST_DIV_CLK_SRC 20
+#define CAM_BIST_MCLK_CC_SLEEP_CLK 21
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_KAANAPALI_H
+#define _DT_BINDINGS_CLK_QCOM_CAM_CC_KAANAPALI_H
+
+/* CAM_CC clocks */
+#define CAM_CC_CAM_TOP_AHB_CLK 0
+#define CAM_CC_CAM_TOP_FAST_AHB_CLK 1
+#define CAM_CC_CAMNOC_DCD_XO_CLK 2
+#define CAM_CC_CAMNOC_NRT_AXI_CLK 3
+#define CAM_CC_CAMNOC_NRT_CRE_CLK 4
+#define CAM_CC_CAMNOC_NRT_IPE_NPS_CLK 5
+#define CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK 6
+#define CAM_CC_CAMNOC_RT_AXI_CLK 7
+#define CAM_CC_CAMNOC_RT_AXI_CLK_SRC 8
+#define CAM_CC_CAMNOC_RT_IFE_LITE_CLK 9
+#define CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK 10
+#define CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK 11
+#define CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK 12
+#define CAM_CC_CAMNOC_XO_CLK 13
+#define CAM_CC_CCI_0_CLK 14
+#define CAM_CC_CCI_0_CLK_SRC 15
+#define CAM_CC_CCI_1_CLK 16
+#define CAM_CC_CCI_1_CLK_SRC 17
+#define CAM_CC_CCI_2_CLK 18
+#define CAM_CC_CCI_2_CLK_SRC 19
+#define CAM_CC_CORE_AHB_CLK 20
+#define CAM_CC_CPHY_RX_CLK_SRC 21
+#define CAM_CC_CRE_AHB_CLK 22
+#define CAM_CC_CRE_CLK 23
+#define CAM_CC_CRE_CLK_SRC 24
+#define CAM_CC_CSI0PHYTIMER_CLK 25
+#define CAM_CC_CSI0PHYTIMER_CLK_SRC 26
+#define CAM_CC_CSI1PHYTIMER_CLK 27
+#define CAM_CC_CSI1PHYTIMER_CLK_SRC 28
+#define CAM_CC_CSI2PHYTIMER_CLK 29
+#define CAM_CC_CSI2PHYTIMER_CLK_SRC 30
+#define CAM_CC_CSI3PHYTIMER_CLK 31
+#define CAM_CC_CSI3PHYTIMER_CLK_SRC 32
+#define CAM_CC_CSI4PHYTIMER_CLK 33
+#define CAM_CC_CSI4PHYTIMER_CLK_SRC 34
+#define CAM_CC_CSI5PHYTIMER_CLK 35
+#define CAM_CC_CSI5PHYTIMER_CLK_SRC 36
+#define CAM_CC_CSID_CLK 37
+#define CAM_CC_CSID_CLK_SRC 38
+#define CAM_CC_CSID_CSIPHY_RX_CLK 39
+#define CAM_CC_CSIPHY0_CLK 40
+#define CAM_CC_CSIPHY1_CLK 41
+#define CAM_CC_CSIPHY2_CLK 42
+#define CAM_CC_CSIPHY3_CLK 43
+#define CAM_CC_CSIPHY4_CLK 44
+#define CAM_CC_CSIPHY5_CLK 45
+#define CAM_CC_DRV_AHB_CLK 46
+#define CAM_CC_DRV_XO_CLK 47
+#define CAM_CC_FAST_AHB_CLK_SRC 48
+#define CAM_CC_GDSC_CLK 49
+#define CAM_CC_ICP_0_AHB_CLK 50
+#define CAM_CC_ICP_0_CLK 51
+#define CAM_CC_ICP_0_CLK_SRC 52
+#define CAM_CC_ICP_1_AHB_CLK 53
+#define CAM_CC_ICP_1_CLK 54
+#define CAM_CC_ICP_1_CLK_SRC 55
+#define CAM_CC_IFE_LITE_AHB_CLK 56
+#define CAM_CC_IFE_LITE_CLK 57
+#define CAM_CC_IFE_LITE_CLK_SRC 58
+#define CAM_CC_IFE_LITE_CPHY_RX_CLK 59
+#define CAM_CC_IFE_LITE_CSID_CLK 60
+#define CAM_CC_IFE_LITE_CSID_CLK_SRC 61
+#define CAM_CC_IPE_NPS_AHB_CLK 62
+#define CAM_CC_IPE_NPS_CLK 63
+#define CAM_CC_IPE_NPS_CLK_SRC 64
+#define CAM_CC_IPE_NPS_FAST_AHB_CLK 65
+#define CAM_CC_IPE_PPS_CLK 66
+#define CAM_CC_IPE_PPS_FAST_AHB_CLK 67
+#define CAM_CC_JPEG_CLK 68
+#define CAM_CC_JPEG_CLK_SRC 69
+#define CAM_CC_OFE_AHB_CLK 70
+#define CAM_CC_OFE_ANCHOR_CLK 71
+#define CAM_CC_OFE_ANCHOR_FAST_AHB_CLK 72
+#define CAM_CC_OFE_CLK_SRC 73
+#define CAM_CC_OFE_HDR_CLK 74
+#define CAM_CC_OFE_HDR_FAST_AHB_CLK 75
+#define CAM_CC_OFE_MAIN_CLK 76
+#define CAM_CC_OFE_MAIN_FAST_AHB_CLK 77
+#define CAM_CC_PLL0 78
+#define CAM_CC_PLL0_OUT_EVEN 79
+#define CAM_CC_PLL0_OUT_ODD 80
+#define CAM_CC_PLL1 81
+#define CAM_CC_PLL1_OUT_EVEN 82
+#define CAM_CC_PLL2 83
+#define CAM_CC_PLL2_OUT_EVEN 84
+#define CAM_CC_PLL3 85
+#define CAM_CC_PLL3_OUT_EVEN 86
+#define CAM_CC_PLL4 87
+#define CAM_CC_PLL4_OUT_EVEN 88
+#define CAM_CC_PLL5 89
+#define CAM_CC_PLL5_OUT_EVEN 90
+#define CAM_CC_PLL6 91
+#define CAM_CC_PLL6_OUT_EVEN 92
+#define CAM_CC_PLL6_OUT_ODD 93
+#define CAM_CC_PLL7 94
+#define CAM_CC_PLL7_OUT_EVEN 95
+#define CAM_CC_QDSS_DEBUG_CLK 96
+#define CAM_CC_QDSS_DEBUG_CLK_SRC 97
+#define CAM_CC_QDSS_DEBUG_XO_CLK 98
+#define CAM_CC_SLEEP_CLK 99
+#define CAM_CC_SLOW_AHB_CLK_SRC 100
+#define CAM_CC_TFE_0_BAYER_CLK 101
+#define CAM_CC_TFE_0_BAYER_FAST_AHB_CLK 102
+#define CAM_CC_TFE_0_CLK_SRC 103
+#define CAM_CC_TFE_0_MAIN_CLK 104
+#define CAM_CC_TFE_0_MAIN_FAST_AHB_CLK 105
+#define CAM_CC_TFE_1_BAYER_CLK 106
+#define CAM_CC_TFE_1_BAYER_FAST_AHB_CLK 107
+#define CAM_CC_TFE_1_CLK_SRC 108
+#define CAM_CC_TFE_1_MAIN_CLK 109
+#define CAM_CC_TFE_1_MAIN_FAST_AHB_CLK 110
+#define CAM_CC_TFE_2_BAYER_CLK 111
+#define CAM_CC_TFE_2_BAYER_FAST_AHB_CLK 112
+#define CAM_CC_TFE_2_CLK_SRC 113
+#define CAM_CC_TFE_2_MAIN_CLK 114
+#define CAM_CC_TFE_2_MAIN_FAST_AHB_CLK 115
+#define CAM_CC_TRACENOC_TPDM_1_CMB_CLK 116
+#define CAM_CC_XO_CLK_SRC 117
+
+/* CAM_CC power domains */
+#define CAM_CC_IPE_0_GDSC 0
+#define CAM_CC_OFE_GDSC 1
+#define CAM_CC_TFE_0_GDSC 2
+#define CAM_CC_TFE_1_GDSC 3
+#define CAM_CC_TFE_2_GDSC 4
+#define CAM_CC_TITAN_TOP_GDSC 5
+
+/* CAM_CC resets */
+#define CAM_CC_DRV_BCR 0
+#define CAM_CC_ICP_BCR 1
+#define CAM_CC_IPE_0_BCR 2
+#define CAM_CC_OFE_BCR 3
+#define CAM_CC_QDSS_DEBUG_BCR 4
+#define CAM_CC_TFE_0_BCR 5
+#define CAM_CC_TFE_1_BCR 6
+#define CAM_CC_TFE_2_BCR 7
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_KAANAPALI_H
+#define _DT_BINDINGS_CLK_QCOM_DISP_CC_KAANAPALI_H
+
+/* DISP_CC clocks */
+#define DISP_CC_ESYNC0_CLK 0
+#define DISP_CC_ESYNC0_CLK_SRC 1
+#define DISP_CC_ESYNC1_CLK 2
+#define DISP_CC_ESYNC1_CLK_SRC 3
+#define DISP_CC_MDSS_ACCU_SHIFT_CLK 4
+#define DISP_CC_MDSS_AHB1_CLK 5
+#define DISP_CC_MDSS_AHB_CLK 6
+#define DISP_CC_MDSS_AHB_CLK_SRC 7
+#define DISP_CC_MDSS_AHB_SWI_CLK 8
+#define DISP_CC_MDSS_AHB_SWI_DIV_CLK_SRC 9
+#define DISP_CC_MDSS_BYTE0_CLK 10
+#define DISP_CC_MDSS_BYTE0_CLK_SRC 11
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 12
+#define DISP_CC_MDSS_BYTE0_INTF_CLK 13
+#define DISP_CC_MDSS_BYTE1_CLK 14
+#define DISP_CC_MDSS_BYTE1_CLK_SRC 15
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 16
+#define DISP_CC_MDSS_BYTE1_INTF_CLK 17
+#define DISP_CC_MDSS_DPTX0_AUX_CLK 18
+#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 19
+#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 20
+#define DISP_CC_MDSS_DPTX0_LINK_CLK 21
+#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 22
+#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 23
+#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 24
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 25
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 26
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 27
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 28
+#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 29
+#define DISP_CC_MDSS_DPTX1_AUX_CLK 30
+#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 31
+#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 32
+#define DISP_CC_MDSS_DPTX1_LINK_CLK 33
+#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 34
+#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 35
+#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 36
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 37
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 38
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 39
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 40
+#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 41
+#define DISP_CC_MDSS_DPTX2_AUX_CLK 42
+#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 43
+#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 44
+#define DISP_CC_MDSS_DPTX2_LINK_CLK 45
+#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 46
+#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 47
+#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 48
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 49
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 50
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 51
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 52
+#define DISP_CC_MDSS_DPTX3_AUX_CLK 53
+#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 54
+#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 55
+#define DISP_CC_MDSS_DPTX3_LINK_CLK 56
+#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 57
+#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 58
+#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 59
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 60
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 61
+#define DISP_CC_MDSS_ESC0_CLK 62
+#define DISP_CC_MDSS_ESC0_CLK_SRC 63
+#define DISP_CC_MDSS_ESC1_CLK 64
+#define DISP_CC_MDSS_ESC1_CLK_SRC 65
+#define DISP_CC_MDSS_MDP1_CLK 66
+#define DISP_CC_MDSS_MDP_CLK 67
+#define DISP_CC_MDSS_MDP_CLK_SRC 68
+#define DISP_CC_MDSS_MDP_LUT1_CLK 69
+#define DISP_CC_MDSS_MDP_LUT_CLK 70
+#define DISP_CC_MDSS_MDP_SS_IP_CLK 71
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 72
+#define DISP_CC_MDSS_PCLK0_CLK 73
+#define DISP_CC_MDSS_PCLK0_CLK_SRC 74
+#define DISP_CC_MDSS_PCLK1_CLK 75
+#define DISP_CC_MDSS_PCLK1_CLK_SRC 76
+#define DISP_CC_MDSS_PCLK2_CLK 77
+#define DISP_CC_MDSS_PCLK2_CLK_SRC 78
+#define DISP_CC_MDSS_VSYNC1_CLK 79
+#define DISP_CC_MDSS_VSYNC_CLK 80
+#define DISP_CC_MDSS_VSYNC_CLK_SRC 81
+#define DISP_CC_OSC_CLK 82
+#define DISP_CC_OSC_CLK_SRC 83
+#define DISP_CC_PLL0 84
+#define DISP_CC_PLL1 85
+#define DISP_CC_PLL2 86
+#define DISP_CC_SLEEP_CLK 87
+#define DISP_CC_XO_CLK 88
+
+/* DISP_CC power domains */
+#define DISP_CC_MDSS_CORE_GDSC 0
+#define DISP_CC_MDSS_CORE_INT2_GDSC 1
+
+/* DISP_CC resets */
+#define DISP_CC_MDSS_CORE_BCR 0
+#define DISP_CC_MDSS_CORE_INT2_BCR 1
+#define DISP_CC_MDSS_RSCC_BCR 2
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_KAANAPALI_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_KAANAPALI_H
+
+/* GPU_CC clocks */
+#define GPU_CC_AHB_CLK 0
+#define GPU_CC_CB_CLK 1
+#define GPU_CC_CX_ACCU_SHIFT_CLK 2
+#define GPU_CC_CX_GMU_CLK 3
+#define GPU_CC_CXO_AON_CLK 4
+#define GPU_CC_CXO_CLK 5
+#define GPU_CC_DEMET_CLK 6
+#define GPU_CC_DPM_CLK 7
+#define GPU_CC_FF_CLK_SRC 8
+#define GPU_CC_FREQ_MEASURE_CLK 9
+#define GPU_CC_GMU_CLK_SRC 10
+#define GPU_CC_GPU_SMMU_VOTE_CLK 11
+#define GPU_CC_GX_ACCU_SHIFT_CLK 12
+#define GPU_CC_GX_GMU_CLK 13
+#define GPU_CC_HUB_AON_CLK 14
+#define GPU_CC_HUB_CLK_SRC 15
+#define GPU_CC_HUB_CX_INT_CLK 16
+#define GPU_CC_HUB_DIV_CLK_SRC 17
+#define GPU_CC_MEMNOC_GFX_CLK 18
+#define GPU_CC_PLL0 19
+#define GPU_CC_PLL0_OUT_EVEN 20
+#define GPU_CC_RSCC_HUB_AON_CLK 21
+#define GPU_CC_RSCC_XO_AON_CLK 22
+#define GPU_CC_SLEEP_CLK 23
+
+/* GPU_CC power domains */
+#define GPU_CC_CX_GDSC 0
+
+/* GPU_CC resets */
+#define GPU_CC_CB_BCR 0
+#define GPU_CC_CX_BCR 1
+#define GPU_CC_FAST_HUB_BCR 2
+#define GPU_CC_FF_BCR 3
+#define GPU_CC_GMU_BCR 4
+#define GPU_CC_GX_BCR 5
+#define GPU_CC_XO_BCR 6
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GX_CLKCTL_KAANAPALI_H
+#define _DT_BINDINGS_CLK_QCOM_GX_CLKCTL_KAANAPALI_H
+
+/* GX_CLKCTL power domains */
+#define GX_CLKCTL_GX_GDSC 0
+#define GX_CLKCTL_GX_SLICE_GDSC 1
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_KAANAPALI_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_KAANAPALI_H
+
+/* VIDEO_CC clocks */
+#define VIDEO_CC_AHB_CLK 0
+#define VIDEO_CC_AHB_CLK_SRC 1
+#define VIDEO_CC_MVS0_CLK 2
+#define VIDEO_CC_MVS0_CLK_SRC 3
+#define VIDEO_CC_MVS0_FREERUN_CLK 4
+#define VIDEO_CC_MVS0_SHIFT_CLK 5
+#define VIDEO_CC_MVS0_VPP0_CLK 6
+#define VIDEO_CC_MVS0_VPP0_FREERUN_CLK 7
+#define VIDEO_CC_MVS0_VPP1_CLK 8
+#define VIDEO_CC_MVS0_VPP1_FREERUN_CLK 9
+#define VIDEO_CC_MVS0A_CLK 10
+#define VIDEO_CC_MVS0A_CLK_SRC 11
+#define VIDEO_CC_MVS0A_FREERUN_CLK 12
+#define VIDEO_CC_MVS0B_CLK 13
+#define VIDEO_CC_MVS0B_CLK_SRC 14
+#define VIDEO_CC_MVS0B_FREERUN_CLK 15
+#define VIDEO_CC_MVS0C_CLK 16
+#define VIDEO_CC_MVS0C_CLK_SRC 17
+#define VIDEO_CC_MVS0C_FREERUN_CLK 18
+#define VIDEO_CC_MVS0C_SHIFT_CLK 19
+#define VIDEO_CC_PLL0 20
+#define VIDEO_CC_PLL1 21
+#define VIDEO_CC_PLL2 22
+#define VIDEO_CC_PLL3 23
+#define VIDEO_CC_SLEEP_CLK 24
+#define VIDEO_CC_TS_XO_CLK 25
+#define VIDEO_CC_XO_CLK 26
+#define VIDEO_CC_XO_CLK_SRC 27
+
+/* VIDEO_CC power domains */
+#define VIDEO_CC_MVS0A_GDSC 0
+#define VIDEO_CC_MVS0_GDSC 1
+#define VIDEO_CC_MVS0_VPP1_GDSC 2
+#define VIDEO_CC_MVS0_VPP0_GDSC 3
+#define VIDEO_CC_MVS0C_GDSC 4
+
+/* VIDEO_CC resets */
+#define VIDEO_CC_INTERFACE_BCR 0
+#define VIDEO_CC_MVS0_BCR 1
+#define VIDEO_CC_MVS0_VPP0_BCR 2
+#define VIDEO_CC_MVS0_VPP1_BCR 3
+#define VIDEO_CC_MVS0A_BCR 4
+#define VIDEO_CC_MVS0C_CLK_ARES 5
+#define VIDEO_CC_MVS0C_BCR 6
+#define VIDEO_CC_MVS0_FREERUN_CLK_ARES 7
+#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES 8
+#define VIDEO_CC_XO_CLK_ARES 9
+
+#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_CLK_QCOM_MSS_SC7180_H
-#define _DT_BINDINGS_CLK_QCOM_MSS_SC7180_H
-
-#define MSS_AXI_CRYPTO_CLK 0
-#define MSS_AXI_NAV_CLK 1
-
-#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_CAM_BIST_MCLK_CC_SM8750_H
+#define _DT_BINDINGS_CLK_QCOM_CAM_BIST_MCLK_CC_SM8750_H
+
+/* CAM_BIST_MCLK_CC clocks */
+#define CAM_BIST_MCLK_CC_MCLK0_CLK 0
+#define CAM_BIST_MCLK_CC_MCLK0_CLK_SRC 1
+#define CAM_BIST_MCLK_CC_MCLK1_CLK 2
+#define CAM_BIST_MCLK_CC_MCLK1_CLK_SRC 3
+#define CAM_BIST_MCLK_CC_MCLK2_CLK 4
+#define CAM_BIST_MCLK_CC_MCLK2_CLK_SRC 5
+#define CAM_BIST_MCLK_CC_MCLK3_CLK 6
+#define CAM_BIST_MCLK_CC_MCLK3_CLK_SRC 7
+#define CAM_BIST_MCLK_CC_MCLK4_CLK 8
+#define CAM_BIST_MCLK_CC_MCLK4_CLK_SRC 9
+#define CAM_BIST_MCLK_CC_MCLK5_CLK 10
+#define CAM_BIST_MCLK_CC_MCLK5_CLK_SRC 11
+#define CAM_BIST_MCLK_CC_MCLK6_CLK 12
+#define CAM_BIST_MCLK_CC_MCLK6_CLK_SRC 13
+#define CAM_BIST_MCLK_CC_MCLK7_CLK 14
+#define CAM_BIST_MCLK_CC_MCLK7_CLK_SRC 15
+#define CAM_BIST_MCLK_CC_PLL0 16
+#define CAM_BIST_MCLK_CC_SLEEP_CLK 17
+#define CAM_BIST_MCLK_CC_SLEEP_CLK_SRC 18
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8750_H
+#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8750_H
+
+/* CAM_CC clocks */
+#define CAM_CC_CAM_TOP_AHB_CLK 0
+#define CAM_CC_CAM_TOP_FAST_AHB_CLK 1
+#define CAM_CC_CAMNOC_DCD_XO_CLK 2
+#define CAM_CC_CAMNOC_NRT_AXI_CLK 3
+#define CAM_CC_CAMNOC_NRT_CRE_CLK 4
+#define CAM_CC_CAMNOC_NRT_IPE_NPS_CLK 5
+#define CAM_CC_CAMNOC_NRT_OFE_ANCHOR_CLK 6
+#define CAM_CC_CAMNOC_NRT_OFE_HDR_CLK 7
+#define CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK 8
+#define CAM_CC_CAMNOC_RT_AXI_CLK 9
+#define CAM_CC_CAMNOC_RT_AXI_CLK_SRC 10
+#define CAM_CC_CAMNOC_RT_IFE_LITE_CLK 11
+#define CAM_CC_CAMNOC_RT_TFE_0_BAYER_CLK 12
+#define CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK 13
+#define CAM_CC_CAMNOC_RT_TFE_1_BAYER_CLK 14
+#define CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK 15
+#define CAM_CC_CAMNOC_RT_TFE_2_BAYER_CLK 16
+#define CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK 17
+#define CAM_CC_CAMNOC_XO_CLK 18
+#define CAM_CC_CCI_0_CLK 19
+#define CAM_CC_CCI_0_CLK_SRC 20
+#define CAM_CC_CCI_1_CLK 21
+#define CAM_CC_CCI_1_CLK_SRC 22
+#define CAM_CC_CCI_2_CLK 23
+#define CAM_CC_CCI_2_CLK_SRC 24
+#define CAM_CC_CORE_AHB_CLK 25
+#define CAM_CC_CPHY_RX_CLK_SRC 26
+#define CAM_CC_CRE_AHB_CLK 27
+#define CAM_CC_CRE_CLK 28
+#define CAM_CC_CRE_CLK_SRC 29
+#define CAM_CC_CSI0PHYTIMER_CLK 30
+#define CAM_CC_CSI0PHYTIMER_CLK_SRC 31
+#define CAM_CC_CSI1PHYTIMER_CLK 32
+#define CAM_CC_CSI1PHYTIMER_CLK_SRC 33
+#define CAM_CC_CSI2PHYTIMER_CLK 34
+#define CAM_CC_CSI2PHYTIMER_CLK_SRC 35
+#define CAM_CC_CSI3PHYTIMER_CLK 36
+#define CAM_CC_CSI3PHYTIMER_CLK_SRC 37
+#define CAM_CC_CSI4PHYTIMER_CLK 38
+#define CAM_CC_CSI4PHYTIMER_CLK_SRC 39
+#define CAM_CC_CSI5PHYTIMER_CLK 40
+#define CAM_CC_CSI5PHYTIMER_CLK_SRC 41
+#define CAM_CC_CSID_CLK 42
+#define CAM_CC_CSID_CLK_SRC 43
+#define CAM_CC_CSID_CSIPHY_RX_CLK 44
+#define CAM_CC_CSIPHY0_CLK 45
+#define CAM_CC_CSIPHY1_CLK 46
+#define CAM_CC_CSIPHY2_CLK 47
+#define CAM_CC_CSIPHY3_CLK 48
+#define CAM_CC_CSIPHY4_CLK 49
+#define CAM_CC_CSIPHY5_CLK 50
+#define CAM_CC_DRV_AHB_CLK 51
+#define CAM_CC_DRV_XO_CLK 52
+#define CAM_CC_FAST_AHB_CLK_SRC 53
+#define CAM_CC_GDSC_CLK 54
+#define CAM_CC_ICP_0_AHB_CLK 55
+#define CAM_CC_ICP_0_CLK 56
+#define CAM_CC_ICP_0_CLK_SRC 57
+#define CAM_CC_ICP_1_AHB_CLK 58
+#define CAM_CC_ICP_1_CLK 59
+#define CAM_CC_ICP_1_CLK_SRC 60
+#define CAM_CC_IFE_LITE_AHB_CLK 61
+#define CAM_CC_IFE_LITE_CLK 62
+#define CAM_CC_IFE_LITE_CLK_SRC 63
+#define CAM_CC_IFE_LITE_CPHY_RX_CLK 64
+#define CAM_CC_IFE_LITE_CSID_CLK 65
+#define CAM_CC_IFE_LITE_CSID_CLK_SRC 66
+#define CAM_CC_IPE_NPS_AHB_CLK 67
+#define CAM_CC_IPE_NPS_CLK 68
+#define CAM_CC_IPE_NPS_CLK_SRC 69
+#define CAM_CC_IPE_NPS_FAST_AHB_CLK 70
+#define CAM_CC_IPE_PPS_CLK 71
+#define CAM_CC_IPE_PPS_FAST_AHB_CLK 72
+#define CAM_CC_JPEG_0_CLK 73
+#define CAM_CC_JPEG_1_CLK 74
+#define CAM_CC_JPEG_CLK_SRC 75
+#define CAM_CC_OFE_AHB_CLK 76
+#define CAM_CC_OFE_ANCHOR_CLK 77
+#define CAM_CC_OFE_ANCHOR_FAST_AHB_CLK 78
+#define CAM_CC_OFE_CLK_SRC 79
+#define CAM_CC_OFE_HDR_CLK 80
+#define CAM_CC_OFE_HDR_FAST_AHB_CLK 81
+#define CAM_CC_OFE_MAIN_CLK 82
+#define CAM_CC_OFE_MAIN_FAST_AHB_CLK 83
+#define CAM_CC_PLL0 84
+#define CAM_CC_PLL0_OUT_EVEN 85
+#define CAM_CC_PLL0_OUT_ODD 86
+#define CAM_CC_PLL1 87
+#define CAM_CC_PLL1_OUT_EVEN 88
+#define CAM_CC_PLL2 89
+#define CAM_CC_PLL2_OUT_EVEN 90
+#define CAM_CC_PLL3 91
+#define CAM_CC_PLL3_OUT_EVEN 92
+#define CAM_CC_PLL4 93
+#define CAM_CC_PLL4_OUT_EVEN 94
+#define CAM_CC_PLL5 95
+#define CAM_CC_PLL5_OUT_EVEN 96
+#define CAM_CC_PLL6 97
+#define CAM_CC_PLL6_OUT_EVEN 98
+#define CAM_CC_PLL6_OUT_ODD 99
+#define CAM_CC_QDSS_DEBUG_CLK 100
+#define CAM_CC_QDSS_DEBUG_CLK_SRC 101
+#define CAM_CC_QDSS_DEBUG_XO_CLK 102
+#define CAM_CC_SLEEP_CLK 103
+#define CAM_CC_SLEEP_CLK_SRC 104
+#define CAM_CC_SLOW_AHB_CLK_SRC 105
+#define CAM_CC_TFE_0_BAYER_CLK 106
+#define CAM_CC_TFE_0_BAYER_FAST_AHB_CLK 107
+#define CAM_CC_TFE_0_CLK_SRC 108
+#define CAM_CC_TFE_0_MAIN_CLK 109
+#define CAM_CC_TFE_0_MAIN_FAST_AHB_CLK 110
+#define CAM_CC_TFE_1_BAYER_CLK 111
+#define CAM_CC_TFE_1_BAYER_FAST_AHB_CLK 112
+#define CAM_CC_TFE_1_CLK_SRC 113
+#define CAM_CC_TFE_1_MAIN_CLK 114
+#define CAM_CC_TFE_1_MAIN_FAST_AHB_CLK 115
+#define CAM_CC_TFE_2_BAYER_CLK 116
+#define CAM_CC_TFE_2_BAYER_FAST_AHB_CLK 117
+#define CAM_CC_TFE_2_CLK_SRC 118
+#define CAM_CC_TFE_2_MAIN_CLK 119
+#define CAM_CC_TFE_2_MAIN_FAST_AHB_CLK 120
+#define CAM_CC_XO_CLK_SRC 121
+
+/* CAM_CC power domains */
+#define CAM_CC_TITAN_TOP_GDSC 0
+#define CAM_CC_IPE_0_GDSC 1
+#define CAM_CC_OFE_GDSC 2
+#define CAM_CC_TFE_0_GDSC 3
+#define CAM_CC_TFE_1_GDSC 4
+#define CAM_CC_TFE_2_GDSC 5
+
+/* CAM_CC resets */
+#define CAM_CC_DRV_BCR 0
+#define CAM_CC_ICP_BCR 1
+#define CAM_CC_IPE_0_BCR 2
+#define CAM_CC_OFE_BCR 3
+#define CAM_CC_QDSS_DEBUG_BCR 4
+#define CAM_CC_TFE_0_BCR 5
+#define CAM_CC_TFE_1_BCR 6
+#define CAM_CC_TFE_2_BCR 7
+
+#endif
#define GCC_USB4_2_PHY_RX0_CLK_SRC 377
#define GCC_USB4_2_PHY_RX1_CLK_SRC 378
#define GCC_USB4_2_PHY_SYS_CLK_SRC 379
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 380
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 381
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 382
/* GCC power domains */
#define GCC_PCIE_0_TUNNEL_GDSC 0
#define R9A09G077_ETCLKC 19
#define R9A09G077_ETCLKD 20
#define R9A09G077_ETCLKE 21
+#define R9A09G077_XSPI_CLK0 22
+#define R9A09G077_XSPI_CLK1 23
+#define R9A09G077_PCLKCAN 24
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */
#define R9A09G087_ETCLKC 19
#define R9A09G087_ETCLKD 20
#define R9A09G087_ETCLKE 21
+#define R9A09G087_XSPI_CLK0 22
+#define R9A09G087_XSPI_CLK1 23
+#define R9A09G087_PCLKCAN 24
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */
#define CLK_MOUT_MFC_WFD_USER 2
#define CLK_DOUT_MFC_NOCP 3
+/* CMU_MFD */
+#define CLK_MOUT_MFD_NOC_USER 1
+#define CLK_DOUT_MFD_NOCP 2
+
#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025 SpacemiT Technology Co. Ltd
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_
+#define _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_
+
+/* APBS (PLL) clocks */
+#define CLK_PLL1 0
+#define CLK_PLL2 1
+#define CLK_PLL3 2
+#define CLK_PLL4 3
+#define CLK_PLL5 4
+#define CLK_PLL6 5
+#define CLK_PLL7 6
+#define CLK_PLL8 7
+#define CLK_PLL1_D2 8
+#define CLK_PLL1_D3 9
+#define CLK_PLL1_D4 10
+#define CLK_PLL1_D5 11
+#define CLK_PLL1_D6 12
+#define CLK_PLL1_D7 13
+#define CLK_PLL1_D8 14
+#define CLK_PLL1_DX 15
+#define CLK_PLL1_D64 16
+#define CLK_PLL1_D10_AUD 17
+#define CLK_PLL1_D100_AUD 18
+#define CLK_PLL2_D1 19
+#define CLK_PLL2_D2 20
+#define CLK_PLL2_D3 21
+#define CLK_PLL2_D4 22
+#define CLK_PLL2_D5 23
+#define CLK_PLL2_D6 24
+#define CLK_PLL2_D7 25
+#define CLK_PLL2_D8 26
+#define CLK_PLL2_66 27
+#define CLK_PLL2_33 28
+#define CLK_PLL2_50 29
+#define CLK_PLL2_25 30
+#define CLK_PLL2_20 31
+#define CLK_PLL2_D24_125 32
+#define CLK_PLL2_D120_25 33
+#define CLK_PLL3_D1 34
+#define CLK_PLL3_D2 35
+#define CLK_PLL3_D3 36
+#define CLK_PLL3_D4 37
+#define CLK_PLL3_D5 38
+#define CLK_PLL3_D6 39
+#define CLK_PLL3_D7 40
+#define CLK_PLL3_D8 41
+#define CLK_PLL4_D1 42
+#define CLK_PLL4_D2 43
+#define CLK_PLL4_D3 44
+#define CLK_PLL4_D4 45
+#define CLK_PLL4_D5 46
+#define CLK_PLL4_D6 47
+#define CLK_PLL4_D7 48
+#define CLK_PLL4_D8 49
+#define CLK_PLL5_D1 50
+#define CLK_PLL5_D2 51
+#define CLK_PLL5_D3 52
+#define CLK_PLL5_D4 53
+#define CLK_PLL5_D5 54
+#define CLK_PLL5_D6 55
+#define CLK_PLL5_D7 56
+#define CLK_PLL5_D8 57
+#define CLK_PLL6_D1 58
+#define CLK_PLL6_D2 59
+#define CLK_PLL6_D3 60
+#define CLK_PLL6_D4 61
+#define CLK_PLL6_D5 62
+#define CLK_PLL6_D6 63
+#define CLK_PLL6_D7 64
+#define CLK_PLL6_D8 65
+#define CLK_PLL6_80 66
+#define CLK_PLL6_40 67
+#define CLK_PLL6_20 68
+#define CLK_PLL7_D1 69
+#define CLK_PLL7_D2 70
+#define CLK_PLL7_D3 71
+#define CLK_PLL7_D4 72
+#define CLK_PLL7_D5 73
+#define CLK_PLL7_D6 74
+#define CLK_PLL7_D7 75
+#define CLK_PLL7_D8 76
+#define CLK_PLL8_D1 77
+#define CLK_PLL8_D2 78
+#define CLK_PLL8_D3 79
+#define CLK_PLL8_D4 80
+#define CLK_PLL8_D5 81
+#define CLK_PLL8_D6 82
+#define CLK_PLL8_D7 83
+#define CLK_PLL8_D8 84
+
+/* MPMU clocks */
+#define CLK_MPMU_PLL1_307P2 0
+#define CLK_MPMU_PLL1_76P8 1
+#define CLK_MPMU_PLL1_61P44 2
+#define CLK_MPMU_PLL1_153P6 3
+#define CLK_MPMU_PLL1_102P4 4
+#define CLK_MPMU_PLL1_51P2 5
+#define CLK_MPMU_PLL1_51P2_AP 6
+#define CLK_MPMU_PLL1_57P6 7
+#define CLK_MPMU_PLL1_25P6 8
+#define CLK_MPMU_PLL1_12P8 9
+#define CLK_MPMU_PLL1_12P8_WDT 10
+#define CLK_MPMU_PLL1_6P4 11
+#define CLK_MPMU_PLL1_3P2 12
+#define CLK_MPMU_PLL1_1P6 13
+#define CLK_MPMU_PLL1_0P8 14
+#define CLK_MPMU_PLL1_409P6 15
+#define CLK_MPMU_PLL1_204P8 16
+#define CLK_MPMU_PLL1_491 17
+#define CLK_MPMU_PLL1_245P76 18
+#define CLK_MPMU_PLL1_614 19
+#define CLK_MPMU_PLL1_47P26 20
+#define CLK_MPMU_PLL1_31P5 21
+#define CLK_MPMU_PLL1_819 22
+#define CLK_MPMU_PLL1_1228 23
+#define CLK_MPMU_APB 24
+#define CLK_MPMU_SLOW_UART 25
+#define CLK_MPMU_SLOW_UART1 26
+#define CLK_MPMU_SLOW_UART2 27
+#define CLK_MPMU_WDT 28
+#define CLK_MPMU_WDT_BUS 29
+#define CLK_MPMU_RIPC 30
+#define CLK_MPMU_I2S_153P6 31
+#define CLK_MPMU_I2S_153P6_BASE 32
+#define CLK_MPMU_I2S_SYSCLK_SRC 33
+#define CLK_MPMU_I2S1_SYSCLK 34
+#define CLK_MPMU_I2S_BCLK 35
+#define CLK_MPMU_I2S0_SYSCLK_SEL 36
+#define CLK_MPMU_I2S2_SYSCLK_SEL 37
+#define CLK_MPMU_I2S3_SYSCLK_SEL 38
+#define CLK_MPMU_I2S4_SYSCLK_SEL 39
+#define CLK_MPMU_I2S5_SYSCLK_SEL 40
+#define CLK_MPMU_I2S0_SYSCLK_DIV 41
+#define CLK_MPMU_I2S2_SYSCLK_DIV 42
+#define CLK_MPMU_I2S3_SYSCLK_DIV 43
+#define CLK_MPMU_I2S4_SYSCLK_DIV 44
+#define CLK_MPMU_I2S5_SYSCLK_DIV 45
+#define CLK_MPMU_I2S0_SYSCLK 46
+#define CLK_MPMU_I2S2_SYSCLK 47
+#define CLK_MPMU_I2S3_SYSCLK 48
+#define CLK_MPMU_I2S4_SYSCLK 49
+#define CLK_MPMU_I2S5_SYSCLK 50
+
+/* APBC clocks */
+#define CLK_APBC_UART0 0
+#define CLK_APBC_UART2 1
+#define CLK_APBC_UART3 2
+#define CLK_APBC_UART4 3
+#define CLK_APBC_UART5 4
+#define CLK_APBC_UART6 5
+#define CLK_APBC_UART7 6
+#define CLK_APBC_UART8 7
+#define CLK_APBC_UART9 8
+#define CLK_APBC_UART10 9
+#define CLK_APBC_UART0_BUS 10
+#define CLK_APBC_UART2_BUS 11
+#define CLK_APBC_UART3_BUS 12
+#define CLK_APBC_UART4_BUS 13
+#define CLK_APBC_UART5_BUS 14
+#define CLK_APBC_UART6_BUS 15
+#define CLK_APBC_UART7_BUS 16
+#define CLK_APBC_UART8_BUS 17
+#define CLK_APBC_UART9_BUS 18
+#define CLK_APBC_UART10_BUS 19
+#define CLK_APBC_GPIO 20
+#define CLK_APBC_GPIO_BUS 21
+#define CLK_APBC_PWM0 22
+#define CLK_APBC_PWM1 23
+#define CLK_APBC_PWM2 24
+#define CLK_APBC_PWM3 25
+#define CLK_APBC_PWM4 26
+#define CLK_APBC_PWM5 27
+#define CLK_APBC_PWM6 28
+#define CLK_APBC_PWM7 29
+#define CLK_APBC_PWM8 30
+#define CLK_APBC_PWM9 31
+#define CLK_APBC_PWM10 32
+#define CLK_APBC_PWM11 33
+#define CLK_APBC_PWM12 34
+#define CLK_APBC_PWM13 35
+#define CLK_APBC_PWM14 36
+#define CLK_APBC_PWM15 37
+#define CLK_APBC_PWM16 38
+#define CLK_APBC_PWM17 39
+#define CLK_APBC_PWM18 40
+#define CLK_APBC_PWM19 41
+#define CLK_APBC_PWM0_BUS 42
+#define CLK_APBC_PWM1_BUS 43
+#define CLK_APBC_PWM2_BUS 44
+#define CLK_APBC_PWM3_BUS 45
+#define CLK_APBC_PWM4_BUS 46
+#define CLK_APBC_PWM5_BUS 47
+#define CLK_APBC_PWM6_BUS 48
+#define CLK_APBC_PWM7_BUS 49
+#define CLK_APBC_PWM8_BUS 50
+#define CLK_APBC_PWM9_BUS 51
+#define CLK_APBC_PWM10_BUS 52
+#define CLK_APBC_PWM11_BUS 53
+#define CLK_APBC_PWM12_BUS 54
+#define CLK_APBC_PWM13_BUS 55
+#define CLK_APBC_PWM14_BUS 56
+#define CLK_APBC_PWM15_BUS 57
+#define CLK_APBC_PWM16_BUS 58
+#define CLK_APBC_PWM17_BUS 59
+#define CLK_APBC_PWM18_BUS 60
+#define CLK_APBC_PWM19_BUS 61
+#define CLK_APBC_SPI0_I2S_BCLK 62
+#define CLK_APBC_SPI1_I2S_BCLK 63
+#define CLK_APBC_SPI3_I2S_BCLK 64
+#define CLK_APBC_SPI0 65
+#define CLK_APBC_SPI1 66
+#define CLK_APBC_SPI3 67
+#define CLK_APBC_SPI0_BUS 68
+#define CLK_APBC_SPI1_BUS 69
+#define CLK_APBC_SPI3_BUS 70
+#define CLK_APBC_RTC 71
+#define CLK_APBC_RTC_BUS 72
+#define CLK_APBC_TWSI0 73
+#define CLK_APBC_TWSI1 74
+#define CLK_APBC_TWSI2 75
+#define CLK_APBC_TWSI4 76
+#define CLK_APBC_TWSI5 77
+#define CLK_APBC_TWSI6 78
+#define CLK_APBC_TWSI8 79
+#define CLK_APBC_TWSI0_BUS 80
+#define CLK_APBC_TWSI1_BUS 81
+#define CLK_APBC_TWSI2_BUS 82
+#define CLK_APBC_TWSI4_BUS 83
+#define CLK_APBC_TWSI5_BUS 84
+#define CLK_APBC_TWSI6_BUS 85
+#define CLK_APBC_TWSI8_BUS 86
+#define CLK_APBC_TIMERS0 87
+#define CLK_APBC_TIMERS1 88
+#define CLK_APBC_TIMERS2 89
+#define CLK_APBC_TIMERS3 90
+#define CLK_APBC_TIMERS4 91
+#define CLK_APBC_TIMERS5 92
+#define CLK_APBC_TIMERS6 93
+#define CLK_APBC_TIMERS7 94
+#define CLK_APBC_TIMERS0_BUS 95
+#define CLK_APBC_TIMERS1_BUS 96
+#define CLK_APBC_TIMERS2_BUS 97
+#define CLK_APBC_TIMERS3_BUS 98
+#define CLK_APBC_TIMERS4_BUS 99
+#define CLK_APBC_TIMERS5_BUS 100
+#define CLK_APBC_TIMERS6_BUS 101
+#define CLK_APBC_TIMERS7_BUS 102
+#define CLK_APBC_AIB 103
+#define CLK_APBC_AIB_BUS 104
+#define CLK_APBC_ONEWIRE 105
+#define CLK_APBC_ONEWIRE_BUS 106
+#define CLK_APBC_I2S0_BCLK 107
+#define CLK_APBC_I2S1_BCLK 108
+#define CLK_APBC_I2S2_BCLK 109
+#define CLK_APBC_I2S3_BCLK 110
+#define CLK_APBC_I2S4_BCLK 111
+#define CLK_APBC_I2S5_BCLK 112
+#define CLK_APBC_I2S0 113
+#define CLK_APBC_I2S1 114
+#define CLK_APBC_I2S2 115
+#define CLK_APBC_I2S3 116
+#define CLK_APBC_I2S4 117
+#define CLK_APBC_I2S5 118
+#define CLK_APBC_I2S0_BUS 119
+#define CLK_APBC_I2S1_BUS 120
+#define CLK_APBC_I2S2_BUS 121
+#define CLK_APBC_I2S3_BUS 122
+#define CLK_APBC_I2S4_BUS 123
+#define CLK_APBC_I2S5_BUS 124
+#define CLK_APBC_DRO 125
+#define CLK_APBC_IR0 126
+#define CLK_APBC_IR1 127
+#define CLK_APBC_TSEN 128
+#define CLK_APBC_TSEN_BUS 129
+#define CLK_APBC_IPC_AP2RCPU 130
+#define CLK_APBC_IPC_AP2RCPU_BUS 131
+#define CLK_APBC_CAN0 132
+#define CLK_APBC_CAN1 133
+#define CLK_APBC_CAN2 134
+#define CLK_APBC_CAN3 135
+#define CLK_APBC_CAN4 136
+#define CLK_APBC_CAN0_BUS 137
+#define CLK_APBC_CAN1_BUS 138
+#define CLK_APBC_CAN2_BUS 139
+#define CLK_APBC_CAN3_BUS 140
+#define CLK_APBC_CAN4_BUS 141
+
+/* APMU clocks */
+#define CLK_APMU_AXICLK 0
+#define CLK_APMU_CCI550 1
+#define CLK_APMU_CPU_C0_CORE 2
+#define CLK_APMU_CPU_C1_CORE 3
+#define CLK_APMU_CPU_C2_CORE 4
+#define CLK_APMU_CPU_C3_CORE 5
+#define CLK_APMU_CCIC2PHY 6
+#define CLK_APMU_CCIC3PHY 7
+#define CLK_APMU_CSI 8
+#define CLK_APMU_ISP_BUS 9
+#define CLK_APMU_D1P_1228P8 10
+#define CLK_APMU_D1P_819P2 11
+#define CLK_APMU_D1P_614P4 12
+#define CLK_APMU_D1P_491P52 13
+#define CLK_APMU_D1P_409P6 14
+#define CLK_APMU_D1P_307P2 15
+#define CLK_APMU_D1P_245P76 16
+#define CLK_APMU_V2D 17
+#define CLK_APMU_DSI_ESC 18
+#define CLK_APMU_LCD_HCLK 19
+#define CLK_APMU_LCD_DSC 20
+#define CLK_APMU_LCD_PXCLK 21
+#define CLK_APMU_LCD_MCLK 22
+#define CLK_APMU_CCIC_4X 23
+#define CLK_APMU_CCIC1PHY 24
+#define CLK_APMU_SC2_HCLK 25
+#define CLK_APMU_SDH_AXI 26
+#define CLK_APMU_SDH0 27
+#define CLK_APMU_SDH1 28
+#define CLK_APMU_SDH2 29
+#define CLK_APMU_USB2_BUS 30
+#define CLK_APMU_USB3_PORTA_BUS 31
+#define CLK_APMU_USB3_PORTB_BUS 32
+#define CLK_APMU_USB3_PORTC_BUS 33
+#define CLK_APMU_USB3_PORTD_BUS 34
+#define CLK_APMU_QSPI 35
+#define CLK_APMU_QSPI_BUS 36
+#define CLK_APMU_DMA 37
+#define CLK_APMU_AES_WTM 38
+#define CLK_APMU_VPU 39
+#define CLK_APMU_DTC 40
+#define CLK_APMU_GPU 41
+#define CLK_APMU_MC_AHB 42
+#define CLK_APMU_TOP_DCLK 43
+#define CLK_APMU_UCIE 44
+#define CLK_APMU_UCIE_SBCLK 45
+#define CLK_APMU_RCPU 46
+#define CLK_APMU_DSI4LN2_DSI_ESC 47
+#define CLK_APMU_DSI4LN2_LCD_DSC 48
+#define CLK_APMU_DSI4LN2_LCD_PXCLK 49
+#define CLK_APMU_DSI4LN2_LCD_MCLK 50
+#define CLK_APMU_DSI4LN2_DPU_ACLK 51
+#define CLK_APMU_DPU_ACLK 52
+#define CLK_APMU_UFS_ACLK 53
+#define CLK_APMU_EDP0_PXCLK 54
+#define CLK_APMU_EDP1_PXCLK 55
+#define CLK_APMU_PCIE_PORTA_MSTE 56
+#define CLK_APMU_PCIE_PORTA_SLV 57
+#define CLK_APMU_PCIE_PORTB_MSTE 58
+#define CLK_APMU_PCIE_PORTB_SLV 59
+#define CLK_APMU_PCIE_PORTC_MSTE 60
+#define CLK_APMU_PCIE_PORTC_SLV 61
+#define CLK_APMU_PCIE_PORTD_MSTE 62
+#define CLK_APMU_PCIE_PORTD_SLV 63
+#define CLK_APMU_PCIE_PORTE_MSTE 64
+#define CLK_APMU_PCIE_PORTE_SLV 65
+#define CLK_APMU_EMAC0_BUS 66
+#define CLK_APMU_EMAC0_REF 67
+#define CLK_APMU_EMAC0_1588 68
+#define CLK_APMU_EMAC0_RGMII_TX 69
+#define CLK_APMU_EMAC1_BUS 70
+#define CLK_APMU_EMAC1_REF 71
+#define CLK_APMU_EMAC1_1588 72
+#define CLK_APMU_EMAC1_RGMII_TX 73
+#define CLK_APMU_EMAC2_BUS 74
+#define CLK_APMU_EMAC2_REF 75
+#define CLK_APMU_EMAC2_1588 76
+#define CLK_APMU_EMAC2_RGMII_TX 77
+#define CLK_APMU_ESPI_SCLK_SRC 78
+#define CLK_APMU_ESPI_SCLK 79
+#define CLK_APMU_ESPI_MCLK 80
+#define CLK_APMU_CAM_SRC1 81
+#define CLK_APMU_CAM_SRC2 82
+#define CLK_APMU_CAM_SRC3 83
+#define CLK_APMU_CAM_SRC4 84
+#define CLK_APMU_ISIM_VCLK0 85
+#define CLK_APMU_ISIM_VCLK1 86
+#define CLK_APMU_ISIM_VCLK2 87
+#define CLK_APMU_ISIM_VCLK3 88
+
+/* DCIU clocks */
+#define CLK_DCIU_HDMA 0
+#define CLK_DCIU_DMA350 1
+#define CLK_DCIU_C2_TCM_PIPE 2
+#define CLK_DCIU_C3_TCM_PIPE 3
+
+#endif /* _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_ */
#define CLK_SRAM3 83
#define CLK_PLL_GMAC_100M 84
#define CLK_UART_SCLK 85
+#define CLK_C910_BUS 86
/* VO clocks */
#define CLK_AXI4_VO_ACLK 0
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2019 Xilinx Inc.
- *
- */
-
-#ifndef _DT_BINDINGS_CLK_VERSAL_H
-#define _DT_BINDINGS_CLK_VERSAL_H
-
-#define PMC_PLL 1
-#define APU_PLL 2
-#define RPU_PLL 3
-#define CPM_PLL 4
-#define NOC_PLL 5
-#define PLL_MAX 6
-#define PMC_PRESRC 7
-#define PMC_POSTCLK 8
-#define PMC_PLL_OUT 9
-#define PPLL 10
-#define NOC_PRESRC 11
-#define NOC_POSTCLK 12
-#define NOC_PLL_OUT 13
-#define NPLL 14
-#define APU_PRESRC 15
-#define APU_POSTCLK 16
-#define APU_PLL_OUT 17
-#define APLL 18
-#define RPU_PRESRC 19
-#define RPU_POSTCLK 20
-#define RPU_PLL_OUT 21
-#define RPLL 22
-#define CPM_PRESRC 23
-#define CPM_POSTCLK 24
-#define CPM_PLL_OUT 25
-#define CPLL 26
-#define PPLL_TO_XPD 27
-#define NPLL_TO_XPD 28
-#define APLL_TO_XPD 29
-#define RPLL_TO_XPD 30
-#define EFUSE_REF 31
-#define SYSMON_REF 32
-#define IRO_SUSPEND_REF 33
-#define USB_SUSPEND 34
-#define SWITCH_TIMEOUT 35
-#define RCLK_PMC 36
-#define RCLK_LPD 37
-#define WDT 38
-#define TTC0 39
-#define TTC1 40
-#define TTC2 41
-#define TTC3 42
-#define GEM_TSU 43
-#define GEM_TSU_LB 44
-#define MUXED_IRO_DIV2 45
-#define MUXED_IRO_DIV4 46
-#define PSM_REF 47
-#define GEM0_RX 48
-#define GEM0_TX 49
-#define GEM1_RX 50
-#define GEM1_TX 51
-#define CPM_CORE_REF 52
-#define CPM_LSBUS_REF 53
-#define CPM_DBG_REF 54
-#define CPM_AUX0_REF 55
-#define CPM_AUX1_REF 56
-#define QSPI_REF 57
-#define OSPI_REF 58
-#define SDIO0_REF 59
-#define SDIO1_REF 60
-#define PMC_LSBUS_REF 61
-#define I2C_REF 62
-#define TEST_PATTERN_REF 63
-#define DFT_OSC_REF 64
-#define PMC_PL0_REF 65
-#define PMC_PL1_REF 66
-#define PMC_PL2_REF 67
-#define PMC_PL3_REF 68
-#define CFU_REF 69
-#define SPARE_REF 70
-#define NPI_REF 71
-#define HSM0_REF 72
-#define HSM1_REF 73
-#define SD_DLL_REF 74
-#define FPD_TOP_SWITCH 75
-#define FPD_LSBUS 76
-#define ACPU 77
-#define DBG_TRACE 78
-#define DBG_FPD 79
-#define LPD_TOP_SWITCH 80
-#define ADMA 81
-#define LPD_LSBUS 82
-#define CPU_R5 83
-#define CPU_R5_CORE 84
-#define CPU_R5_OCM 85
-#define CPU_R5_OCM2 86
-#define IOU_SWITCH 87
-#define GEM0_REF 88
-#define GEM1_REF 89
-#define GEM_TSU_REF 90
-#define USB0_BUS_REF 91
-#define UART0_REF 92
-#define UART1_REF 93
-#define SPI0_REF 94
-#define SPI1_REF 95
-#define CAN0_REF 96
-#define CAN1_REF 97
-#define I2C0_REF 98
-#define I2C1_REF 99
-#define DBG_LPD 100
-#define TIMESTAMP_REF 101
-#define DBG_TSTMP 102
-#define CPM_TOPSW_REF 103
-#define USB3_DUAL_REF 104
-#define OUTCLK_MAX 105
-#define REF_CLK 106
-#define PL_ALT_REF_CLK 107
-#define MUXED_IRO 108
-#define PL_EXT 109
-#define PL_LB 110
-#define MIO_50_OR_51 111
-#define MIO_24_OR_25 112
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Xilinx Zynq MPSoC Firmware layer
- *
- * Copyright (C) 2014-2018 Xilinx, Inc.
- *
- */
-
-#ifndef _DT_BINDINGS_CLK_ZYNQMP_H
-#define _DT_BINDINGS_CLK_ZYNQMP_H
-
-/*
- * These bindings are deprecated, because they do not match the actual
- * concept of bindings but rather contain pure firmware values.
- * Instead include the header in the DTS source directory.
- */
-#warning "These bindings are deprecated. Instead use the header in the DTS source directory."
-
-#define IOPLL 0
-#define RPLL 1
-#define APLL 2
-#define DPLL 3
-#define VPLL 4
-#define IOPLL_TO_FPD 5
-#define RPLL_TO_FPD 6
-#define APLL_TO_LPD 7
-#define DPLL_TO_LPD 8
-#define VPLL_TO_LPD 9
-#define ACPU 10
-#define ACPU_HALF 11
-#define DBF_FPD 12
-#define DBF_LPD 13
-#define DBG_TRACE 14
-#define DBG_TSTMP 15
-#define DP_VIDEO_REF 16
-#define DP_AUDIO_REF 17
-#define DP_STC_REF 18
-#define GDMA_REF 19
-#define DPDMA_REF 20
-#define DDR_REF 21
-#define SATA_REF 22
-#define PCIE_REF 23
-#define GPU_REF 24
-#define GPU_PP0_REF 25
-#define GPU_PP1_REF 26
-#define TOPSW_MAIN 27
-#define TOPSW_LSBUS 28
-#define GTGREF0_REF 29
-#define LPD_SWITCH 30
-#define LPD_LSBUS 31
-#define USB0_BUS_REF 32
-#define USB1_BUS_REF 33
-#define USB3_DUAL_REF 34
-#define USB0 35
-#define USB1 36
-#define CPU_R5 37
-#define CPU_R5_CORE 38
-#define CSU_SPB 39
-#define CSU_PLL 40
-#define PCAP 41
-#define IOU_SWITCH 42
-#define GEM_TSU_REF 43
-#define GEM_TSU 44
-#define GEM0_TX 45
-#define GEM1_TX 46
-#define GEM2_TX 47
-#define GEM3_TX 48
-#define GEM0_RX 49
-#define GEM1_RX 50
-#define GEM2_RX 51
-#define GEM3_RX 52
-#define QSPI_REF 53
-#define SDIO0_REF 54
-#define SDIO1_REF 55
-#define UART0_REF 56
-#define UART1_REF 57
-#define SPI0_REF 58
-#define SPI1_REF 59
-#define NAND_REF 60
-#define I2C0_REF 61
-#define I2C1_REF 62
-#define CAN0_REF 63
-#define CAN1_REF 64
-#define CAN0 65
-#define CAN1 66
-#define DLL_REF 67
-#define ADMA_REF 68
-#define TIMESTAMP_REF 69
-#define AMS_REF 70
-#define PL0_REF 71
-#define PL1_REF 72
-#define PL2_REF 73
-#define PL3_REF 74
-#define WDT 75
-#define IOPLL_INT 76
-#define IOPLL_PRE_SRC 77
-#define IOPLL_HALF 78
-#define IOPLL_INT_MUX 79
-#define IOPLL_POST_SRC 80
-#define RPLL_INT 81
-#define RPLL_PRE_SRC 82
-#define RPLL_HALF 83
-#define RPLL_INT_MUX 84
-#define RPLL_POST_SRC 85
-#define APLL_INT 86
-#define APLL_PRE_SRC 87
-#define APLL_HALF 88
-#define APLL_INT_MUX 89
-#define APLL_POST_SRC 90
-#define DPLL_INT 91
-#define DPLL_PRE_SRC 92
-#define DPLL_HALF 93
-#define DPLL_INT_MUX 94
-#define DPLL_POST_SRC 95
-#define VPLL_INT 96
-#define VPLL_PRE_SRC 97
-#define VPLL_HALF 98
-#define VPLL_INT_MUX 99
-#define VPLL_POST_SRC 100
-#define CAN0_MIO 101
-#define CAN1_MIO 102
-#define ACPU_FULL 103
-#define GEM0_REF 104
-#define GEM1_REF 105
-#define GEM2_REF 106
-#define GEM3_REF 107
-#define GEM0_REF_UNG 108
-#define GEM1_REF_UNG 109
-#define GEM2_REF_UNG 110
-#define GEM3_REF_UNG 111
-#define LPD_WDT 112
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * This header provides macros for JZ4775 DMA bindings.
- *
- * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
- */
-
-#ifndef __DT_BINDINGS_DMA_JZ4775_DMA_H__
-#define __DT_BINDINGS_DMA_JZ4775_DMA_H__
-
-/*
- * Request type numbers for the JZ4775 DMA controller (written to the DRTn
- * register for the channel).
- */
-#define JZ4775_DMA_I2S0_TX 0x6
-#define JZ4775_DMA_I2S0_RX 0x7
-#define JZ4775_DMA_AUTO 0x8
-#define JZ4775_DMA_SADC_RX 0x9
-#define JZ4775_DMA_UART3_TX 0x0e
-#define JZ4775_DMA_UART3_RX 0x0f
-#define JZ4775_DMA_UART2_TX 0x10
-#define JZ4775_DMA_UART2_RX 0x11
-#define JZ4775_DMA_UART1_TX 0x12
-#define JZ4775_DMA_UART1_RX 0x13
-#define JZ4775_DMA_UART0_TX 0x14
-#define JZ4775_DMA_UART0_RX 0x15
-#define JZ4775_DMA_SSI0_TX 0x16
-#define JZ4775_DMA_SSI0_RX 0x17
-#define JZ4775_DMA_MSC0_TX 0x1a
-#define JZ4775_DMA_MSC0_RX 0x1b
-#define JZ4775_DMA_MSC1_TX 0x1c
-#define JZ4775_DMA_MSC1_RX 0x1d
-#define JZ4775_DMA_MSC2_TX 0x1e
-#define JZ4775_DMA_MSC2_RX 0x1f
-#define JZ4775_DMA_PCM0_TX 0x20
-#define JZ4775_DMA_PCM0_RX 0x21
-#define JZ4775_DMA_SMB0_TX 0x24
-#define JZ4775_DMA_SMB0_RX 0x25
-#define JZ4775_DMA_SMB1_TX 0x26
-#define JZ4775_DMA_SMB1_RX 0x27
-#define JZ4775_DMA_SMB2_TX 0x28
-#define JZ4775_DMA_SMB2_RX 0x29
-
-#endif /* __DT_BINDINGS_DMA_JZ4775_DMA_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * This header provides macros for X2000 DMA bindings.
- *
- * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
- */
-
-#ifndef __DT_BINDINGS_DMA_X2000_DMA_H__
-#define __DT_BINDINGS_DMA_X2000_DMA_H__
-
-/*
- * Request type numbers for the X2000 DMA controller (written to the DRTn
- * register for the channel).
- */
-#define X2000_DMA_AUTO 0x8
-#define X2000_DMA_UART5_TX 0xa
-#define X2000_DMA_UART5_RX 0xb
-#define X2000_DMA_UART4_TX 0xc
-#define X2000_DMA_UART4_RX 0xd
-#define X2000_DMA_UART3_TX 0xe
-#define X2000_DMA_UART3_RX 0xf
-#define X2000_DMA_UART2_TX 0x10
-#define X2000_DMA_UART2_RX 0x11
-#define X2000_DMA_UART1_TX 0x12
-#define X2000_DMA_UART1_RX 0x13
-#define X2000_DMA_UART0_TX 0x14
-#define X2000_DMA_UART0_RX 0x15
-#define X2000_DMA_SSI0_TX 0x16
-#define X2000_DMA_SSI0_RX 0x17
-#define X2000_DMA_SSI1_TX 0x18
-#define X2000_DMA_SSI1_RX 0x19
-#define X2000_DMA_I2C0_TX 0x24
-#define X2000_DMA_I2C0_RX 0x25
-#define X2000_DMA_I2C1_TX 0x26
-#define X2000_DMA_I2C1_RX 0x27
-#define X2000_DMA_I2C2_TX 0x28
-#define X2000_DMA_I2C2_RX 0x29
-#define X2000_DMA_I2C3_TX 0x2a
-#define X2000_DMA_I2C3_RX 0x2b
-#define X2000_DMA_I2C4_TX 0x2c
-#define X2000_DMA_I2C4_RX 0x2d
-#define X2000_DMA_I2C5_TX 0x2e
-#define X2000_DMA_I2C5_RX 0x2f
-#define X2000_DMA_UART6_TX 0x30
-#define X2000_DMA_UART6_RX 0x31
-#define X2000_DMA_UART7_TX 0x32
-#define X2000_DMA_UART7_RX 0x33
-#define X2000_DMA_UART8_TX 0x34
-#define X2000_DMA_UART8_RX 0x35
-#define X2000_DMA_UART9_TX 0x36
-#define X2000_DMA_UART9_RX 0x37
-#define X2000_DMA_SADC_RX 0x38
-
-#endif /* __DT_BINDINGS_DMA_X2000_DMA_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2019 MediaTek Inc.
- * Author: Dennis-YC Hsieh <dennis-yc.hsieh@mediatek.com>
- */
-
-#ifndef _DT_BINDINGS_GCE_MT6779_H
-#define _DT_BINDINGS_GCE_MT6779_H
-
-#define CMDQ_NO_TIMEOUT 0xffffffff
-
-/* GCE HW thread priority */
-#define CMDQ_THR_PRIO_LOWEST 0
-#define CMDQ_THR_PRIO_1 1
-#define CMDQ_THR_PRIO_2 2
-#define CMDQ_THR_PRIO_3 3
-#define CMDQ_THR_PRIO_4 4
-#define CMDQ_THR_PRIO_5 5
-#define CMDQ_THR_PRIO_6 6
-#define CMDQ_THR_PRIO_HIGHEST 7
-
-/* GCE subsys table */
-#define SUBSYS_1300XXXX 0
-#define SUBSYS_1400XXXX 1
-#define SUBSYS_1401XXXX 2
-#define SUBSYS_1402XXXX 3
-#define SUBSYS_1502XXXX 4
-#define SUBSYS_1880XXXX 5
-#define SUBSYS_1881XXXX 6
-#define SUBSYS_1882XXXX 7
-#define SUBSYS_1883XXXX 8
-#define SUBSYS_1884XXXX 9
-#define SUBSYS_1000XXXX 10
-#define SUBSYS_1001XXXX 11
-#define SUBSYS_1002XXXX 12
-#define SUBSYS_1003XXXX 13
-#define SUBSYS_1004XXXX 14
-#define SUBSYS_1005XXXX 15
-#define SUBSYS_1020XXXX 16
-#define SUBSYS_1028XXXX 17
-#define SUBSYS_1700XXXX 18
-#define SUBSYS_1701XXXX 19
-#define SUBSYS_1702XXXX 20
-#define SUBSYS_1703XXXX 21
-#define SUBSYS_1800XXXX 22
-#define SUBSYS_1801XXXX 23
-#define SUBSYS_1802XXXX 24
-#define SUBSYS_1804XXXX 25
-#define SUBSYS_1805XXXX 26
-#define SUBSYS_1808XXXX 27
-#define SUBSYS_180aXXXX 28
-#define SUBSYS_180bXXXX 29
-#define CMDQ_SUBSYS_OFF 32
-
-/* GCE hardware events */
-#define CMDQ_EVENT_DISP_RDMA0_SOF 0
-#define CMDQ_EVENT_DISP_RDMA1_SOF 1
-#define CMDQ_EVENT_MDP_RDMA0_SOF 2
-#define CMDQ_EVENT_MDP_RDMA1_SOF 3
-#define CMDQ_EVENT_MDP_RSZ0_SOF 4
-#define CMDQ_EVENT_MDP_RSZ1_SOF 5
-#define CMDQ_EVENT_MDP_TDSHP_SOF 6
-#define CMDQ_EVENT_MDP_WROT0_SOF 7
-#define CMDQ_EVENT_MDP_WROT1_SOF 8
-#define CMDQ_EVENT_DISP_OVL0_SOF 9
-#define CMDQ_EVENT_DISP_2L_OVL0_SOF 10
-#define CMDQ_EVENT_DISP_2L_OVL1_SOF 11
-#define CMDQ_EVENT_DISP_WDMA0_SOF 12
-#define CMDQ_EVENT_DISP_COLOR0_SOF 13
-#define CMDQ_EVENT_DISP_CCORR0_SOF 14
-#define CMDQ_EVENT_DISP_AAL0_SOF 15
-#define CMDQ_EVENT_DISP_GAMMA0_SOF 16
-#define CMDQ_EVENT_DISP_DITHER0_SOF 17
-#define CMDQ_EVENT_DISP_PWM0_SOF 18
-#define CMDQ_EVENT_DISP_DSI0_SOF 19
-#define CMDQ_EVENT_DISP_DPI0_SOF 20
-#define CMDQ_EVENT_DISP_POSTMASK0_SOF 21
-#define CMDQ_EVENT_DISP_RSZ0_SOF 22
-#define CMDQ_EVENT_MDP_AAL_SOF 23
-#define CMDQ_EVENT_MDP_CCORR_SOF 24
-#define CMDQ_EVENT_DISP_DBI0_SOF 25
-#define CMDQ_EVENT_ISP_RELAY_SOF 26
-#define CMDQ_EVENT_IPU_RELAY_SOF 27
-#define CMDQ_EVENT_DISP_RDMA0_EOF 28
-#define CMDQ_EVENT_DISP_RDMA1_EOF 29
-#define CMDQ_EVENT_MDP_RDMA0_EOF 30
-#define CMDQ_EVENT_MDP_RDMA1_EOF 31
-#define CMDQ_EVENT_MDP_RSZ0_EOF 32
-#define CMDQ_EVENT_MDP_RSZ1_EOF 33
-#define CMDQ_EVENT_MDP_TDSHP_EOF 34
-#define CMDQ_EVENT_MDP_WROT0_W_EOF 35
-#define CMDQ_EVENT_MDP_WROT1_W_EOF 36
-#define CMDQ_EVENT_DISP_OVL0_EOF 37
-#define CMDQ_EVENT_DISP_2L_OVL0_EOF 38
-#define CMDQ_EVENT_DISP_2L_OVL1_EOF 39
-#define CMDQ_EVENT_DISP_WDMA0_EOF 40
-#define CMDQ_EVENT_DISP_COLOR0_EOF 41
-#define CMDQ_EVENT_DISP_CCORR0_EOF 42
-#define CMDQ_EVENT_DISP_AAL0_EOF 43
-#define CMDQ_EVENT_DISP_GAMMA0_EOF 44
-#define CMDQ_EVENT_DISP_DITHER0_EOF 45
-#define CMDQ_EVENT_DISP_DSI0_EOF 46
-#define CMDQ_EVENT_DISP_DPI0_EOF 47
-#define CMDQ_EVENT_DISP_RSZ0_EOF 49
-#define CMDQ_EVENT_MDP_AAL_FRAME_DONE 50
-#define CMDQ_EVENT_MDP_CCORR_FRAME_DONE 51
-#define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE 52
-#define CMDQ_EVENT_MUTEX0_STREAM_EOF 130
-#define CMDQ_EVENT_MUTEX1_STREAM_EOF 131
-#define CMDQ_EVENT_MUTEX2_STREAM_EOF 132
-#define CMDQ_EVENT_MUTEX3_STREAM_EOF 133
-#define CMDQ_EVENT_MUTEX4_STREAM_EOF 134
-#define CMDQ_EVENT_MUTEX5_STREAM_EOF 135
-#define CMDQ_EVENT_MUTEX6_STREAM_EOF 136
-#define CMDQ_EVENT_MUTEX7_STREAM_EOF 137
-#define CMDQ_EVENT_MUTEX8_STREAM_EOF 138
-#define CMDQ_EVENT_MUTEX9_STREAM_EOF 139
-#define CMDQ_EVENT_MUTEX10_STREAM_EOF 140
-#define CMDQ_EVENT_MUTEX11_STREAM_EOF 141
-#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 142
-#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 143
-#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 144
-#define CMDQ_EVENT_DISP_RDMA3_UNDERRUN 145
-#define CMDQ_EVENT_DSI0_TE 146
-#define CMDQ_EVENT_DSI0_IRQ_EVENT 147
-#define CMDQ_EVENT_DSI0_DONE_EVENT 148
-#define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE 150
-#define CMDQ_EVENT_DISP_WDMA0_RST_DONE 151
-#define CMDQ_EVENT_MDP_WROT0_RST_DONE 153
-#define CMDQ_EVENT_MDP_RDMA0_RST_DONE 154
-#define CMDQ_EVENT_DISP_OVL0_RST_DONE 155
-#define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE 156
-#define CMDQ_EVENT_DISP_OVL1_2L_RST_DONE 157
-#define CMDQ_EVENT_DIP_CQ_THREAD0_EOF 257
-#define CMDQ_EVENT_DIP_CQ_THREAD1_EOF 258
-#define CMDQ_EVENT_DIP_CQ_THREAD2_EOF 259
-#define CMDQ_EVENT_DIP_CQ_THREAD3_EOF 260
-#define CMDQ_EVENT_DIP_CQ_THREAD4_EOF 261
-#define CMDQ_EVENT_DIP_CQ_THREAD5_EOF 262
-#define CMDQ_EVENT_DIP_CQ_THREAD6_EOF 263
-#define CMDQ_EVENT_DIP_CQ_THREAD7_EOF 264
-#define CMDQ_EVENT_DIP_CQ_THREAD8_EOF 265
-#define CMDQ_EVENT_DIP_CQ_THREAD9_EOF 266
-#define CMDQ_EVENT_DIP_CQ_THREAD10_EOF 267
-#define CMDQ_EVENT_DIP_CQ_THREAD11_EOF 268
-#define CMDQ_EVENT_DIP_CQ_THREAD12_EOF 269
-#define CMDQ_EVENT_DIP_CQ_THREAD13_EOF 270
-#define CMDQ_EVENT_DIP_CQ_THREAD14_EOF 271
-#define CMDQ_EVENT_DIP_CQ_THREAD15_EOF 272
-#define CMDQ_EVENT_DIP_CQ_THREAD16_EOF 273
-#define CMDQ_EVENT_DIP_CQ_THREAD17_EOF 274
-#define CMDQ_EVENT_DIP_CQ_THREAD18_EOF 275
-#define CMDQ_EVENT_DIP_DMA_ERR_EVENT 276
-#define CMDQ_EVENT_AMD_FRAME_DONE 277
-#define CMDQ_EVENT_MFB_DONE 278
-#define CMDQ_EVENT_WPE_A_EOF 279
-#define CMDQ_EVENT_VENC_EOF 289
-#define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE 290
-#define CMDQ_EVENT_JPEG_ENC_EOF 291
-#define CMDQ_EVENT_VENC_MB_DONE 292
-#define CMDQ_EVENT_VENC_128BYTE_CNT_DONE 293
-#define CMDQ_EVENT_ISP_FRAME_DONE_A 321
-#define CMDQ_EVENT_ISP_FRAME_DONE_B 322
-#define CMDQ_EVENT_ISP_FRAME_DONE_C 323
-#define CMDQ_EVENT_ISP_CAMSV_0_PASS1_DONE 324
-#define CMDQ_EVENT_ISP_CAMSV_0_2_PASS1_DONE 325
-#define CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE 326
-#define CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE 327
-#define CMDQ_EVENT_ISP_CAMSV_3_PASS1_DONE 328
-#define CMDQ_EVENT_ISP_TSF_DONE 329
-#define CMDQ_EVENT_SENINF_0_FIFO_FULL 330
-#define CMDQ_EVENT_SENINF_1_FIFO_FULL 331
-#define CMDQ_EVENT_SENINF_2_FIFO_FULL 332
-#define CMDQ_EVENT_SENINF_3_FIFO_FULL 333
-#define CMDQ_EVENT_SENINF_4_FIFO_FULL 334
-#define CMDQ_EVENT_SENINF_5_FIFO_FULL 335
-#define CMDQ_EVENT_SENINF_6_FIFO_FULL 336
-#define CMDQ_EVENT_SENINF_7_FIFO_FULL 337
-#define CMDQ_EVENT_TG_OVRUN_A_INT_DLY 338
-#define CMDQ_EVENT_TG_OVRUN_B_INT_DLY 339
-#define CMDQ_EVENT_TG_OVRUN_C_INT 340
-#define CMDQ_EVENT_TG_GRABERR_A_INT_DLY 341
-#define CMDQ_EVENT_TG_GRABERR_B_INT_DLY 342
-#define CMDQ_EVENT_TG_GRABERR_C_INT 343
-#define CMDQ_EVENT_CQ_VR_SNAP_A_INT_DLY 344
-#define CMDQ_EVENT_CQ_VR_SNAP_B_INT_DLY 345
-#define CMDQ_EVENT_CQ_VR_SNAP_C_INT 346
-#define CMDQ_EVENT_DMA_R1_ERROR_A_INT_DLY 347
-#define CMDQ_EVENT_DMA_R1_ERROR_B_INT_DLY 348
-#define CMDQ_EVENT_DMA_R1_ERROR_C_INT 349
-#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_0 353
-#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_1 354
-#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_2 355
-#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_3 356
-#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_0 385
-#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_1 386
-#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_2 387
-#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_3 388
-#define CMDQ_EVENT_VDEC_EVENT_0 416
-#define CMDQ_EVENT_VDEC_EVENT_1 417
-#define CMDQ_EVENT_VDEC_EVENT_2 418
-#define CMDQ_EVENT_VDEC_EVENT_3 419
-#define CMDQ_EVENT_VDEC_EVENT_4 420
-#define CMDQ_EVENT_VDEC_EVENT_5 421
-#define CMDQ_EVENT_VDEC_EVENT_6 422
-#define CMDQ_EVENT_VDEC_EVENT_7 423
-#define CMDQ_EVENT_VDEC_EVENT_8 424
-#define CMDQ_EVENT_VDEC_EVENT_9 425
-#define CMDQ_EVENT_VDEC_EVENT_10 426
-#define CMDQ_EVENT_VDEC_EVENT_11 427
-#define CMDQ_EVENT_VDEC_EVENT_12 428
-#define CMDQ_EVENT_VDEC_EVENT_13 429
-#define CMDQ_EVENT_VDEC_EVENT_14 430
-#define CMDQ_EVENT_VDEC_EVENT_15 431
-#define CMDQ_EVENT_FDVT_DONE 449
-#define CMDQ_EVENT_FE_DONE 450
-#define CMDQ_EVENT_RSC_EOF 451
-#define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT 452
-#define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT 453
-#define CMDQ_EVENT_DSI0_TE_INFRA 898
-
-#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. */
+
+/*
+ * This header provides constants for binding nvidia,tegra264-gpio*.
+ *
+ * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
+ * provide names for this.
+ *
+ * The second cell contains standard flag values specified in gpio.h.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_TEGRA264_GPIO_H
+#define _DT_BINDINGS_GPIO_TEGRA264_GPIO_H
+
+#include <dt-bindings/gpio/gpio.h>
+
+/* GPIOs implemented by main GPIO controller */
+#define TEGRA264_MAIN_GPIO_PORT_T 0
+#define TEGRA264_MAIN_GPIO_PORT_U 1
+#define TEGRA264_MAIN_GPIO_PORT_V 2
+#define TEGRA264_MAIN_GPIO_PORT_W 3
+#define TEGRA264_MAIN_GPIO_PORT_AL 4
+#define TEGRA264_MAIN_GPIO_PORT_Y 5
+#define TEGRA264_MAIN_GPIO_PORT_Z 6
+#define TEGRA264_MAIN_GPIO_PORT_X 7
+#define TEGRA264_MAIN_GPIO_PORT_H 8
+#define TEGRA264_MAIN_GPIO_PORT_J 9
+#define TEGRA264_MAIN_GPIO_PORT_K 10
+#define TEGRA264_MAIN_GPIO_PORT_L 11
+#define TEGRA264_MAIN_GPIO_PORT_M 12
+#define TEGRA264_MAIN_GPIO_PORT_P 13
+#define TEGRA264_MAIN_GPIO_PORT_Q 14
+#define TEGRA264_MAIN_GPIO_PORT_R 15
+#define TEGRA264_MAIN_GPIO_PORT_S 16
+#define TEGRA264_MAIN_GPIO_PORT_F 17
+#define TEGRA264_MAIN_GPIO_PORT_G 18
+
+#define TEGRA264_MAIN_GPIO(port, offset) \
+ ((TEGRA264_MAIN_GPIO_PORT_##port * 8) + (offset))
+
+/* GPIOs implemented by AON GPIO controller */
+#define TEGRA264_AON_GPIO_PORT_AA 0
+#define TEGRA264_AON_GPIO_PORT_BB 1
+#define TEGRA264_AON_GPIO_PORT_CC 2
+#define TEGRA264_AON_GPIO_PORT_DD 3
+#define TEGRA264_AON_GPIO_PORT_EE 4
+
+#define TEGRA264_AON_GPIO(port, offset) \
+ ((TEGRA264_AON_GPIO_PORT_##port * 8) + (offset))
+
+#define TEGRA264_UPHY_GPIO_PORT_A 0
+#define TEGRA264_UPHY_GPIO_PORT_B 1
+#define TEGRA264_UPHY_GPIO_PORT_C 2
+#define TEGRA264_UPHY_GPIO_PORT_D 3
+#define TEGRA264_UPHY_GPIO_PORT_E 4
+
+#define TEGRA264_UPHY_GPIO(port, offset) \
+ ((TEGRA264_UPHY_GPIO_PORT_##port * 8) + (offset))
+
+#endif
#define KEY_EPRIVACY_SCREEN_ON 0x252
#define KEY_EPRIVACY_SCREEN_OFF 0x253
+#define KEY_ACTION_ON_SELECTION 0x254 /* AL Action on Selection (HUTRR119) */
+#define KEY_CONTEXTUAL_INSERT 0x255 /* AL Contextual Insertion (HUTRR119) */
+#define KEY_CONTEXTUAL_QUERY 0x256 /* AL Contextual Query (HUTRR119) */
+
#define KEY_KBDINPUTASSIST_PREV 0x260
#define KEY_KBDINPUTASSIST_NEXT 0x261
#define KEY_KBDINPUTASSIST_PREVGROUP 0x262
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8196_H
+#define __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8196_H
+
+#define SLAVE_DDR_EMI 0
+#define MASTER_MCUSYS 1
+#define MASTER_MCU_0 2
+#define MASTER_MCU_1 3
+#define MASTER_MCU_2 4
+#define MASTER_MCU_3 5
+#define MASTER_MCU_4 6
+#define MASTER_GPUSYS 7
+#define MASTER_MMSYS 8
+#define MASTER_MM_VPU 9
+#define MASTER_MM_DISP 10
+#define MASTER_MM_VDEC 11
+#define MASTER_MM_VENC 12
+#define MASTER_MM_CAM 13
+#define MASTER_MM_IMG 14
+#define MASTER_MM_MDP 15
+#define MASTER_VPUSYS 16
+#define MASTER_VPU_0 17
+#define MASTER_VPU_1 18
+#define MASTER_MDLASYS 19
+#define MASTER_MDLA_0 20
+#define MASTER_UFS 21
+#define MASTER_PCIE 22
+#define MASTER_USB 23
+#define MASTER_WIFI 24
+#define MASTER_BT 25
+#define MASTER_NETSYS 26
+#define MASTER_DBGIF 27
+#define SLAVE_HRT_DDR_EMI 28
+#define MASTER_HRT_MMSYS 29
+#define MASTER_HRT_MM_DISP 30
+#define MASTER_HRT_MM_VDEC 31
+#define MASTER_HRT_MM_VENC 32
+#define MASTER_HRT_MM_CAM 33
+#define MASTER_HRT_MM_IMG 34
+#define MASTER_HRT_MM_MDP 35
+#define MASTER_HRT_ADSP 36
+#define MASTER_HRT_DBGIF 37
+#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2019 MediaTek Inc.
- * Author: Chao Hao <chao.hao@mediatek.com>
- */
-
-#ifndef _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_
-#define _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_
-
-#include <dt-bindings/memory/mtk-memory-port.h>
-
-#define M4U_LARB0_ID 0
-#define M4U_LARB1_ID 1
-#define M4U_LARB2_ID 2
-#define M4U_LARB3_ID 3
-#define M4U_LARB4_ID 4
-#define M4U_LARB5_ID 5
-#define M4U_LARB6_ID 6
-#define M4U_LARB7_ID 7
-#define M4U_LARB8_ID 8
-#define M4U_LARB9_ID 9
-#define M4U_LARB10_ID 10
-#define M4U_LARB11_ID 11
-
-/* larb0 */
-#define M4U_PORT_DISP_POSTMASK0 MTK_M4U_ID(M4U_LARB0_ID, 0)
-#define M4U_PORT_DISP_OVL0_HDR MTK_M4U_ID(M4U_LARB0_ID, 1)
-#define M4U_PORT_DISP_OVL1_HDR MTK_M4U_ID(M4U_LARB0_ID, 2)
-#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 3)
-#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4)
-#define M4U_PORT_DISP_PVRIC0 MTK_M4U_ID(M4U_LARB0_ID, 5)
-#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6)
-#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 7)
-#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 8)
-
-/* larb1 */
-#define M4U_PORT_DISP_OVL0_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 0)
-#define M4U_PORT_DISP_OVL1_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 1)
-#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB1_ID, 2)
-#define M4U_PORT_DISP_OVL1_2L MTK_M4U_ID(M4U_LARB1_ID, 3)
-#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 4)
-#define M4U_PORT_MDP_PVRIC0 MTK_M4U_ID(M4U_LARB1_ID, 5)
-#define M4U_PORT_MDP_PVRIC1 MTK_M4U_ID(M4U_LARB1_ID, 6)
-#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB1_ID, 7)
-#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 8)
-#define M4U_PORT_MDP_WROT0_R MTK_M4U_ID(M4U_LARB1_ID, 9)
-#define M4U_PORT_MDP_WROT0_W MTK_M4U_ID(M4U_LARB1_ID, 10)
-#define M4U_PORT_MDP_WROT1_R MTK_M4U_ID(M4U_LARB1_ID, 11)
-#define M4U_PORT_MDP_WROT1_W MTK_M4U_ID(M4U_LARB1_ID, 12)
-#define M4U_PORT_DISP_FAKE1 MTK_M4U_ID(M4U_LARB1_ID, 13)
-
-/* larb2-VDEC */
-#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0)
-#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB2_ID, 1)
-#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 2)
-#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 3)
-#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 4)
-#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 5)
-#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB2_ID, 6)
-#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 7)
-#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB2_ID, 8)
-#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 9)
-#define M4U_PORT_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(M4U_LARB2_ID, 10)
-#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB2_ID, 11)
-
-/* larb3-VENC */
-#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0)
-#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1)
-#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2)
-#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3)
-#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4)
-#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5)
-#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 6)
-#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB3_ID, 7)
-#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB3_ID, 8)
-#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB3_ID, 9)
-#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 10)
-#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 11)
-#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 12)
-#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 13)
-#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 14)
-#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 15)
-#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 16)
-#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 17)
-#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 18)
-
-/* larb4-dummy */
-
-/* larb5-IMG */
-#define M4U_PORT_IMGI_D1 MTK_M4U_ID(M4U_LARB5_ID, 0)
-#define M4U_PORT_IMGBI_D1 MTK_M4U_ID(M4U_LARB5_ID, 1)
-#define M4U_PORT_DMGI_D1 MTK_M4U_ID(M4U_LARB5_ID, 2)
-#define M4U_PORT_DEPI_D1 MTK_M4U_ID(M4U_LARB5_ID, 3)
-#define M4U_PORT_LCEI_D1 MTK_M4U_ID(M4U_LARB5_ID, 4)
-#define M4U_PORT_SMTI_D1 MTK_M4U_ID(M4U_LARB5_ID, 5)
-#define M4U_PORT_SMTO_D2 MTK_M4U_ID(M4U_LARB5_ID, 6)
-#define M4U_PORT_SMTO_D1 MTK_M4U_ID(M4U_LARB5_ID, 7)
-#define M4U_PORT_CRZO_D1 MTK_M4U_ID(M4U_LARB5_ID, 8)
-#define M4U_PORT_IMG3O_D1 MTK_M4U_ID(M4U_LARB5_ID, 9)
-#define M4U_PORT_VIPI_D1 MTK_M4U_ID(M4U_LARB5_ID, 10)
-#define M4U_PORT_WPE_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 11)
-#define M4U_PORT_WPE_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 12)
-#define M4U_PORT_WPE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 13)
-#define M4U_PORT_TIMGO_D1 MTK_M4U_ID(M4U_LARB5_ID, 14)
-#define M4U_PORT_MFB_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 15)
-#define M4U_PORT_MFB_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 16)
-#define M4U_PORT_MFB_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 17)
-#define M4U_PORT_MFB_RDMA3 MTK_M4U_ID(M4U_LARB5_ID, 18)
-#define M4U_PORT_MFB_WDMA MTK_M4U_ID(M4U_LARB5_ID, 19)
-#define M4U_PORT_RESERVE1 MTK_M4U_ID(M4U_LARB5_ID, 20)
-#define M4U_PORT_RESERVE2 MTK_M4U_ID(M4U_LARB5_ID, 21)
-#define M4U_PORT_RESERVE3 MTK_M4U_ID(M4U_LARB5_ID, 22)
-#define M4U_PORT_RESERVE4 MTK_M4U_ID(M4U_LARB5_ID, 23)
-#define M4U_PORT_RESERVE5 MTK_M4U_ID(M4U_LARB5_ID, 24)
-#define M4U_PORT_RESERVE6 MTK_M4U_ID(M4U_LARB5_ID, 25)
-
-/* larb6-IMG-VPU */
-#define M4U_PORT_IMG_IPUO MTK_M4U_ID(M4U_LARB6_ID, 0)
-#define M4U_PORT_IMG_IPU3O MTK_M4U_ID(M4U_LARB6_ID, 1)
-#define M4U_PORT_IMG_IPUI MTK_M4U_ID(M4U_LARB6_ID, 2)
-
-/* larb7-DVS */
-#define M4U_PORT_DVS_RDMA MTK_M4U_ID(M4U_LARB7_ID, 0)
-#define M4U_PORT_DVS_WDMA MTK_M4U_ID(M4U_LARB7_ID, 1)
-#define M4U_PORT_DVP_RDMA MTK_M4U_ID(M4U_LARB7_ID, 2)
-#define M4U_PORT_DVP_WDMA MTK_M4U_ID(M4U_LARB7_ID, 3)
-
-/* larb8-IPESYS */
-#define M4U_PORT_FDVT_RDA MTK_M4U_ID(M4U_LARB8_ID, 0)
-#define M4U_PORT_FDVT_RDB MTK_M4U_ID(M4U_LARB8_ID, 1)
-#define M4U_PORT_FDVT_WRA MTK_M4U_ID(M4U_LARB8_ID, 2)
-#define M4U_PORT_FDVT_WRB MTK_M4U_ID(M4U_LARB8_ID, 3)
-#define M4U_PORT_FE_RD0 MTK_M4U_ID(M4U_LARB8_ID, 4)
-#define M4U_PORT_FE_RD1 MTK_M4U_ID(M4U_LARB8_ID, 5)
-#define M4U_PORT_FE_WR0 MTK_M4U_ID(M4U_LARB8_ID, 6)
-#define M4U_PORT_FE_WR1 MTK_M4U_ID(M4U_LARB8_ID, 7)
-#define M4U_PORT_RSC_RDMA0 MTK_M4U_ID(M4U_LARB8_ID, 8)
-#define M4U_PORT_RSC_WDMA MTK_M4U_ID(M4U_LARB8_ID, 9)
-
-/* larb9-CAM */
-#define M4U_PORT_CAM_IMGO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 0)
-#define M4U_PORT_CAM_RRZO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 1)
-#define M4U_PORT_CAM_LSCI_R1_C MTK_M4U_ID(M4U_LARB9_ID, 2)
-#define M4U_PORT_CAM_BPCI_R1_C MTK_M4U_ID(M4U_LARB9_ID, 3)
-#define M4U_PORT_CAM_YUVO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 4)
-#define M4U_PORT_CAM_UFDI_R2_C MTK_M4U_ID(M4U_LARB9_ID, 5)
-#define M4U_PORT_CAM_RAWI_R2_C MTK_M4U_ID(M4U_LARB9_ID, 6)
-#define M4U_PORT_CAM_RAWI_R5_C MTK_M4U_ID(M4U_LARB9_ID, 7)
-#define M4U_PORT_CAM_CAMSV_1 MTK_M4U_ID(M4U_LARB9_ID, 8)
-#define M4U_PORT_CAM_CAMSV_2 MTK_M4U_ID(M4U_LARB9_ID, 9)
-#define M4U_PORT_CAM_CAMSV_3 MTK_M4U_ID(M4U_LARB9_ID, 10)
-#define M4U_PORT_CAM_CAMSV_4 MTK_M4U_ID(M4U_LARB9_ID, 11)
-#define M4U_PORT_CAM_CAMSV_5 MTK_M4U_ID(M4U_LARB9_ID, 12)
-#define M4U_PORT_CAM_CAMSV_6 MTK_M4U_ID(M4U_LARB9_ID, 13)
-#define M4U_PORT_CAM_AAO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 14)
-#define M4U_PORT_CAM_AFO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 15)
-#define M4U_PORT_CAM_FLKO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 16)
-#define M4U_PORT_CAM_LCESO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 17)
-#define M4U_PORT_CAM_CRZO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 18)
-#define M4U_PORT_CAM_LTMSO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 19)
-#define M4U_PORT_CAM_RSSO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 20)
-#define M4U_PORT_CAM_CCUI MTK_M4U_ID(M4U_LARB9_ID, 21)
-#define M4U_PORT_CAM_CCUO MTK_M4U_ID(M4U_LARB9_ID, 22)
-#define M4U_PORT_CAM_FAKE MTK_M4U_ID(M4U_LARB9_ID, 23)
-
-/* larb10-CAM_A */
-#define M4U_PORT_CAM_IMGO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 0)
-#define M4U_PORT_CAM_RRZO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 1)
-#define M4U_PORT_CAM_LSCI_R1_A MTK_M4U_ID(M4U_LARB10_ID, 2)
-#define M4U_PORT_CAM_BPCI_R1_A MTK_M4U_ID(M4U_LARB10_ID, 3)
-#define M4U_PORT_CAM_YUVO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 4)
-#define M4U_PORT_CAM_UFDI_R2_A MTK_M4U_ID(M4U_LARB10_ID, 5)
-#define M4U_PORT_CAM_RAWI_R2_A MTK_M4U_ID(M4U_LARB10_ID, 6)
-#define M4U_PORT_CAM_RAWI_R5_A MTK_M4U_ID(M4U_LARB10_ID, 7)
-#define M4U_PORT_CAM_IMGO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 8)
-#define M4U_PORT_CAM_RRZO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 9)
-#define M4U_PORT_CAM_LSCI_R1_B MTK_M4U_ID(M4U_LARB10_ID, 10)
-#define M4U_PORT_CAM_BPCI_R1_B MTK_M4U_ID(M4U_LARB10_ID, 11)
-#define M4U_PORT_CAM_YUVO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 12)
-#define M4U_PORT_CAM_UFDI_R2_B MTK_M4U_ID(M4U_LARB10_ID, 13)
-#define M4U_PORT_CAM_RAWI_R2_B MTK_M4U_ID(M4U_LARB10_ID, 14)
-#define M4U_PORT_CAM_RAWI_R5_B MTK_M4U_ID(M4U_LARB10_ID, 15)
-#define M4U_PORT_CAM_CAMSV_0 MTK_M4U_ID(M4U_LARB10_ID, 16)
-#define M4U_PORT_CAM_AAO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 17)
-#define M4U_PORT_CAM_AFO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 18)
-#define M4U_PORT_CAM_FLKO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 19)
-#define M4U_PORT_CAM_LCESO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 20)
-#define M4U_PORT_CAM_CRZO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 21)
-#define M4U_PORT_CAM_AAO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 22)
-#define M4U_PORT_CAM_AFO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 23)
-#define M4U_PORT_CAM_FLKO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 24)
-#define M4U_PORT_CAM_LCESO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 25)
-#define M4U_PORT_CAM_CRZO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 26)
-#define M4U_PORT_CAM_LTMSO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 27)
-#define M4U_PORT_CAM_RSSO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 28)
-#define M4U_PORT_CAM_LTMSO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 29)
-#define M4U_PORT_CAM_RSSO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 30)
-
-/* larb11-CAM-VPU */
-#define M4U_PORT_CAM_IPUO MTK_M4U_ID(M4U_LARB11_ID, 0)
-#define M4U_PORT_CAM_IPU2O MTK_M4U_ID(M4U_LARB11_ID, 1)
-#define M4U_PORT_CAM_IPU3O MTK_M4U_ID(M4U_LARB11_ID, 2)
-#define M4U_PORT_CAM_IPUI MTK_M4U_ID(M4U_LARB11_ID, 3)
-#define M4U_PORT_CAM_IPU2I MTK_M4U_ID(M4U_LARB11_ID, 4)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This header provides constants for SERDES MUX for TI SoCs
- */
-
-#ifndef _DT_BINDINGS_MUX_TI_SERDES
-#define _DT_BINDINGS_MUX_TI_SERDES
-
-/*
- * These bindings are deprecated, because they do not match the actual
- * concept of bindings but rather contain pure constants values used only
- * in DTS board files.
- * Instead include the header in the DTS source directory.
- */
-#warning "These bindings are deprecated. Instead, use the header in the DTS source directory."
-
-/* J721E */
-
-#define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0
-#define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1
-#define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2
-#define J721E_SERDES0_LANE0_IP4_UNUSED 0x3
-
-#define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0
-#define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1
-#define J721E_SERDES0_LANE1_USB3_0 0x2
-#define J721E_SERDES0_LANE1_IP4_UNUSED 0x3
-
-#define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0
-#define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1
-#define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2
-#define J721E_SERDES1_LANE0_SGMII_LANE0 0x3
-
-#define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0
-#define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1
-#define J721E_SERDES1_LANE1_USB3_1 0x2
-#define J721E_SERDES1_LANE1_SGMII_LANE1 0x3
-
-#define J721E_SERDES2_LANE0_IP1_UNUSED 0x0
-#define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1
-#define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2
-#define J721E_SERDES2_LANE0_SGMII_LANE0 0x3
-
-#define J721E_SERDES2_LANE1_IP1_UNUSED 0x0
-#define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1
-#define J721E_SERDES2_LANE1_USB3_1 0x2
-#define J721E_SERDES2_LANE1_SGMII_LANE1 0x3
-
-#define J721E_SERDES3_LANE0_IP1_UNUSED 0x0
-#define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1
-#define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2
-#define J721E_SERDES3_LANE0_IP4_UNUSED 0x3
-
-#define J721E_SERDES3_LANE1_IP1_UNUSED 0x0
-#define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1
-#define J721E_SERDES3_LANE1_USB3_0 0x2
-#define J721E_SERDES3_LANE1_IP4_UNUSED 0x3
-
-#define J721E_SERDES4_LANE0_EDP_LANE0 0x0
-#define J721E_SERDES4_LANE0_IP2_UNUSED 0x1
-#define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2
-#define J721E_SERDES4_LANE0_IP4_UNUSED 0x3
-
-#define J721E_SERDES4_LANE1_EDP_LANE1 0x0
-#define J721E_SERDES4_LANE1_IP2_UNUSED 0x1
-#define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2
-#define J721E_SERDES4_LANE1_IP4_UNUSED 0x3
-
-#define J721E_SERDES4_LANE2_EDP_LANE2 0x0
-#define J721E_SERDES4_LANE2_IP2_UNUSED 0x1
-#define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2
-#define J721E_SERDES4_LANE2_IP4_UNUSED 0x3
-
-#define J721E_SERDES4_LANE3_EDP_LANE3 0x0
-#define J721E_SERDES4_LANE3_IP2_UNUSED 0x1
-#define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2
-#define J721E_SERDES4_LANE3_IP4_UNUSED 0x3
-
-/* J7200 */
-
-#define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0
-#define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1
-#define J7200_SERDES0_LANE0_IP3_UNUSED 0x2
-#define J7200_SERDES0_LANE0_IP4_UNUSED 0x3
-
-#define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0
-#define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1
-#define J7200_SERDES0_LANE1_IP3_UNUSED 0x2
-#define J7200_SERDES0_LANE1_IP4_UNUSED 0x3
-
-#define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0
-#define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1
-#define J7200_SERDES0_LANE2_IP3_UNUSED 0x2
-#define J7200_SERDES0_LANE2_IP4_UNUSED 0x3
-
-#define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0
-#define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1
-#define J7200_SERDES0_LANE3_USB 0x2
-#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3
-
-/* AM64 */
-
-#define AM64_SERDES0_LANE0_PCIE0 0x0
-#define AM64_SERDES0_LANE0_USB 0x1
-
-/* J721S2 */
-
-#define J721S2_SERDES0_LANE0_EDP_LANE0 0x0
-#define J721S2_SERDES0_LANE0_PCIE1_LANE0 0x1
-#define J721S2_SERDES0_LANE0_IP3_UNUSED 0x2
-#define J721S2_SERDES0_LANE0_IP4_UNUSED 0x3
-
-#define J721S2_SERDES0_LANE1_EDP_LANE1 0x0
-#define J721S2_SERDES0_LANE1_PCIE1_LANE1 0x1
-#define J721S2_SERDES0_LANE1_USB 0x2
-#define J721S2_SERDES0_LANE1_IP4_UNUSED 0x3
-
-#define J721S2_SERDES0_LANE2_EDP_LANE2 0x0
-#define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1
-#define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2
-#define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3
-
-#define J721S2_SERDES0_LANE3_EDP_LANE3 0x0
-#define J721S2_SERDES0_LANE3_PCIE1_LANE3 0x1
-#define J721S2_SERDES0_LANE3_USB 0x2
-#define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3
-
-/* J784S4 */
-
-#define J784S4_SERDES0_LANE0_IP1_UNUSED 0x0
-#define J784S4_SERDES0_LANE0_PCIE1_LANE0 0x1
-#define J784S4_SERDES0_LANE0_IP3_UNUSED 0x2
-#define J784S4_SERDES0_LANE0_IP4_UNUSED 0x3
-
-#define J784S4_SERDES0_LANE1_IP1_UNUSED 0x0
-#define J784S4_SERDES0_LANE1_PCIE1_LANE1 0x1
-#define J784S4_SERDES0_LANE1_IP3_UNUSED 0x2
-#define J784S4_SERDES0_LANE1_IP4_UNUSED 0x3
-
-#define J784S4_SERDES0_LANE2_PCIE3_LANE0 0x0
-#define J784S4_SERDES0_LANE2_PCIE1_LANE2 0x1
-#define J784S4_SERDES0_LANE2_IP3_UNUSED 0x2
-#define J784S4_SERDES0_LANE2_IP4_UNUSED 0x3
-
-#define J784S4_SERDES0_LANE3_PCIE3_LANE1 0x0
-#define J784S4_SERDES0_LANE3_PCIE1_LANE3 0x1
-#define J784S4_SERDES0_LANE3_USB 0x2
-#define J784S4_SERDES0_LANE3_IP4_UNUSED 0x3
-
-#define J784S4_SERDES1_LANE0_QSGMII_LANE3 0x0
-#define J784S4_SERDES1_LANE0_PCIE0_LANE0 0x1
-#define J784S4_SERDES1_LANE0_IP3_UNUSED 0x2
-#define J784S4_SERDES1_LANE0_IP4_UNUSED 0x3
-
-#define J784S4_SERDES1_LANE1_QSGMII_LANE4 0x0
-#define J784S4_SERDES1_LANE1_PCIE0_LANE1 0x1
-#define J784S4_SERDES1_LANE1_IP3_UNUSED 0x2
-#define J784S4_SERDES1_LANE1_IP4_UNUSED 0x3
-
-#define J784S4_SERDES1_LANE2_QSGMII_LANE1 0x0
-#define J784S4_SERDES1_LANE2_PCIE0_LANE2 0x1
-#define J784S4_SERDES1_LANE2_PCIE2_LANE0 0x2
-#define J784S4_SERDES1_LANE2_IP4_UNUSED 0x3
-
-#define J784S4_SERDES1_LANE3_QSGMII_LANE2 0x0
-#define J784S4_SERDES1_LANE3_PCIE0_LANE3 0x1
-#define J784S4_SERDES1_LANE3_PCIE2_LANE1 0x2
-#define J784S4_SERDES1_LANE3_IP4_UNUSED 0x3
-
-#define J784S4_SERDES2_LANE0_QSGMII_LANE5 0x0
-#define J784S4_SERDES2_LANE0_IP2_UNUSED 0x1
-#define J784S4_SERDES2_LANE0_IP3_UNUSED 0x2
-#define J784S4_SERDES2_LANE0_IP4_UNUSED 0x3
-
-#define J784S4_SERDES2_LANE1_QSGMII_LANE6 0x0
-#define J784S4_SERDES2_LANE1_IP2_UNUSED 0x1
-#define J784S4_SERDES2_LANE1_IP3_UNUSED 0x2
-#define J784S4_SERDES2_LANE1_IP4_UNUSED 0x3
-
-#define J784S4_SERDES2_LANE2_QSGMII_LANE7 0x0
-#define J784S4_SERDES2_LANE2_QSGMII_LANE1 0x1
-#define J784S4_SERDES2_LANE2_IP3_UNUSED 0x2
-#define J784S4_SERDES2_LANE2_IP4_UNUSED 0x3
-
-#define J784S4_SERDES2_LANE3_QSGMII_LANE8 0x0
-#define J784S4_SERDES2_LANE3_QSGMII_LANE2 0x1
-#define J784S4_SERDES2_LANE3_IP3_UNUSED 0x2
-#define J784S4_SERDES2_LANE3_IP4_UNUSED 0x3
-
-#endif /* _DT_BINDINGS_MUX_TI_SERDES */
#define PHY_TYPE_DPHY 10
#define PHY_TYPE_CPHY 11
#define PHY_TYPE_USXGMII 12
+#define PHY_TYPE_XAUI 13
+
+#define PHY_POL_NORMAL 0
+#define PHY_POL_INVERT 1
+#define PHY_POL_AUTO 2
#endif /* _DT_BINDINGS_PHY */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __DTS_MT6397_PINFUNC_H
-#define __DTS_MT6397_PINFUNC_H
-
-#include <dt-bindings/pinctrl/mt65xx.h>
-
-#define MT6397_PIN_0_INT__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
-#define MT6397_PIN_0_INT__FUNC_INT (MTK_PIN_NO(0) | 1)
-
-#define MT6397_PIN_1_SRCVOLTEN__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
-#define MT6397_PIN_1_SRCVOLTEN__FUNC_SRCVOLTEN (MTK_PIN_NO(1) | 1)
-#define MT6397_PIN_1_SRCVOLTEN__FUNC_TEST_CK1 (MTK_PIN_NO(1) | 6)
-
-#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
-#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_SRCLKEN_PERI (MTK_PIN_NO(2) | 1)
-#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_TEST_CK2 (MTK_PIN_NO(2) | 6)
-
-#define MT6397_PIN_3_RTC_32K1V8__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
-#define MT6397_PIN_3_RTC_32K1V8__FUNC_RTC_32K1V8 (MTK_PIN_NO(3) | 1)
-#define MT6397_PIN_3_RTC_32K1V8__FUNC_TEST_CK3 (MTK_PIN_NO(3) | 6)
-
-#define MT6397_PIN_4_WRAP_EVENT__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
-#define MT6397_PIN_4_WRAP_EVENT__FUNC_WRAP_EVENT (MTK_PIN_NO(4) | 1)
-
-#define MT6397_PIN_5_SPI_CLK__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
-#define MT6397_PIN_5_SPI_CLK__FUNC_SPI_CLK (MTK_PIN_NO(5) | 1)
-
-#define MT6397_PIN_6_SPI_CSN__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
-#define MT6397_PIN_6_SPI_CSN__FUNC_SPI_CSN (MTK_PIN_NO(6) | 1)
-
-#define MT6397_PIN_7_SPI_MOSI__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
-#define MT6397_PIN_7_SPI_MOSI__FUNC_SPI_MOSI (MTK_PIN_NO(7) | 1)
-
-#define MT6397_PIN_8_SPI_MISO__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
-#define MT6397_PIN_8_SPI_MISO__FUNC_SPI_MISO (MTK_PIN_NO(8) | 1)
-
-#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
-#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_AUD_CLK (MTK_PIN_NO(9) | 1)
-#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_TEST_IN0 (MTK_PIN_NO(9) | 6)
-#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_TEST_OUT0 (MTK_PIN_NO(9) | 7)
-
-#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
-#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_AUD_MISO (MTK_PIN_NO(10) | 1)
-#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_TEST_IN1 (MTK_PIN_NO(10) | 6)
-#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_TEST_OUT1 (MTK_PIN_NO(10) | 7)
-
-#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
-#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_AUD_MOSI (MTK_PIN_NO(11) | 1)
-#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_TEST_IN2 (MTK_PIN_NO(11) | 6)
-#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_TEST_OUT2 (MTK_PIN_NO(11) | 7)
-
-#define MT6397_PIN_12_COL0__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
-#define MT6397_PIN_12_COL0__FUNC_COL0_USBDL (MTK_PIN_NO(12) | 1)
-#define MT6397_PIN_12_COL0__FUNC_EINT10_1X (MTK_PIN_NO(12) | 2)
-#define MT6397_PIN_12_COL0__FUNC_PWM1_3X (MTK_PIN_NO(12) | 3)
-#define MT6397_PIN_12_COL0__FUNC_TEST_IN3 (MTK_PIN_NO(12) | 6)
-#define MT6397_PIN_12_COL0__FUNC_TEST_OUT3 (MTK_PIN_NO(12) | 7)
-
-#define MT6397_PIN_13_COL1__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
-#define MT6397_PIN_13_COL1__FUNC_COL1 (MTK_PIN_NO(13) | 1)
-#define MT6397_PIN_13_COL1__FUNC_EINT11_1X (MTK_PIN_NO(13) | 2)
-#define MT6397_PIN_13_COL1__FUNC_SCL0_2X (MTK_PIN_NO(13) | 3)
-#define MT6397_PIN_13_COL1__FUNC_TEST_IN4 (MTK_PIN_NO(13) | 6)
-#define MT6397_PIN_13_COL1__FUNC_TEST_OUT4 (MTK_PIN_NO(13) | 7)
-
-#define MT6397_PIN_14_COL2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
-#define MT6397_PIN_14_COL2__FUNC_COL2 (MTK_PIN_NO(14) | 1)
-#define MT6397_PIN_14_COL2__FUNC_EINT12_1X (MTK_PIN_NO(14) | 2)
-#define MT6397_PIN_14_COL2__FUNC_SDA0_2X (MTK_PIN_NO(14) | 3)
-#define MT6397_PIN_14_COL2__FUNC_TEST_IN5 (MTK_PIN_NO(14) | 6)
-#define MT6397_PIN_14_COL2__FUNC_TEST_OUT5 (MTK_PIN_NO(14) | 7)
-
-#define MT6397_PIN_15_COL3__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
-#define MT6397_PIN_15_COL3__FUNC_COL3 (MTK_PIN_NO(15) | 1)
-#define MT6397_PIN_15_COL3__FUNC_EINT13_1X (MTK_PIN_NO(15) | 2)
-#define MT6397_PIN_15_COL3__FUNC_SCL1_2X (MTK_PIN_NO(15) | 3)
-#define MT6397_PIN_15_COL3__FUNC_TEST_IN6 (MTK_PIN_NO(15) | 6)
-#define MT6397_PIN_15_COL3__FUNC_TEST_OUT6 (MTK_PIN_NO(15) | 7)
-
-#define MT6397_PIN_16_COL4__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
-#define MT6397_PIN_16_COL4__FUNC_COL4 (MTK_PIN_NO(16) | 1)
-#define MT6397_PIN_16_COL4__FUNC_EINT14_1X (MTK_PIN_NO(16) | 2)
-#define MT6397_PIN_16_COL4__FUNC_SDA1_2X (MTK_PIN_NO(16) | 3)
-#define MT6397_PIN_16_COL4__FUNC_TEST_IN7 (MTK_PIN_NO(16) | 6)
-#define MT6397_PIN_16_COL4__FUNC_TEST_OUT7 (MTK_PIN_NO(16) | 7)
-
-#define MT6397_PIN_17_COL5__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
-#define MT6397_PIN_17_COL5__FUNC_COL5 (MTK_PIN_NO(17) | 1)
-#define MT6397_PIN_17_COL5__FUNC_EINT15_1X (MTK_PIN_NO(17) | 2)
-#define MT6397_PIN_17_COL5__FUNC_SCL2_2X (MTK_PIN_NO(17) | 3)
-#define MT6397_PIN_17_COL5__FUNC_TEST_IN8 (MTK_PIN_NO(17) | 6)
-#define MT6397_PIN_17_COL5__FUNC_TEST_OUT8 (MTK_PIN_NO(17) | 7)
-
-#define MT6397_PIN_18_COL6__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
-#define MT6397_PIN_18_COL6__FUNC_COL6 (MTK_PIN_NO(18) | 1)
-#define MT6397_PIN_18_COL6__FUNC_EINT16_1X (MTK_PIN_NO(18) | 2)
-#define MT6397_PIN_18_COL6__FUNC_SDA2_2X (MTK_PIN_NO(18) | 3)
-#define MT6397_PIN_18_COL6__FUNC_GPIO32K_0 (MTK_PIN_NO(18) | 4)
-#define MT6397_PIN_18_COL6__FUNC_GPIO26M_0 (MTK_PIN_NO(18) | 5)
-#define MT6397_PIN_18_COL6__FUNC_TEST_IN9 (MTK_PIN_NO(18) | 6)
-#define MT6397_PIN_18_COL6__FUNC_TEST_OUT9 (MTK_PIN_NO(18) | 7)
-
-#define MT6397_PIN_19_COL7__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
-#define MT6397_PIN_19_COL7__FUNC_COL7 (MTK_PIN_NO(19) | 1)
-#define MT6397_PIN_19_COL7__FUNC_EINT17_1X (MTK_PIN_NO(19) | 2)
-#define MT6397_PIN_19_COL7__FUNC_PWM2_3X (MTK_PIN_NO(19) | 3)
-#define MT6397_PIN_19_COL7__FUNC_GPIO32K_1 (MTK_PIN_NO(19) | 4)
-#define MT6397_PIN_19_COL7__FUNC_GPIO26M_1 (MTK_PIN_NO(19) | 5)
-#define MT6397_PIN_19_COL7__FUNC_TEST_IN10 (MTK_PIN_NO(19) | 6)
-#define MT6397_PIN_19_COL7__FUNC_TEST_OUT10 (MTK_PIN_NO(19) | 7)
-
-#define MT6397_PIN_20_ROW0__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
-#define MT6397_PIN_20_ROW0__FUNC_ROW0 (MTK_PIN_NO(20) | 1)
-#define MT6397_PIN_20_ROW0__FUNC_EINT18_1X (MTK_PIN_NO(20) | 2)
-#define MT6397_PIN_20_ROW0__FUNC_SCL0_3X (MTK_PIN_NO(20) | 3)
-#define MT6397_PIN_20_ROW0__FUNC_TEST_IN11 (MTK_PIN_NO(20) | 6)
-#define MT6397_PIN_20_ROW0__FUNC_TEST_OUT11 (MTK_PIN_NO(20) | 7)
-
-#define MT6397_PIN_21_ROW1__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
-#define MT6397_PIN_21_ROW1__FUNC_ROW1 (MTK_PIN_NO(21) | 1)
-#define MT6397_PIN_21_ROW1__FUNC_EINT19_1X (MTK_PIN_NO(21) | 2)
-#define MT6397_PIN_21_ROW1__FUNC_SDA0_3X (MTK_PIN_NO(21) | 3)
-#define MT6397_PIN_21_ROW1__FUNC_AUD_TSTCK (MTK_PIN_NO(21) | 4)
-#define MT6397_PIN_21_ROW1__FUNC_TEST_IN12 (MTK_PIN_NO(21) | 6)
-#define MT6397_PIN_21_ROW1__FUNC_TEST_OUT12 (MTK_PIN_NO(21) | 7)
-
-#define MT6397_PIN_22_ROW2__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
-#define MT6397_PIN_22_ROW2__FUNC_ROW2 (MTK_PIN_NO(22) | 1)
-#define MT6397_PIN_22_ROW2__FUNC_EINT20_1X (MTK_PIN_NO(22) | 2)
-#define MT6397_PIN_22_ROW2__FUNC_SCL1_3X (MTK_PIN_NO(22) | 3)
-#define MT6397_PIN_22_ROW2__FUNC_TEST_IN13 (MTK_PIN_NO(22) | 6)
-#define MT6397_PIN_22_ROW2__FUNC_TEST_OUT13 (MTK_PIN_NO(22) | 7)
-
-#define MT6397_PIN_23_ROW3__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
-#define MT6397_PIN_23_ROW3__FUNC_ROW3 (MTK_PIN_NO(23) | 1)
-#define MT6397_PIN_23_ROW3__FUNC_EINT21_1X (MTK_PIN_NO(23) | 2)
-#define MT6397_PIN_23_ROW3__FUNC_SDA1_3X (MTK_PIN_NO(23) | 3)
-#define MT6397_PIN_23_ROW3__FUNC_TEST_IN14 (MTK_PIN_NO(23) | 6)
-#define MT6397_PIN_23_ROW3__FUNC_TEST_OUT14 (MTK_PIN_NO(23) | 7)
-
-#define MT6397_PIN_24_ROW4__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
-#define MT6397_PIN_24_ROW4__FUNC_ROW4 (MTK_PIN_NO(24) | 1)
-#define MT6397_PIN_24_ROW4__FUNC_EINT22_1X (MTK_PIN_NO(24) | 2)
-#define MT6397_PIN_24_ROW4__FUNC_SCL2_3X (MTK_PIN_NO(24) | 3)
-#define MT6397_PIN_24_ROW4__FUNC_TEST_IN15 (MTK_PIN_NO(24) | 6)
-#define MT6397_PIN_24_ROW4__FUNC_TEST_OUT15 (MTK_PIN_NO(24) | 7)
-
-#define MT6397_PIN_25_ROW5__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
-#define MT6397_PIN_25_ROW5__FUNC_ROW5 (MTK_PIN_NO(25) | 1)
-#define MT6397_PIN_25_ROW5__FUNC_EINT23_1X (MTK_PIN_NO(25) | 2)
-#define MT6397_PIN_25_ROW5__FUNC_SDA2_3X (MTK_PIN_NO(25) | 3)
-#define MT6397_PIN_25_ROW5__FUNC_TEST_IN16 (MTK_PIN_NO(25) | 6)
-#define MT6397_PIN_25_ROW5__FUNC_TEST_OUT16 (MTK_PIN_NO(25) | 7)
-
-#define MT6397_PIN_26_ROW6__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
-#define MT6397_PIN_26_ROW6__FUNC_ROW6 (MTK_PIN_NO(26) | 1)
-#define MT6397_PIN_26_ROW6__FUNC_EINT24_1X (MTK_PIN_NO(26) | 2)
-#define MT6397_PIN_26_ROW6__FUNC_PWM3_3X (MTK_PIN_NO(26) | 3)
-#define MT6397_PIN_26_ROW6__FUNC_GPIO32K_2 (MTK_PIN_NO(26) | 4)
-#define MT6397_PIN_26_ROW6__FUNC_GPIO26M_2 (MTK_PIN_NO(26) | 5)
-#define MT6397_PIN_26_ROW6__FUNC_TEST_IN17 (MTK_PIN_NO(26) | 6)
-#define MT6397_PIN_26_ROW6__FUNC_TEST_OUT17 (MTK_PIN_NO(26) | 7)
-
-#define MT6397_PIN_27_ROW7__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
-#define MT6397_PIN_27_ROW7__FUNC_ROW7 (MTK_PIN_NO(27) | 1)
-#define MT6397_PIN_27_ROW7__FUNC_EINT3_1X (MTK_PIN_NO(27) | 2)
-#define MT6397_PIN_27_ROW7__FUNC_CBUS (MTK_PIN_NO(27) | 3)
-#define MT6397_PIN_27_ROW7__FUNC_GPIO32K_3 (MTK_PIN_NO(27) | 4)
-#define MT6397_PIN_27_ROW7__FUNC_GPIO26M_3 (MTK_PIN_NO(27) | 5)
-#define MT6397_PIN_27_ROW7__FUNC_TEST_IN18 (MTK_PIN_NO(27) | 6)
-#define MT6397_PIN_27_ROW7__FUNC_TEST_OUT18 (MTK_PIN_NO(27) | 7)
-
-#define MT6397_PIN_28_PWM1__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
-#define MT6397_PIN_28_PWM1__FUNC_PWM1 (MTK_PIN_NO(28) | 1)
-#define MT6397_PIN_28_PWM1__FUNC_EINT4_1X (MTK_PIN_NO(28) | 2)
-#define MT6397_PIN_28_PWM1__FUNC_GPIO32K_4 (MTK_PIN_NO(28) | 4)
-#define MT6397_PIN_28_PWM1__FUNC_GPIO26M_4 (MTK_PIN_NO(28) | 5)
-#define MT6397_PIN_28_PWM1__FUNC_TEST_IN19 (MTK_PIN_NO(28) | 6)
-#define MT6397_PIN_28_PWM1__FUNC_TEST_OUT19 (MTK_PIN_NO(28) | 7)
-
-#define MT6397_PIN_29_PWM2__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
-#define MT6397_PIN_29_PWM2__FUNC_PWM2 (MTK_PIN_NO(29) | 1)
-#define MT6397_PIN_29_PWM2__FUNC_EINT5_1X (MTK_PIN_NO(29) | 2)
-#define MT6397_PIN_29_PWM2__FUNC_GPIO32K_5 (MTK_PIN_NO(29) | 4)
-#define MT6397_PIN_29_PWM2__FUNC_GPIO26M_5 (MTK_PIN_NO(29) | 5)
-#define MT6397_PIN_29_PWM2__FUNC_TEST_IN20 (MTK_PIN_NO(29) | 6)
-#define MT6397_PIN_29_PWM2__FUNC_TEST_OUT20 (MTK_PIN_NO(29) | 7)
-
-#define MT6397_PIN_30_PWM3__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
-#define MT6397_PIN_30_PWM3__FUNC_PWM3 (MTK_PIN_NO(30) | 1)
-#define MT6397_PIN_30_PWM3__FUNC_EINT6_1X (MTK_PIN_NO(30) | 2)
-#define MT6397_PIN_30_PWM3__FUNC_COL0 (MTK_PIN_NO(30) | 3)
-#define MT6397_PIN_30_PWM3__FUNC_GPIO32K_6 (MTK_PIN_NO(30) | 4)
-#define MT6397_PIN_30_PWM3__FUNC_GPIO26M_6 (MTK_PIN_NO(30) | 5)
-#define MT6397_PIN_30_PWM3__FUNC_TEST_IN21 (MTK_PIN_NO(30) | 6)
-#define MT6397_PIN_30_PWM3__FUNC_TEST_OUT21 (MTK_PIN_NO(30) | 7)
-
-#define MT6397_PIN_31_SCL0__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
-#define MT6397_PIN_31_SCL0__FUNC_SCL0 (MTK_PIN_NO(31) | 1)
-#define MT6397_PIN_31_SCL0__FUNC_EINT7_1X (MTK_PIN_NO(31) | 2)
-#define MT6397_PIN_31_SCL0__FUNC_PWM1_2X (MTK_PIN_NO(31) | 3)
-#define MT6397_PIN_31_SCL0__FUNC_TEST_IN22 (MTK_PIN_NO(31) | 6)
-#define MT6397_PIN_31_SCL0__FUNC_TEST_OUT22 (MTK_PIN_NO(31) | 7)
-
-#define MT6397_PIN_32_SDA0__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
-#define MT6397_PIN_32_SDA0__FUNC_SDA0 (MTK_PIN_NO(32) | 1)
-#define MT6397_PIN_32_SDA0__FUNC_EINT8_1X (MTK_PIN_NO(32) | 2)
-#define MT6397_PIN_32_SDA0__FUNC_TEST_IN23 (MTK_PIN_NO(32) | 6)
-#define MT6397_PIN_32_SDA0__FUNC_TEST_OUT23 (MTK_PIN_NO(32) | 7)
-
-#define MT6397_PIN_33_SCL1__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
-#define MT6397_PIN_33_SCL1__FUNC_SCL1 (MTK_PIN_NO(33) | 1)
-#define MT6397_PIN_33_SCL1__FUNC_EINT9_1X (MTK_PIN_NO(33) | 2)
-#define MT6397_PIN_33_SCL1__FUNC_PWM2_2X (MTK_PIN_NO(33) | 3)
-#define MT6397_PIN_33_SCL1__FUNC_TEST_IN24 (MTK_PIN_NO(33) | 6)
-#define MT6397_PIN_33_SCL1__FUNC_TEST_OUT24 (MTK_PIN_NO(33) | 7)
-
-#define MT6397_PIN_34_SDA1__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
-#define MT6397_PIN_34_SDA1__FUNC_SDA1 (MTK_PIN_NO(34) | 1)
-#define MT6397_PIN_34_SDA1__FUNC_EINT0_1X (MTK_PIN_NO(34) | 2)
-#define MT6397_PIN_34_SDA1__FUNC_TEST_IN25 (MTK_PIN_NO(34) | 6)
-#define MT6397_PIN_34_SDA1__FUNC_TEST_OUT25 (MTK_PIN_NO(34) | 7)
-
-#define MT6397_PIN_35_SCL2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
-#define MT6397_PIN_35_SCL2__FUNC_SCL2 (MTK_PIN_NO(35) | 1)
-#define MT6397_PIN_35_SCL2__FUNC_EINT1_1X (MTK_PIN_NO(35) | 2)
-#define MT6397_PIN_35_SCL2__FUNC_PWM3_2X (MTK_PIN_NO(35) | 3)
-#define MT6397_PIN_35_SCL2__FUNC_TEST_IN26 (MTK_PIN_NO(35) | 6)
-#define MT6397_PIN_35_SCL2__FUNC_TEST_OUT26 (MTK_PIN_NO(35) | 7)
-
-#define MT6397_PIN_36_SDA2__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
-#define MT6397_PIN_36_SDA2__FUNC_SDA2 (MTK_PIN_NO(36) | 1)
-#define MT6397_PIN_36_SDA2__FUNC_EINT2_1X (MTK_PIN_NO(36) | 2)
-#define MT6397_PIN_36_SDA2__FUNC_TEST_IN27 (MTK_PIN_NO(36) | 6)
-#define MT6397_PIN_36_SDA2__FUNC_TEST_OUT27 (MTK_PIN_NO(36) | 7)
-
-#define MT6397_PIN_37_HDMISD__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
-#define MT6397_PIN_37_HDMISD__FUNC_HDMISD (MTK_PIN_NO(37) | 1)
-#define MT6397_PIN_37_HDMISD__FUNC_TEST_IN28 (MTK_PIN_NO(37) | 6)
-#define MT6397_PIN_37_HDMISD__FUNC_TEST_OUT28 (MTK_PIN_NO(37) | 7)
-
-#define MT6397_PIN_38_HDMISCK__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
-#define MT6397_PIN_38_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(38) | 1)
-#define MT6397_PIN_38_HDMISCK__FUNC_TEST_IN29 (MTK_PIN_NO(38) | 6)
-#define MT6397_PIN_38_HDMISCK__FUNC_TEST_OUT29 (MTK_PIN_NO(38) | 7)
-
-#define MT6397_PIN_39_HTPLG__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
-#define MT6397_PIN_39_HTPLG__FUNC_HTPLG (MTK_PIN_NO(39) | 1)
-#define MT6397_PIN_39_HTPLG__FUNC_TEST_IN30 (MTK_PIN_NO(39) | 6)
-#define MT6397_PIN_39_HTPLG__FUNC_TEST_OUT30 (MTK_PIN_NO(39) | 7)
-
-#define MT6397_PIN_40_CEC__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
-#define MT6397_PIN_40_CEC__FUNC_CEC (MTK_PIN_NO(40) | 1)
-#define MT6397_PIN_40_CEC__FUNC_TEST_IN31 (MTK_PIN_NO(40) | 6)
-#define MT6397_PIN_40_CEC__FUNC_TEST_OUT31 (MTK_PIN_NO(40) | 7)
-
-#endif /* __DTS_MT6397_PINFUNC_H */
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2021 Google LLC
+ * Copyright 2025 Linaro Ltd.
+ *
+ * Device Tree binding constants for the Samsung S2MPG1x PMIC regulators
+ */
+
+#ifndef _DT_BINDINGS_REGULATOR_SAMSUNG_S2MPG10_H
+#define _DT_BINDINGS_REGULATOR_SAMSUNG_S2MPG10_H
+
+/*
+ * Several regulators may be controlled via external signals instead of via
+ * software. These constants describe the possible signals for such regulators
+ * and generally correspond to the respecitve on-chip pins.
+ *
+ * S2MPG10 regulators supporting these are:
+ * - buck1m .. buck7m buck10m
+ * - ldo3m .. ldo19m
+ *
+ * ldo20m supports external control, but using a different set of control
+ * signals.
+ *
+ * S2MPG11 regulators supporting these are:
+ * - buck1s .. buck3s buck5s buck8s buck9s bucka buckd
+ * - ldo1s ldo2s ldo8s ldo13s
+ */
+#define S2MPG10_EXTCTRL_PWREN 0 /* PWREN pin */
+#define S2MPG10_EXTCTRL_PWREN_MIF 1 /* PWREN_MIF pin */
+#define S2MPG10_EXTCTRL_AP_ACTIVE_N 2 /* ~AP_ACTIVE_N pin */
+#define S2MPG10_EXTCTRL_CPUCL1_EN 3 /* CPUCL1_EN pin */
+#define S2MPG10_EXTCTRL_CPUCL1_EN2 4 /* CPUCL1_EN & PWREN pins */
+#define S2MPG10_EXTCTRL_CPUCL2_EN 5 /* CPUCL2_EN pin */
+#define S2MPG10_EXTCTRL_CPUCL2_EN2 6 /* CPUCL2_E2 & PWREN pins */
+#define S2MPG10_EXTCTRL_TPU_EN 7 /* TPU_EN pin */
+#define S2MPG10_EXTCTRL_TPU_EN2 8 /* TPU_EN & ~AP_ACTIVE_N pins */
+#define S2MPG10_EXTCTRL_TCXO_ON 9 /* TCXO_ON pin */
+#define S2MPG10_EXTCTRL_TCXO_ON2 10 /* TCXO_ON & ~AP_ACTIVE_N pins */
+
+#define S2MPG10_EXTCTRL_LDO20M_EN2 11 /* VLDO20M_EN & LDO20M_SFR */
+#define S2MPG10_EXTCTRL_LDO20M_EN 12 /* VLDO20M_EN pin */
+
+#define S2MPG11_EXTCTRL_PWREN 0 /* PWREN pin */
+#define S2MPG11_EXTCTRL_PWREN_MIF 1 /* PWREN_MIF pin */
+#define S2MPG11_EXTCTRL_AP_ACTIVE_N 2 /* ~AP_ACTIVE_N pin */
+#define S2MPG11_EXTCTRL_G3D_EN 3 /* G3D_EN pin */
+#define S2MPG11_EXTCTRL_G3D_EN2 4 /* G3D_EN & ~AP_ACTIVE_N pins */
+#define S2MPG11_EXTCTRL_AOC_VDD 5 /* AOC_VDD pin */
+#define S2MPG11_EXTCTRL_AOC_RET 6 /* AOC_RET pin */
+#define S2MPG11_EXTCTRL_UFS_EN 7 /* UFS_EN pin */
+#define S2MPG11_EXTCTRL_LDO13S_EN 8 /* VLDO13S_EN pin */
+
+#endif /* _DT_BINDINGS_REGULATOR_SAMSUNG_S2MPG10_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-
-#ifndef __DT_BINDINGS_RESET_BCM6318_H
-#define __DT_BINDINGS_RESET_BCM6318_H
-
-#define BCM6318_RST_SPI 0
-#define BCM6318_RST_EPHY 1
-#define BCM6318_RST_SAR 2
-#define BCM6318_RST_ENETSW 3
-#define BCM6318_RST_USBD 4
-#define BCM6318_RST_USBH 5
-#define BCM6318_RST_PCIE_CORE 6
-#define BCM6318_RST_PCIE 7
-#define BCM6318_RST_PCIE_EXT 8
-#define BCM6318_RST_PCIE_HARD 9
-#define BCM6318_RST_ADSL 10
-#define BCM6318_RST_PHYMIPS 11
-#define BCM6318_RST_HOSTMIPS 12
-
-#endif /* __DT_BINDINGS_RESET_BCM6318_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright 2021 NXP
- */
-
-#ifndef DT_BINDING_PCC_RESET_IMX8ULP_H
-#define DT_BINDING_PCC_RESET_IMX8ULP_H
-
-/* PCC3 */
-#define PCC3_WDOG3_SWRST 0
-#define PCC3_WDOG4_SWRST 1
-#define PCC3_LPIT1_SWRST 2
-#define PCC3_TPM4_SWRST 3
-#define PCC3_TPM5_SWRST 4
-#define PCC3_FLEXIO1_SWRST 5
-#define PCC3_I3C2_SWRST 6
-#define PCC3_LPI2C4_SWRST 7
-#define PCC3_LPI2C5_SWRST 8
-#define PCC3_LPUART4_SWRST 9
-#define PCC3_LPUART5_SWRST 10
-#define PCC3_LPSPI4_SWRST 11
-#define PCC3_LPSPI5_SWRST 12
-
-/* PCC4 */
-#define PCC4_FLEXSPI2_SWRST 0
-#define PCC4_TPM6_SWRST 1
-#define PCC4_TPM7_SWRST 2
-#define PCC4_LPI2C6_SWRST 3
-#define PCC4_LPI2C7_SWRST 4
-#define PCC4_LPUART6_SWRST 5
-#define PCC4_LPUART7_SWRST 6
-#define PCC4_SAI4_SWRST 7
-#define PCC4_SAI5_SWRST 8
-#define PCC4_USDHC0_SWRST 9
-#define PCC4_USDHC1_SWRST 10
-#define PCC4_USDHC2_SWRST 11
-#define PCC4_USB0_SWRST 12
-#define PCC4_USB0_PHY_SWRST 13
-#define PCC4_USB1_SWRST 14
-#define PCC4_USB1_PHY_SWRST 15
-#define PCC4_ENET_SWRST 16
-
-/* PCC5 */
-#define PCC5_TPM8_SWRST 0
-#define PCC5_SAI6_SWRST 1
-#define PCC5_SAI7_SWRST 2
-#define PCC5_SPDIF_SWRST 3
-#define PCC5_ISI_SWRST 4
-#define PCC5_CSI_REGS_SWRST 5
-#define PCC5_CSI_SWRST 6
-#define PCC5_DSI_SWRST 7
-#define PCC5_WDOG5_SWRST 8
-#define PCC5_EPDC_SWRST 9
-#define PCC5_PXP_SWRST 10
-#define PCC5_GPU2D_SWRST 11
-#define PCC5_GPU3D_SWRST 12
-#define PCC5_DC_NANO_SWRST 13
-
-#endif /*DT_BINDING_RESET_IMX8ULP_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef DT_RESET_OXSEMI_OX810SE_H
-#define DT_RESET_OXSEMI_OX810SE_H
-
-#define RESET_ARM 0
-#define RESET_COPRO 1
-/* Reserved 2 */
-/* Reserved 3 */
-#define RESET_USBHS 4
-#define RESET_USBHSPHY 5
-#define RESET_MAC 6
-#define RESET_PCI 7
-#define RESET_DMA 8
-#define RESET_DPE 9
-#define RESET_DDR 10
-#define RESET_SATA 11
-#define RESET_SATA_LINK 12
-#define RESET_SATA_PHY 13
- /* Reserved 14 */
-#define RESET_NAND 15
-#define RESET_GPIO 16
-#define RESET_UART1 17
-#define RESET_UART2 18
-#define RESET_MISC 19
-#define RESET_I2S 20
-#define RESET_AHB_MON 21
-#define RESET_UART3 22
-#define RESET_UART4 23
-#define RESET_SGDMA 24
-/* Reserved 25 */
-/* Reserved 26 */
-/* Reserved 27 */
-/* Reserved 28 */
-/* Reserved 29 */
-/* Reserved 30 */
-#define RESET_BUS 31
-
-#endif /* DT_RESET_OXSEMI_OX810SE_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef DT_RESET_OXSEMI_OX820_H
-#define DT_RESET_OXSEMI_OX820_H
-
-#define RESET_SCU 0
-#define RESET_LEON 1
-#define RESET_ARM0 2
-#define RESET_ARM1 3
-#define RESET_USBHS 4
-#define RESET_USBPHYA 5
-#define RESET_MAC 6
-#define RESET_PCIEA 7
-#define RESET_SGDMA 8
-#define RESET_CIPHER 9
-#define RESET_DDR 10
-#define RESET_SATA 11
-#define RESET_SATA_LINK 12
-#define RESET_SATA_PHY 13
-#define RESET_PCIEPHY 14
-#define RESET_NAND 15
-#define RESET_GPIO 16
-#define RESET_UART1 17
-#define RESET_UART2 18
-#define RESET_MISC 19
-#define RESET_I2S 20
-#define RESET_SD 21
-#define RESET_MAC_2 22
-#define RESET_PCIEB 23
-#define RESET_VIDEO 24
-#define RESET_DDR_PHY 25
-#define RESET_USBPHYB 26
-#define RESET_USBDEV 27
-/* Reserved 29 */
-#define RESET_ARMDBG 29
-#define RESET_PLLA 30
-#define RESET_PLLB 31
-
-#endif /* DT_RESET_OXSEMI_OX820_H */
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025 SpacemiT Technology Co. Ltd
+ */
+
+#ifndef _DT_BINDINGS_RESET_SPACEMIT_K3_RESETS_H_
+#define _DT_BINDINGS_RESET_SPACEMIT_K3_RESETS_H_
+
+/* MPMU resets */
+#define RESET_MPMU_WDT 0
+#define RESET_MPMU_RIPC 1
+
+/* APBC resets */
+#define RESET_APBC_UART0 0
+#define RESET_APBC_UART2 1
+#define RESET_APBC_UART3 2
+#define RESET_APBC_UART4 3
+#define RESET_APBC_UART5 4
+#define RESET_APBC_UART6 5
+#define RESET_APBC_UART7 6
+#define RESET_APBC_UART8 7
+#define RESET_APBC_UART9 8
+#define RESET_APBC_UART10 9
+#define RESET_APBC_GPIO 10
+#define RESET_APBC_PWM0 11
+#define RESET_APBC_PWM1 12
+#define RESET_APBC_PWM2 13
+#define RESET_APBC_PWM3 14
+#define RESET_APBC_PWM4 15
+#define RESET_APBC_PWM5 16
+#define RESET_APBC_PWM6 17
+#define RESET_APBC_PWM7 18
+#define RESET_APBC_PWM8 19
+#define RESET_APBC_PWM9 20
+#define RESET_APBC_PWM10 21
+#define RESET_APBC_PWM11 22
+#define RESET_APBC_PWM12 23
+#define RESET_APBC_PWM13 24
+#define RESET_APBC_PWM14 25
+#define RESET_APBC_PWM15 26
+#define RESET_APBC_PWM16 27
+#define RESET_APBC_PWM17 28
+#define RESET_APBC_PWM18 29
+#define RESET_APBC_PWM19 30
+#define RESET_APBC_SPI0 31
+#define RESET_APBC_SPI1 32
+#define RESET_APBC_SPI3 33
+#define RESET_APBC_RTC 34
+#define RESET_APBC_TWSI0 35
+#define RESET_APBC_TWSI1 36
+#define RESET_APBC_TWSI2 37
+#define RESET_APBC_TWSI4 38
+#define RESET_APBC_TWSI5 39
+#define RESET_APBC_TWSI6 40
+#define RESET_APBC_TWSI8 41
+#define RESET_APBC_TIMERS0 42
+#define RESET_APBC_TIMERS1 43
+#define RESET_APBC_TIMERS2 44
+#define RESET_APBC_TIMERS3 45
+#define RESET_APBC_TIMERS4 46
+#define RESET_APBC_TIMERS5 47
+#define RESET_APBC_TIMERS6 48
+#define RESET_APBC_TIMERS7 49
+#define RESET_APBC_AIB 50
+#define RESET_APBC_ONEWIRE 51
+#define RESET_APBC_I2S0 52
+#define RESET_APBC_I2S1 53
+#define RESET_APBC_I2S2 54
+#define RESET_APBC_I2S3 55
+#define RESET_APBC_I2S4 56
+#define RESET_APBC_I2S5 57
+#define RESET_APBC_DRO 58
+#define RESET_APBC_IR0 59
+#define RESET_APBC_IR1 60
+#define RESET_APBC_TSEN 61
+#define RESET_IPC_AP2AUD 62
+#define RESET_APBC_CAN0 63
+#define RESET_APBC_CAN1 64
+#define RESET_APBC_CAN2 65
+#define RESET_APBC_CAN3 66
+#define RESET_APBC_CAN4 67
+
+/* APMU resets */
+#define RESET_APMU_CSI 0
+#define RESET_APMU_CCIC2PHY 1
+#define RESET_APMU_CCIC3PHY 2
+#define RESET_APMU_ISP_CIBUS 3
+#define RESET_APMU_DSI_ESC 4
+#define RESET_APMU_LCD 5
+#define RESET_APMU_V2D 6
+#define RESET_APMU_LCD_MCLK 7
+#define RESET_APMU_LCD_DSCCLK 8
+#define RESET_APMU_SC2_HCLK 9
+#define RESET_APMU_CCIC_4X 10
+#define RESET_APMU_CCIC1_PHY 11
+#define RESET_APMU_SDH_AXI 12
+#define RESET_APMU_SDH0 13
+#define RESET_APMU_SDH1 14
+#define RESET_APMU_SDH2 15
+#define RESET_APMU_USB2_AHB 16
+#define RESET_APMU_USB2_VCC 17
+#define RESET_APMU_USB2_PHY 18
+#define RESET_APMU_USB3_A_AHB 19
+#define RESET_APMU_USB3_A_VCC 20
+#define RESET_APMU_QSPI 21
+#define RESET_APMU_QSPI_BUS 22
+#define RESET_APMU_DMA 23
+#define RESET_APMU_AES_WTM 24
+#define RESET_APMU_MCB_DCLK 25
+#define RESET_APMU_MCB_ACLK 26
+#define RESET_APMU_VPU 27
+#define RESET_APMU_DTC 28
+#define RESET_APMU_GPU 29
+#define RESET_APMU_ALZO 30
+#define RESET_APMU_MC 31
+#define RESET_APMU_CPU0_POP 32
+#define RESET_APMU_CPU0_SW 33
+#define RESET_APMU_CPU1_POP 34
+#define RESET_APMU_CPU1_SW 35
+#define RESET_APMU_CPU2_POP 36
+#define RESET_APMU_CPU2_SW 37
+#define RESET_APMU_CPU3_POP 38
+#define RESET_APMU_CPU3_SW 39
+#define RESET_APMU_C0_MPSUB_SW 40
+#define RESET_APMU_CPU4_POP 41
+#define RESET_APMU_CPU4_SW 42
+#define RESET_APMU_CPU5_POP 43
+#define RESET_APMU_CPU5_SW 44
+#define RESET_APMU_CPU6_POP 45
+#define RESET_APMU_CPU6_SW 46
+#define RESET_APMU_CPU7_POP 47
+#define RESET_APMU_CPU7_SW 48
+#define RESET_APMU_C1_MPSUB_SW 49
+#define RESET_APMU_MPSUB_DBG 50
+#define RESET_APMU_USB3_A_PHY 51 /* USB3 A */
+#define RESET_APMU_USB3_B_AHB 52
+#define RESET_APMU_DSI4LN2_ESCCLK 53
+#define RESET_APMU_DSI4LN2_LCD_SW 54
+#define RESET_APMU_DSI4LN2_LCD_MCLK 55
+#define RESET_APMU_DSI4LN2_LCD_DSCCLK 56
+#define RESET_APMU_DSI4LN2_DPU_ACLK 57
+#define RESET_APMU_DPU_ACLK 58
+#define RESET_APMU_UFS_ACLK 59
+#define RESET_APMU_EDP0 60
+#define RESET_APMU_EDP1 61
+#define RESET_APMU_USB3_B_VCC 62 /* USB3 B */
+#define RESET_APMU_USB3_B_PHY 63
+#define RESET_APMU_USB3_C_AHB 64
+#define RESET_APMU_USB3_C_VCC 65
+#define RESET_APMU_USB3_C_PHY 66
+#define RESET_APMU_EMAC0 67
+#define RESET_APMU_EMAC1 68
+#define RESET_APMU_EMAC2 69
+#define RESET_APMU_ESPI_MCLK 70
+#define RESET_APMU_ESPI_SCLK 71
+#define RESET_APMU_USB3_D_AHB 72 /* USB3 D */
+#define RESET_APMU_USB3_D_VCC 73
+#define RESET_APMU_USB3_D_PHY 74
+#define RESET_APMU_UCIE_IP 75
+#define RESET_APMU_UCIE_HOT 76
+#define RESET_APMU_UCIE_MON 77
+#define RESET_APMU_RCPU_AUDIO_SYS 78
+#define RESET_APMU_RCPU_MCU_CORE 79
+#define RESET_APMU_RCPU_AUDIO_APMU 80
+#define RESET_APMU_PCIE_A_DBI 81
+#define RESET_APMU_PCIE_A_SLAVE 82
+#define RESET_APMU_PCIE_A_MASTER 83
+#define RESET_APMU_PCIE_B_DBI 84
+#define RESET_APMU_PCIE_B_SLAVE 85
+#define RESET_APMU_PCIE_B_MASTER 86
+#define RESET_APMU_PCIE_C_DBI 87
+#define RESET_APMU_PCIE_C_SLAVE 88
+#define RESET_APMU_PCIE_C_MASTER 89
+#define RESET_APMU_PCIE_D_DBI 90
+#define RESET_APMU_PCIE_D_SLAVE 91
+#define RESET_APMU_PCIE_D_MASTER 92
+#define RESET_APMU_PCIE_E_DBI 93
+#define RESET_APMU_PCIE_E_SLAVE 94
+#define RESET_APMU_PCIE_E_MASTER 95
+
+/* DCIU resets*/
+#define RESET_DCIU_HDMA 0
+#define RESET_DCIU_DMA350 1
+#define RESET_DCIU_DMA350_0 2
+#define RESET_DCIU_DMA350_1 3
+#define RESET_DCIU_AXIDMA0 4
+#define RESET_DCIU_AXIDMA1 5
+#define RESET_DCIU_AXIDMA2 6
+#define RESET_DCIU_AXIDMA3 7
+#define RESET_DCIU_AXIDMA4 8
+#define RESET_DCIU_AXIDMA5 9
+#define RESET_DCIU_AXIDMA6 10
+#define RESET_DCIU_AXIDMA7 11
+
+#endif /* _DT_BINDINGS_RESET_SPACEMIT_K3_H_ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __AUDIO_JACK_EVENTS_H
-#define __AUDIO_JACK_EVENTS_H
-
-#define JACK_HEADPHONE 1
-#define JACK_MICROPHONE 2
-#define JACK_LINEOUT 3
-#define JACK_LINEIN 4
-
-#endif /* __AUDIO_JACK_EVENTS_H */
#ifndef __MEDIATEK_LVTS_DT_H
#define __MEDIATEK_LVTS_DT_H
+#define MT7987_CPU 0
+#define MT7987_ETH2P5G 1
+
#define MT7988_CPU_0 0
#define MT7988_CPU_1 1
#define MT7988_ETH2P5G_0 2
#define MT8192_AP_MD1 15
#define MT8192_AP_MD2 16
+#define MT8196_MCU_MEDIUM_CPU6_0 0
+#define MT8196_MCU_MEDIUM_CPU6_1 1
+#define MT8196_MCU_DSU2 2
+#define MT8196_MCU_DSU3 3
+#define MT8196_MCU_LITTLE_CPU3 4
+#define MT8196_MCU_LITTLE_CPU0 5
+#define MT8196_MCU_LITTLE_CPU1 6
+#define MT8196_MCU_LITTLE_CPU2 7
+#define MT8196_MCU_MEDIUM_CPU4_0 8
+#define MT8196_MCU_MEDIUM_CPU4_1 9
+#define MT8196_MCU_MEDIUM_CPU5_0 10
+#define MT8196_MCU_MEDIUM_CPU5_1 11
+#define MT8196_MCU_DSU0 12
+#define MT8196_MCU_DSU1 13
+#define MT8196_MCU_BIG_CPU7_0 14
+#define MT8196_MCU_BIG_CPU7_1 15
+
+#define MT8196_AP_TOP0 0
+#define MT8196_AP_TOP1 1
+#define MT8196_AP_TOP2 2
+#define MT8196_AP_TOP3 3
+#define MT8196_AP_BOT0 4
+#define MT8196_AP_BOT1 5
+#define MT8196_AP_BOT2 6
+#define MT8196_AP_BOT3 7
+
#endif /* __MEDIATEK_LVTS_DT_H */
&i2c1 {
/* pull-ups and devices require AXP209 LDO3 */
- status = "failed";
+ status = "fail";
};
&i2c2 {
&i2c1 {
/* pull-ups and devices require AXP209 LDO3 */
- status = "failed";
+ status = "fail";
};
&i2c2 {
/* The P66 uses a different EINT then the reference design */
interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */
/* The icn8318 binding expects wake-gpios instead of power-gpios */
+ /delete-property/ power-gpios;
wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
&i2c0 {
/* pull-ups and devices require AXP221 DLDO3 */
- status = "failed";
+ status = "fail";
};
&i2c1 {
&i2c0 {
/* pull-ups and device VDDIO use AXP221 DLDO3 */
- status = "failed";
+ status = "fail";
};
&i2c1 {
#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
#include <riscv/allwinner/sunxi-d1s-t113.dtsi>
#include <riscv/allwinner/sunxi-d1-t113.dtsi>
reg = <0>;
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
reg = <1>;
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
+ #cooling-cells = <2>;
};
};
<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
+
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths>;
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-crit {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
};
#size-cells = <1>;
interrupt-parent = <&gic>;
- iio-hwmon {
- compatible = "iio-hwmon";
- io-channels = <&saradc 8>;
- };
-
soc {
compatible = "simple-bus";
#address-cells = <1>;
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
- oscclk0 {
+ clock-controller-0 {
/* MCC static memory clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
clock-output-names = "v2m:oscclk0";
};
- v2m_oscclk1: oscclk1 {
+ v2m_oscclk1: clock-controller-1 {
/* CLCD clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
clock-output-names = "v2m:oscclk1";
};
- v2m_oscclk2: oscclk2 {
+ v2m_oscclk2: clock-controller-2 {
/* IO FPGA peripheral clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 2>;
clock-output-names = "v2m:oscclk2";
};
- volt-vio {
+ regulator-vio {
/* Logic level voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
&uart5 {
// Workaround for A0
compatible = "snps,dw-apb-uart";
+ /delete-property/ no-loopback-test;
};
&i2c0 {
status = "okay";
bus-width = <4>;
max-frequency = <100000000>;
- sdhci-drive-type = /bits/ 8 <3>;
sdhci-caps-mask = <0x7 0x0>;
- sdhci,wp-inverted;
+ wp-inverted;
vmmc-supply = <&vcc_sdhci0>;
vqmmc-supply = <&vccq_sdhci0>;
clk-phase-sd-hs = <7>, <200>;
status = "okay";
bus-width = <4>;
max-frequency = <100000000>;
- sdhci-drive-type = /bits/ 8 <3>;
sdhci-caps-mask = <0x7 0x0>;
- sdhci,wp-inverted;
+ wp-inverted;
vmmc-supply = <&vcc_sdhci1>;
vqmmc-supply = <&vccq_sdhci1>;
clk-phase-sd-hs = <7>, <200>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/i2c/i2c.h>
+
+/ {
+ model = "ASRock ALTRAD8 BMC";
+ compatible = "asrock,altrad8-bmc", "aspeed,ast2500";
+
+ aliases {
+ serial4 = &uart5;
+ i2c50 = &nvme1;
+ i2c51 = &pcie4;
+ i2c52 = &pcie5;
+ i2c53 = &pcie6;
+ i2c54 = &pcie7;
+ i2c55 = &nvme3;
+ i2c56 = &nvme2;
+ i2c57 = &nvme0;
+ i2c58 = &nvme4;
+ i2c59 = &nvme5;
+ i2c60 = &nvme6;
+ i2c61 = &nvme7;
+ i2c62 = &nvme8;
+ i2c63 = &nvme9;
+ i2c64 = &nvme10;
+ i2c65 = &nvme11;
+ };
+
+ chosen {
+ stdout-path = "uart5:115200n8";
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+ <&adc 4> ,<&adc 5>, <&adc 6>, <&adc 7>,
+ <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>,
+ <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-system-fault {
+ gpios = <&gpio ASPEED_GPIO(G,3) GPIO_ACTIVE_LOW>;
+ label = "platform:red:fault";
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_FAULT;
+ };
+
+ led-heartbeat {
+ gpios = <&gpio ASPEED_GPIO(G,0) GPIO_ACTIVE_LOW>;
+ label = "platform:green:heartbeat";
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_INDICATOR;
+ linux,default-trigger = "timer";
+ };
+
+ led-fan1-fault {
+ retain-state-shutdown;
+ default-state = "off";
+ gpios = <&io_expander0 0 GPIO_ACTIVE_LOW>;
+ label = "fan1:red:fault";
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_FAULT;
+ };
+
+ led-fan2-fault {
+ retain-state-shutdown;
+ default-state = "off";
+ gpios = <&io_expander0 1 GPIO_ACTIVE_LOW>;
+ label = "fan2:red:fault";
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_FAULT;
+ };
+
+ led-fan3-fault {
+ retain-state-shutdown;
+ default-state = "off";
+ gpios = <&io_expander0 2 GPIO_ACTIVE_LOW>;
+ label = "fan3:red:fault";
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_FAULT;
+ };
+
+ led-fan4-fault {
+ retain-state-shutdown;
+ default-state = "off";
+ gpios = <&io_expander0 3 GPIO_ACTIVE_LOW>;
+ label = "fan4:red:fault";
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_FAULT;
+ };
+
+ led-fan5-fault {
+ retain-state-shutdown;
+ default-state = "off";
+ gpios = <&io_expander0 4 GPIO_ACTIVE_LOW>;
+ label = "fan5:red:fault";
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_FAULT;
+ };
+ };
+
+ memory@80000000 {
+ reg = <0x80000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gfx_memory: framebuffer {
+ compatible = "shared-dma-pool";
+ size = <0x01000000>;
+ alignment = <0x01000000>;
+ reusable;
+ };
+
+ vga_memory: framebuffer@9f000000 {
+ no-map;
+ reg = <0x9f000000 0x01000000>; /* 16M */
+ };
+
+ video_engine_memory: jpegbuffer {
+ compatible = "shared-dma-pool";
+ size = <0x02000000>; /* 32M */
+ alignment = <0x01000000>;
+ reusable;
+ };
+ };
+};
+
+&adc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc0_default
+ &pinctrl_adc1_default
+ &pinctrl_adc2_default
+ &pinctrl_adc3_default
+ &pinctrl_adc4_default
+ &pinctrl_adc5_default
+ &pinctrl_adc6_default
+ &pinctrl_adc7_default
+ &pinctrl_adc8_default
+ &pinctrl_adc9_default
+ &pinctrl_adc10_default
+ &pinctrl_adc11_default
+ &pinctrl_adc12_default
+ &pinctrl_adc13_default
+ &pinctrl_adc14_default
+ &pinctrl_adc15_default>;
+};
+
+&fmc {
+ status = "okay";
+
+ flash@0 {
+ label = "bmc";
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ status = "okay";
+#include "openbmc-flash-layout-64.dtsi"
+ };
+};
+
+&gfx {
+ memory-region = <&gfx_memory>;
+ status = "okay";
+};
+
+&gpio {
+ gpio-line-names =
+ /*A0-A7*/ "","","","bmc-ready","","","","",
+ /*B0-B7*/ "i2c-backup-sel","","","","","","","host0-shd-ack-n",
+ /*C0-C7*/ "","","","","","","","",
+ /*D0-D7*/ "button-power-n","control-power-n","button-reset-n",
+ "host0-sysreset-n","","","power-chassis-good","",
+ /*E0-E7*/ "","s0-vrd1-vddq0123-fault-n",
+ "s0-vrd1-vddq4567-fault-n","s0-vrd0-vddc-fault-n",
+ "s0-vrd3-p0v75-fault-n","","","",
+ /*F0-F7*/ "","","ps-atx-on-n","","","","","",
+ /*G0-G7*/ "led-bmc-heartbeat-n","button-identify-n","",
+ "led-system-fault-n","uboot-ready","bmc-salt2-n","","",
+ /*H0-H7*/ "ps-pwr-ok","","","","","","","",
+ /*I0-I7*/ "","","","","","","","",
+ /*J0-J7*/ "s0-hightemp-n","","","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "","","","","","","","",
+ /*M0-M7*/ "cpld-disable-bmc-n","","","","","s0-spi-auth-fail-n","","",
+ /*N0-N7*/ "","","","","","","","",
+ /*O0-O7*/ "","","","","","","","",
+ /*P0-P7*/ "","","","","","","","",
+ /*Q0-Q7*/ "","","","","","","led-identify-n",
+ "chassis-intrusion-n",
+ /*R0-R7*/ "","","ext-hightemp-n","spi0-program-sel","",
+ "output-hwm-bat-en","","",
+ /*S0-S7*/ "s0-vr-hot-n","","input-salt2-n","bmc-sysreset-n","","","","",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","","","","","","",
+ /*V0-V7*/ "","","","","","","","",
+ /*W0-W7*/ "","","","","","","","",
+ /*X0-X7*/ "","","","","","","","",
+ /*Y0-Y7*/ "","","","","","","","",
+ /*Z0-Z7*/ "","","","s0-rtc-lock","","","","",
+ /*AA0-AA7*/ "s0-rtc-int-n","","","","","pmbus-sel-n","","",
+ /*AB0-AB7*/ "host0-reboot-ack-n","s0-sys-auth-failure-n",
+ "","","","","","",
+ /*AC0-AC7*/ "s0-fault-alert","host0-ready","s0-overtemp-n",
+ "","bmc-ok","host0-special-boot","presence-cpu0",
+ "host0-shd-req-n";
+
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ ipmb@10 {
+ compatible = "ipmb-dev";
+ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+ i2c-protocol;
+ };
+
+};
+
+&i2c1 {
+ status = "okay";
+
+ i2c-mux1@73 {
+ compatible = "nxp,pca9548";
+ reg = <0x73>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ nvme1: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ pcie4: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ pcie5: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ pcie6: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+
+ pcie7: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+
+ nvme3: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+
+ nvme2: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+
+ nvme0: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
+
+ i2c-mux2@75 {
+ compatible = "nxp,pca9548";
+ reg = <0x75>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ nvme4: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ nvme5: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ nvme6: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ nvme7: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+
+ nvme8: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+
+ nvme9: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+
+ nvme10: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+
+ nvme11: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ smpro@4f {
+ compatible = "ampere,smpro";
+ reg = <0x4f>;
+ };
+};
+
+&i2c3 {
+ status = "okay";
+
+ // PSU FRU
+ eeprom@38 {
+ compatible = "atmel,24c02";
+ reg = <0x38>;
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ temperature-sensor@29 {
+ compatible = "nuvoton,nct7802";
+ reg = <0x29>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 { /* LTD */
+ reg = <0>;
+ status = "okay";
+ };
+
+ channel@1 { /* RTD1 */
+ reg = <1>;
+ sensor-type = "temperature";
+ temperature-mode = "thermistor";
+ };
+
+ channel@2 { /* RTD2 */
+ reg = <2>;
+ sensor-type = "temperature";
+ temperature-mode = "thermal-diode";
+ };
+ };
+
+ temperature-sensor@4c {
+ compatible = "nuvoton,w83773g";
+ reg = <0x4c>;
+ };
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+
+ rtc@6f {
+ compatible = "isil,isl1208";
+ reg = <0x6f>;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+
+ // BMC FRU
+ eeprom@57 {
+ compatible = "atmel,24c128";
+ reg = <0x57>;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eth1_macaddress: macaddress@3f80 {
+ reg = <0x3f80 6>;
+ };
+
+ // The offset for eth0 really is at 0x3f88.
+ // eth0 and eth1 are swapped from what might be
+ // expected.
+ eth0_macaddress: macaddress@3f88 {
+ reg = <0x3f88 6>;
+ };
+ };
+ };
+};
+
+&i2c8 {
+ status = "okay";
+
+ io_expander0: gpio@1c {
+ compatible = "nxp,pca9557";
+ reg = <0x1c>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+};
+
+// Bus for accessing the SCP EEPROM
+&i2c12 {
+ status = "okay";
+};
+
+&i2c13 {
+ status = "okay";
+
+ ssif-bmc@10 {
+ compatible = "ssif-bmc";
+ reg = <0x10>;
+ };
+};
+
+// Connected to host Intel X550 (ALTRAD8UD-1L2T) or
+// Broadcom BCM57414 (ALTRAD8UD2-1L2Q) interface.
+// Unconnected on ALTRAD8UD-1L
+&mac0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
+ use-ncsi;
+ nvmem-cells = <ð0_macaddress>;
+ nvmem-cell-names = "mac-address";
+
+ status = "okay";
+};
+
+// Connected to Realtek RTL8211E
+&mac1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
+
+ nvmem-cells = <ð1_macaddress>;
+ nvmem-cell-names = "mac-address";
+
+ status = "okay";
+};
+
+&pwm_tacho {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default
+ &pinctrl_pwm1_default
+ &pinctrl_pwm2_default
+ &pinctrl_pwm3_default
+ &pinctrl_pwm4_default
+ &pinctrl_pwm5_default
+ &pinctrl_pwm6_default
+ &pinctrl_pwm7_default>;
+
+ status = "okay";
+
+ fan@0 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x00 0x08>;
+ };
+
+ fan@1 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x01 0x09>;
+ };
+
+ fan@2 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x02 0x0a>;
+ };
+
+ fan@3 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0b>;
+ };
+
+ fan@4 {
+ reg = <0x04>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0c>;
+ };
+
+ fan@5 {
+ reg = <0x05>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x05 0x0d>;
+ };
+
+ fan@6 {
+ reg = <0x06>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x06 0x0e>;
+ };
+
+ fan@7 {
+ reg = <0x07>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x07 0x0f>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ status = "okay";
+
+ // Host BIOS/UEFI EEPROM
+ flash@0 {
+ m25p,fast-read;
+ label = "pnor";
+ spi-max-frequency = <100000000>;
+ status = "okay";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ tfa@400000 {
+ reg = <0x400000 0x200000>;
+ label = "pnor-tfa";
+ };
+
+ uefi@600000 {
+ reg = <0x600000 0x1A00000>;
+ label = "pnor-uefi";
+ };
+ };
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd1_default
+ &pinctrl_rxd1_default
+ &pinctrl_ncts1_default
+ &pinctrl_nrts1_default>;
+
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd2_default
+ &pinctrl_rxd2_default>;
+
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd3_default
+ &pinctrl_rxd3_default>;
+
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd4_default
+ &pinctrl_rxd4_default>;
+
+ status = "okay";
+};
+
+// The BMC's uart
+&uart5 {
+ status = "okay";
+};
+
+&vhub {
+ status = "okay";
+};
+
+&video {
+ memory-region = <&video_engine_memory>;
+
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/dts-v1/;
+#include "aspeed-g6.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+
+/ {
+ model = "Facebook Anacapa BMC";
+ compatible = "facebook,anacapa-bmc", "aspeed,ast2600";
+
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ i2c16 = &i2c0mux0ch0;
+ i2c17 = &i2c0mux0ch1;
+ i2c18 = &i2c0mux0ch2;
+ i2c19 = &i2c0mux0ch3;
+ i2c20 = &i2c1mux0ch0;
+ i2c21 = &i2c1mux0ch1;
+ i2c22 = &i2c1mux0ch2;
+ i2c23 = &i2c1mux0ch3;
+ i2c24 = &i2c4mux0ch0;
+ i2c25 = &i2c4mux0ch1;
+ i2c26 = &i2c4mux0ch2;
+ i2c27 = &i2c4mux0ch3;
+ i2c28 = &i2c4mux0ch4;
+ i2c29 = &i2c4mux0ch5;
+ i2c30 = &i2c4mux0ch6;
+ i2c31 = &i2c4mux0ch7;
+ i2c32 = &i2c8mux0ch0;
+ i2c33 = &i2c8mux0ch1;
+ i2c34 = &i2c8mux0ch2;
+ i2c35 = &i2c8mux0ch3;
+ i2c36 = &i2c10mux0ch0;
+ i2c37 = &i2c10mux0ch1;
+ i2c38 = &i2c10mux0ch2;
+ i2c39 = &i2c10mux0ch3;
+ i2c40 = &i2c10mux0ch4;
+ i2c41 = &i2c10mux0ch5;
+ i2c42 = &i2c10mux0ch6;
+ i2c43 = &i2c10mux0ch7;
+ i2c44 = &i2c11mux0ch0;
+ i2c45 = &i2c11mux0ch1;
+ i2c46 = &i2c11mux0ch2;
+ i2c47 = &i2c11mux0ch3;
+ i2c48 = &i2c11mux0ch4;
+ i2c49 = &i2c11mux0ch5;
+ i2c50 = &i2c11mux0ch6;
+ i2c51 = &i2c11mux0ch7;
+ i2c52 = &i2c13mux0ch0;
+ i2c53 = &i2c13mux0ch1;
+ i2c54 = &i2c13mux0ch2;
+ i2c55 = &i2c13mux0ch3;
+ i2c56 = &i2c13mux0ch4;
+ i2c57 = &i2c13mux0ch5;
+ i2c58 = &i2c13mux0ch6;
+ i2c59 = &i2c13mux0ch7;
+ };
+
+ chosen {
+ stdout-path = "serial4:57600n8";
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
+ <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
+ <&adc1 2>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ label = "bmc_heartbeat_amber";
+ gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-1 {
+ label = "fp_id_amber";
+ default-state = "off";
+ gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ video_engine_memory: video {
+ size = <0x02c00000>;
+ alignment = <0x00100000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+
+ gfx_memory: framebuffer {
+ size = <0x01000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
+ p3v3_bmc_aux: regulator-p3v3-bmc-aux {
+ compatible = "regulator-fixed";
+ regulator-name = "p3v3_bmc_aux";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ spi_gpio: spi {
+ compatible = "spi-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
+ miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>;
+ num-chipselects = <1>;
+ status = "okay";
+
+ tpm@0 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ spi-max-frequency = <33000000>;
+ reg = <0>;
+ };
+ };
+};
+
+&adc0 {
+ aspeed,int-vref-microvolt = <2500000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
+ &pinctrl_adc2_default &pinctrl_adc3_default
+ &pinctrl_adc4_default &pinctrl_adc5_default
+ &pinctrl_adc6_default &pinctrl_adc7_default>;
+ status = "okay";
+};
+
+&adc1 {
+ aspeed,int-vref-microvolt = <2500000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc10_default>;
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&fmc {
+ status = "okay";
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout-128.dtsi"
+ };
+
+ flash@1 {
+ status = "okay";
+ m25p,fast-read;
+ label = "alt-bmc";
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&gfx {
+ status = "okay";
+ memory-region = <&gfx_memory>;
+};
+
+&gpio0 {
+ gpio-line-names =
+
+ /*A0-A7*/
+ "","","","","","","","",
+
+ /*B0-B7*/
+ "BATTERY_DETECT", "", "", "BMC_READY",
+ "", "FM_ID_LED", "", "",
+
+ /*C0-C7*/
+ "","","","","","","","",
+
+ /*D0-D7*/
+ "","","","","","","","",
+
+ /*E0-E7*/
+ "","","","","","","","",
+
+ /*F0-F7*/
+ "","","","","","","","",
+
+ /*G0-G7*/
+ "FM_MUX1_SEL", "", "", "",
+ "", "", "FM_DEBUG_PORT_PRSNT_N", "FM_BMC_DBP_PRESENT_N",
+
+ /*H0-H7*/
+ "","","","","","","","",
+
+ /*I0-I7*/
+ "", "", "", "",
+ "", "FLASH_WP_STATUS", "BMC_JTAG_MUX_SEL", "",
+
+ /*J0-J7*/
+ "","","","","","","","",
+
+ /*K0-K7*/
+ "","","","","","","","",
+
+ /*L0-L7*/
+ "","","","","","","","",
+
+ /*M0-M7*/
+ "", "BMC_FRU_WP", "", "",
+ "", "", "", "",
+
+ /*N0-N7*/
+ "LED_POSTCODE_0", "LED_POSTCODE_1", "LED_POSTCODE_2", "LED_POSTCODE_3",
+ "LED_POSTCODE_4", "LED_POSTCODE_5", "LED_POSTCODE_6", "LED_POSTCODE_7",
+
+ /*O0-O7*/
+ "","","","","","","","",
+
+ /*P0-P7*/
+ "PWR_BTN_BMC_BUF_N", "", "ID_RST_BTN_BMC_N", "",
+ "PWR_LED", "", "", "BMC_HEARTBEAT_N",
+
+ /*Q0-Q7*/
+ "","","","","","","","",
+
+ /*R0-R7*/
+ "","","","","","","","",
+
+ /*S0-S7*/
+ "", "", "SYS_BMC_PWRBTN_N", "",
+ "", "", "", "RUN_POWER_FAULT",
+
+ /*T0-T7*/
+ "","","","","","","","",
+
+ /*U0-U7*/
+ "","","","","","","","",
+
+ /*V0-V7*/
+ "","","","","","","","",
+
+ /*W0-W7*/
+ "","","","","","","","",
+
+ /*X0-X7*/
+ "","","","","","","","",
+
+ /*Y0-Y7*/
+ "","","","","","","","",
+
+ /*Z0-Z7*/
+ "SPI_BMC_TPM_CS2_N", "", "", "SPI_BMC_TPM_CLK",
+ "SPI_BMC_TPM_MOSI", "SPI_BMC_TPM_MISO", "", "";
+};
+
+&gpio1 {
+ gpio-line-names =
+ /*18A0-18A7*/
+ "","","","","","","","",
+
+ /*18B0-18B7*/
+ "","","","",
+ "FM_BOARD_BMC_REV_ID0", "FM_BOARD_BMC_REV_ID1",
+ "FM_BOARD_BMC_REV_ID2", "",
+
+ /*18C0-18C7*/
+ "","","","","","","","",
+
+ /*18D0-18D7*/
+ "","","","","","","","",
+
+ /*18E0-18E3*/
+ "FM_BMC_PROT_LS_EN", "AC_PWR_BMC_BTN_N", "", "";
+};
+
+// L Bridge Board
+&i2c0 {
+ status = "okay";
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c0mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c0mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c0mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c0mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// R Bridge Board
+&i2c1 {
+ status = "okay";
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c1mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c1mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c1mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c1mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// MB - E1.S
+&i2c4 {
+ status = "okay";
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9548";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c4mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch4: i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch5: i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch6: i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch7: i2c@7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// AMC
+&i2c5 {
+ status = "okay";
+};
+
+// MB
+&i2c6 {
+ status = "okay";
+
+ // HPM FRU
+ eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ };
+};
+
+// SCM
+&i2c7 {
+ status = "okay";
+
+
+};
+
+// MB - PDB
+&i2c8 {
+ status = "okay";
+
+ i2c-mux@72 {
+ compatible = "nxp,pca9546";
+ reg = <0x72>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c8mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@1f {
+ compatible = "ti,adc128d818";
+ reg = <0x1f>;
+ ti,mode = /bits/ 8 <1>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TEMP75_U8_ALERT_R_N",
+ "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP",
+ "RPDB_FAN_CT_FAN_FAIL_R_N", "",
+ "", "",
+ "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N",
+ "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N",
+ "RPDB_I2C_P12V_MB_VRM_ALERT_R_N",
+ "RPDB_I2C_P12V_STBY_VRM_ALERT_R_N",
+ "RPDB_PGD_P3V3_STBY_PWRGD_R",
+ "RPDB_P12V_STBY_VRM_PWRGD_BUF_R";
+ };
+
+ gpio@24 {
+ compatible = "nxp,pca9555";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R",
+ "RPDB_PWRGD_P50V_HSC4_SYS_R",
+ "RPDB_PWRGD_P50V_STBY_SYS_BUF_R",
+ "RPDB_P50V_FAN1_R2_PG", "RPDB_P50V_FAN2_R2_PG",
+ "RPDB_P50V_FAN3_R2_PG", "RPDB_P50V_FAN4_R2_PG",
+ "", "RPDB_FAN1_PRSNT_N_R",
+ "", "RPDB_FAN2_PRSNT_N_R",
+ "RPDB_FAN3_PRSNT_N_R", "RPDB_FAN4_PRSNT_N_R",
+ "", "";
+ };
+
+ // R-PDB FRU
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+ };
+ i2c8mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "LPDB_FAN_FULL_SPEED_R_N","LPDB_I2C_TEMP75_U8_ALERT_R_N",
+ "LPDB_I2C_TMP432_U29_ALERT_R_N","LPDB_GLOBAL_WP",
+ "LPDB_FAN_CT_FAN_FAIL_R_N","",
+ "","",
+ "LPDB_ALERT_P50V_HSC0_R_N","LPDB_ALERT_P50V_HSC1_R_N",
+ "LPDB_ALERT_P50V_HSC5_R_N","LPDB_I2C_P12V_SW_VRM_ALERT_R_N",
+ "LPDB_EAM0_PRSNT_MOS_N_R","LPDB_EAM1_PRSNT_MOS_N_R",
+ "LPDB_PWRGD_P50V_HSC5_SYS_R","";
+ };
+
+ gpio@24 {
+ compatible = "nxp,pca9555";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "LPDB_P50V_FAN1_R2_PG","LPDB_P50V_FAN2_R2_PG",
+ "LPDB_P50V_FAN3_R2_PG","LPDB_P50V_FAN4_R2_PG",
+ "LPDB_P50V_FAN5_R2_PG","LPDB_FAN1_PRSNT_N_R",
+ "LPDB_FAN2_PRSNT_N_R","LPDB_FAN3_PRSNT_N_R",
+ "LPDB_FAN4_PRSNT_N_R","LPDB_FAN5_PRSNT_N_R",
+ "","",
+ "","",
+ "","";
+ };
+
+ // L-PDB FRU
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+ };
+ i2c8mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c8mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// SCM
+&i2c9 {
+ status = "okay";
+
+ // SCM FRU
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ // BSM FRU
+ eeprom@56 {
+ compatible = "atmel,24c64";
+ reg = <0x56>;
+ };
+};
+
+// R Bridge Board
+&i2c10 {
+ status = "okay";
+
+ i2c-mux@71 {
+ compatible = "nxp,pca9548";
+ reg = <0x71>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c10mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch4: i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch5: i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "","",
+ "","RBB_CPLD_REFRESH_IN_PRGRS_R_L",
+ "RBB_EAM0_NIC_CBL_PRSNT_R_L","RBB_EAM1_NIC_CBL_PRSNT_R_L",
+ "RBB_AINIC_JTAG_MUX_R2_SEL","RBB_SPI_MUX0_R2_SEL",
+ "RBB_AINIC_PRSNT_R_L","RBB_AINIC_OE_R_N",
+ "RBB_AINIC_BOARD_R2_ID","RBB_RST_USB2_HUB_R_N",
+ "RBB_RST_FT4222_R_N","RBB_RST_MCP2210_R_N",
+ "","";
+ };
+
+ // R Bridge Board FRU
+ eeprom@52 {
+ compatible = "atmel,24c256";
+ reg = <0x52>;
+ };
+ };
+ i2c10mux0ch6: i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch7: i2c@7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// L Bridge Board
+&i2c11 {
+ status = "okay";
+
+ i2c-mux@71 {
+ compatible = "nxp,pca9548";
+ reg = <0x71>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c11mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch4: i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch5: i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "","",
+ "","LBB_CPLD_REFRESH_IN_PRGRS_R_L",
+ "LBB_EAM0_NIC_CBL_PRSNT_R_L","LBB_EAM1_NIC_CBL_PRSNT_R_L",
+ "LBB_AINIC_JTAG_MUX_R2_SEL","LBB_SPI_MUX0_R2_SEL",
+ "LBB_AINIC_PRSNT_R_L","LBB_AINIC_OE_R_N",
+ "LBB_AINIC_BOARD_R2_ID","LBB_RST_USB2_HUB_R_N",
+ "LBB_RST_FT4222_R_N","LBB_RST_MCP2210_R_N",
+ "","";
+ };
+
+ // L Bridge Board FRU
+ eeprom@52 {
+ compatible = "atmel,24c256";
+ reg = <0x52>;
+ };
+ };
+ i2c11mux0ch6: i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch7: i2c@7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// Debug Card
+&i2c12 {
+ status = "okay";
+};
+
+// MB
+&i2c13 {
+ status = "okay";
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9548";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c13mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@1f {
+ compatible = "ti,adc128d818";
+ reg = <0x1f>;
+ ti,mode = /bits/ 8 <1>;
+ };
+ };
+ i2c13mux0ch4: i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ // HPM BRD ID FRU
+ eeprom@51 {
+ compatible = "atmel,24c256";
+ reg = <0x51>;
+ };
+ };
+ i2c13mux0ch5: i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch6: i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch7: i2c@7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// SCM
+&i2c14 {
+ status = "okay";
+};
+
+&i2c15 {
+ status = "okay";
+};
+
+&kcs2 {
+ aspeed,lpc-io-reg = <0xca8>;
+ status = "okay";
+};
+
+&kcs3 {
+ aspeed,lpc-io-reg = <0xca2>;
+ status = "okay";
+};
+
+&lpc_ctrl {
+ status = "okay";
+};
+
+&mac2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ncsi3_default>;
+ use-ncsi;
+};
+
+&sgpiom0 {
+ ngpios = <128>;
+ bus-frequency = <2000000>;
+ gpio-line-names =
+ /*in - out - in - out */
+ /* A0-A7 line 0-15 */
+ "", "FM_CPU0_SYS_RESET_N", "", "CPU0_KBRST_N",
+ "", "FM_CPU0_PROCHOT_trigger_N", "", "FM_CLR_CMOS_R_P0",
+ "", "Force_I3C_SEL", "", "SYSTEM_Force_Run_AC_Cycle",
+ "", "", "", "",
+
+ /* B0-B7 line 16-31 */
+ "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL",
+ "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL",
+ "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL",
+ "Channel3_leakage", "FM_CPU0_NMI_SYNC_FLOOD_N",
+ "Channel4_leakage_Manifold2", "",
+ "Channel5_leakage_EAM1", "",
+ "Channel6_leakage_CPU_DIMM", "",
+ "Channel7_leakage_EAM2", "",
+
+ /* C0-C7 line 32-47 */
+ "RSVD_RMC_GPIO3", "", "", "",
+ "", "", "", "",
+ "LEAK_DETECT_RMC_N", "", "", "",
+ "", "", "", "",
+
+ /* D0-D7 line 48-63 */
+ "PWRGD_PDB_EAMHSC0_CPLD_PG_R", "",
+ "PWRGD_PDB_EAMHSC1_CPLD_PG_R", "",
+ "PWRGD_PDB_EAMHSC2_CPLD_PG_R", "",
+ "PWRGD_PDB_EAMHSC3_CPLD_PG_R", "",
+ "AMC_BRD_PRSNT_CPLD_L", "", "", "",
+ "", "", "", "",
+
+ /* E0-E7 line 64-79 */
+ "AMC_PDB_EAMHSC0_CPLD_EN_R", "",
+ "AMC_PDB_EAMHSC1_CPLD_EN_R", "",
+ "AMC_PDB_EAMHSC2_CPLD_EN_R", "",
+ "AMC_PDB_EAMHSC3_CPLD_EN_R", "",
+ "", "", "", "",
+ "", "", "", "",
+
+ /* F0-F7 line 80-95 */
+ "PWRGD_PVDDCR_CPU1_P0", "SGPIO_READY",
+ "PWRGD_PVDDCR_CPU0_P0", "",
+ "", "", "", "",
+ "", "", "", "",
+
+ /* G0-G7 line 96-111 */
+ "PWRGD_PVDDCR_SOC_P0", "",
+ "PWRGD_PVDDIO_P0", "",
+ "PWRGD_PVDDIO_MEM_S3_P0", "",
+ "PWRGD_CHMP_CPU0_FPGA", "",
+ "PWRGD_CHIL_CPU0_FPGA", "",
+ "PWRGD_CHEH_CPU0_FPGA", "",
+ "PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD",
+ "", "",
+
+ /* H0-H7 line 112-127 */
+ "PWRGD_P3V3", "",
+ "P12V_DDR_IP_PWRGD_R", "",
+ "P12V_DDR_AH_PWRGD_R", "",
+ "PWRGD_P12V_VRM1_CPLD_PG_R", "",
+ "PWRGD_P12V_VRM0_CPLD_PG_R", "",
+ "PWRGD_PDB_HSC4_CPLD_PG_R", "",
+ "PWRGD_PVDD18_S5_P0_PG", "",
+ "PWRGD_PVDD33_S5_P0_PG", "",
+
+ /* I0-I7 line 128-143 */
+ "EAM0_BRD_PRSNT_R_L", "",
+ "EAM1_BRD_PRSNT_R_L", "",
+ "EAM2_BRD_PRSNT_R_L", "",
+ "EAM3_BRD_PRSNT_R_L", "",
+ "EAM0_CPU_MOD_PWR_GD_R", "",
+ "EAM1_CPU_MOD_PWR_GD_R", "",
+ "EAM2_CPU_MOD_PWR_GD_R", "",
+ "EAM3_CPU_MOD_PWR_GD_R", "",
+
+ /* J0-J7 line 144-159 */
+ "PRSNT_L_BIRDGE_R", "",
+ "PRSNT_R_BIRDGE_R", "",
+ "BRIDGE_L_MAIN_PG_R", "",
+ "BRIDGE_R_MAIN_PG_R", "",
+ "BRIDGE_L_STBY_PG_R", "",
+ "BRIDGE_R_STBY_PG_R", "",
+ "", "", "", "",
+
+ /* K0-K7 line 160-175 */
+ "ADC_I2C_ALERT_N", "",
+ "TEMP_I2C_ALERT_R_L", "",
+ "CPU0_VR_SMB_ALERT_CPLD_N", "",
+ "COVER_INTRUDER_R_N", "",
+ "HANDLE_INTRUDER_CPLD_N", "",
+ "IRQ_MCIO_CPLD_WAKE_R_N", "",
+ "APML_CPU0_ALERT_R_N", "",
+ "PDB_ALERT_R_N", "",
+
+ /* L0-L7 line 176-191 */
+ "CPU0_SP7R1", "", "CPU0_SP7R2", "",
+ "CPU0_SP7R3", "", "CPU0_SP7R4", "",
+ "CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "",
+ "CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "",
+
+ /* M0-M7 line 192-207 */
+ "EAM0_SMERR_CPLD_R_L", "",
+ "EAM1_SMERR_CPLD_R_L", "",
+ "EAM2_SMERR_CPLD_R_L", "",
+ "EAM3_SMERR_CPLD_R_L", "",
+ "CPU0_SMERR_N_R", "",
+ "CPU0_NV_SAVE_N_R", "",
+ "PDB_PWR_LOSS_CPLD_N", "",
+ "IRQ_BMC_SMI_ACTIVE_R_N", "",
+
+ /* N0-N7 line 208-223 */
+ "AMCROT_BMC_S5_RDY_R", "",
+ "AMC_RDY_R", "",
+ "AMC_STBY_PGOOD_R", "",
+ "CPU_AMC_SLP_S5_R_L", "",
+ "AMC_CPU_EAMPG_R", "",
+ "", "", "", "",
+
+ /* O0-O7 line 224-239 */
+ "HPM_PWR_FAIL", "Port80_b0",
+ "FM_DIMM_IP_FAIL", "Port80_b1",
+ "FM_DIMM_AH_FAIL", "Port80_b2",
+ "HPM_AMC_THERMTRIP_R_L", "Port80_b3",
+ "FM_CPU0_THERMTRIP_N", "Port80_b4",
+ "PVDDCR_SOC_P0_OCP_L", "Port80_b5",
+ "CPLD_SGPIO_RDY", "Port80_b6",
+ "", "Port80_b7",
+
+ /* P0-P7 line 240-255 */
+ "CPU0_SLP_S5_N_R", "NFC_VEN",
+ "CPU0_SLP_S3_N_R", "",
+ "FM_CPU0_PWRGD", "",
+ "PWRGD_RMC", "",
+ "FM_RST_CPU0_RESET_N", "",
+ "FM_PWRGD_CPU0_PWROK", "",
+ "wS5_PWR_Ready", "",
+ "wS0_ON_N", "PWRGD_P1V0_AUX";
+ status = "okay";
+};
+
+// BIOS Flash
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2_default>;
+ status = "okay";
+ reg = <0x1e631000 0xc4>, <0x50000000 0x8000000>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ label = "pnor";
+ spi-max-frequency = <12000000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ status = "okay";
+ };
+};
+
+// HOST BIOS Debug
+&uart1 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+// BMC Debug Console
+&uart5 {
+ status = "okay";
+};
+
+&uart_routing {
+ status = "okay";
+};
+
+&uhci {
+ status = "okay";
+};
+
+&vhub {
+ status = "okay";
+ pinctrl-names = "default";
+};
+
+&video {
+ status = "okay";
+ memory-region = <&video_engine_memory>;
+};
+
+&wdt1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdtrst1_default>;
+ aspeed,reset-type = "soc";
+ aspeed,external-signal;
+ aspeed,ext-push-pull;
+ aspeed,ext-active-high;
+ aspeed,ext-pulse-duration = <256>;
+ status = "okay";
+};
<&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>;
};
- spi1_gpio: spi1-gpio {
+ spi1_gpio: spi {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
- gpio-sck = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
- gpio-mosi = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
- gpio-miso = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>;
+ sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
+ miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>;
front_gpio_leds {
compatible = "gpio-leds";
- sys_log_id {
+ led-0 {
+ label = "sys_log_id";
default-state = "off";
gpios = <&front_leds 0 GPIO_ACTIVE_LOW>;
};
fan_gpio_leds {
compatible = "gpio-leds";
- fan0_blue {
+ led-0 {
+ label = "fan0_blue";
retain-state-shutdown;
default-state = "on";
gpios = <&fan_leds 8 GPIO_ACTIVE_HIGH>;
};
- fan1_blue {
+ led-1 {
+ label = "fan1_blue";
retain-state-shutdown;
default-state = "on";
gpios = <&fan_leds 9 GPIO_ACTIVE_HIGH>;
};
- fan2_blue {
+ led-2 {
+ label = "fan2_blue";
retain-state-shutdown;
default-state = "on";
gpios = <&fan_leds 10 GPIO_ACTIVE_HIGH>;
};
- fan3_blue {
+ led-3 {
+ label = "fan3_blue";
retain-state-shutdown;
default-state = "on";
gpios = <&fan_leds 11 GPIO_ACTIVE_HIGH>;
};
- fan0_amber {
+ led-4 {
+ label = "fan0_amber";
retain-state-shutdown;
default-state = "off";
gpios = <&fan_leds 12 GPIO_ACTIVE_HIGH>;
};
- fan1_amber {
+ led-5 {
+ label = "fan1_amber";
retain-state-shutdown;
default-state = "off";
gpios = <&fan_leds 13 GPIO_ACTIVE_HIGH>;
};
- fan2_amber {
+ led-6 {
+ label = "fan2_amber";
retain-state-shutdown;
default-state = "off";
gpios = <&fan_leds 14 GPIO_ACTIVE_HIGH>;
};
- fan3_amber {
+ led-7 {
+ label = "fan3_amber";
retain-state-shutdown;
default-state = "off";
gpios = <&fan_leds 15 GPIO_ACTIVE_HIGH>;
sled1_gpio_leds {
compatible = "gpio-leds";
- sled1_amber {
+ led-0 {
+ label = "sled1_amber";
retain-state-shutdown;
default-state = "keep";
gpios = <&sled1_leds 0 GPIO_ACTIVE_LOW>;
};
- sled1_blue {
+ led-1 {
+ label = "sled1_blue";
retain-state-shutdown;
default-state = "keep";
gpios = <&sled1_leds 1 GPIO_ACTIVE_LOW>;
sled2_gpio_leds {
compatible = "gpio-leds";
- sled2_amber {
+ led-0 {
+ label = "sled2_amber";
retain-state-shutdown;
default-state = "keep";
gpios = <&sled2_leds 0 GPIO_ACTIVE_LOW>;
};
- sled2_blue {
+ led-1 {
+ label = "sled2_blue";
retain-state-shutdown;
default-state = "keep";
gpios = <&sled2_leds 1 GPIO_ACTIVE_LOW>;
sled3_gpio_leds {
compatible = "gpio-leds";
- sled3_amber {
+ led-0 {
+ label = "sled3_amber";
retain-state-shutdown;
default-state = "keep";
gpios = <&sled3_leds 0 GPIO_ACTIVE_LOW>;
};
- sled3_blue {
+ led-1 {
+ label = "sled3_blue";
retain-state-shutdown;
default-state = "keep";
gpios = <&sled3_leds 1 GPIO_ACTIVE_LOW>;
sled4_gpio_leds {
compatible = "gpio-leds";
- sled4_amber {
+ led-0 {
+ label = "sled4_amber";
retain-state-shutdown;
default-state = "keep";
gpios = <&sled4_leds 0 GPIO_ACTIVE_LOW>;
};
- sled4_blue {
+ led-1 {
+ label = "sled4_blue";
retain-state-shutdown;
default-state = "keep";
gpios = <&sled4_leds 1 GPIO_ACTIVE_LOW>;
sled5_gpio_leds {
compatible = "gpio-leds";
- sled5_amber {
+ led-0 {
+ label = "sled5_amber";
retain-state-shutdown;
default-state = "keep";
gpios = <&sled5_leds 0 GPIO_ACTIVE_LOW>;
};
- sled5_blue {
+ led-1 {
+ label = "sled5_blue";
retain-state-shutdown;
default-state = "keep";
gpios = <&sled5_leds 1 GPIO_ACTIVE_LOW>;
sled6_gpio_leds {
compatible = "gpio-leds";
- sled6_amber {
+ led-0 {
+ label = "sled6_amber";
retain-state-shutdown;
default-state = "keep";
gpios = <&sled6_leds 0 GPIO_ACTIVE_LOW>;
};
- sled6_blue {
+ led-1 {
+ label = "sled6_blue";
retain-state-shutdown;
default-state = "keep";
gpios = <&sled6_leds 1 GPIO_ACTIVE_LOW>;
gpio-keys {
compatible = "gpio-keys";
- presence-sled1 {
+ presence-sled1-switch {
label = "presence-sled1";
gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(H, 2)>;
};
- presence-sled2 {
+ presence-sled2-switch {
label = "presence-sled2";
gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(H, 3)>;
};
- presence-sled3 {
+ presence-sled3-switch {
label = "presence-sled3";
gpios = <&gpio0 ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(H, 4)>;
};
- presence-sled4 {
+ presence-sled4-switch {
label = "presence-sled4";
gpios = <&gpio0 ASPEED_GPIO(H, 5) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(H, 5)>;
};
- presence-sled5 {
+ presence-sled5-switch {
label = "presence-sled5";
gpios = <&gpio0 ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(H, 6)>;
};
- presence-sled6 {
+ presence-sled6-switch {
label = "presence-sled6";
gpios = <&gpio0 ASPEED_GPIO(H, 7) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(H, 7)>;
sled1_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
- #address-cells = <1>;
- #size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
label = "USB-C";
pd-revision = /bits/ 8 <0x2 0x0 0x1 0x20>;
power-role = "dual";
- try-power-role = "sink";
data-role = "dual";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sled2_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
- #address-cells = <1>;
- #size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
label = "USB-C";
pd-revision = /bits/ 8 <0x2 0x0 0x1 0x20>;
power-role = "dual";
- try-power-role = "sink";
data-role = "dual";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sled3_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
- #address-cells = <1>;
- #size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
label = "USB-C";
pd-revision = /bits/ 8 <0x2 0x0 0x1 0x20>;
power-role = "dual";
- try-power-role = "sink";
data-role = "dual";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sled4_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
- #address-cells = <1>;
- #size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
label = "USB-C";
pd-revision = /bits/ 8 <0x2 0x0 0x1 0x20>;
power-role = "dual";
- try-power-role = "sink";
data-role = "dual";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sled5_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
- #address-cells = <1>;
- #size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
label = "USB-C";
pd-revision = /bits/ 8 <0x2 0x0 0x1 0x20>;
power-role = "dual";
- try-power-role = "sink";
data-role = "dual";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sled6_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
- #address-cells = <1>;
- #size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
label = "USB-C";
pd-revision = /bits/ 8 <0x2 0x0 0x1 0x20>;
power-role = "dual";
- try-power-role = "sink";
data-role = "dual";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
&i2c13 {
multi-master;
- aspeed,hw-timeout-ms = <1000>;
status = "okay";
//USB Debug Connector
};
&adc0 {
- vref = <1800>;
+ aspeed,int-vref-microvolt = <2500000>;
status = "okay";
pinctrl-names = "default";
};
&adc1 {
- vref = <2500>;
+ aspeed,int-vref-microvolt = <2500000>;
status = "okay";
pinctrl-names = "default";
&wdt1 {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdtrst1_default>;
aspeed,reset-type = "soc";
- aspeed,external-signal;
- aspeed,ext-push-pull;
- aspeed,ext-active-high;
- aspeed,ext-pulse-duration = <256>;
};
gpios = <&gpio0 ASPEED_GPIO(P, 5) (GPIO_ACTIVE_HIGH|GPIO_TRANSITORY)>;
};
- led-hdd {
+ };
+
+ hdd-leds {
+ compatible = "gpio-leds";
+
+ led-0 {
label = "hdd_led";
gpios = <&io_expander13 1 GPIO_ACTIVE_LOW>;
};
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
+
+ // HDD NVMe SSD FRU 0
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ };
};
i2c0mux0ch1mux0ch1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
+
+ // HDD NVMe SSD FRU 1
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ };
};
i2c0mux0ch1mux0ch3: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
+
+ // HDD NVMe SSD FRU 2
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ };
};
i2c0mux3ch1mux0ch1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
+
+ // HDD NVMe SSD FRU 3
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ };
};
i2c0mux3ch1mux0ch3: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
+
+ // BOOT DRIVE FRU
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ };
};
i2c0mux5ch2: i2c@2 {
"",
"",
"",
- "",
+ "shdn_force_l_cpld",
"",
"",
"",
use-ncsi;
};
-&udma {
- status = "okay";
-};
-
&uart1 {
status = "okay";
};
"irq-pvddcore1-ocp-alert","",
"","",
/*O4-O7 line 232-239*/
- "","","","","","","","",
+ "","","","",
+ "presence-lower-fanboard1","",
+ "presence-lower-fanboard2","",
/*P0-P3 line 240-247*/
- "","","","","","","","",
+ "presence-upper-fanboard1","",
+ "presence-upper-fanboard2","",
+ "","","","",
/*P4-P7 line 248-255*/
"","","","","","","","";
};
};
&i2c7 {
+ multi-master;
status = "okay";
+
+ ipmb@10 {
+ compatible = "ipmb-dev";
+ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+ i2c-protocol;
+ };
};
&i2c8 {
&i2c12 {
status = "okay";
+ gpio@27 {
+ compatible = "nxp,pca9555";
+ reg = <0x27>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names =
+ "PEX0_MODE_SEL1_R","PEX0_MODE_SEL2_R",
+ "PEX0_MODE_SEL3_R","PEX0_MODE_SEL4_R",
+ "","","","",
+ "UART_MUX_SEL","RST_SMB_NIC_R_N",
+ "RST_SMB_N","RST_CP2102N_N",
+ "SPI_MUX_SEL","","","";
+ };
+
// SWB FRU
eeprom@52 {
compatible = "atmel,24c64";
"","BIOS_DEBUG_MODE",
/*H0-H3 line 112-119*/
"FM_IOEXP_U538_INT_N","",
- "FM_IOEXP_U539_INT_N","",
- "FM_IOEXP_U540_INT_N","",
- "FM_IOEXP_U541_INT_N","",
+ "FM_IOEXP_U539_INT_N","FM_MODULE_PWR_EN_N_1B",
+ "FM_IOEXP_U540_INT_N","FM_MODULE_PWR_EN_N_2B",
+ "FM_IOEXP_U541_INT_N","FM_MODULE_PWR_EN_N_3B",
/*H4-H7 line 120-127*/
- "FM_IOEXP_PDB2_U1003_INT_N","",
+ "FM_IOEXP_PDB2_U1003_INT_N","FM_MODULE_PWR_EN_N_4B",
"","",
"","",
"FM_MAIN_PWREN_RMC_EN_ISO_R","",
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+
+/ {
+ model = "AST2600 MSX4 BMC";
+ compatible = "nvidia,msx4-bmc", "aspeed,ast2600";
+
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ };
+
+ chosen {
+ stdout-path = "uart5:115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gfx_memory: framebuffer {
+ compatible = "shared-dma-pool";
+ size = <0x01000000>;
+ alignment = <0x01000000>;
+ reusable;
+ };
+
+ video_engine_memory: jpegbuffer {
+ compatible = "shared-dma-pool";
+ size = <0x02000000>; /* 32M */
+ alignment = <0x01000000>;
+ reusable;
+ };
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&fmc {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ label = "bmc";
+ status = "okay";
+ #include "openbmc-flash-layout-128.dtsi"
+ };
+
+ flash@1 {
+ compatible = "jedec,spi-nor";
+ label = "alt-bmc";
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ status = "okay";
+ };
+};
+
+&gfx {
+ memory-region = <&gfx_memory>;
+ status = "okay";
+};
+
+&gpio0 {
+ gpio-line-names =
+ /*A0-A7*/ "","","","","","","","",
+ /*B0-B7*/ "ASSERT_BMC_READY","","","","","","","",
+ /*C0-C7*/ "MON_PWR_GOOD","","","","","","","FP_ID_LED_N",
+ /*D0-D7*/ "","","","","","","","",
+ /*E0-E7*/ "","","","","","","","",
+ /*F0-F7*/ "","","","","","","","",
+ /*G0-G7*/ "","","FP_LED_STATUS_GREEN_N","FP_LED_STATUS_AMBER_N",
+ "","","","",
+ /*H0-H7*/ "","","","","","","","",
+ /*I0-I7*/ "","","","","","","","",
+ /*J0-J7*/ "","","","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "","","","","","","","",
+ /*M0-M7*/ "","","","","","","","",
+ /*N0-N7*/ "","","","","","","","",
+ /*O0-O7*/ "","","","","","","","",
+ /*P0-P7*/ "MON_PWR_BTN_L","ASSERT_PWR_BTN_L","MON_RST_BTN_L",
+ "ASSERT_RST_BTN_L","","ASSERT_NMI_BTN_L","","",
+ /*Q0-Q7*/ "","","MEMORY_HOT_0","MEMORY_HOT_1","","","","",
+ /*R0-R7*/ "ID_BTN","","","","","VBAT_GPIO","","",
+ /*S0-S7*/ "","","RST_PCA_MUX","","","","","",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","","","","","","",
+ /*V0-V7*/ "","","","","","","","",
+ /*W0-W7*/ "","","","","","","","",
+ /*X0-X7*/ "","","","","","","","",
+ /*Y0-Y7*/ "","","","","","","","",
+ /*Z0-Z7*/ "","","","","","","","";
+};
+
+&gpio1 {
+ gpio-line-names =
+ /*18A0-18A7*/ "","","","","","","","",
+ /*18B0-18B7*/ "","","","","","","","",
+ /*18C0-18C7*/ "","","","","","","","",
+ /*18D0-18D7*/ "","","","","","","","",
+ /*18E0-18E3*/ "","","BMC_INIT_DONE","";
+};
+
+// Devices on these busses are available after POST
+// however there isn't a great way to defer probing
+// until that point today, as the BMC doesn't
+// have direct control over when the host completes
+// POST, especially from the kernel.
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "atmel,24c256";
+ reg = <0x51>;
+ pagesize = <64>;
+ label = "sku";
+ };
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&i2c8 {
+ status = "okay";
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+&i2c13 {
+ status = "okay";
+};
+
+&i2c15 {
+ status = "okay";
+};
+
+&kcs1 {
+ aspeed,lpc-io-reg = <0xca0>;
+ status = "okay";
+};
+
+&kcs2 {
+ aspeed,lpc-io-reg = <0xca8>;
+ status = "okay";
+};
+
+&kcs3 {
+ aspeed,lpc-io-reg = <0xca2>;
+ status = "okay";
+};
+
+&lpc_reset {
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sgpiom0 {
+ ngpios = <80>;
+ status = "okay";
+};
+
+&uart_routing {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&video {
+ memory-region = <&video_engine_memory>;
+ status = "okay";
+};
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
- clocks = <&syscon ASPEED_CLK_HPLL>;
arm,cpu-registers-not-fw-configured;
always-on;
};
edac: sdram@1e6e0000 {
- compatible = "aspeed,ast2600-sdram-edac", "syscon";
+ compatible = "aspeed,ast2600-sdram-edac";
reg = <0x1e6e0000 0x174>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
interrupt-controller;
status = "disabled";
};
-
- udma: dma-controller@1e79e000 {
- compatible = "aspeed,ast2600-udma";
- reg = <0x1e79e000 0x1000>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
- dma-channels = <28>;
- #dma-cells = <1>;
- status = "disabled";
- };
};
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
#size-cells = <0>;
eeprom@0 {
- at25,byte-len = <0x80000>;
- at25,addr-mode = <4>;
- at25,page-size = <256>;
-
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
+
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
};
};
};
* The firmware will find whether the emmc2bus alias is defined, and if
* so, it'll edit the dma-ranges property below accordingly.
*/
- emmc2bus: emmc2bus {
+ emmc2bus: emmc2-bus@fe000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
};
};
- scb {
+ scb-bus@fc000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
};
};
- base_fpga_region {
+ base_fpga_region: fpga-region {
compatible = "fpga-region";
fpga-mgr = <&fpgamgr0>;
#address-cells = <0x1>;
#size-cells = <0x1>;
+ ranges;
};
can0: can@ffc00000 {
ocram: sram@ffff0000 {
compatible = "mmio-sram";
reg = <0xffff0000 0x10000>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ ranges;
};
qspi: spi@ff705000 {
};
};
- base_fpga_region {
+ base_fpga_region: fpga-region {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "fpga-region";
fpga-mgr = <&fpga_mgr>;
+ ranges;
};
clkmgr@ffd04000 {
ocram: sram@ffe00000 {
compatible = "mmio-sram";
reg = <0xffe00000 0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
};
eccmgr: eccmgr {
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * lan966x-pcb8385.dts - Device Tree file for PCB8385
+ */
+/dts-v1/;
+
+#include "lan966x.dtsi"
+#include "dt-bindings/phy/phy-lan966x-serdes.h"
+
+/ {
+ model = "Microchip EVB - LAN9668";
+ compatible = "microchip,lan9668-pcb8385", "microchip,lan9668", "microchip,lan966";
+
+ aliases {
+ serial0 = &usart3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 59 GPIO_ACTIVE_LOW>;
+ open-source;
+ priority = <200>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-p1-green {
+ label = "cu0:green";
+ gpios = <&sgpio_out 2 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-p1-yellow {
+ label = "cu0:yellow";
+ gpios = <&sgpio_out 2 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-p2-green {
+ label = "cu1:green";
+ gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-p2-yellow {
+ label = "cu1:yellow";
+ gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+};
+
+&aes {
+ status = "reserved"; /* Reserved by secure OS */
+};
+
+&flx0 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "okay";
+};
+
+&flx3 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+ status = "okay";
+};
+
+&gpio {
+ fc0_b_pins: fc0-b-pins {
+ /* SCL, SDA */
+ pins = "GPIO_25", "GPIO_26";
+ function = "fc0_b";
+ };
+
+ fc3_b_pins: fc3-b-pins {
+ /* RX, TX */
+ pins = "GPIO_52", "GPIO_53";
+ function = "fc3_b";
+ };
+
+ sgpio_a_pins: sgpio-a-pins {
+ /* SCK, D0, D1, LD */
+ pins = "GPIO_32", "GPIO_33", "GPIO_34", "GPIO_35";
+ function = "sgpio_a";
+ };
+};
+
+&i2c0 {
+ pinctrl-0 = <&fc0_b_pins>;
+ pinctrl-names = "default";
+ dmas = <0>, <0>;
+ i2c-analog-filter;
+ i2c-digital-filter;
+ i2c-digital-filter-width-ns = <35>;
+ i2c-sda-hold-time-ns = <1500>;
+ status = "okay";
+
+ eeprom@54 {
+ compatible = "atmel,24c01";
+ reg = <0x54>;
+ };
+
+ eeprom@55 {
+ compatible = "atmel,24c01";
+ reg = <0x55>;
+ };
+};
+
+&sgpio {
+ pinctrl-0 = <&sgpio_a_pins>;
+ pinctrl-names = "default";
+ microchip,sgpio-port-ranges = <0 3>;
+ status = "okay";
+
+ gpio@0 {
+ ngpios = <64>;
+ };
+ gpio@1 {
+ ngpios = <64>;
+ };
+};
+
+&usart3 {
+ pinctrl-0 = <&fc3_b_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
interrupt-controller;
#gpio-cells = <2>;
gpio-controller;
- #gpio-lines = <26>;
+ #gpio-lines = <27>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
dma-names = "tx", "rx";
atmel,use-dma-rx;
atmel,use-dma-tx;
+ atmel,fifo-size = <32>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
status = "disabled";
};
+ spi0: spi@400 {
+ compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
+ clock-names = "spi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>,
+ <&dma1 AT91_XDMAC_DT_PERID(5)>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
i2c0: i2c@600 {
compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
#size-cells = <1>;
status = "disabled";
+ uart1: serial@200 {
+ compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 35>;
+ clock-names = "usart";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>,
+ <&dma0 AT91_XDMAC_DT_PERID(7)>;
+ dma-names = "tx", "rx";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ atmel,fifo-size = <32>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+ status = "disabled";
+ };
+
spi1: spi@400 {
compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi";
reg = <0x400 0x200>;
dma-names = "tx", "rx";
atmel,use-dma-rx;
atmel,use-dma-tx;
+ atmel,fifo-size = <32>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
status = "disabled";
};
+
+ spi2: spi@400 {
+ compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 36>;
+ clock-names = "spi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dma1 AT91_XDMAC_DT_PERID(10)>,
+ <&dma1 AT91_XDMAC_DT_PERID(9)>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@600 {
+ compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 36>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dma1 AT91_XDMAC_DT_PERID(10)>,
+ <&dma1 AT91_XDMAC_DT_PERID(9)>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
};
flx3: flexcom@e182c000 {
dma-names = "tx", "rx";
atmel,use-dma-rx;
atmel,use-dma-tx;
+ atmel,fifo-size = <32>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
status = "disabled";
};
+ spi3: spi@400 {
+ compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
+ clock-names = "spi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>,
+ <&dma0 AT91_XDMAC_DT_PERID(11)>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
i2c3: i2c@600 {
compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
atmel,fifo-size = <32>;
status = "disabled";
};
+
+ i2c4: i2c@600 {
+ compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>,
+ <&dma1 AT91_XDMAC_DT_PERID(13)>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
};
flx5: flexcom@e201c000 {
#size-cells = <1>;
status = "disabled";
+ uart5: serial@200 {
+ compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
+ clock-names = "usart";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(16)>,
+ <&dma0 AT91_XDMAC_DT_PERID(15)>;
+ dma-names = "tx", "rx";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ atmel,fifo-size = <32>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+ status = "disabled";
+ };
+
+ spi5: spi@400 {
+ compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
+ clock-names = "spi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(16)>,
+ <&dma0 AT91_XDMAC_DT_PERID(15)>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
i2c5: i2c@600 {
compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
clock-names = "usart";
+ dmas = <&dma1 AT91_XDMAC_DT_PERID(18)>,
+ <&dma1 AT91_XDMAC_DT_PERID(17)>;
+ dma-names = "tx", "rx";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
atmel,fifo-size = <32>;
status = "disabled";
};
+
+ spi6: spi@400 {
+ compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
+ clock-names = "spi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dma1 AT91_XDMAC_DT_PERID(18)>,
+ <&dma1 AT91_XDMAC_DT_PERID(17)>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@600 {
+ compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dma1 AT91_XDMAC_DT_PERID(18)>,
+ <&dma1 AT91_XDMAC_DT_PERID(17)>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
};
flx7: flexcom@e2024000 {
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
status = "disabled";
};
+
+ spi7: spi@400 {
+ compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
+ clock-names = "spi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>,
+ <&dma1 AT91_XDMAC_DT_PERID(19)>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@600 {
+ compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>,
+ <&dma1 AT91_XDMAC_DT_PERID(19)>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
};
flx8: flexcom@e281c000 {
#size-cells = <1>;
status = "disabled";
+ uart8: serial@200 {
+ compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
+ clock-names = "usart";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>,
+ <&dma0 AT91_XDMAC_DT_PERID(21)>;
+ dma-names = "tx", "rx";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ atmel,fifo-size = <32>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+ status = "disabled";
+ };
+
+ spi8: spi@400 {
+ compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
+ clock-names = "spi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>,
+ <&dma0 AT91_XDMAC_DT_PERID(21)>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
i2c8: i2c@600 {
compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
#size-cells = <1>;
status = "disabled";
+ uart9: serial@200 {
+ compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
+ clock-names = "usart";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>,
+ <&dma0 AT91_XDMAC_DT_PERID(23)>;
+ dma-names = "tx", "rx";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ atmel,fifo-size = <32>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+ status = "disabled";
+ };
+
+ spi9: spi@400 {
+ compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
+ clock-names = "spi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>,
+ <&dma0 AT91_XDMAC_DT_PERID(23)>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
i2c9: i2c@600 {
compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
#size-cells = <1>;
status = "disabled";
+ uart10: serial@200 {
+ compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
+ clock-names = "usart";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(26)>,
+ <&dma0 AT91_XDMAC_DT_PERID(25)>;
+ dma-names = "tx", "rx";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ atmel,fifo-size = <32>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+ status = "disabled";
+ };
+
+ spi10: spi@400 {
+ compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
+ clock-names = "spi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(26)>,
+ <&dma0 AT91_XDMAC_DT_PERID(25)>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
i2c10: i2c@600 {
compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * calao-dab-mmx.dtsi - Device Tree Include file for Calao DAB-MMX Daughter Board
- *
- * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- */
-
-/ {
- ahb {
- apb {
- usart1: serial@fffb4000 {
- status = "okay";
- };
-
- usart3: serial@fffd0000 {
- status = "okay";
- };
- };
- };
-
- i2c-gpio@0 {
- status = "okay";
- };
-
- leds {
- compatible = "gpio-leds";
-
- user_led1 {
- label = "user_led1";
- gpios = <&pioB 20 GPIO_ACTIVE_LOW>;
- };
-
-/*
-* led already used by mother board but active as high
-* user_led2 {
-* label = "user_led2";
-* gpios = <&pioB 21 GPIO_ACTIVE_LOW>;
-* };
-*/
- user_led3 {
- label = "user_led3";
- gpios = <&pioB 22 GPIO_ACTIVE_LOW>;
- };
-
- user_led4 {
- label = "user_led4";
- gpios = <&pioB 23 GPIO_ACTIVE_LOW>;
- };
-
- red {
- label = "red";
- gpios = <&pioB 24 GPIO_ACTIVE_LOW>;
- };
-
- orange {
- label = "orange";
- gpios = <&pioB 30 GPIO_ACTIVE_LOW>;
- };
-
- green {
- label = "green";
- gpios = <&pioB 31 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio_keys {
- compatible = "gpio-keys";
-
- button-user-pb1 {
- label = "user_pb1";
- gpios = <&pioB 25 GPIO_ACTIVE_LOW>;
- linux,code = <0x100>;
- };
-
- button-user-pb2 {
- label = "user_pb2";
- gpios = <&pioB 13 GPIO_ACTIVE_LOW>;
- linux,code = <0x101>;
- };
-
- button-user-pb3 {
- label = "user_pb3";
- gpios = <&pioA 26 GPIO_ACTIVE_LOW>;
- linux,code = <0x102>;
- };
-
- button-user-pb4 {
- label = "user_pb4";
- gpios = <&pioC 9 GPIO_ACTIVE_LOW>;
- linux,code = <0x103>;
- };
- };
-};
status = "disabled";
reg = <0xf0842000 0x200>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk NPCM7XX_CLK_AHB>;
+ clocks = <&clk NPCM7XX_CLK_AHB>;
clock-names = "clk_mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc8_pins
status = "disabled";
reg = <0xf0840000 0x200>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk NPCM7XX_CLK_AHB>;
+ clocks = <&clk NPCM7XX_CLK_AHB>;
clock-names = "clk_sdhc";
pinctrl-names = "default";
pinctrl-0 = <&sd1_pins>;
reset-names = "dsi";
power-domains = <&pd_core>;
operating-points-v2 = <&dsi_dvfs_opp_table>;
+ nvidia,mipi-calibrate = <&csi 3>; /* DSI pad */
status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
};
};
reset-names = "dsi";
power-domains = <&pd_core>;
operating-points-v2 = <&dsia_dvfs_opp_table>;
+ nvidia,mipi-calibrate = <&csi 3>; /* DSIA pad */
status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
};
dsi@54400000 {
reset-names = "dsi";
power-domains = <&pd_core>;
operating-points-v2 = <&dsib_dvfs_opp_table>;
+ nvidia,mipi-calibrate = <&csi 4>; /* DSIB pad */
status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
};
};
stdout-path = &uart1;
};
+ epd_pmic_supply: regulator-epd-pmic-in {
+ compatible = "regulator-fixed";
+ regulator-name = "epd_pmic_supply";
+ gpio = <&gpio2 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <20000>;
+ };
+
gpio_keys: gpio-keys {
compatible = "gpio-keys";
vdd-supply = <&ldo5_reg>;
};
- /* TODO: TPS65185 PMIC for E Ink at 0x68 */
+ tps65185: pmic@68 {
+ compatible = "ti,tps65185";
+ reg = <0x68>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+ vin-supply = <&epd_pmic_supply>;
+ pwr-good-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+ vcom-ctrl-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
+
+ regulators {
+ vcom_reg: vcom {
+ regulator-name = "vcom";
+ };
+
+ vposneg_reg: vposneg {
+ regulator-name = "vposneg";
+ regulator-min-microvolt = <15000000>;
+ regulator-max-microvolt = <15000000>;
+ };
+ v3p3_reg: v3p3 {
+ regulator-name = "v3p3";
+ };
+ };
+ };
};
&i2c3 {
};
};
+ epd_pmic_supply: regulator-epd-pmic-in {
+ compatible = "regulator-fixed";
+ regulator-name = "epd_pmic_supply";
+ gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <20000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_epd_pmic_supply>;
+ };
+
sd2_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
- /* TODO: TPS65185 PMIC for E Ink at 0x68 */
+ pmic@68 {
+ compatible = "ti,tps65185";
+ reg = <0x68>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_epd_pmic>;
+ pwr-good-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
+ vcom-ctrl-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>;
+ wakeup-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&epd_pmic_supply>;
+ interrupts-extended = <&gpio4 15 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ vcom {
+ regulator-name = "vcom";
+ };
+
+ vposneg {
+ regulator-name = "vposneg";
+ regulator-min-microvolt = <15000000>;
+ regulator-max-microvolt = <15000000>;
+ };
+
+ v3p3 {
+ regulator-name = "v3p3";
+ };
+ };
+ };
};
&i2c3 {
>;
};
+ pinctrl_epd_pmic: epd-pmic-grp {
+ fsl,pins = <
+ /* PWRUP */
+ MX50_PAD_EPDC_PWRCTRL1__GPIO3_30 0x0
+ /* WAKEUP */
+ MX50_PAD_EPDC_PWRCTRL0__GPIO3_29 0x0
+ /* VCOMCTRL */
+ MX50_PAD_EPDC_VCOM0__GPIO4_21 0x0
+ /* PWRGOOD: enable internal 100k pull-up */
+ MX50_PAD_EPDC_PWRSTAT__GPIO3_28 0xe0
+ /* INT: enable internal 100k pull-up */
+ MX50_PAD_ECSPI1_SS0__GPIO4_15 0xe0
+ >;
+ };
+
+ pinctrl_epd_pmic_supply: epd-pmic-supply-grp {
+ fsl,pins = <
+ MX50_PAD_EIM_CRE__GPIO1_27 0x0
+ >;
+ };
+
pinctrl_gpiokeys: gpiokeysgrp {
fsl,pins = <
MX50_PAD_CSPI_MISO__GPIO4_10 0x0
compatible = "fsl,imx6q-gpmi-nand";
reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
reg-names = "gpmi-nand", "bch";
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "bch";
clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
gpc: gpc@20dc000 {
compatible = "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
+ #address-cells = <0>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
stdout-path = &uart1;
};
+ epd_pmic_supply: regulator-epd-pmic-in {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_epd_pmic_supply>;
+ regulator-name = "epd_pmic_supply";
+ gpio = <&gpio2 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <20000>;
+ };
+
gpio_keys: gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
touchscreen-inverted-x;
};
- /* TODO: TPS65185 PMIC for E Ink at 0x68 */
+ tps65185: pmic@68 {
+ compatible = "ti,tps65185";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tps65185_gpio>;
+ reg = <0x68>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+ vin-supply = <&epd_pmic_supply>;
+ pwr-good-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+ vcom-ctrl-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
+
+ regulators {
+ vcom_reg: vcom {
+ regulator-name = "vcom";
+ };
+
+ vposneg_reg: vposneg {
+ regulator-name = "vposneg";
+ regulator-min-microvolt = <15000000>;
+ regulator-max-microvolt = <15000000>;
+ };
+ v3p3_reg: v3p3 {
+ regulator-name = "v3p3";
+ };
+ };
+ };
};
&i2c3 {
>;
};
+ pinctrl_epd_pmic_supply: epdc-pmic-supplygrp {
+ fsl,pins = <
+ MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14 0x40010059 /* pwrall */
+ >;
+ };
+
pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059
>;
};
+ pinctrl_tps65185_gpio: tps65185-gpio-grp {
+ fsl,pins = <
+ MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03 0x40010059 /* vcom_ctrl */
+ MX6SL_PAD_EPDC_PWRCTRL0__GPIO2_IO07 0x40010059 /* wakeup */
+ MX6SL_PAD_EPDC_PWRCTRL1__GPIO2_IO08 0x40010059 /* enable */
+ MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x17059 /* nINT */
+ MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13 0x17059 /* pwr-good */
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
compatible = "kobo,tolino-shine3", "fsl,imx6sl";
};
+&epd_pmic_supply {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_epd_pmic_supply>;
+};
+
&gpio_keys {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
>;
};
+ pinctrl_epd_pmic_supply: epdc-pmic-supplygrp {
+ fsl,pins = <
+ MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14 0x40010059
+ >;
+ };
+
pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 /* PWR_SW */
>;
};
+ pinctrl_tps65185_gpio: tps65185-gpio-grp {
+ fsl,pins = <
+ MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03 0x40010059 /* vcom_ctrl */
+ MX6SL_PAD_EPDC_PWRCTRL0__GPIO2_IO07 0x40010059 /* wakeup */
+ MX6SL_PAD_EPDC_PWRCTRL1__GPIO2_IO08 0x40010059 /* enable */
+ MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x17059 /* nINT */
+ MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13 0x17059 /* pwr-good */
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
pinctrl-0 = <&pinctrl_ricoh_gpio>;
};
+&tps65185 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tps65185_gpio>;
+};
+
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
};
lcdif: lcdif@20f8000 {
- compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
+ compatible = "fsl,imx6sl-lcdif", "fsl,imx6sx-lcdif";
reg = <0x020f8000 0x4000>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
/ {
model = "Kobo Clara 2E";
compatible = "kobo,clara2e-b", "kobo,clara2e", "fsl,imx6sll";
+
+ epd_pmic_supply: regulator-epd-pmic-in {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_epd_pmic_supply>;
+ regulator-name = "epd_pmic_supply";
+ gpio = <&gpio2 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <20000>;
+ };
};
&i2c2 {
- /* EPD PMIC JD9930 at 0x18 */
+ jd9930: pmic@18 {
+ compatible = "fitipower,jd9930", "fitipower,fp9931";
+ reg = <0x18>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_jd9930_gpio>;
+ vin-supply = <&epd_pmic_supply>;
+ pg-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+ en-ts-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
+ fitipower,tdly-ms = <2 2 2 2>;
+
+ regulators {
+ vcom_reg: vcom {
+ regulator-name = "vcom";
+ /*
+ * For optimal performance these should be
+ * tuned on a per batch basis e.g. using
+ * overlays.
+ */
+ regulator-min-microvolt = <2352840>;
+ regulator-max-microvolt = <2352840>;
+ };
+
+ vposneg_reg: vposneg {
+ regulator-name = "vposneg";
+ regulator-min-microvolt = <15060000>;
+ regulator-max-microvolt = <15060000>;
+ };
+
+ v3p3_reg: v3p3 {
+ regulator-name = "v3p3";
+ };
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl_jd9930_gpio: jd9930-gpiogrp {
+ fsl,pins = <
+ MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x17059 /* PG */
+ MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 0x40010059 /* EN */
+ MX6SLL_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 0x40010059 /* EN_TS */
+ >;
+ };
+
+ pinctrl_epd_pmic_supply: epd-pmic-supplygrp {
+ fsl,pins = <
+ MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x40010059
+ >;
+ };
};
soc-supply = <&dcdc1_reg>;
};
+&epd_pmic_supply {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_epd_pmic_supply>;
+};
+
&gpio_keys {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
>;
};
+ pinctrl_epd_pmic_supply: epdc-pmic-supplygrp {
+ fsl,pins = <
+ MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x40010059
+ >;
+ };
+
pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x17059 /* PWR_SW */
>;
};
+ pinctrl_tps65185_gpio: tps65185-gpio-grp {
+ fsl,pins = <
+ MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x40010059 /* vcom_ctrl */
+ MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x40010059 /* wakeup */
+ MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 0x40010059 /* enable */
+ MX6SLL_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 0x17059 /* nINT */
+ MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x17059 /* pwr-good */
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
pinctrl-0 = <&pinctrl_ricoh_gpio>;
};
+&tps65185 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tps65185_gpio>;
+};
+
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
};
lcdif: lcd-controller@20f8000 {
- compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif";
+ compatible = "fsl,imx6sll-lcdif", "fsl,imx6sx-lcdif";
reg = <0x020f8000 0x4000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>,
gpmi: nand-controller@1806000 {
compatible = "fsl,imx6sx-gpmi-nand";
#address-cells = <1>;
- #size-cells = <1>;
+ #size-cells = <0>;
reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
reg-names = "gpmi-nand", "bch";
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
gpios = <&gpio 4 1 0>; /* GPI_P3 1 */
};
- key1 {
+ key-1 {
label = "KEY1";
linux,code = <1>;
gpios = <&pca9532 0 0>;
};
- key2 {
+ key-2 {
label = "KEY2";
linux,code = <2>;
gpios = <&pca9532 1 0>;
};
- key3 {
+ key-3 {
label = "KEY3";
linux,code = <3>;
gpios = <&pca9532 2 0>;
};
- key4 {
+ key-4 {
label = "KEY4";
linux,code = <4>;
gpios = <&pca9532 3 0>;
};
- joy0 {
+ key-joy0 {
label = "Joystick Key 0";
linux,code = <10>;
gpios = <&gpio 2 0 0>; /* P2.0 */
};
- joy1 {
+ key-joy1 {
label = "Joystick Key 1";
linux,code = <11>;
gpios = <&gpio 2 1 0>; /* P2.1 */
};
- joy2 {
+ key-joy2 {
label = "Joystick Key 2";
linux,code = <12>;
gpios = <&gpio 2 2 0>; /* P2.2 */
};
- joy3 {
+ key-joy3 {
label = "Joystick Key 3";
linux,code = <13>;
gpios = <&gpio 2 3 0>; /* P2.3 */
};
- joy4 {
+ key-joy4 {
label = "Joystick Key 4";
linux,code = <14>;
gpios = <&gpio 2 4 0>; /* P2.4 */
cs-gpios = <&gpio 3 5 0>;
status = "okay";
- eeprom: at25@0 {
+ eeprom: eeprom@0 {
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <5000000>;
pl022,wait-state = <0>;
pl022,duplex = <0>;
- at25,byte-len = <0x8000>;
- at25,addr-mode = <2>;
- at25,page-size = <64>;
+ size = <0x8000>;
+ address-width = <16>;
+ pagesize = <64>;
};
};
/*
* Enable either SLC or MLC
*/
- slc: flash@20020000 {
+ slc: nand-controller@20020000 {
compatible = "nxp,lpc3220-slc";
reg = <0x20020000 0x1000>;
+ interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LPC32XX_CLK_SLC>;
+ dmas = <&dma 1 1>;
+ dma-names = "rx-tx";
status = "disabled";
};
- mlc: flash@200a8000 {
+ mlc: nand-controller@200a8000 {
compatible = "nxp,lpc3220-mlc";
reg = <0x200a8000 0x11000>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LPC32XX_CLK_MLC>;
+ dmas = <&dma 12 1>;
+ dma-names = "rx-tx";
status = "disabled";
};
interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LPC32XX_CLK_DMA>;
clock-names = "apb_pclk";
+ dma-channels = <8>;
+ dma-requests = <16>;
+ lli-bus-interface-ahb1;
+ lli-bus-interface-ahb2;
+ mem-bus-interface-ahb1;
+ mem-bus-interface-ahb2;
+ memcpy-burst-size = <256>;
+ memcpy-bus-width = <32>;
#dma-cells = <2>;
};
- usb {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges = <0x0 0x31020000 0x00001000>;
-
- /*
- * Enable either ohci or usbd (gadget)!
- */
- ohci: usb@0 {
- compatible = "nxp,ohci-nxp", "usb-ohci";
- reg = <0x0 0x300>;
- interrupt-parent = <&sic1>;
- interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
- status = "disabled";
- };
+ /*
+ * Enable either ohci or usbd (gadget)!
+ */
+ ohci: usb@31020000 {
+ compatible = "nxp,ohci-nxp", "usb-ohci";
+ reg = <0x31020000 0x300>;
+ interrupt-parent = <&sic1>;
+ interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
+ status = "disabled";
+ };
- usbd: usbd@0 {
- compatible = "nxp,lpc3220-udc";
- reg = <0x0 0x300>;
- interrupt-parent = <&sic1>;
- interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
- <30 IRQ_TYPE_LEVEL_HIGH>,
- <28 IRQ_TYPE_LEVEL_HIGH>,
- <26 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
- status = "disabled";
- };
+ usbd: usbd@31020000 {
+ compatible = "nxp,lpc3220-udc";
+ reg = <0x31020000 0x300>;
+ interrupt-parent = <&sic1>;
+ interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
+ <30 IRQ_TYPE_LEVEL_HIGH>,
+ <28 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
+ status = "disabled";
+ };
- i2cusb: i2c@300 {
- compatible = "nxp,pnx-i2c";
- reg = <0x300 0x100>;
- interrupt-parent = <&sic1>;
- interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
+ i2cusb: i2c@31020300 {
+ compatible = "nxp,pnx-i2c";
+ reg = <0x31020300 0x100>;
+ interrupt-parent = <&sic1>;
+ interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
- usbclk: clock-controller@f00 {
- compatible = "nxp,lpc3220-usb-clk";
- reg = <0xf00 0x100>;
- #clock-cells = <1>;
- };
+ usbclk: clock-controller@31020f00 {
+ compatible = "nxp,lpc3220-usb-clk";
+ reg = <0x31020f00 0x100>;
+ #clock-cells = <1>;
};
clcd: clcd@31040000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x20084000 0x1000>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk LPC32XX_CLK_SSP0>;
- clock-names = "apb_pclk";
+ clocks = <&clk LPC32XX_CLK_SSP0>, <&clk LPC32XX_CLK_SSP0>;
+ clock-names = "sspclk", "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
compatible = "nxp,lpc3220-spi";
reg = <0x20088000 0x1000>;
clocks = <&clk LPC32XX_CLK_SPI1>;
+ dmas = <&dmamux 11 1 0>;
+ dma-names = "rx-tx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
compatible = "arm,pl022", "arm,primecell";
reg = <0x2008c000 0x1000>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk LPC32XX_CLK_SSP1>;
- clock-names = "apb_pclk";
+ clocks = <&clk LPC32XX_CLK_SSP1>, <&clk LPC32XX_CLK_SSP1>;
+ clock-names = "sspclk", "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
compatible = "nxp,lpc3220-spi";
reg = <0x20090000 0x1000>;
clocks = <&clk LPC32XX_CLK_SPI2>;
+ dmas = <&dmamux 3 1 0>;
+ dma-names = "rx-tx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
i2s0: i2s@20094000 {
compatible = "nxp,lpc3220-i2s";
reg = <0x20094000 0x1000>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LPC32XX_CLK_I2S0>;
+ dmas = <&dma 0 1>, <&dma 13 1>;
+ dma-names = "rx", "tx";
+ #sound-dai-cells = <0>;
status = "disabled";
};
i2s1: i2s@2009c000 {
compatible = "nxp,lpc3220-i2s";
reg = <0x2009c000 0x1000>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LPC32XX_CLK_I2S1>;
+ dmas = <&dma 2 1>, <&dmamux 10 1 1>;
+ dma-names = "rx", "tx";
+ #sound-dai-cells = <0>;
status = "disabled";
};
mpwm: pwm@400e8000 {
compatible = "nxp,lpc3220-motor-pwm";
reg = <0x400e8000 0x78>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk LPC32XX_CLK_MCPWM>;
#pwm-cells = <3>;
status = "disabled";
};
ranges = <0x20000000 0x20000000 0x30000000>;
/* System Control Block */
- scb {
- compatible = "simple-bus";
- ranges = <0x0 0x40004000 0x00001000>;
+ syscon@40004000 {
+ compatible = "nxp,lpc3220-scb", "syscon", "simple-mfd";
+ reg = <0x40004000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+ ranges = <0 0x40004000 0x1000>;
clk: clock-controller@0 {
compatible = "nxp,lpc3220-clk";
reg = <0x00 0x114>;
#clock-cells = <1>;
-
clocks = <&xtal_32k>, <&xtal>;
clock-names = "xtal_32k", "xtal";
};
+
+ dmamux: dma-router@78 {
+ compatible = "nxp,lpc3220-dmamux";
+ reg = <0x78 0x8>;
+ dma-masters = <&dma>;
+ #dma-cells = <3>;
+ };
};
mic: interrupt-controller@40008000 {
};
&remoteproc_adsp {
- cx-supply = <&pm8841_s2>;
-
firmware-name = "qcom/apq8074/adsp.mbn";
status = "okay";
};
&remoteproc_mss {
- cx-supply = <&pm8841_s2>;
mss-supply = <&pm8841_s3>;
mx-supply = <&pm8841_s1>;
pll-supply = <&pm8941_l12>;
regulator-max-microvolt = <1050000>;
};
- pm8841_s2: s2 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1050000>;
- };
-
pm8841_s3: s3 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1050000>;
};
-
- pm8841_s4: s4 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1050000>;
- };
};
regulators-1 {
resets = <&gcc GCC_MSS_RESTART>;
reset-names = "mss_restart";
- power-domains = <&rpmpd MSM8226_VDDCX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
power-domain-names = "cx";
qcom,ext-bhs-reg = <&tcsr_regs_1 0x194>;
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
- power-domains = <&rpmpd MSM8226_VDDCX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
power-domain-names = "cx";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
};
};
+&gsbi2 {
+ qcom,mode = <GSBI_PROT_I2C>;
+
+ status = "okay";
+};
+
+&gsbi2_i2c {
+ status = "okay";
+
+ light-sensor@39 {
+ compatible = "amstaos,tmd2772";
+ reg = <0x39>;
+ interrupts-extended = <&pm8921_gpio 6 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <&pm8921_l9>;
+ vddio-supply = <&pm8921_lvs4>;
+
+ /* TODO: Proximity doesn't work */
+ amstaos,proximity-diodes = <0>;
+ led-max-microamp = <100000>;
+
+ pinctrl-0 = <&prox_sensor_int>;
+ pinctrl-names = "default";
+ };
+};
+
&gsbi5 {
qcom,mode = <GSBI_PROT_I2C_UART>;
status = "okay";
bias-disable;
drive-strength = <2>;
};
+
+ nfc_default: nfc-default-state {
+ irq-pins {
+ pins = "gpio106";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ firmware-pins {
+ pins = "gpio92";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
};
&pm8921 {
interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>;
};
+&pm8921_gpio {
+ prox_sensor_int: prox-sensor-int-state {
+ pins = "gpio6";
+ function = "normal";
+ input-enable;
+ bias-disable;
+ };
+
+ nfc_enable: nfc-enable-state {
+ pins = "gpio21";
+ function = "normal";
+ bias-disable;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+ power-source = <PM8921_GPIO_S4>;
+ };
+};
+
&rpm {
regulators {
compatible = "qcom,rpm-pm8921-regulators";
dr_mode = "otg";
status = "okay";
};
+
+&gsbi7 {
+ qcom,mode = <GSBI_PROT_I2C>;
+
+ status = "okay";
+};
+
+&gsbi7_i2c {
+ status = "okay";
+
+ nfc@2b {
+ compatible = "nxp,pn544-i2c";
+ reg = <0x2b>;
+ interrupts-extended = <&tlmm 106 IRQ_TYPE_EDGE_RISING>;
+ enable-gpios = <&pm8921_gpio 21 GPIO_ACTIVE_HIGH>;
+ firmware-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&nfc_default &nfc_enable>;
+ pinctrl-names = "default";
+ };
+};
+
+&gsbi12 {
+ qcom,mode = <GSBI_PROT_I2C>;
+
+ status = "okay";
+};
+
+&gsbi12_i2c {
+ status = "okay";
+
+ accelerometer@18 {
+ compatible = "bosch,bma254";
+ reg = <0x18>;
+ vdd-supply = <&pm8921_l9>;
+ vddio-supply = <&pm8921_lvs4>;
+
+ mount-matrix = "-1", "0", "0",
+ "0", "-1", "0",
+ "0", "0", "1";
+ };
+
+ magnetometer@2e {
+ compatible = "yamaha,yas532";
+ reg = <0x2e>;
+ vdd-supply = <&pm8921_l9>;
+ iovdd-supply = <&pm8921_lvs4>;
+
+ /* TODO: Figure out Mount Matrix */
+ };
+};
};
};
+ i2c2_default_state: i2c2-default-state {
+ i2c2-pins {
+ pins = "gpio12", "gpio13";
+ function = "gsbi2";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ i2c2_sleep_state: i2c2-sleep-state {
+ i2c2-pins {
+ pins = "gpio12", "gpio13";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-bus-hold;
+ };
+ };
+
i2c3_default_state: i2c3-default-state {
i2c3-pins {
pins = "gpio16", "gpio17";
};
};
+ i2c7_default_state: i2c7-default-state {
+ i2c7-pins {
+ pins = "gpio32", "gpio33";
+ function = "gsbi7";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ i2c7_sleep_state: i2c7-sleep-state {
+ i2c7-pins {
+ pins = "gpio32", "gpio33";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-bus-hold;
+ };
+ };
+
i2c8_default_state: i2c8-default-state {
i2c8-pins {
pins = "gpio36", "gpio37";
};
};
+ gsbi2: gsbi@16100000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ reg = <0x16100000 0x100>;
+ ranges;
+ cell-index = <2>;
+ clocks = <&gcc GSBI2_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ status = "disabled";
+
+ gsbi2_i2c: i2c@16180000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x16180000 0x1000>;
+ pinctrl-0 = <&i2c2_default_state>;
+ pinctrl-1 = <&i2c2_sleep_state>;
+ pinctrl-names = "default", "sleep";
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI2_QUP_CLK>,
+ <&gcc GSBI2_H_CLK>;
+ clock-names = "core",
+ "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
gsbi3: gsbi@16200000 {
compatible = "qcom,gsbi-v1.0.0";
reg = <0x16200000 0x100>;
};
};
+ gsbi7: gsbi@16600000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ reg = <0x16600000 0x100>;
+ ranges;
+ cell-index = <7>;
+ clocks = <&gcc GSBI7_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ status = "disabled";
+
+ gsbi7_i2c: i2c@16680000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x16680000 0x1000>;
+ pinctrl-0 = <&i2c7_default_state>;
+ pinctrl-1 = <&i2c7_sleep_state>;
+ pinctrl-names = "default", "sleep";
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI7_QUP_CLK>,
+ <&gcc GSBI7_H_CLK>;
+ clock-names = "core",
+ "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
gsbi8: gsbi@1a000000 {
compatible = "qcom,gsbi-v1.0.0";
reg = <0x1a000000 0x100>;
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
- model = "LGE MSM 8974 HAMMERHEAD";
+ model = "LG Nexus 5";
compatible = "lge,hammerhead", "qcom,msm8974";
chassis-type = "handset";
};
&remoteproc_adsp {
- cx-supply = <&pm8841_s2>;
status = "okay";
};
&remoteproc_mss {
- cx-supply = <&pm8841_s2>;
mss-supply = <&pm8841_s3>;
mx-supply = <&pm8841_s1>;
pll-supply = <&pm8941_l12>;
regulator-max-microvolt = <1050000>;
};
- pm8841_s2: s2 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1050000>;
- };
-
pm8841_s3: s3 {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
};
-
- pm8841_s4: s4 {
- regulator-min-microvolt = <815000>;
- regulator-max-microvolt = <900000>;
- };
};
regulators-1 {
};
&remoteproc_adsp {
- cx-supply = <&pm8841_s2>;
status = "okay";
};
&remoteproc_mss {
- cx-supply = <&pm8841_s2>;
mss-supply = <&pm8841_s3>;
mx-supply = <&pm8841_s1>;
pll-supply = <&pm8941_l12>;
regulator-max-microvolt = <1050000>;
};
- pm8841_s2: s2 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1050000>;
- };
-
pm8841_s3: s3 {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
};
-
- pm8841_s4: s4 {
- regulator-min-microvolt = <815000>;
- regulator-max-microvolt = <900000>;
- };
};
regulators-1 {
};
&remoteproc_adsp {
- cx-supply = <&pm8841_s2>;
status = "okay";
};
&remoteproc_mss {
- cx-supply = <&pm8841_s2>;
mss-supply = <&pm8841_s3>;
mx-supply = <&pm8841_s1>;
pll-supply = <&pm8941_l12>;
regulator-max-microvolt = <1050000>;
};
- pm8841_s2: s2 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1050000>;
- };
-
pm8841_s3: s3 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1050000>;
};
-
- pm8841_s4: s4 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1050000>;
- };
};
regulators-1 {
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
-#include <dt-bindings/interconnect/qcom,msm8974.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
-#include <dt-bindings/reset/qcom,gcc-msm8974.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,msm8974.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/reset/qcom,gcc-msm8974.h>
/ {
#address-cells = <1>;
clocks = <&xo_board>;
clock-names = "xo";
};
+
+ rpmpd: power-controller {
+ compatible = "qcom,msm8974-rpmpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmpd_opp_table>;
+
+ rpmpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmpd_opp_ret: opp1 {
+ opp-level = <1>;
+ };
+
+ rpmpd_opp_svs_krait: opp2 {
+ opp-level = <2>;
+ };
+
+ rpmpd_opp_svs_soc: opp3 {
+ opp-level = <3>;
+ };
+
+ rpmpd_opp_nom: opp4 {
+ opp-level = <4>;
+ };
+
+ rpmpd_opp_turbo: opp5 {
+ opp-level = <5>;
+ };
+
+ rpmpd_opp_super_turbo: opp6 {
+ opp-level = <6>;
+ };
+ };
+ };
};
};
};
<&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
+ power-domains = <&rpmpd MSM8974_VDDCX>;
+ power-domain-names = "cx";
+
qcom,smem-states = <&wcnss_smp2p_out 0>;
qcom,smem-state-names = "stop";
resets = <&gcc GCC_MSS_RESTART>;
reset-names = "mss_restart";
+ power-domains = <&rpmpd MSM8974_VDDCX>;
+ power-domain-names = "cx";
+
qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>;
qcom,smem-states = <&modem_smp2p_out 0>;
clocks = <&xo_board>;
clock-names = "xo";
+ power-domains = <&rpmpd MSM8974_VDDCX>;
+ power-domain-names = "cx";
+
memory-region = <&adsp_region>;
qcom,smem-states = <&adsp_smp2p_out 0>;
status = "okay";
vddmx-supply = <&pm8841_s1>;
- vddcx-supply = <&pm8841_s2>;
vddpx-supply = <&pm8941_s3>;
pinctrl-names = "default";
&remoteproc_adsp {
status = "okay";
- cx-supply = <&pm8841_s2>;
};
&remoteproc_mss {
status = "okay";
- cx-supply = <&pm8841_s2>;
mss-supply = <&pm8841_s3>;
mx-supply = <&pm8841_s1>;
pll-supply = <&pm8941_l12>;
regulator-max-microvolt = <1050000>;
};
- pm8841_s2: s2 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1050000>;
- };
-
pm8841_s3: s3 {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
&pronto {
vddmx-supply = <&pm8841_s1>;
- vddcx-supply = <&pm8841_s2>;
vddpx-supply = <&pm8941_s3>;
pinctrl-0 = <&wcnss_pin_a>;
regulator-max-microvolt = <1050000>;
};
- pm8841_s2: s2 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1050000>;
- };
-
pm8841_s3: s3 {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
};
-
- pm8841_s4: s4 {
- regulator-min-microvolt = <815000>;
- regulator-max-microvolt = <900000>;
- };
};
regulators-1 {
&pronto {
vddmx-supply = <&pm8841_s1>;
- vddcx-supply = <&pm8841_s2>;
vddpx-supply = <&pm8941_s3>;
pinctrl-names = "default";
};
&remoteproc_adsp {
- cx-supply = <&pm8841_s2>;
-
status = "okay";
};
regulator-max-microvolt = <1050000>;
};
- pm8841_s2: s2 {
- regulator-min-microvolt = <875000>;
- regulator-max-microvolt = <1050000>;
- regulator-always-on;
- };
-
pm8841_s3: s3 {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
&remoteproc_adsp {
status = "okay";
- cx-supply = <&pma8084_s2>;
};
&remoteproc_mss {
status = "okay";
- cx-supply = <&pma8084_s2>;
mss-supply = <&pma8084_s6>;
mx-supply = <&pma8084_s1>;
pll-supply = <&pma8084_l12>;
regulator-always-on;
};
- pma8084_s2: s2 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1050000>;
- };
-
pma8084_s3: s3 {
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
};
};
+&rpmpd {
+ compatible = "qcom,msm8974pro-pma8084-rpmpd";
+};
+
&sdhc_1 {
status = "okay";
};
&remoteproc_adsp {
- cx-supply = <&pm8841_s2>;
status = "okay";
};
&remoteproc_mss {
- cx-supply = <&pm8841_s2>;
mss-supply = <&pm8841_s3>;
mx-supply = <&pm8841_s1>;
pll-supply = <&pm8941_l12>;
regulator-max-microvolt = <1050000>;
};
- pm8841_s2: s2 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1050000>;
- };
-
pm8841_s3: s3 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1050000>;
};
-
- pm8841_s4: s4 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1050000>;
- };
};
regulators-1 {
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the GR-Peach audiocamera shield expansion board
- *
- * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org>
- */
-
-#include "r7s72100.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
-
-/ {
- /* On-board camera clock. */
- camera_clk: camera_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <27000000>;
- };
-};
-
-&pinctrl {
- i2c1_pins: i2c1 {
- /* P1_2 as SCL; P1_3 as SDA */
- pinmux = <RZA1_PINMUX(1, 2, 1)>, <RZA1_PINMUX(1, 3, 1)>;
- };
-
- vio_pins: vio {
- /* CEU pins: VIO_D[0-10], VIO_VD, VIO_HD, VIO_CLK */
- pinmux = <RZA1_PINMUX(1, 0, 5)>, /* VIO_VD */
- <RZA1_PINMUX(1, 1, 5)>, /* VIO_HD */
- <RZA1_PINMUX(2, 0, 7)>, /* VIO_D0 */
- <RZA1_PINMUX(2, 1, 7)>, /* VIO_D1 */
- <RZA1_PINMUX(2, 2, 7)>, /* VIO_D2 */
- <RZA1_PINMUX(2, 3, 7)>, /* VIO_D3 */
- <RZA1_PINMUX(2, 4, 7)>, /* VIO_D4 */
- <RZA1_PINMUX(2, 5, 7)>, /* VIO_D5 */
- <RZA1_PINMUX(2, 6, 7)>, /* VIO_D6 */
- <RZA1_PINMUX(2, 7, 7)>, /* VIO_D7 */
- <RZA1_PINMUX(10, 0, 6)>; /* VIO_CLK */
- };
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
-
- status = "okay";
- clock-frequency = <100000>;
-
- camera@48 {
- compatible = "aptina,mt9v111";
- reg = <0x48>;
-
- clocks = <&camera_clk>;
-
- port {
- mt9v111_out: endpoint {
- remote-endpoint = <&ceu_in>;
- };
- };
- };
-};
-
-&ceu {
- pinctrl-names = "default";
- pinctrl-0 = <&vio_pins>;
-
- status = "okay";
-
- port {
- ceu_in: endpoint {
- remote-endpoint = <&mt9v111_out>;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Common file for the AA121TD01 panel connected to Renesas R-Car boards
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-
-/ {
- panel {
- compatible = "mitsubishi,aa121td01", "panel-lvds";
-
- width-mm = <261>;
- height-mm = <163>;
- data-mapping = "jeida-18";
-
- panel-timing {
- /* 1280x800 @60Hz */
- clock-frequency = <71000000>;
- hactive = <1280>;
- vactive = <800>;
- hsync-len = <70>;
- hfront-porch = <20>;
- hback-porch = <70>;
- vsync-len = <5>;
- vfront-porch = <3>;
- vback-porch = <15>;
- };
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&lvds_connector>;
- };
- };
- };
-};
-
-&lvds_connector {
- remote-endpoint = <&panel_in>;
-};
<&sysctrl R9A06G032_CLK_SWITCH>;
clock-names = "hclk", "clk";
power-domains = <&sysctrl>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dlr", "switch", "prp", "hub", "ptrn";
status = "disabled";
ethernet-ports {
<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ /*
+ * The GPIO mapping to the corresponding pins is not obvious.
+ * See the hardware documentation for details.
+ */
+ gpio0: gpio@5000b000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x5000b000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&sysctrl R9A06G032_HCLK_GPIO0>;
+ clock-names = "bus";
+
+ /* GPIO0a[0] connected to pin GPIO0 */
+ /* GPIO0a[1..2] connected to pins GPIO3..4 */
+ /* GPIO0a[3..4] connected to pins GPIO9..10 */
+ /* GPIO0a[5] connected to pin GPIO12 */
+ /* GPIO0a[6..7] connected to pins GPIO15..16 */
+ /* GPIO0a[8..9] connected to pins GPIO21..22 */
+ /* GPIO0a[10] connected to pin GPIO24 */
+ /* GPIO0a[11..12] connected to pins GPIO27..28 */
+ /* GPIO0a[13..14] connected to pins GPIO33..34 */
+ /* GPIO0a[15] connected to pin GPIO36 */
+ /* GPIO0a[16..17] connected to pins GPIO39..40 */
+ /* GPIO0a[18..19] connected to pins GPIO45..46 */
+ /* GPIO0a[20] connected to pin GPIO48 */
+ /* GPIO0a[21..22] connected to pins GPIO51..52 */
+ /* GPIO0a[23..24] connected to pins GPIO57..58 */
+ /* GPIO0a[25..31] connected to pins GPIO62..68 */
+ gpio0a: gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+
+ interrupt-controller;
+ interrupt-parent = <&gpioirqmux>;
+ interrupts = < 0 1 2 3 4 5 6 7
+ 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23
+ 24 25 26 27 28 29 30 31>;
+ #interrupt-cells = <2>;
+ };
+
+ /* GPIO0b[0..1] connected to pins GPIO1..2 */
+ /* GPIO0b[2..5] connected to pins GPIO5..8 */
+ /* GPIO0b[6] connected to pin GPIO11 */
+ /* GPIO0b[7..8] connected to pins GPIO13..14 */
+ /* GPIO0b[9..12] connected to pins GPIO17..20 */
+ /* GPIO0b[13] connected to pin GPIO23 */
+ /* GPIO0b[14..15] connected to pins GPIO25..26 */
+ /* GPIO0b[16..19] connected to pins GPIO29..32 */
+ /* GPIO0b[20] connected to pin GPIO35 */
+ /* GPIO0b[21..22] connected to pins GPIO37..38 */
+ /* GPIO0b[23..26] connected to pins GPIO41..44 */
+ /* GPIO0b[27] connected to pin GPIO47 */
+ /* GPIO0b[28..29] connected to pins GPIO49..50 */
+ /* GPIO0b[30..31] connected to pins GPIO53..54 */
+ gpio0b: gpio-port@1 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ };
+ };
+
+ gpio1: gpio@5000c000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x5000c000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&sysctrl R9A06G032_HCLK_GPIO1>;
+ clock-names = "bus";
+
+ /* GPIO1a[0..4] connected to pins GPIO69..73 */
+ /* GPIO1a[5..31] connected to pins GPIO95..121 */
+ gpio1a: gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+
+ interrupt-controller;
+ interrupt-parent = <&gpioirqmux>;
+ interrupts = <32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47
+ 48 49 50 51 52 53 54 55
+ 56 57 58 59 60 61 62 63>;
+ #interrupt-cells = <2>;
+ };
+
+ /* GPIO1b[0..1] connected to pins GPIO55..56 */
+ /* GPIO1b[2..4] connected to pins GPIO59..61 */
+ /* GPIO1b[5..25] connected to pins GPIO74..94 */
+ /* GPIO1b[26..31] connected to pins GPIO150..155 */
+ gpio1b: gpio-port@1 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ };
+ };
+
+ gpio2: gpio@5000d000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x5000d000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&sysctrl R9A06G032_HCLK_GPIO2>;
+ clock-names = "bus";
+
+ /* GPIO2a[0..27] connected to pins GPIO122..149 */
+ /* GPIO2a[28..31] connected to pins GPIO156..159 */
+ gpio2a: gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+
+ interrupt-controller;
+ interrupt-parent = <&gpioirqmux>;
+ interrupts = <64 65 66 67 68 69 70 71
+ 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87
+ 88 89 90 91 92 93 94 95>;
+ #interrupt-cells = <2>;
+ };
+
+ /* GPIO2b[0..9] connected to pins GPIO160..169 */
+ gpio2b: gpio-port@1 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <10>;
+ };
+ };
+
+ gpioirqmux: interrupt-controller@51000480 {
+ compatible = "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioirqmux";
+ reg = <0x51000480 0x20>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ interrupt-map-mask = <0x7f>;
+
+ /*
+ * Example mapping entry. Board DTs need to overwrite
+ * 'interrupt-map' with their specific mapping. Check
+ * the irqmux binding documentation for details.
+ */
+ interrupt-map = <0 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+ };
+
can0: can@52104000 {
compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000";
reg = <0x52104000 0x800>;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
- mshc0 = &emmc;
- mshc1 = &sdmmc;
- mshc2 = &sdio;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
power-domains = <&power RK3288_PD_VIDEO>;
};
+ hevc: video-codec@ff9c0000 {
+ compatible = "rockchip,rk3288-vdec";
+ reg = <0x0 0xff9c0000 0x0 0x440>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
+ <&cru SCLK_HEVC_CABAC>, <&cru SCLK_HEVC_CORE>;
+ clock-names = "axi", "ahb", "cabac", "core";
+ assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
+ <&cru SCLK_HEVC_CABAC>, <&cru SCLK_HEVC_CORE>;
+ assigned-clock-rates = <400000000>, <100000000>,
+ <300000000>, <300000000>;
+ iommus = <&hevc_mmu>;
+ power-domains = <&power RK3288_PD_HEVC>;
+ };
+
hevc_mmu: iommu@ff9c0440 {
compatible = "rockchip,iommu";
reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
- status = "disabled";
+ power-domains = <&power RK3288_PD_HEVC>;
};
gpu: gpu@ffa30000 {
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Samsung's S3C6400 SoC device tree source
- *
- * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
- *
- * Samsung's S3C6400 SoC device nodes are listed in this file. S3C6400
- * based board files can include this file and provide values for board specific
- * bindings.
- *
- * Note: This file does not include device nodes for all the controllers in
- * S3C6400 SoC. As device tree coverage for S3C6400 increases, additional
- * nodes can be added to this file.
- */
-
-#include "s3c64xx.dtsi"
-
-/ {
- compatible = "samsung,s3c6400";
-};
-
-&vic0 {
- valid-mask = <0xfffffe1f>;
- valid-wakeup-mask = <0x00200004>;
-};
-
-&vic1 {
- valid-mask = <0xffffffff>;
- valid-wakeup-mask = <0x53020000>;
-};
-
-&soc {
- clocks: clock-controller@7e00f000 {
- compatible = "samsung,s3c6400-clock";
- reg = <0x7e00f000 0x1000>;
- #clock-cells = <1>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * DTS file for SPEAr320s SoC
- *
- * Copyright 2021 Herve Codina <herve.codina@bootlin.com>
- */
-
-/include/ "spear320.dtsi"
-
-/ {
- ahb {
- apb {
- gpiopinctrl: gpio@b3000000 {
- /*
- * The "RM0321 SPEAr320s address and map
- * registers" document mentions interrupt 6
- * (NPGIO_INTR) for the PL_GPIO interrupt.
- */
- interrupts = <6>;
- interrupt-parent = <&shirq>;
- };
- };
- };
-};
/dts-v1/;
#include "stm32f429.dtsi"
#include "stm32f429-pinctrl.dtsi"
-#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/media/video-interfaces.h>
/ {
dma-ranges = <0xc0000000 0x0 0x10000000>;
};
- vdda: regulator-vdda {
- compatible = "regulator-fixed";
- regulator-name = "vdda";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vref: regulator-vref {
- compatible = "regulator-fixed";
- regulator-name = "vref";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vdd_panel: vdd-panel {
- compatible = "regulator-fixed";
- regulator-name = "vdd_panel";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
leds {
compatible = "gpio-leds";
- led-green {
+ led_green: led-green {
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&gpiog 6 1>;
linux,default-trigger = "heartbeat";
};
led-orange {
+ color = <LED_COLOR_ID_ORANGE>;
gpios = <&gpiog 7 1>;
};
led-red {
+ color = <LED_COLOR_ID_RED>;
gpios = <&gpiog 10 1>;
};
led-blue {
+ color = <LED_COLOR_ID_BLUE>;
gpios = <&gpiog 12 1>;
};
};
};
};
- usbotg_hs_phy: usbphy {
- #phy-cells = <0>;
- compatible = "usb-nop-xceiv";
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>;
- clock-names = "main_clk";
+ mmc_vcard: mmc_vcard {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc_vcard";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ boot-led = <&led_green>;
+ };
};
panel_rgb: panel-rgb {
};
};
- mmc_vcard: mmc_vcard {
+ vdda: regulator-vdda {
compatible = "regulator-fixed";
- regulator-name = "mmc_vcard";
+ regulator-name = "vdda";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vref: regulator-vref {
+ compatible = "regulator-fixed";
+ regulator-name = "vref";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ usbotg_hs_phy: usbphy {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>;
+ clock-names = "main_clk";
+ };
+
+ vdd_panel: vdd-panel {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_panel";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
#include "stm32f746-pinctrl.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
/ {
model = "STMicroelectronics STM32746g-EVAL board";
leds {
compatible = "gpio-leds";
- led-green {
+ led_green: led-green {
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&gpiof 10 1>;
linux,default-trigger = "heartbeat";
};
led-orange {
+ color = <LED_COLOR_ID_ORANGE>;
gpios = <&stmfx_pinctrl 17 1>;
};
led-red {
+ color = <LED_COLOR_ID_RED>;
gpios = <&gpiob 7 1>;
};
led-blue {
+ color = <LED_COLOR_ID_BLUE>;
gpios = <&stmfx_pinctrl 19 1>;
};
};
};
};
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ boot-led = <&led_green>;
+ };
+ };
+
usbotg_hs_phy: usb-phy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
/dts-v1/;
#include "stm32f429.dtsi"
#include "stm32f429-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
/ {
model = "STMicroelectronics STM32F429i-DISCO board";
leds {
compatible = "gpio-leds";
led-red {
+ color = <LED_COLOR_ID_RED>;
gpios = <&gpiog 14 0>;
};
- led-green {
+ led_green: led-green {
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&gpiog 13 0>;
linux,default-trigger = "heartbeat";
};
};
};
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ boot-led = <&led_green>;
+ };
+ };
+
/* This turns on vbus for otg for host mode (dwc2) */
vcc5v_otg: vcc5v-otg-regulator {
compatible = "regulator-fixed";
#include "stm32f469-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
/ {
model = "STMicroelectronics STM32F469i-DISCO board";
leds {
compatible = "gpio-leds";
- led-green {
+ led_green: led-green {
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&gpiog 6 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
led-orange {
+ color = <LED_COLOR_ID_ORANGE>;
gpios = <&gpiod 4 GPIO_ACTIVE_LOW>;
};
led-red {
+ color = <LED_COLOR_ID_RED>;
gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
};
led-blue {
+ color = <LED_COLOR_ID_BLUE>;
gpios = <&gpiok 3 GPIO_ACTIVE_LOW>;
};
};
};
};
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ boot-led = <&led_green>;
+ };
+ };
+
/* This turns on vbus for otg for host mode (dwc2) */
vcc5v_otg: vcc5v-otg-regulator {
compatible = "regulator-fixed";
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
/ {
model = "STMicroelectronics STM32F746-DISCO board";
leds {
compatible = "gpio-leds";
- led-usr {
+ led_usr: led-usr {
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&gpioi 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
};
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ boot-led = <&led_usr>;
+ };
+ };
+
usbotg_hs_phy: usb-phy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
#include "stm32f769-pinctrl.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
/ {
model = "STMicroelectronics STM32F769-DISCO board";
leds {
compatible = "gpio-leds";
- led-usr2 {
+ led_usr2: led-usr2 {
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
led-usr1 {
+ color = <LED_COLOR_ID_RED>;
gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>;
};
led-usr3 {
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&gpioa 12 GPIO_ACTIVE_HIGH>;
};
};
};
};
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ boot-led = <&led_usr2>;
+ };
+ };
+
usbotg_hs_phy: usb-phy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
/dts-v1/;
#include "stm32h743.dtsi"
#include "stm32h7-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
/ {
model = "STMicroelectronics STM32H743i-Discovery board";
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
+
+ leds {
+ compatible = "gpio-leds";
+ led_green: led-green {
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioi 12 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-orange {
+ color = <LED_COLOR_ID_ORANGE>;
+ gpios = <&gpioi 13 GPIO_ACTIVE_LOW>;
+ };
+
+ led-red {
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpioi 14 GPIO_ACTIVE_LOW>;
+ };
+
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ boot-led = <&led_green>;
+ };
+ };
};
&clk_hse {
/dts-v1/;
#include "stm32h743.dtsi"
#include "stm32h7-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
/ {
model = "STMicroelectronics STM32H743i-EVAL board";
serial0 = &usart1;
};
+ led {
+ compatible = "gpio-leds";
+ led_green: led-green {
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpiof 10 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ led-red {
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ boot-led = <&led_green>;
+ };
+ };
+
vdda: regulator-vdda {
compatible = "regulator-fixed";
regulator-name = "vdda";
#include "stm32h7-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
/ {
model = "STMicroelectronics STM32H747i-Discovery board";
leds {
compatible = "gpio-leds";
- led-green {
+ led_green: led-green {
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&gpioi 12 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
led-orange {
+ color = <LED_COLOR_ID_ORANGE>;
gpios = <&gpioi 13 GPIO_ACTIVE_LOW>;
};
led-red {
+ color = <LED_COLOR_ID_RED>;
gpios = <&gpioi 14 GPIO_ACTIVE_LOW>;
};
led-blue {
+ color = <LED_COLOR_ID_BLUE>;
gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
};
};
gpios = <&gpiok 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
};
};
+
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ boot-led = <&led_green>;
+ };
+ };
};
&clk_hse {
leds {
compatible = "gpio-leds";
- led-blue {
+ led_blue: led-blue {
function = LED_FUNCTION_HEARTBEAT;
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
+
+ led-red {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ boot-led = <&led_blue>;
+ };
};
panel_backlight: panel-backlight {
led {
compatible = "gpio-leds";
- led-blue {
+ led_blue: led-blue {
gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "off";
function = LED_FUNCTION_HEARTBEAT;
color = <LED_COLOR_ID_BLUE>;
};
+
+ led-red {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ boot-led = <&led_blue>;
+ };
};
sd_switch: regulator-sd_switch {
};
&spi1 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi1_pins_a>;
+ pinctrl-1 = <&spi1_sleep_pins_a>;
status = "disabled";
};
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/mfd/st,stpmic1.h>
/ {
led {
compatible = "gpio-leds";
- led-blue {
- label = "heartbeat";
+ led_blue: led-blue {
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_BLUE>;
gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
+
+ led-red {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ boot-led = <&led_blue>;
+ };
};
sound {
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
- */
-
-&pinctrl {
- st,package = <STM32MP_PKG_AB>;
-
- gpioa: gpio@50002000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@50003000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@50004000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@50005000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@50006000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@50007000 {
- status = "okay";
- ngpios = <6>;
- gpio-ranges = <&pinctrl 6 86 6>;
- };
-
- gpiog: gpio@50008000 {
- status = "okay";
- ngpios = <10>;
- gpio-ranges = <&pinctrl 6 102 10>;
- };
-
- gpioh: gpio@50009000 {
- status = "okay";
- ngpios = <2>;
- gpio-ranges = <&pinctrl 0 112 2>;
- };
-};
linux,default-trigger = "default-on";
gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
default-state = "on";
+ panic-indicator;
};
led_wlan: led-wlan {
label = "onrisc:blue:wlan";
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION
- *
- * Copyright (C) 2013 ISEE 2007 SL - https://www.isee.biz
- */
-
-#include "am335x-igep0033.dtsi"
-
-/ {
- model = "IGEP COM AM335x on AQUILA Expansion";
- compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx";
-
- hdmi {
- compatible = "ti,tilcdc,slave";
- i2c = <&i2c0>;
- pinctrl-names = "default", "off";
- pinctrl-0 = <&nxp_hdmi_pins>;
- pinctrl-1 = <&nxp_hdmi_off_pins>;
- status = "okay";
- };
-
- leds_base {
- pinctrl-names = "default";
- pinctrl-0 = <&leds_base_pins>;
-
- compatible = "gpio-leds";
-
- led0 {
- label = "base:red:user";
- gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; /* gpio1_21 */
- default-state = "off";
- };
-
- led1 {
- label = "base:green:user";
- gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; /* gpio2_0 */
- default-state = "off";
- };
- };
-};
-
-&am33xx_pinmux {
- nxp_hdmi_pins: nxp-hdmi-pins {
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
- >;
- };
- nxp_hdmi_off_pins: nxp-hdmi-off-pins {
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */
- >;
- };
-
- leds_base_pins: leds-base-pins {
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */
- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn3.gpio2_0 */
- >;
- };
-};
-
-&lcdc {
- status = "okay";
-};
-
-&i2c0 {
- eeprom: eeprom@50 {
- compatible = "atmel,24c256";
- reg = <0x50>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2020 André Hentschel <nerv@dawncrow.de>
- */
-
-#include "omap36xx.dtsi"
-
-&iva {
- status = "disabled";
-};
-
-&sgx_module {
- status = "disabled";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2020 André Hentschel <nerv@dawncrow.de>
- */
-
-#include "omap36xx.dtsi"
-
-&iva {
- status = "disabled";
-};
scm_conf1: scm_conf@1c04 {
compatible = "syscon";
reg = <0x1c04 0x0020>;
- #syscon-cells = <2>;
};
scm_conf_pcie: scm_conf@1c24 {
interrupts = <93>;
};
- wd_timer2: wdt@49016000 {
+ wd_timer2: watchdog@49016000 {
compatible = "ti,omap2-wdt";
ti,hwmods = "wd_timer2";
reg = <0x49016000 0x80>;
status = "disabled";
};
- wdt2: wdt@48314000 {
+ wdt2: watchdog@48314000 {
compatible = "ti,omap3-wdt";
reg = <0x48314000 0x80>;
ti,hwmods = "wd_timer2";
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for OMAP3430 ES1 clock data
- *
- * Copyright (C) 2013 Texas Instruments, Inc.
- */
-&cm_clocks {
- gfx_l3_ck: gfx_l3_ck@b10 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&l3_ick>;
- reg = <0x0b10>;
- ti,bit-shift = <0>;
- };
-
- gfx_l3_fck: gfx_l3_fck@b40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&l3_ick>;
- ti,max-div = <7>;
- reg = <0x0b40>;
- ti,index-starts-at-one;
- };
-
- gfx_l3_ick: gfx_l3_ick {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&gfx_l3_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- gfx_cg1_ck: gfx_cg1_ck@b00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&gfx_l3_fck>;
- reg = <0x0b00>;
- ti,bit-shift = <1>;
- };
-
- gfx_cg2_ck: gfx_cg2_ck@b00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&gfx_l3_fck>;
- reg = <0x0b00>;
- ti,bit-shift = <2>;
- };
-
- clock@a00 {
- compatible = "ti,clksel";
- reg = <0xa00>;
- #clock-cells = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- d2d_26m_fck: clock-d2d-26m-fck@3 {
- reg = <3>;
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clock-output-names = "d2d_26m_fck";
- clocks = <&sys_ck>;
- };
-
- fshostusb_fck: clock-fshostusb-fck@5 {
- reg = <5>;
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clock-output-names = "fshostusb_fck";
- clocks = <&core_48m_fck>;
- };
-
- ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1@0 {
- reg = <0>;
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clock-output-names = "ssi_ssr_gate_fck_3430es1";
- clocks = <&corex2_fck>;
- };
- };
-
- clock@a40 {
- compatible = "ti,clksel";
- reg = <0xa40>;
- #clock-cells = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1@8 {
- reg = <8>;
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clock-output-names = "ssi_ssr_div_fck_3430es1";
- clocks = <&corex2_fck>;
- ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
- };
-
- usb_l4_div_ick: clock-usb-l4-div-ick@4 {
- reg = <4>;
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clock-output-names = "usb_l4_div_ick";
- clocks = <&l4_ick>;
- ti,max-div = <1>;
- ti,index-starts-at-one;
- };
- };
-
- ssi_ssr_fck: ssi_ssr_fck_3430es1 {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
- };
-
- ssi_sst_fck: ssi_sst_fck_3430es1 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&ssi_ssr_fck>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- clock@a10 {
- compatible = "ti,clksel";
- reg = <0xa10>;
- #clock-cells = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1@4 {
- reg = <4>;
- #clock-cells = <0>;
- compatible = "ti,omap3-no-wait-interface-clock";
- clock-output-names = "hsotgusb_ick_3430es1";
- clocks = <&core_l3_ick>;
- };
-
- fac_ick: clock-fac-ick@8 {
- reg = <8>;
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clock-output-names = "fac_ick";
- clocks = <&core_l4_ick>;
- };
-
- ssi_ick: clock-ssi-ick-3430es1@0 {
- reg = <0>;
- #clock-cells = <0>;
- compatible = "ti,omap3-no-wait-interface-clock";
- clock-output-names = "ssi_ick_3430es1";
- clocks = <&ssi_l4_ick>;
- };
-
- usb_l4_gate_ick: clock-usb-l4-gate-ick@5 {
- reg = <5>;
- #clock-cells = <0>;
- compatible = "ti,composite-interface-clock";
- clock-output-names = "usb_l4_gate_ick";
- clocks = <&l4_ick>;
- };
- };
-
- ssi_l4_ick: ssi_l4_ick {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&l4_ick>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- usb_l4_ick: usb_l4_ick {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
- };
-
- clock@e00 {
- compatible = "ti,clksel";
- reg = <0xe00>;
- #clock-cells = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- dss1_alwon_fck: clock-dss1-alwon-fck-3430es1@0 {
- reg = <0>;
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clock-output-names = "dss1_alwon_fck_3430es1";
- clocks = <&dpll4_m4x2_ck>;
- ti,set-rate-parent;
- };
- };
-
- dss_ick: dss_ick_3430es1@e10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-no-wait-interface-clock";
- clocks = <&l4_ick>;
- reg = <0x0e10>;
- ti,bit-shift = <0>;
- };
-};
-
-&cm_clockdomains {
- core_l3_clkdm: core_l3_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>;
- };
-
- gfx_3430es1_clkdm: gfx_3430es1_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>;
- };
-
- dss_clkdm: dss_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
- <&dss1_alwon_fck>, <&dss_ick>;
- };
-
- d2d_clkdm: d2d_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&d2d_26m_fck>;
- };
-
- core_l4_clkdm: core_l4_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
- <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
- <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
- <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
- <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
- <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
- <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
- <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
- <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
- <&fshostusb_fck>, <&fac_ick>, <&ssi_ick>;
- };
-};
interrupts = <11>;
};
+ pwrbutton {
+ compatible = "ti,twl6030-pwrbutton";
+ interrupts = <0>;
+ };
+
ldo2: regulator-ldo2 {
compatible = "ti,twl6032-ldo2";
regulator-min-microvolt = <1000000>;
ranges = <0x0 0x30000 0x1000>,
<0x49030000 0x49030000 0x1000>;
- wdt3: wdt@0 {
+ wdt3: watchdog@0 {
compatible = "ti,omap4-wdt", "ti,omap3-wdt";
reg = <0x0 0x80>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
#size-cells = <1>;
ranges = <0x0 0x4000 0x1000>;
- wdt2: wdt@0 {
+ wdt2: watchdog@0 {
compatible = "ti,omap4-wdt", "ti,omap3-wdt";
reg = <0x0 0x80>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
#size-cells = <1>;
ranges = <0x0 0x4000 0x1000>;
- wdt2: wdt@0 {
+ wdt2: watchdog@0 {
compatible = "ti,omap5-wdt", "ti,omap3-wdt";
reg = <0x0 0x80>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
&tps {
compatible = "ti,tps65910";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
regulators {
#address-cells = <1>;
reg = <0x00600000 0x03200000>;
};
- tclinux_slave@3800000 {
+ tclinux-slave@3800000 {
label = "tclinux_alt";
reg = <0x03800000 0x03200000>;
};
- rootfs_data@6a00000 {
+ rootfs-data@6a00000 {
label = "rootfs_data";
reg = <0x06a00000 0x01400000>;
};
- reserved_bmt@7e00000 {
+ reserved-bmt@7e00000 {
label = "reserved_bmt";
reg = <0x07e00000 0x00200000>;
read-only;
#size-cells = <0>;
};
+ ledc: led-controller@5018000 {
+ compatible = "allwinner,sun50i-a100-ledc";
+ reg = <0x5018000 0x400>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_LEDC>;
+ dmas = <&dma 42>;
+ dma-names = "tx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
emac0: ethernet@5020000 {
compatible = "allwinner,sun50i-a100-emac",
"allwinner,sun50i-a64-emac";
allwinner,pinmux = <2>;
};
+ /omit-if-no-ref/
+ spi0_pc_pins: spi0-pc-pins {
+ pins = "PC2", "PC4", "PC12";
+ function = "spi0";
+ allwinner,pinmux = <4>;
+ };
+
+ /omit-if-no-ref/
+ spi0_cs0_pc_pin: spi0-cs0-pc-pin {
+ pins = "PC3";
+ function = "spi0";
+ allwinner,pinmux = <4>;
+ };
+
+ /omit-if-no-ref/
+ spi0_cs1_pc_pin: spi0-cs1-pc-pin {
+ pins = "PC7";
+ function = "spi0";
+ allwinner,pinmux = <4>;
+ };
+
+ /omit-if-no-ref/
+ spi0_hold_pc_pin: spi0-hold-pc-pin {
+ /* conflicts with eMMC D7 */
+ pins = "PC16";
+ function = "spi0";
+ allwinner,pinmux = <4>;
+ };
+
+ /omit-if-no-ref/
+ spi0_wp_pc_pin: spi0-wp-pc-pin {
+ /* conflicts with eMMC D2 */
+ pins = "PC15";
+ function = "spi0";
+ allwinner,pinmux = <4>;
+ };
+
uart0_pb_pins: uart0-pb-pins {
pins = "PB9", "PB10";
allwinner,pinmux = <2>;
#size-cells = <0>;
};
+ spi0: spi@4025000 {
+ compatible = "allwinner,sun55i-a523-spi";
+ reg = <0x04025000 0x1000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 22>, <&dma 22>;
+ dma-names = "rx", "tx";
+ resets = <&ccu RST_BUS_SPI0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@4026000 {
+ compatible = "allwinner,sun55i-a523-spi-dbi",
+ "allwinner,sun55i-a523-spi";
+ reg = <0x04026000 0x1000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 23>, <&dma 23>;
+ dma-names = "rx", "tx";
+ resets = <&ccu RST_BUS_SPI1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi2: spi@4027000 {
+ compatible = "allwinner,sun55i-a523-spi";
+ reg = <0x04027000 0x1000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 24>, <&dma 24>;
+ dma-names = "rx", "tx";
+ resets = <&ccu RST_BUS_SPI2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
usb_otg: usb@4100000 {
compatible = "allwinner,sun55i-a523-musb",
"allwinner,sun8i-a33-musb";
#clock-cells = <1>;
};
+ r_spi0: spi@7092000 {
+ compatible = "allwinner,sun55i-a523-spi";
+ reg = <0x07092000 0x1000>;
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_BUS_R_SPI>, <&r_ccu CLK_R_SPI>;
+ clock-names = "ahb", "mod";
+ dmas = <&mcu_dma 13>, <&mcu_dma 13>;
+ dma-names = "rx", "tx";
+ resets = <&r_ccu RST_BUS_R_SPI>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
mcu_ccu: clock-controller@7102000 {
compatible = "allwinner,sun55i-a523-mcu-ccu";
reg = <0x7102000 0x200>;
assigned-clock-rates = <32768>;
};
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pc_pins>, <&spi0_cs0_pc_pin>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ vcc-supply = <®_cldo1>;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
pinctrl0: pinctrl@ffd13000 {
compatible = "pinctrl-single";
- reg = <0xffd13000 0xA0>;
+ reg = <0xffd13000 0xa0>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
root: partition@4200000 {
label = "Root Filesystem - UBIFS";
- reg = <0x04200000 0x0BE00000>;
+ reg = <0x04200000 0x0be00000>;
};
};
};
qspi_boot: partition@0 {
label = "Boot and fpga data";
- reg = <0x0 0x03FE0000>;
+ reg = <0x0 0x03fe0000>;
};
qspi_rootfs: partition@3fe0000 {
label = "Root Filesystem - JFFS2";
- reg = <0x03FE0000 0x0C020000>;
+ reg = <0x03fe0000 0x0c020000>;
};
};
};
firmware {
scmi: scmi {
compatible = "arm,scmi-smc";
- arm,smc-id = <0x820000C1>;
+ arm,smc-id = <0x820000c1>;
shmem = <&scmi_shmem>;
#address-cells = <1>;
#size-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
- internal_ephy: ethernet_phy@8 {
+ internal_ephy: ethernet-phy@8 {
compatible = "ethernet-phy-id0180.3301",
"ethernet-phy-ieee802.3-c22";
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
no-sd;
resets = <&reset RESET_SD_EMMC_A>;
status = "disabled";
+
+ assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_A>;
+ assigned-clock-rates = <24000000>;
+
};
sd: mmc@8a000 {
no-sdio;
resets = <&reset RESET_SD_EMMC_B>;
status = "disabled";
+
+ assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_B>;
+ assigned-clock-rates = <24000000>;
};
nand: nand-controller@8d000 {
compatible = "amlogic,meson-axg-nfc";
reg = <0x0 0x8d000 0x0 0x200>,
- <0x0 0x8C000 0x0 0x4>;
+ <0x0 0x8c000 0x0 0x4>;
reg-names = "nfc", "emmc";
interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_C>,
memory@0 {
device_type = "memory";
- reg = <0x00000000 0x00000000 0x00000000 0xE0000000
+ reg = <0x00000000 0x00000000 0x00000000 0xe0000000
0x00000001 0x00000000 0x00000000 0x20000000>;
};
clock-names = "core",
"clkin0",
"clkin1";
- assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_SEL2>;
- assigned-clock-parents = <&xtal>;
resets = <&reset RESET_SD_EMMC_A>;
power-domains = <&pwrc PWRC_SD_EMMC_ID>;
status = "disabled";
+
+ assigned-clocks = <&clkc_periphs CLKID_SD_EMMC>;
+ assigned-clock-rates = <24000000>;
};
};
assigned-clocks = <&clkc CLKID_HIFI_PLL>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <589824000>,
<270950400>,
<393216000>;
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_B>;
+
+ assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>;
+ assigned-clock-rates = <24000000>;
};
sd_emmc_c: mmc@7000 {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
+
+ assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>;
+ assigned-clock-rates = <24000000>;
};
nfc: nand-controller@7800 {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_A>;
+
+ assigned-clocks = <&clkc CLKID_SD_EMMC_A_CLK0>;
+ assigned-clock-rates = <24000000>;
};
sd_emmc_b: mmc@ffe05000 {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_B>;
+
+ assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>;
+ assigned-clock-rates = <24000000>;
};
sd_emmc_c: mmc@ffe07000 {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
+
+ assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>;
+ assigned-clock-rates = <24000000>;
};
usb: usb@ffe09000 {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
&cpu0 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
ðmac {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
&cpu0 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cvbs_vdac_port {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
&cpu0 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cvbs_vdac_port {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
&cpu0 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&clkc_audio {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
&cpu0 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cvbs_vdac_port {
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
};
cpu1: cpu@1 {
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
};
cpu2: cpu@2 {
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
};
cpu3: cpu@3 {
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
};
l2: l2-cache0 {
/dts-v1/;
-#include <dt-bindings/clock/g12a-clkc.h>
#include "meson-g12b-a311d.dtsi"
#include "meson-libretech-cottonwood.dtsi"
&cpu0 {
cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&pwm_ab {
};
};
};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opp_table_0>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opp_table_0>;
+};
+
+&cpu100 {
+ operating-points-v2 = <&cpub_opp_table_1>;
+};
+
+&cpu101 {
+ operating-points-v2 = <&cpub_opp_table_1>;
+};
+
+&cpu102 {
+ operating-points-v2 = <&cpub_opp_table_1>;
+};
+
+&cpu103 {
+ operating-points-v2 = <&cpub_opp_table_1>;
+};
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
&cpu0 {
cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&ext_mdio {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
&cpu0 {
cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
ðmac {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
&cpu0 {
cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&pwm_ab {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
&cpu0 {
cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
/* RK817 only supports 12.5mV steps, round up the values */
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
&cpu0 {
cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu_thermal {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
&cpu0 {
cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu_thermal {
};
};
+/* Also exposed on the 40-pin header: SDA pin 3, SCL pin 5 */
+&i2c3 {
+ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ fusb0: typec-portc@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+
+ pinctrl-0 = <&fusb302_irq_pins>;
+ pinctrl-names = "default";
+ interrupt-parent = <&gpio_intc>;
+ interrupts = <74 IRQ_TYPE_LEVEL_LOW>;
+
+ vbus-supply = <&ao_5v>;
+
+ connector {
+ compatible = "usb-c-connector";
+ };
+ };
+};
+
&ir {
status = "disabled";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
+&periphs_pinctrl {
+ fusb302_irq_pins: fusb302-irq {
+ mux {
+ groups = "GPIOA_13";
+ function = "gpio_periphs";
+ bias-pull-up;
+ output-disable;
+ };
+ };
+};
+
&pwm_ab {
pinctrl-0 = <&pwm_a_e_pins>;
pinctrl-names = "default";
status = "okay";
};
+&npu {
+ status = "okay";
+};
+
&saradc {
status = "okay";
vref-supply = <&vddao_1v8>;
};
};
};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opp_table_0>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opp_table_0>;
+};
+
+&cpu100 {
+ operating-points-v2 = <&cpub_opp_table_1>;
+};
+
+&cpu101 {
+ operating-points-v2 = <&cpub_opp_table_1>;
+};
+
+&cpu102 {
+ operating-points-v2 = <&cpub_opp_table_1>;
+};
+
+&cpu103 {
+ operating-points-v2 = <&cpub_opp_table_1>;
+};
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
&cpu0 {
cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
};
&cvbs_vdac_port {
i-cache-sets = <32>;
next-level-cache = <&l2_cache_l>;
#cooling-cells = <2>;
+ clocks = <&clkc CLKID_CPU_CLK>;
};
cpu1: cpu@1 {
i-cache-sets = <32>;
next-level-cache = <&l2_cache_l>;
#cooling-cells = <2>;
+ clocks = <&clkc CLKID_CPU_CLK>;
};
cpu100: cpu@100 {
i-cache-sets = <32>;
next-level-cache = <&l2_cache_b>;
#cooling-cells = <2>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
};
cpu101: cpu@101 {
i-cache-sets = <32>;
next-level-cache = <&l2_cache_b>;
#cooling-cells = <2>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
};
cpu102: cpu@102 {
i-cache-sets = <64>;
next-level-cache = <&l2_cache_b>;
#cooling-cells = <2>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
};
cpu103: cpu@103 {
i-cache-sets = <64>;
next-level-cache = <&l2_cache_b>;
#cooling-cells = <2>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
};
l2_cache_l: l2-cache-cluster0 {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_A>;
+
+ assigned-clocks = <&clkc CLKID_SD_EMMC_A_CLK0>;
+ assigned-clock-rates = <24000000>;
};
&sd_emmc_b {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_B>;
+
+ assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>;
+ assigned-clock-rates = <24000000>;
};
&sd_emmc_c {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
+
+ assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>;
+ assigned-clock-rates = <24000000>;
};
&simplefb_hdmi {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_A>;
+
+ assigned-clocks = <&clkc CLKID_SD_EMMC_A_CLK0>;
+ assigned-clock-rates = <24000000>;
};
&sd_emmc_b {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_B>;
+
+ assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>;
+ assigned-clock-rates = <24000000>;
};
&sd_emmc_c {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
+
+ assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>;
+ assigned-clock-rates = <24000000>;
};
&simplefb_hdmi {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
memory@0 {
device_type = "memory";
- reg = <0x0 0x0 0x0 0xC0000000>;
+ reg = <0x0 0x0 0x0 0xc0000000>;
};
adc-keys {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
/ {
model = "Amlogic Meson S4 AQ222 Development Board";
- compatible = "amlogic,aq222", "amlogic,s4";
+ compatible = "amlogic,aq222", "amlogic,s805x2", "amlogic,s4";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2026 Khadas Technology Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "meson-s4.dtsi"
+
+/ {
+ model = "Khadas VIM1S";
+ compatible = "khadas,vim1s", "amlogic,s905y4", "amlogic,s4";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ mmc0 = &emmc; /* eMMC */
+ mmc1 = &sd; /* SD card */
+ mmc2 = &sdio; /* SDIO */
+ serial0 = &uart_b;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 52 MiB reserved for ARM Trusted Firmware */
+ secmon_reserved: secmon@5000000 {
+ reg = <0x0 0x05000000 0x0 0x3400000>;
+ no-map;
+ };
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio GPIOB_9 GPIO_ACTIVE_LOW>;
+ };
+
+ sdio_32k: sdio-32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&sdio_32k>;
+ clock-names = "ext_clock";
+ };
+
+ main_5v: regulator-main-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ sd_3v3: regulator-sd-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "SD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio GPIOD_4 GPIO_ACTIVE_LOW>;
+ regulator-always-on;
+ };
+
+ vddio_sd: regulator-vddio-sd {
+ compatible = "regulator-gpio";
+ regulator-name = "VDDIO_SD";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <1800000 1
+ 3300000 0>;
+ };
+
+ vddao_3v3: regulator-vddao-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&main_5v>;
+ regulator-always-on;
+ };
+
+ vddio_ao1v8: regulator-vddio-ao1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ /* SY8120B1ABC DC/DC Regulator. */
+ vddcpu: regulator-vddcpu {
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU";
+ regulator-min-microvolt = <689000>;
+ regulator-max-microvolt = <1049000>;
+
+ vin-supply = <&main_5v>;
+
+ pwms = <&pwm_ij 1 1500 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ /* Voltage Duty-Cycle */
+ voltage-table = <1049000 0>,
+ <1039000 3>,
+ <1029000 6>,
+ <1019000 9>,
+ <1009000 12>,
+ <999000 14>,
+ <989000 17>,
+ <979000 20>,
+ <969000 23>,
+ <959000 26>,
+ <949000 29>,
+ <939000 31>,
+ <929000 34>,
+ <919000 37>,
+ <909000 40>,
+ <899000 43>,
+ <889000 45>,
+ <879000 48>,
+ <869000 51>,
+ <859000 54>,
+ <849000 56>,
+ <839000 59>,
+ <829000 62>,
+ <819000 65>,
+ <809000 68>,
+ <799000 70>,
+ <789000 73>,
+ <779000 76>,
+ <769000 79>,
+ <759000 81>,
+ <749000 84>,
+ <739000 87>,
+ <729000 89>,
+ <719000 92>,
+ <709000 95>,
+ <699000 98>,
+ <689000 100>;
+ };
+};
+
+&emmc {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_ao1v8>;
+};
+
+ðmac {
+ status = "okay";
+ phy-handle = <&internal_ephy>;
+ phy-mode = "rmii";
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins1>;
+ pinctrl-names = "default";
+};
+
+&pwm_ij {
+ status = "okay";
+};
+
+&sd {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&sd_3v3>;
+ vqmmc-supply = <&vddio_sd>;
+};
+
+&sdio {
+ status = "okay";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ max-frequency = <50000000>;
+ non-removable;
+ disable-wp;
+
+ no-sd;
+ no-mmc;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_ao1v8>;
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac";
+ };
+};
+
+&spicc0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins_x>;
+ cs-gpios = <&gpio GPIOX_10 GPIO_ACTIVE_LOW>;
+};
+
+&uart_b {
+ status = "okay";
+};
reg = <0x0 0xfe088000 0x0 0x800>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc_periphs CLKID_SDEMMC_A>,
- <&xtal>,
+ <&clkc_periphs CLKID_SD_EMMC_A>,
<&clkc_pll CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_A>;
cap-sdio-irq;
keep-power-in-suspend;
status = "disabled";
+
+ assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_A>;
+ assigned-clock-rates = <24000000>;
};
sd: mmc@fe08a000 {
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_B>;
status = "disabled";
+
+ assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_B>;
+ assigned-clock-rates = <24000000>;
};
emmc: mmc@fe08c000 {
reg = <0x0 0xfe08c000 0x0 0x800>;
interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc_periphs CLKID_NAND>,
- <&xtal>,
+ <&clkc_periphs CLKID_SD_EMMC_C>,
<&clkc_pll CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_NAND_EMMC>;
no-sdio;
no-sd;
status = "disabled";
+
+ assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_C>;
+ assigned-clock-rates = <24000000>;
};
};
};
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
&cpu0 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU1_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU2_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU3_CLK>;
};
&cvbs_vdac_port {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
&cpu0 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU1_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU2_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU3_CLK>;
};
&ext_mdio {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
&cpu0 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU1_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU2_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU3_CLK>;
};
&pwm_AO_cd {
gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
enable-active-high;
+ regulator-boot-on;
regulator-always-on;
};
gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
enable-active-high;
+ regulator-boot-on;
regulator-always-on;
};
gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>;
enable-active-high;
+ regulator-boot-on;
regulator-always-on;
};
enable-gpios = <&gpio_ao GPIOE_2 GPIO_OPEN_DRAIN>;
enable-active-high;
+ regulator-boot-on;
regulator-always-on;
gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_SOURCE>;
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
regulator-always-on;
vin-supply = <&main_12v>;
gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
&cpu0 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU1_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU2_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU3_CLK>;
};
&ext_mdio {
/dts-v1/;
-#include <dt-bindings/clock/g12a-clkc.h>
#include "meson-sm1.dtsi"
#include "meson-libretech-cottonwood.dtsi"
&cpu0 {
cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU1_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU2_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU3_CLK>;
};
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
&cpu0 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU1_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU2_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU3_CLK>;
};
ðmac {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
};
cpu1: cpu@1 {
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU1_CLK>;
};
cpu2: cpu@2 {
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU2_CLK>;
};
cpu3: cpu@3 {
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU3_CLK>;
};
l2: l2-cache0 {
poweroff: poweroff@10548010 {
compatible = "syscon-poweroff";
+ reg = <0x0 0x10548010 0x0 0x4>;
regmap = <&poweroff_mbox>;
offset = <0x10>;
mask = <0x1>;
poweroff: poweroff@10548010 {
compatible = "syscon-poweroff";
+ reg = <0x0 0x10548010 0x0 0x4>;
regmap = <&poweroff_mbox>;
offset = <0x10>;
mask = <0x1>;
clock-frequency = <50000000>;
};
- i2cslimpro {
+ i2c {
compatible = "apm,xgene-slimpro-i2c";
mboxes = <&mailbox 0>;
};
socplldiv2: socplldiv2 {
compatible = "fixed-factor-clock";
- #clock-cells = <1>;
+ #clock-cells = <0>;
clocks = <&socpll 0>;
clock-mult = <1>;
clock-div = <2>;
ahbclk: ahbclk@17000000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
- clocks = <&socplldiv2 0>;
+ clocks = <&socplldiv2>;
reg = <0x0 0x17000000 0x0 0x2000>;
reg-names = "div-reg";
divider-offset = <0x164>;
sdioclk: sdioclk@1f2ac000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
- clocks = <&socplldiv2 0>;
+ clocks = <&socplldiv2>;
reg = <0x0 0x1f2ac000 0x0 0x1000
0x0 0x17000000 0x0 0x2000>;
reg-names = "csr-reg", "div-reg";
pcie0clk: pcie0clk@1f2bc000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
- clocks = <&socplldiv2 0>;
+ clocks = <&socplldiv2>;
reg = <0x0 0x1f2bc000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "pcie0clk";
pcie1clk: pcie1clk@1f2cc000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
- clocks = <&socplldiv2 0>;
+ clocks = <&socplldiv2>;
reg = <0x0 0x1f2cc000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "pcie1clk";
xge0clk: xge0clk@1f61c000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
- clocks = <&socplldiv2 0>;
+ clocks = <&socplldiv2>;
reg = <0x0 0x1f61c000 0x0 0x1000>;
reg-names = "csr-reg";
enable-mask = <0x3>;
xge1clk: xge1clk@1f62c000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
- clocks = <&socplldiv2 0>;
+ clocks = <&socplldiv2>;
reg = <0x0 0x1f62c000 0x0 0x1000>;
reg-names = "csr-reg";
enable-mask = <0x3>;
rngpkaclk: rngpkaclk@17000000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
- clocks = <&socplldiv2 0>;
+ clocks = <&socplldiv2>;
reg = <0x0 0x17000000 0x0 0x2000>;
reg-names = "csr-reg";
csr-offset = <0xc>;
reboot: reboot@17000014 {
compatible = "syscon-reboot";
+ reg = <0x0 0x17000014 0x0 0x4>;
regmap = <&scu>;
offset = <0x14>;
mask = <0x1>;
compatible = "snps,designware-i2c";
reg = <0x0 0x10511000 0x0 0x1000>;
interrupts = <0 0x45 0x4>;
- #clock-cells = <1>;
clocks = <&sbapbclk 0>;
};
interrupts = <1 12 0xff04>;
};
- i2cslimpro {
+ i2c {
compatible = "apm,xgene-slimpro-i2c";
mboxes = <&mailbox 0>;
};
reboot: reboot@17000014 {
compatible = "syscon-reboot";
+ reg = <0x0 0x17000014 0x0 0x4>;
regmap = <&scu>;
offset = <0x14>;
mask = <0x1>;
dma: dma@1f270000 {
compatible = "apm,xgene-storm-dma";
- device_type = "dma";
reg = <0x0 0x1f270000 0x0 0x10000>,
<0x0 0x1f200000 0x0 0x10000>,
<0x0 0x1b000000 0x0 0x400000>,
* Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com>
*/
+&dwi_bl {
+ status = "okay";
+};
+
&ps_dcs4 {
apple,always-on; /* LPDDR4 interface */
};
power-domains = <&ps_aic>;
};
+ dwi_bl: backlight@20e200080 {
+ compatible = "apple,s8000-dwi-bl", "apple,dwi-bl";
+ reg = <0x2 0x0e200080 0x0 0x8>;
+ power-domains = <&ps_dwi>;
+ status = "disabled";
+ };
+
pinctrl_ap: pinctrl@20f100000 {
compatible = "apple,s8000-pinctrl", "apple,pinctrl";
reg = <0x2 0x0f100000 0x0 0x100000>;
#include <dt-bindings/interrupt-controller/apple-aic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/apple.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/spmi/spmi.h>
#include "multi-die-cpp.h"
/ {
compatible = "apple,j375d", "apple,t6002", "apple,arm-platform";
model = "Apple Mac Studio (M1 Ultra, 2022)";
+ aliases {
+ atcphy4 = &atcphy0_die1;
+ atcphy5 = &atcphy1_die1;
+ };
};
/* USB Type C */
interrupt-parent = <&pinctrl_ap>;
interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
+
+ typec4: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C Front Right";
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec4_connector_hs: endpoint {
+ remote-endpoint = <&dwc3_4_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec4_connector_ss: endpoint {
+ remote-endpoint = <&atcphy4_typec_lanes>;
+ };
+ };
+ };
+ };
};
/* front-left */
interrupt-parent = <&pinctrl_ap>;
interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
+
+ typec5: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C Front Left";
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec5_connector_hs: endpoint {
+ remote-endpoint = <&dwc3_5_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec5_connector_ss: endpoint {
+ remote-endpoint = <&atcphy5_typec_lanes>;
+ };
+ };
+ };
+ };
};
};
brcm,board-type = "apple,okinawa";
};
+/* USB controllers on die 1 */
+&dwc3_0_die1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dwc3_4_hs: endpoint {
+ remote-endpoint = <&typec4_connector_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dwc3_4_ss: endpoint {
+ remote-endpoint = <&atcphy4_usb3>;
+ };
+ };
+ };
+};
+
+&dwc3_1_die1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dwc3_5_hs: endpoint {
+ remote-endpoint = <&typec5_connector_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dwc3_5_ss: endpoint {
+ remote-endpoint = <&atcphy5_usb3>;
+ };
+ };
+ };
+};
+
+/* Type-C PHYs */
+&atcphy0_die1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ atcphy4_typec_lanes: endpoint {
+ remote-endpoint = <&typec4_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ atcphy4_usb3: endpoint {
+ remote-endpoint = <&dwc3_4_ss>;
+ };
+ };
+ };
+};
+
+&atcphy1_die1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ atcphy5_typec_lanes: endpoint {
+ remote-endpoint = <&typec5_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ atcphy5_usb3: endpoint {
+ remote-endpoint = <&dwc3_5_ss>;
+ };
+ };
+ };
+};
+
+/* delete unused USB nodes on die 1 */
+
+/delete-node/ &dwc3_2_dart_0_die1;
+/delete-node/ &dwc3_2_dart_1_die1;
+/delete-node/ &dwc3_2_die1;
+/delete-node/ &atcphy2_die1;
+
+/delete-node/ &dwc3_3_dart_0_die1;
+/delete-node/ &dwc3_3_dart_1_die1;
+/delete-node/ &dwc3_3_die1;
+/delete-node/ &atcphy3_die1;
+
/* delete unused always-on power-domains on die 1 */
/delete-node/ &ps_atc2_usb_aon_die1;
#include <dt-bindings/interrupt-controller/apple-aic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/apple.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/spmi/spmi.h>
#include "multi-die-cpp.h"
nvmem-cell-names = "shutdown_flag", "boot_stage",
"boot_error_count", "panic_count";
};
+
+ rtc {
+ compatible = "apple,smc-rtc";
+ nvmem-cells = <&rtc_offset>;
+ nvmem-cell-names = "rtc_offset";
+ };
};
smc_mbox: mbox@290408000 {
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ DIE_NODE(dwc3_0): usb@702280000 {
+ compatible = "apple,t6000-dwc3", "apple,t8103-dwc3";
+ reg = <0x7 0x02280000 0x0 0xcd00>, <0x7 0x0228cd00 0x0 0x3200>;
+ reg-names = "dwc3-core", "dwc3-apple";
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1190 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "host";
+ iommus = <&DIE_NODE(dwc3_0_dart_0) 0>,
+ <&DIE_NODE(dwc3_0_dart_1) 1>;
+ power-domains = <&DIE_NODE(ps_atc0_usb)>;
+ resets = <&DIE_NODE(atcphy0)>;
+ phys = <&DIE_NODE(atcphy0) PHY_TYPE_USB2>, <&DIE_NODE(atcphy0) PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+
+ DIE_NODE(dwc3_0_dart_0): iommu@702f00000 {
+ compatible = "apple,t6000-dart";
+ reg = <0x7 0x02f00000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1194 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&DIE_NODE(ps_atc0_usb)>;
+ #iommu-cells = <1>;
+ };
+
+ DIE_NODE(dwc3_0_dart_1): iommu@702f80000 {
+ compatible = "apple,t6000-dart";
+ reg = <0x7 0x02f80000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1194 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&DIE_NODE(ps_atc0_usb)>;
+ #iommu-cells = <1>;
+ };
+
+ DIE_NODE(atcphy0): phy@703000000 {
+ compatible = "apple,t6000-atcphy", "apple,t8103-atcphy";
+ reg = <0x7 0x03000000 0x0 0x4c000>,
+ <0x7 0x03050000 0x0 0x8000>,
+ <0x7 0x00000000 0x0 0x4000>,
+ <0x7 0x02a90000 0x0 0x4000>,
+ <0x7 0x02a84000 0x0 0x4000>;
+ reg-names = "core", "lpdptx", "axi2af", "usb2phy",
+ "pipehandler";
+
+ #phy-cells = <1>;
+ #reset-cells = <0>;
+
+ orientation-switch;
+ mode-switch;
+ power-domains = <&DIE_NODE(ps_atc0_usb)>;
+ };
+
+ DIE_NODE(dwc3_1): usb@b02280000 {
+ compatible = "apple,t6000-dwc3", "apple,t8103-dwc3";
+ reg = <0xb 0x02280000 0x0 0xcd00>, <0xb 0x0228cd00 0x0 0x3200>;
+ reg-names = "dwc3-core", "dwc3-apple";
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1207 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "host";
+ iommus = <&DIE_NODE(dwc3_1_dart_0) 0>,
+ <&DIE_NODE(dwc3_1_dart_1) 1>;
+ power-domains = <&DIE_NODE(ps_atc1_usb)>;
+ resets = <&DIE_NODE(atcphy1)>;
+ phys = <&DIE_NODE(atcphy1) PHY_TYPE_USB2>, <&DIE_NODE(atcphy1) PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+
+ DIE_NODE(dwc3_1_dart_0): iommu@b02f00000 {
+ compatible = "apple,t6000-dart";
+ reg = <0xb 0x02f00000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1211 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&DIE_NODE(ps_atc1_usb)>;
+ #iommu-cells = <1>;
+ };
+
+ DIE_NODE(dwc3_1_dart_1): iommu@b02f80000 {
+ compatible = "apple,t6000-dart";
+ reg = <0xb 0x02f80000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1211 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&DIE_NODE(ps_atc1_usb)>;
+ #iommu-cells = <1>;
+ };
+
+ DIE_NODE(atcphy1): phy@b03000000 {
+ compatible = "apple,t6000-atcphy", "apple,t8103-atcphy";
+ reg = <0xb 0x03000000 0x0 0x4c000>,
+ <0xb 0x03050000 0x0 0x8000>,
+ <0xb 0x00000000 0x0 0x4000>,
+ <0xb 0x02a90000 0x0 0x4000>,
+ <0xb 0x02a84000 0x0 0x4000>;
+ reg-names = "core", "lpdptx", "axi2af", "usb2phy",
+ "pipehandler";
+
+ #phy-cells = <1>;
+ #reset-cells = <0>;
+
+ orientation-switch;
+ mode-switch;
+ power-domains = <&DIE_NODE(ps_atc1_usb)>;
+ };
+
+ DIE_NODE(dwc3_2): usb@f02280000 {
+ compatible = "apple,t6000-dwc3", "apple,t8103-dwc3";
+ reg = <0xf 0x02280000 0x0 0xcd00>, <0xf 0x0228cd00 0x0 0x3200>;
+ reg-names = "dwc3-core", "dwc3-apple";
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1224 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "host";
+ iommus = <&DIE_NODE(dwc3_2_dart_0) 0>,
+ <&DIE_NODE(dwc3_2_dart_1) 1>;
+ power-domains = <&DIE_NODE(ps_atc2_usb)>;
+ resets = <&DIE_NODE(atcphy2)>;
+ phys = <&DIE_NODE(atcphy2) PHY_TYPE_USB2>, <&DIE_NODE(atcphy2) PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+
+ DIE_NODE(dwc3_2_dart_0): iommu@f02f00000 {
+ compatible = "apple,t6000-dart";
+ reg = <0xf 0x02f00000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1228 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&DIE_NODE(ps_atc2_usb)>;
+ #iommu-cells = <1>;
+ };
+
+ DIE_NODE(dwc3_2_dart_1): iommu@f02f80000 {
+ compatible = "apple,t6000-dart";
+ reg = <0xf 0x02f80000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1228 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&DIE_NODE(ps_atc2_usb)>;
+ #iommu-cells = <1>;
+ };
+
+ DIE_NODE(atcphy2): phy@f03000000 {
+ compatible = "apple,t6000-atcphy", "apple,t8103-atcphy";
+ reg = <0xf 0x03000000 0x0 0x4c000>,
+ <0xf 0x03050000 0x0 0x8000>,
+ <0xf 0x00000000 0x0 0x4000>,
+ <0xf 0x02a90000 0x0 0x4000>,
+ <0xf 0x02a84000 0x0 0x4000>;
+ reg-names = "core", "lpdptx", "axi2af", "usb2phy",
+ "pipehandler";
+
+ #phy-cells = <1>;
+ #reset-cells = <0>;
+
+ orientation-switch;
+ mode-switch;
+ power-domains = <&DIE_NODE(ps_atc2_usb)>;
+ };
+
+ DIE_NODE(dwc3_3): usb@1302280000 {
+ compatible = "apple,t6000-dwc3", "apple,t8103-dwc3";
+ reg = <0x13 0x02280000 0x0 0xcd00>, <0x13 0x0228cd00 0x0 0x3200>;
+ reg-names = "dwc3-core", "dwc3-apple";
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1241 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "host";
+ iommus = <&DIE_NODE(dwc3_3_dart_0) 0>,
+ <&DIE_NODE(dwc3_3_dart_1) 1>;
+ power-domains = <&DIE_NODE(ps_atc3_usb)>;
+ resets = <&DIE_NODE(atcphy3)>;
+ phys = <&DIE_NODE(atcphy3) PHY_TYPE_USB2>, <&DIE_NODE(atcphy3) PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+
+ DIE_NODE(dwc3_3_dart_0): iommu@1302f00000 {
+ compatible = "apple,t6000-dart";
+ reg = <0x13 0x02f00000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1245 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&DIE_NODE(ps_atc3_usb)>;
+ #iommu-cells = <1>;
+ };
+
+ DIE_NODE(dwc3_3_dart_1): iommu@1302f80000 {
+ compatible = "apple,t6000-dart";
+ reg = <0x13 0x02f80000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1245 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&DIE_NODE(ps_atc3_usb)>;
+ #iommu-cells = <1>;
+ };
+
+ DIE_NODE(atcphy3): phy@1303000000 {
+ compatible = "apple,t6000-atcphy", "apple,t8103-atcphy";
+ reg = <0x13 0x03000000 0x0 0x4c000>,
+ <0x13 0x03050000 0x0 0x8000>,
+ <0x13 0x00000000 0x0 0x4000>,
+ <0x13 0x02a90000 0x0 0x4000>,
+ <0x13 0x02a84000 0x0 0x4000>;
+ reg-names = "core", "lpdptx", "axi2af", "usb2phy",
+ "pipehandler";
+
+ #phy-cells = <1>;
+ #reset-cells = <0>;
+
+ orientation-switch;
+ mode-switch;
+ power-domains = <&DIE_NODE(ps_atc3_usb)>;
+ };
#include <dt-bindings/leds/common.h>
/ {
+ chassis-type = "laptop";
+
aliases {
+ atcphy0 = &atcphy0;
+ atcphy1 = &atcphy1;
+ atcphy2 = &atcphy2;
+ atcphy3 = &atcphy3;
bluetooth0 = &bluetooth0;
serial0 = &serial0;
wifi0 = &wifi0;
interrupt-parent = <&pinctrl_ap>;
interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
+
+ typec0: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C Left Rear";
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec0_connector_hs: endpoint {
+ remote-endpoint = <&dwc3_0_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec0_connector_ss: endpoint {
+ remote-endpoint = <&atcphy0_typec_lanes>;
+ };
+ };
+ };
+ };
};
hpm1: usb-pd@3f {
interrupt-parent = <&pinctrl_ap>;
interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
+
+ typec1: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C Left Front";
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec1_connector_hs: endpoint {
+ remote-endpoint = <&dwc3_1_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec1_connector_ss: endpoint {
+ remote-endpoint = <&atcphy1_typec_lanes>;
+ };
+ };
+ };
+ };
};
hpm2: usb-pd@3b {
interrupt-parent = <&pinctrl_ap>;
interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
+
+ typec2: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C Right";
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec2_connector_hs: endpoint {
+ remote-endpoint = <&dwc3_2_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec2_connector_ss: endpoint {
+ remote-endpoint = <&atcphy2_typec_lanes>;
+ };
+ };
+ };
+ };
};
/* MagSafe port */
status = "okay";
};
+/* USB controllers */
+&dwc3_0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dwc3_0_hs: endpoint {
+ remote-endpoint = <&typec0_connector_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dwc3_0_ss: endpoint {
+ remote-endpoint = <&atcphy0_usb3>;
+ };
+ };
+ };
+};
+
+&dwc3_1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dwc3_1_hs: endpoint {
+ remote-endpoint = <&typec1_connector_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dwc3_1_ss: endpoint {
+ remote-endpoint = <&atcphy1_usb3>;
+ };
+ };
+ };
+};
+
+&dwc3_2 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dwc3_2_hs: endpoint {
+ remote-endpoint = <&typec2_connector_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dwc3_2_ss: endpoint {
+ remote-endpoint = <&atcphy2_usb3>;
+ };
+ };
+ };
+};
+
+/*
+ * ps_atc3_usb_aon power-domain is always-on to keep dwc3 working over suspend.
+ * atc3 is used exclusively for the DP-to-HDMI so do not keep this always on.
+ */
+&ps_atc3_usb_aon {
+ /delete-property/ apple,always-on;
+};
+
+/* ATC3 is used for DisplayPort -> HDMI only */
+&dwc3_3_dart_0 {
+ status = "disabled";
+};
+
+&dwc3_3_dart_1 {
+ status = "disabled";
+};
+
+&dwc3_3 {
+ status = "disabled";
+};
+
+/* Delete unused dwc3_3 to prevent dt_disable_missing_devs() from disabling
+ * atcphy3 via phandle references from a disablecd device.
+ */
+/delete-node/ &dwc3_3;
+
+/* Type-C PHYs */
+&atcphy0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ atcphy0_typec_lanes: endpoint {
+ remote-endpoint = <&typec0_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ atcphy0_usb3: endpoint {
+ remote-endpoint = <&dwc3_0_ss>;
+ };
+ };
+ };
+};
+
+&atcphy1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ atcphy1_typec_lanes: endpoint {
+ remote-endpoint = <&typec1_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ atcphy1_usb3: endpoint {
+ remote-endpoint = <&dwc3_1_ss>;
+ };
+ };
+ };
+};
+
+&atcphy2 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ atcphy2_typec_lanes: endpoint {
+ remote-endpoint = <&typec2_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ atcphy2_usb3: endpoint {
+ remote-endpoint = <&dwc3_2_ss>;
+ };
+ };
+ };
+};
+
+&atcphy3 {
+ status = "disabled";
+};
+
#include "spi1-nvram.dtsi"
*/
/ {
+ chassis-type = "desktop";
+
aliases {
+ atcphy0 = &atcphy0;
+ atcphy1 = &atcphy1;
+ atcphy2 = &atcphy2;
+ atcphy3 = &atcphy3;
bluetooth0 = &bluetooth0;
ethernet0 = ðernet0;
serial0 = &serial0;
interrupt-parent = <&pinctrl_ap>;
interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
+
+ typec0: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C Back Left";
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec0_connector_hs: endpoint {
+ remote-endpoint = <&dwc3_0_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec0_connector_ss: endpoint {
+ remote-endpoint = <&atcphy0_typec_lanes>;
+ };
+ };
+ };
+ };
};
hpm1: usb-pd@3f {
interrupt-parent = <&pinctrl_ap>;
interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
+
+ typec1: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C Back Left Middle";
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec1_connector_hs: endpoint {
+ remote-endpoint = <&dwc3_1_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec1_connector_ss: endpoint {
+ remote-endpoint = <&atcphy1_typec_lanes>;
+ };
+ };
+ };
+ };
};
hpm2: usb-pd@3b {
interrupt-parent = <&pinctrl_ap>;
interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
+
+ typec2: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C Back Right Middle";
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec2_connector_hs: endpoint {
+ remote-endpoint = <&dwc3_2_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec2_connector_ss: endpoint {
+ remote-endpoint = <&atcphy2_typec_lanes>;
+ };
+ };
+ };
+ };
};
hpm3: usb-pd@3c {
interrupt-parent = <&pinctrl_ap>;
interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
+
+ typec3: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C Back Right";
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec3_connector_hs: endpoint {
+ remote-endpoint = <&dwc3_3_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec3_connector_ss: endpoint {
+ remote-endpoint = <&atcphy3_typec_lanes>;
+ };
+ };
+ };
+ };
+ };
+};
+
+/* USB controllers */
+&dwc3_0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dwc3_0_hs: endpoint {
+ remote-endpoint = <&typec0_connector_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dwc3_0_ss: endpoint {
+ remote-endpoint = <&atcphy0_usb3>;
+ };
+ };
+ };
+};
+
+&dwc3_1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dwc3_1_hs: endpoint {
+ remote-endpoint = <&typec1_connector_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dwc3_1_ss: endpoint {
+ remote-endpoint = <&atcphy1_usb3>;
+ };
+ };
+ };
+};
+
+&dwc3_2 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dwc3_2_hs: endpoint {
+ remote-endpoint = <&typec2_connector_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dwc3_2_ss: endpoint {
+ remote-endpoint = <&atcphy2_usb3>;
+ };
+ };
+ };
+};
+
+&dwc3_3 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dwc3_3_hs: endpoint {
+ remote-endpoint = <&typec3_connector_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dwc3_3_ss: endpoint {
+ remote-endpoint = <&atcphy3_usb3>;
+ };
+ };
+ };
+};
+
+/* Type-C PHYs */
+&atcphy0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ atcphy0_typec_lanes: endpoint {
+ remote-endpoint = <&typec0_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ atcphy0_usb3: endpoint {
+ remote-endpoint = <&dwc3_0_ss>;
+ };
+ };
+ };
+};
+
+&atcphy1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ atcphy1_typec_lanes: endpoint {
+ remote-endpoint = <&typec1_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ atcphy1_usb3: endpoint {
+ remote-endpoint = <&dwc3_1_ss>;
+ };
+ };
+ };
+};
+
+&atcphy2 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ atcphy2_typec_lanes: endpoint {
+ remote-endpoint = <&typec2_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ atcphy2_usb3: endpoint {
+ remote-endpoint = <&dwc3_2_ss>;
+ };
+ };
+ };
+};
+
+&atcphy3 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ atcphy3_typec_lanes: endpoint {
+ remote-endpoint = <&typec3_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ atcphy3_usb3: endpoint {
+ remote-endpoint = <&dwc3_3_ss>;
+ };
+ };
};
};
/ {
compatible = "apple,j180d", "apple,t6022", "apple,arm-platform";
model = "Apple Mac Pro (M2 Ultra, 2023)";
+ chassis-type = "server";
+
aliases {
+ atcphy0 = &atcphy0;
+ atcphy1 = &atcphy1;
+ atcphy2 = &atcphy2;
+ atcphy3 = &atcphy3;
+ atcphy4 = &atcphy0_die1;
+ atcphy5 = &atcphy1_die1;
+ atcphy6 = &atcphy2_die1;
+ atcphy7 = &atcphy3_die1;
nvram = &nvram;
serial0 = &serial0;
};
interrupt-parent = <&pinctrl_ap>;
interrupts = <44 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
+
+ typec2: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C Back 1";
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec2_connector_hs: endpoint {
+ remote-endpoint = <&dwc3_2_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec2_connector_ss: endpoint {
+ remote-endpoint = <&atcphy2_typec_lanes>;
+ };
+ };
+ };
+ };
};
hpm3: usb-pd@3c {
interrupt-parent = <&pinctrl_ap>;
interrupts = <44 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
+
+ typec3: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C Back 2";
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec3_connector_hs: endpoint {
+ remote-endpoint = <&dwc3_3_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec3_connector_ss: endpoint {
+ remote-endpoint = <&atcphy3_typec_lanes>;
+ };
+ };
+ };
+ };
};
/* hpm4 and hpm5 included from t6022-jxxxd.dtsi */
interrupt-parent = <&pinctrl_ap>;
interrupts = <44 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
+
+ typec6: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C Back 5";
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec6_connector_hs: endpoint {
+ remote-endpoint = <&dwc3_6_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec6_connector_ss: endpoint {
+ remote-endpoint = <&atcphy6_typec_lanes>;
+ };
+ };
+ };
+ };
};
hpm7: usb-pd@3e {
interrupt-parent = <&pinctrl_ap>;
interrupts = <44 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
+
+ typec7: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C Back 6";
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec7_connector_hs: endpoint {
+ remote-endpoint = <&dwc3_7_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec7_connector_ss: endpoint {
+ remote-endpoint = <&atcphy7_typec_lanes>;
+ };
+ };
+ };
+ };
};
};
+&typec4 {
+ label = "USB-C Back 3";
+};
+
+&typec5 {
+ label = "USB-C Back 4";
+};
+
/* USB Type C Front */
&i2c3 {
status = "okay";
interrupt-parent = <&pinctrl_ap>;
interrupts = <60 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
+
+ typec0: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C Top Right";
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec0_connector_hs: endpoint {
+ remote-endpoint = <&dwc3_0_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec0_connector_ss: endpoint {
+ remote-endpoint = <&atcphy0_typec_lanes>;
+ };
+ };
+ };
+ };
};
hpm1: usb-pd@3f {
interrupt-parent = <&pinctrl_ap>;
interrupts = <60 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
+
+ typec1: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C Top Left";
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec1_connector_hs: endpoint {
+ remote-endpoint = <&dwc3_1_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec1_connector_ss: endpoint {
+ remote-endpoint = <&atcphy1_typec_lanes>;
+ };
+ };
+ };
+ };
+ };
+};
+
+/* USB controllers */
+&dwc3_0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dwc3_0_hs: endpoint {
+ remote-endpoint = <&typec0_connector_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dwc3_0_ss: endpoint {
+ remote-endpoint = <&atcphy0_usb3>;
+ };
+ };
+ };
+};
+
+&dwc3_1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dwc3_1_hs: endpoint {
+ remote-endpoint = <&typec1_connector_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dwc3_1_ss: endpoint {
+ remote-endpoint = <&atcphy1_usb3>;
+ };
+ };
+ };
+};
+
+&dwc3_2 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dwc3_2_hs: endpoint {
+ remote-endpoint = <&typec2_connector_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dwc3_2_ss: endpoint {
+ remote-endpoint = <&atcphy2_usb3>;
+ };
+ };
+ };
+};
+
+&dwc3_3 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dwc3_3_hs: endpoint {
+ remote-endpoint = <&typec3_connector_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dwc3_3_ss: endpoint {
+ remote-endpoint = <&atcphy3_usb3>;
+ };
+ };
+ };
+};
+
+/* USB controllers on die 1 */
+&dwc3_2_die1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dwc3_6_hs: endpoint {
+ remote-endpoint = <&typec6_connector_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dwc3_6_ss: endpoint {
+ remote-endpoint = <&atcphy6_usb3>;
+ };
+ };
+ };
+};
+
+&dwc3_3_die1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dwc3_7_hs: endpoint {
+ remote-endpoint = <&typec7_connector_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dwc3_7_ss: endpoint {
+ remote-endpoint = <&atcphy7_usb3>;
+ };
+ };
+ };
+};
+
+/* Type-C PHYs */
+&atcphy0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ atcphy0_typec_lanes: endpoint {
+ remote-endpoint = <&typec0_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ atcphy0_usb3: endpoint {
+ remote-endpoint = <&dwc3_0_ss>;
+ };
+ };
+ };
+};
+
+&atcphy1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ atcphy1_typec_lanes: endpoint {
+ remote-endpoint = <&typec1_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ atcphy1_usb3: endpoint {
+ remote-endpoint = <&dwc3_1_ss>;
+ };
+ };
+ };
+};
+
+&atcphy2 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ atcphy2_typec_lanes: endpoint {
+ remote-endpoint = <&typec2_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ atcphy2_usb3: endpoint {
+ remote-endpoint = <&dwc3_2_ss>;
+ };
+ };
+ };
+};
+
+&atcphy3 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ atcphy3_typec_lanes: endpoint {
+ remote-endpoint = <&typec3_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ atcphy3_usb3: endpoint {
+ remote-endpoint = <&dwc3_3_ss>;
+ };
+ };
+ };
+};
+
+&atcphy2_die1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ atcphy6_typec_lanes: endpoint {
+ remote-endpoint = <&typec6_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ atcphy6_usb3: endpoint {
+ remote-endpoint = <&dwc3_6_ss>;
+ };
+ };
+ };
+};
+
+&atcphy3_die1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ atcphy7_typec_lanes: endpoint {
+ remote-endpoint = <&typec7_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ atcphy7_usb3: endpoint {
+ remote-endpoint = <&dwc3_7_ss>;
+ };
+ };
};
};
/ {
compatible = "apple,j475d", "apple,t6022", "apple,arm-platform";
model = "Apple Mac Studio (M2 Ultra, 2023)";
+
+ aliases {
+ atcphy4 = &atcphy0_die1;
+ atcphy5 = &atcphy1_die1;
+ };
};
&framebuffer0 {
status = "okay";
};
+&typec4 {
+ label = "USB-C Front Right";
+};
+
+&typec5 {
+ label = "USB-C Front Left";
+};
+
+/* delete unused USB nodes on die 1 */
+/delete-node/ &dwc3_2_dart_0_die1;
+/delete-node/ &dwc3_2_dart_1_die1;
+/delete-node/ &dwc3_2_die1;
+/delete-node/ &atcphy2_die1;
+
+/delete-node/ &dwc3_3_dart_0_die1;
+/delete-node/ &dwc3_3_dart_1_die1;
+/delete-node/ &dwc3_3_die1;
+/delete-node/ &atcphy3_die1;
+
+/* delete unused always-on power-domains on die 1 */
+/delete-node/ &ps_atc2_usb_aon_die1;
+/delete-node/ &ps_atc2_usb_die1;
+
+/delete-node/ &ps_atc3_usb_aon_die1;
+/delete-node/ &ps_atc3_usb_die1;
+
&wifi0 {
compatible = "pci14e4,4434";
brcm,board-type = "apple,canary";
interrupt-parent = <&pinctrl_ap>;
interrupts = <44 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
+
+ typec4: connector {
+ compatible = "usb-c-connector";
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec4_connector_hs: endpoint {
+ remote-endpoint = <&dwc3_4_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec4_connector_ss: endpoint {
+ remote-endpoint = <&atcphy4_typec_lanes>;
+ };
+ };
+ };
+ };
};
/* front-left */
interrupt-parent = <&pinctrl_ap>;
interrupts = <44 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
+
+ typec5: connector {
+ compatible = "usb-c-connector";
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec5_connector_hs: endpoint {
+ remote-endpoint = <&dwc3_5_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec5_connector_ss: endpoint {
+ remote-endpoint = <&atcphy5_typec_lanes>;
+ };
+ };
+ };
+ };
+ };
+};
+
+
+/* USB controllers on die 1 */
+&dwc3_0_die1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dwc3_4_hs: endpoint {
+ remote-endpoint = <&typec4_connector_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dwc3_4_ss: endpoint {
+ remote-endpoint = <&atcphy4_usb3>;
+ };
+ };
+ };
+};
+
+&dwc3_1_die1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dwc3_5_hs: endpoint {
+ remote-endpoint = <&typec5_connector_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dwc3_5_ss: endpoint {
+ remote-endpoint = <&atcphy5_usb3>;
+ };
+ };
+ };
+};
+
+/* Type-C PHYs */
+&atcphy0_die1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ atcphy4_typec_lanes: endpoint {
+ remote-endpoint = <&typec4_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ atcphy4_usb3: endpoint {
+ remote-endpoint = <&dwc3_4_ss>;
+ };
+ };
+ };
+};
+
+&atcphy1_die1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ atcphy5_typec_lanes: endpoint {
+ remote-endpoint = <&typec5_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ atcphy5_usb3: endpoint {
+ remote-endpoint = <&dwc3_5_ss>;
+ };
+ };
};
};
nvmem-cell-names = "shutdown_flag", "boot_stage",
"boot_error_count", "panic_count";
};
+
+ rtc {
+ compatible = "apple,smc-rtc";
+ nvmem-cells = <&rtc_offset>;
+ nvmem-cell-names = "rtc_offset";
+ };
};
pinctrl_smc: pinctrl@2a2820000 {
reg = <0x4 0x4e80000 0 0x4000>;
};
+
+ DIE_NODE(dwc3_0): usb@702280000 {
+ compatible = "apple,t6020-dwc3", "apple,t8103-dwc3";
+ reg = <0x7 0x02280000 0x0 0xcd00>, <0x7 0x0228cd00 0x0 0x3200>;
+ reg-names = "dwc3-core", "dwc3-apple";
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1256 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "host";
+ iommus = <&DIE_NODE(dwc3_0_dart_0) 0>,
+ <&DIE_NODE(dwc3_0_dart_1) 1>;
+ power-domains = <&DIE_NODE(ps_atc0_usb)>;
+ resets = <&DIE_NODE(atcphy0)>;
+ phys = <&DIE_NODE(atcphy0) PHY_TYPE_USB2>, <&DIE_NODE(atcphy0) PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+
+ DIE_NODE(dwc3_0_dart_0): iommu@702f00000 {
+ compatible = "apple,t6020-dart", "apple,t8110-dart";
+ reg = <0x7 0x02f00000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1260 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&DIE_NODE(ps_atc0_usb)>;
+ #iommu-cells = <1>;
+ };
+
+ DIE_NODE(dwc3_0_dart_1): iommu@702f80000 {
+ compatible = "apple,t6020-dart", "apple,t8110-dart";
+ reg = <0x7 0x02f80000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1260 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&DIE_NODE(ps_atc0_usb)>;
+ #iommu-cells = <1>;
+ };
+
+ DIE_NODE(atcphy0): phy@703000000 {
+ compatible = "apple,t6020-atcphy", "apple,t8103-atcphy";
+ reg = <0x7 0x03000000 0x0 0x4c000>,
+ <0x7 0x03050000 0x0 0x8000>,
+ <0x7 0x00000000 0x0 0x4000>,
+ <0x7 0x02a90000 0x0 0x4000>,
+ <0x7 0x02a84000 0x0 0x4000>;
+ reg-names = "core", "lpdptx", "axi2af", "usb2phy",
+ "pipehandler";
+
+ #phy-cells = <1>;
+ #reset-cells = <0>;
+
+ orientation-switch;
+ mode-switch;
+ power-domains = <&DIE_NODE(ps_atc0_usb)>;
+ };
+
+ DIE_NODE(dwc3_1): usb@b02280000 {
+ compatible = "apple,t6020-dwc3", "apple,t8103-dwc3";
+ reg = <0xb 0x02280000 0x0 0xcd00>, <0xb 0x0228cd00 0x0 0x3200>;
+ reg-names = "dwc3-core", "dwc3-apple";
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1274 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "host";
+ iommus = <&DIE_NODE(dwc3_1_dart_0) 0>,
+ <&DIE_NODE(dwc3_1_dart_1) 1>;
+ power-domains = <&DIE_NODE(ps_atc1_usb)>;
+ resets = <&DIE_NODE(atcphy1)>;
+ phys = <&DIE_NODE(atcphy1) PHY_TYPE_USB2>, <&DIE_NODE(atcphy1) PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+
+ DIE_NODE(dwc3_1_dart_0): iommu@b02f00000 {
+ compatible = "apple,t6020-dart", "apple,t8110-dart";
+ reg = <0xb 0x02f00000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1278 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&DIE_NODE(ps_atc1_usb)>;
+ #iommu-cells = <1>;
+ };
+
+ DIE_NODE(dwc3_1_dart_1): iommu@b02f80000 {
+ compatible = "apple,t6020-dart", "apple,t8110-dart";
+ reg = <0xb 0x02f80000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1278 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&DIE_NODE(ps_atc1_usb)>;
+ #iommu-cells = <1>;
+ };
+
+ DIE_NODE(atcphy1): phy@b03000000 {
+ compatible = "apple,t6020-atcphy", "apple,t8103-atcphy";
+ reg = <0xb 0x03000000 0x0 0x4c000>,
+ <0xb 0x03050000 0x0 0x8000>,
+ <0xb 0x00000000 0x0 0x4000>,
+ <0xb 0x02a90000 0x0 0x4000>,
+ <0xb 0x02a84000 0x0 0x4000>;
+ reg-names = "core", "lpdptx", "axi2af", "usb2phy",
+ "pipehandler";
+
+ #phy-cells = <1>;
+ #reset-cells = <0>;
+
+ orientation-switch;
+ mode-switch;
+ power-domains = <&DIE_NODE(ps_atc1_usb)>;
+ };
+
+ DIE_NODE(dwc3_2): usb@f02280000 {
+ compatible = "apple,t6020-dwc3", "apple,t8103-dwc3";
+ reg = <0xf 0x02280000 0x0 0xcd00>, <0xf 0x0228cd00 0x0 0x3200>;
+ reg-names = "dwc3-core", "dwc3-apple";
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1292 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "host";
+ iommus = <&DIE_NODE(dwc3_2_dart_0) 0>,
+ <&DIE_NODE(dwc3_2_dart_1) 1>;
+ power-domains = <&DIE_NODE(ps_atc2_usb)>;
+ resets = <&DIE_NODE(atcphy2)>;
+ phys = <&DIE_NODE(atcphy2) PHY_TYPE_USB2>, <&DIE_NODE(atcphy2) PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+
+ DIE_NODE(dwc3_2_dart_0): iommu@f02f00000 {
+ compatible = "apple,t6020-dart", "apple,t8110-dart";
+ reg = <0xf 0x02f00000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1296 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&DIE_NODE(ps_atc2_usb)>;
+ #iommu-cells = <1>;
+ };
+
+ DIE_NODE(dwc3_2_dart_1): iommu@f02f80000 {
+ compatible = "apple,t6020-dart", "apple,t8110-dart";
+ reg = <0xf 0x02f80000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1296 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&DIE_NODE(ps_atc2_usb)>;
+ #iommu-cells = <1>;
+ };
+
+ DIE_NODE(atcphy2): phy@f03000000 {
+ compatible = "apple,t6020-atcphy", "apple,t8103-atcphy";
+ reg = <0xf 0x03000000 0x0 0x4c000>,
+ <0xf 0x03050000 0x0 0x8000>,
+ <0xf 0x00000000 0x0 0x4000>,
+ <0xf 0x02a90000 0x0 0x4000>,
+ <0xf 0x02a84000 0x0 0x4000>;
+ reg-names = "core", "lpdptx", "axi2af", "usb2phy",
+ "pipehandler";
+
+ #phy-cells = <1>;
+ #reset-cells = <0>;
+
+ orientation-switch;
+ mode-switch;
+ power-domains = <&DIE_NODE(ps_atc2_usb)>;
+ };
+
+ DIE_NODE(dwc3_3): usb@1302280000 {
+ compatible = "apple,t6020-dwc3", "apple,t8103-dwc3";
+ reg = <0x13 0x02280000 0x0 0xcd00>, <0x13 0x0228cd00 0x0 0x3200>;
+ reg-names = "dwc3-core", "dwc3-apple";
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1310 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "host";
+ iommus = <&DIE_NODE(dwc3_3_dart_0) 0>,
+ <&DIE_NODE(dwc3_3_dart_1) 1>;
+ power-domains = <&DIE_NODE(ps_atc3_usb)>;
+ resets = <&DIE_NODE(atcphy3)>;
+ phys = <&DIE_NODE(atcphy3) PHY_TYPE_USB2>, <&DIE_NODE(atcphy3) PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+
+ DIE_NODE(dwc3_3_dart_0): iommu@1302f00000 {
+ compatible = "apple,t6020-dart", "apple,t8110-dart";
+ reg = <0x13 0x02f00000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1314 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&DIE_NODE(ps_atc3_usb)>;
+ #iommu-cells = <1>;
+ };
+
+ DIE_NODE(dwc3_3_dart_1): iommu@1302f80000 {
+ compatible = "apple,t6020-dart", "apple,t8110-dart";
+ reg = <0x13 0x02f80000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1314 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&DIE_NODE(ps_atc3_usb)>;
+ #iommu-cells = <1>;
+ };
+
+ DIE_NODE(atcphy3): phy@1303000000 {
+ compatible = "apple,t6020-atcphy", "apple,t8103-atcphy";
+ reg = <0x13 0x03000000 0x0 0x4c000>,
+ <0x13 0x03050000 0x0 0x8000>,
+ <0x13 0x00000000 0x0 0x4000>,
+ <0x13 0x02a90000 0x0 0x4000>,
+ <0x13 0x02a84000 0x0 0x4000>;
+ reg-names = "core", "lpdptx", "axi2af", "usb2phy",
+ "pipehandler";
+
+ #phy-cells = <1>;
+ #reset-cells = <0>;
+
+ orientation-switch;
+ mode-switch;
+ power-domains = <&DIE_NODE(ps_atc3_usb)>;
+ };
/ {
compatible = "apple,j274", "apple,t8103", "apple,arm-platform";
model = "Apple Mac mini (M1, 2020)";
+ chassis-type = "desktop";
aliases {
ethernet0 = ðernet0;
brcm,board-type = "apple,atlantisb";
};
+/*
+ * Provide labels for the USB type C ports.
+ */
+
+&typec0 {
+ label = "USB-C Back-left";
+};
+
+&typec1 {
+ label = "USB-C Back-right";
+};
+
/*
* Force the bus number assignments so that we can declare some of the
* on-board devices and properties that are populated by the bootloader
/ {
compatible = "apple,j293", "apple,t8103", "apple,arm-platform";
model = "Apple MacBook Pro (13-inch, M1, 2020)";
+ chassis-type = "laptop";
/*
* All of those are used by the bootloader to pass calibration
brcm,board-type = "apple,honshu";
};
+/*
+ * Provide labels for the USB type C ports.
+ */
+
+&typec0 {
+ label = "USB-C Left-back";
+};
+
+&typec1 {
+ label = "USB-C Left-front";
+};
+
&i2c2 {
status = "okay";
};
/ {
compatible = "apple,j313", "apple,t8103", "apple,arm-platform";
model = "Apple MacBook Air (M1, 2020)";
+ chassis-type = "laptop";
led-controller {
compatible = "pwm-leds";
&fpwm1 {
status = "okay";
};
+
+/*
+ * Provide labels for the USB type C ports.
+ */
+
+&typec0 {
+ label = "USB-C Left-back";
+};
+
+&typec1 {
+ label = "USB-C Left-front";
+};
/ {
compatible = "apple,j456", "apple,t8103", "apple,arm-platform";
model = "Apple iMac (24-inch, 4x USB-C, M1, 2021)";
+ chassis-type = "all-in-one";
aliases {
ethernet0 = ðernet0;
};
};
+/*
+ * Provide labels for the USB type C ports.
+ */
+
+&typec0 {
+ label = "USB-C Back-right";
+};
+
+&typec1 {
+ label = "USB-C Back-right-middle";
+};
+
/*
* Force the bus number assignments so that we can declare some of the
* on-board devices and properties that are populated by the bootloader
/ {
compatible = "apple,j457", "apple,t8103", "apple,arm-platform";
model = "Apple iMac (24-inch, 2x USB-C, M1, 2021)";
+ chassis-type = "all-in-one";
aliases {
ethernet0 = ðernet0;
brcm,board-type = "apple,santorini";
};
+/*
+ * Provide labels for the USB type C ports.
+ */
+
+&typec0 {
+ label = "USB-C Back-right";
+};
+
+&typec1 {
+ label = "USB-C Back-left";
+};
+
/*
* Force the bus number assignments so that we can declare some of the
* on-board devices and properties that are populated by the bootloader
serial0 = &serial0;
serial2 = &serial2;
wifi0 = &wifi0;
+ atcphy0 = &atcphy0;
+ atcphy1 = &atcphy1;
};
chosen {
interrupt-parent = <&pinctrl_ap>;
interrupts = <106 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
+
+ typec0: connector {
+ compatible = "usb-c-connector";
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec0_connector_hs: endpoint {
+ remote-endpoint = <&dwc3_0_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec0_connector_ss: endpoint {
+ remote-endpoint = <&atcphy0_typec_lanes>;
+ };
+ };
+ };
+ };
};
hpm1: usb-pd@3f {
interrupt-parent = <&pinctrl_ap>;
interrupts = <106 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
+
+ typec1: connector {
+ compatible = "usb-c-connector";
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec1_connector_hs: endpoint {
+ remote-endpoint = <&dwc3_1_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec1_connector_ss: endpoint {
+ remote-endpoint = <&atcphy1_typec_lanes>;
+ };
+ };
+ };
+ };
+ };
+};
+
+/* USB controllers */
+&dwc3_0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dwc3_0_hs: endpoint {
+ remote-endpoint = <&typec0_connector_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dwc3_0_ss: endpoint {
+ remote-endpoint = <&atcphy0_usb3>;
+ };
+ };
+ };
+};
+
+&dwc3_1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dwc3_1_hs: endpoint {
+ remote-endpoint = <&typec1_connector_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dwc3_1_ss: endpoint {
+ remote-endpoint = <&atcphy1_usb3>;
+ };
+ };
+ };
+};
+
+/* Type-C PHYs */
+&atcphy0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ atcphy0_typec_lanes: endpoint {
+ remote-endpoint = <&typec0_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ atcphy0_usb3: endpoint {
+ remote-endpoint = <&dwc3_0_ss>;
+ };
+ };
+ };
+};
+
+&atcphy1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ atcphy1_typec_lanes: endpoint {
+ remote-endpoint = <&typec1_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ atcphy1_usb3: endpoint {
+ remote-endpoint = <&dwc3_1_ss>;
+ };
+ };
};
};
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "gfx";
+ power-domains = <&ps_pmp>;
};
ps_dcs4: power-controller@320 {
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "atc0_usb_aon";
+ apple,always-on; /* Needs to stay on for dwc3 to work */
};
ps_atc1_usb_aon: power-controller@90 {
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "atc1_usb_aon";
+ apple,always-on; /* Needs to stay on for dwc3 to work */
};
ps_atc0_usb: power-controller@98 {
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/apple.h>
#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/phy/phy.h>
/ {
compatible = "apple,t8103", "apple,arm-platform";
nvmem-cell-names = "shutdown_flag", "boot_stage",
"boot_error_count", "panic_count";
};
+
+ rtc {
+ compatible = "apple,smc-rtc";
+ nvmem-cells = <&rtc_offset>;
+ nvmem-cell-names = "rtc_offset";
+ };
};
smc_mbox: mbox@23e408000 {
resets = <&ps_ans2>;
};
+ dwc3_0: usb@382280000 {
+ compatible = "apple,t8103-dwc3";
+ reg = <0x3 0x82280000 0x0 0xcd00>, <0x3 0x8228cd00 0x0 0x3200>;
+ reg-names = "dwc3-core", "dwc3-apple";
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 777 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "host";
+ iommus = <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>;
+ power-domains = <&ps_atc0_usb>;
+ resets = <&atcphy0>;
+ phys = <&atcphy0 PHY_TYPE_USB2>, <&atcphy0 PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+
+ dwc3_0_dart_0: iommu@382f00000 {
+ compatible = "apple,t8103-dart";
+ reg = <0x3 0x82f00000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ power-domains = <&ps_atc0_usb>;
+ };
+
+ dwc3_0_dart_1: iommu@382f80000 {
+ compatible = "apple,t8103-dart";
+ reg = <0x3 0x82f80000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ power-domains = <&ps_atc0_usb>;
+ };
+
+ atcphy0: phy@383000000 {
+ compatible = "apple,t8103-atcphy";
+ reg = <0x3 0x83000000 0x0 0x4c000>,
+ <0x3 0x83050000 0x0 0x8000>,
+ <0x3 0x80000000 0x0 0x4000>,
+ <0x3 0x82a90000 0x0 0x4000>,
+ <0x3 0x82a84000 0x0 0x4000>;
+ reg-names = "core", "lpdptx", "axi2af", "usb2phy",
+ "pipehandler";
+
+ #phy-cells = <1>;
+ #reset-cells = <0>;
+
+ orientation-switch;
+ mode-switch;
+ power-domains = <&ps_atc0_usb>;
+ };
+
+ dwc3_1: usb@502280000 {
+ compatible = "apple,t8103-dwc3";
+ reg = <0x5 0x02280000 0x0 0xcd00>, <0x5 0x0228cd00 0x0 0x3200>;
+ reg-names = "dwc3-core", "dwc3-apple";
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 857 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "host";
+ iommus = <&dwc3_1_dart_0 0>, <&dwc3_1_dart_1 1>;
+ power-domains = <&ps_atc1_usb>;
+ resets = <&atcphy1>;
+ phys = <&atcphy1 PHY_TYPE_USB2>, <&atcphy1 PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+
+ dwc3_1_dart_0: iommu@502f00000 {
+ compatible = "apple,t8103-dart";
+ reg = <0x5 0x02f00000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 861 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ power-domains = <&ps_atc1_usb>;
+ };
+
+ dwc3_1_dart_1: iommu@502f80000 {
+ compatible = "apple,t8103-dart";
+ reg = <0x5 0x02f80000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 861 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ power-domains = <&ps_atc1_usb>;
+ };
+
+ atcphy1: phy@503000000 {
+ compatible = "apple,t8103-atcphy";
+ reg = <0x5 0x03000000 0x0 0x4c000>,
+ <0x5 0x03050000 0x0 0x8000>,
+ <0x5 0x0 0x0 0x4000>,
+ <0x5 0x02a90000 0x0 0x4000>,
+ <0x5 0x02a84000 0x0 0x4000>;
+ reg-names = "core", "lpdptx", "axi2af", "usb2phy",
+ "pipehandler";
+
+ #phy-cells = <1>;
+ #reset-cells = <0>;
+
+ orientation-switch;
+ mode-switch;
+ power-domains = <&ps_atc1_usb>;
+ };
+
pcie0_dart_0: iommu@681008000 {
compatible = "apple,t8103-dart";
reg = <0x6 0x81008000 0x0 0x4000>;
/ {
compatible = "apple,j413", "apple,t8112", "apple,arm-platform";
model = "Apple MacBook Air (13-inch, M2, 2022)";
+ chassis-type = "laptop";
aliases {
bluetooth0 = &bluetooth0;
};
};
+/*
+ * Provide labels for the USB type C ports.
+ */
+
+&typec0 {
+ label = "USB-C Left-back";
+};
+
+&typec1 {
+ label = "USB-C Left-front";
+};
+
&i2c0 {
/* MagSafe port */
hpm5: usb-pd@3a {
/ {
compatible = "apple,j415", "apple,t8112", "apple,arm-platform";
model = "Apple MacBook Air (15-inch, M2, 2023)";
+ chassis-type = "laptop";
aliases {
bluetooth0 = &bluetooth0;
};
};
+/*
+ * Provide labels for the USB type C ports.
+ */
+
+&typec0 {
+ label = "USB-C Left-back";
+};
+
+&typec1 {
+ label = "USB-C Left-front";
+};
+
&i2c0 {
/* MagSafe port */
hpm5: usb-pd@3a {
/ {
compatible = "apple,j473", "apple,t8112", "apple,arm-platform";
model = "Apple Mac mini (M2, 2023)";
+ chassis-type = "desktop";
aliases {
ethernet0 = ðernet0;
};
};
+/*
+ * Keep the power-domains used for the HDMI port on.
+ */
+&framebuffer0 {
+ power-domains = <&ps_dispext_cpu0>, <&ps_dptx_ext_phy>;
+};
+
+/*
+ * The M2 Mac mini uses dispext for the HDMI output so it's not necessary to
+ * keep disp0 power-domains always-on.
+ */
+&ps_disp0_sys {
+ /delete-property/ apple,always-on;
+};
+
+&ps_disp0_fe {
+ /delete-property/ apple,always-on;
+};
+
/*
* Force the bus number assignments so that we can declare some of the
* on-board devices and properties that are populated by the bootloader
&pcie2_dart {
status = "okay";
};
+
+/*
+ * Provide labels for the USB type C ports.
+ */
+
+&typec0 {
+ label = "USB-C Back-left";
+};
+
+&typec1 {
+ label = "USB-C Back-right";
+};
/ {
compatible = "apple,j493", "apple,t8112", "apple,arm-platform";
model = "Apple MacBook Pro (13-inch, M2, 2022)";
+ chassis-type = "laptop";
/*
* All of those are used by the bootloader to pass calibration
};
};
+/*
+ * Provide labels for the USB type C ports.
+ */
+
+&typec0 {
+ label = "USB-C Left-back";
+};
+
+&typec1 {
+ label = "USB-C Left-front";
+};
+
&i2c4 {
status = "okay";
};
/ {
aliases {
+ atcphy0 = &atcphy0;
+ atcphy1 = &atcphy1;
serial0 = &serial0;
serial2 = &serial2;
};
interrupt-parent = <&pinctrl_ap>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
+
+ typec0: connector {
+ compatible = "usb-c-connector";
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec0_connector_hs: endpoint {
+ remote-endpoint = <&dwc3_0_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec0_connector_ss: endpoint {
+ remote-endpoint = <&atcphy0_typec_lanes>;
+ };
+ };
+ };
+ };
};
hpm1: usb-pd@3f {
interrupt-parent = <&pinctrl_ap>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
+
+ typec1: connector {
+ compatible = "usb-c-connector";
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec1_connector_hs: endpoint {
+ remote-endpoint = <&dwc3_1_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec1_connector_ss: endpoint {
+ remote-endpoint = <&atcphy1_typec_lanes>;
+ };
+ };
+ };
+ };
+ };
+};
+
+/* USB controllers */
+&dwc3_0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dwc3_0_hs: endpoint {
+ remote-endpoint = <&typec0_connector_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dwc3_0_ss: endpoint {
+ remote-endpoint = <&atcphy0_usb3>;
+ };
+ };
+ };
+};
+
+&dwc3_1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dwc3_1_hs: endpoint {
+ remote-endpoint = <&typec1_connector_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dwc3_1_ss: endpoint {
+ remote-endpoint = <&atcphy1_usb3>;
+ };
+ };
+ };
+};
+
+/* Type-C PHYs */
+&atcphy0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ atcphy0_typec_lanes: endpoint {
+ remote-endpoint = <&typec0_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ atcphy0_usb3: endpoint {
+ remote-endpoint = <&dwc3_0_ss>;
+ };
+ };
+ };
+};
+
+&atcphy1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ atcphy1_typec_lanes: endpoint {
+ remote-endpoint = <&typec1_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ atcphy1_usb3: endpoint {
+ remote-endpoint = <&dwc3_1_ss>;
+ };
+ };
};
};
#include <dt-bindings/interrupt-controller/apple-aic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/apple.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/spmi/spmi.h>
/ {
nvmem-cell-names = "shutdown_flag", "boot_stage",
"boot_error_count", "panic_count";
};
+
+ rtc {
+ compatible = "apple,smc-rtc";
+ nvmem-cells = <&rtc_offset>;
+ nvmem-cell-names = "rtc_offset";
+ };
};
smc_mbox: mbox@23e408000 {
resets = <&ps_ans>;
};
+ dwc3_0: usb@382280000 {
+ compatible = "apple,t8112-dwc3", "apple,t8103-dwc3";
+ reg = <0x3 0x82280000 0x0 0xcd00>, <0x3 0x8228cd00 0x0 0x3200>;
+ reg-names = "dwc3-core", "dwc3-apple";
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 1031 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "host";
+ iommus = <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>;
+ power-domains = <&ps_atc0_usb>;
+ resets = <&atcphy0>;
+ phys = <&atcphy0 PHY_TYPE_USB2>, <&atcphy0 PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+
+ dwc3_0_dart_0: iommu@382f00000 {
+ compatible = "apple,t8110-dart";
+ reg = <0x3 0x82f00000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 1035 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ power-domains = <&ps_atc0_usb>;
+ };
+
+ dwc3_0_dart_1: iommu@382f80000 {
+ compatible = "apple,t8110-dart";
+ reg = <0x3 0x82f80000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 1035 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ power-domains = <&ps_atc0_usb>;
+ };
+
+ atcphy0: phy@383000000 {
+ compatible = "apple,t8112-atcphy", "apple,t8103-atcphy";
+ reg = <0x3 0x83000000 0x0 0x4c000>,
+ <0x3 0x83050000 0x0 0x8000>,
+ <0x3 0x80000000 0x0 0x4000>,
+ <0x3 0x82a90000 0x0 0x4000>,
+ <0x3 0x82a84000 0x0 0x4000>;
+ reg-names = "core", "lpdptx", "axi2af", "usb2phy",
+ "pipehandler";
+
+ #phy-cells = <1>;
+ #reset-cells = <0>;
+
+ orientation-switch;
+ mode-switch;
+ power-domains = <&ps_atc0_usb>;
+ };
+
+ dwc3_1: usb@502280000 {
+ compatible = "apple,t8112-dwc3", "apple,t8103-dwc3";
+ reg = <0x5 0x02280000 0x0 0xcd00>, <0x5 0x0228cd00 0x0 0x3200>;
+ reg-names = "dwc3-core", "dwc3-apple";
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 1112 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "host";
+ iommus = <&dwc3_1_dart_0 0>, <&dwc3_1_dart_1 1>;
+ power-domains = <&ps_atc1_usb>;
+ resets = <&atcphy1>;
+ phys = <&atcphy1 PHY_TYPE_USB2>, <&atcphy1 PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+
+ dwc3_1_dart_0: iommu@502f00000 {
+ compatible = "apple,t8110-dart";
+ reg = <0x5 0x02f00000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 1116 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ power-domains = <&ps_atc1_usb>;
+ };
+
+ dwc3_1_dart_1: iommu@502f80000 {
+ compatible = "apple,t8110-dart";
+ reg = <0x5 0x02f80000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 1116 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ power-domains = <&ps_atc1_usb>;
+ };
+
+ atcphy1: phy@503000000 {
+ compatible = "apple,t8112-atcphy", "apple,t8103-atcphy";
+ reg = <0x5 0x03000000 0x0 0x4c000>,
+ <0x5 0x03050000 0x0 0x8000>,
+ <0x5 0x0 0x0 0x4000>,
+ <0x5 0x02a90000 0x0 0x4000>,
+ <0x5 0x02a84000 0x0 0x4000>;
+ reg-names = "core", "lpdptx", "axi2af", "usb2phy",
+ "pipehandler";
+
+ #phy-cells = <1>;
+ #reset-cells = <0>;
+
+ orientation-switch;
+ mode-switch;
+ power-domains = <&ps_atc1_usb>;
+ };
+
pcie0_dart: iommu@681008000 {
compatible = "apple,t8110-dart";
reg = <0x6 0x81008000 0x0 0x4000>;
clock-output-names = "bp:clock24mhz";
};
- block_0: virtio_block@1c170000 {
+ block_0: virtio-block@1c170000 {
compatible = "virtio,mmio";
reg = <0x0 0x1c170000 0x0 0x200>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
};
- net_0: virtio_net@1c180000 {
+ net_0: virtio-net@1c180000 {
compatible = "virtio,mmio";
reg = <0x0 0x1c180000 0x0 0x200>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
};
- rng_0: virtio_rng@1c190000 {
+ rng_0: virtio-rng@1c190000 {
compatible = "virtio,mmio";
reg = <0x0 0x1c190000 0x0 0x200>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
};
- p9_0: virtio_p9@1c1a0000 {
+ p9_0: virtio-p9@1c1a0000 {
compatible = "virtio,mmio";
reg = <0x0 0x1c1a0000 0x0 0x200>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
};
+ pmu@50000000 {
+ compatible = "arm,cmn-600";
+ reg = <0x0 0x50000000 0x0 0x4000000>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ arm,root-node = <0x804000>;
+ };
+
pcie_ctlr: pcie@28c0000000 {
device_type = "pci";
compatible = "pci-host-ecam-generic";
status = "disabled";
};
+ pm: watchdog@7d200000 {
+ compatible = "brcm,bcm2712-pm", "brcm,bcm2835-pm-wdt";
+ reg = <0x7d200000 0x604>;
+ reg-names = "pm";
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+ system-power-controller;
+ };
+
pinctrl: pinctrl@7d504100 {
compatible = "brcm,bcm2712c0-pinctrl";
reg = <0x7d504100 0x30>;
reg = <0x7d510700 0x20>;
};
+ random: rng@7d208000 {
+ compatible = "brcm,bcm2711-rng200";
+ reg = <0x7d208000 0x28>;
+ status = "okay";
+ };
+
interrupt-controller@7d517000 {
compatible = "brcm,bcm7271-l2-intc";
reg = <0x7d517000 0x10>;
partition@0 {
label = "cferom";
reg = <0x0 0x100000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x0 0x100000>;
nvmem-layout {
compatible = "fixed-layout";
+++ /dev/null
-/*
- * BSD LICENSE
- *
- * Copyright (c) 2016 Broadcom. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Broadcom Corporation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <dt-bindings/clock/bcm-ns2.h>
-
- osc: oscillator {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <25000000>;
- };
-
- lcpll_ddr: lcpll_ddr@6501d058 {
- #clock-cells = <1>;
- compatible = "brcm,ns2-lcpll-ddr";
- reg = <0x6501d058 0x20>,
- <0x6501c020 0x4>,
- <0x6501d04c 0x4>;
- clocks = <&osc>;
- clock-output-names = "lcpll_ddr", "pcie_sata_usb",
- "ddr", "ddr_ch2_unused",
- "ddr_ch3_unused", "ddr_ch4_unused",
- "ddr_ch5_unused";
- };
-
- lcpll_ports: lcpll_ports@6501d078 {
- #clock-cells = <1>;
- compatible = "brcm,ns2-lcpll-ports";
- reg = <0x6501d078 0x20>,
- <0x6501c020 0x4>,
- <0x6501d054 0x4>;
- clocks = <&osc>;
- clock-output-names = "lcpll_ports", "wan", "rgmii",
- "ports_ch2_unused",
- "ports_ch3_unused",
- "ports_ch4_unused",
- "ports_ch5_unused";
- };
-
- genpll_scr: genpll_scr@6501d098 {
- #clock-cells = <1>;
- compatible = "brcm,ns2-genpll-scr";
- reg = <0x6501d098 0x32>,
- <0x6501c020 0x4>,
- <0x6501d044 0x4>;
- clocks = <&osc>;
- clock-output-names = "genpll_scr", "scr", "fs",
- "audio_ref", "scr_ch3_unused",
- "scr_ch4_unused", "scr_ch5_unused";
- };
-
- iprocmed: iprocmed {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- iprocslow: iprocslow {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
- clock-div = <4>;
- clock-mult = <1>;
- };
-
- genpll_sw: genpll_sw@6501d0c4 {
- #clock-cells = <1>;
- compatible = "brcm,ns2-genpll-sw";
- reg = <0x6501d0c4 0x32>,
- <0x6501c020 0x4>,
- <0x6501d044 0x4>;
- clocks = <&osc>;
- clock-output-names = "genpll_sw", "rpe", "250", "nic",
- "chimp", "port", "sdio";
- };
&ssp0 {
status = "okay";
-
- slic@0 {
- compatible = "silabs,si3226x";
- reg = <0>;
- spi-max-frequency = <5000000>;
- spi-cpha;
- spi-cpol;
- pl022,interface = <0>;
- pl022,slave-tx-disable = <0>;
- pl022,com-mode = <0>;
- pl022,rx-level-trig = <1>;
- pl022,tx-level-trig = <1>;
- pl022,ctrl-len = <11>;
- pl022,wait-state = <0>;
- pl022,duplex = <0>;
- };
};
&ssp1 {
status = "okay";
- at25@0 {
+ eeprom@0 {
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <5000000>;
- at25,byte-len = <0x8000>;
- at25,addr-mode = <2>;
- at25,page-size = <64>;
+ size = <0x8000>;
+ address-width = <16>;
+ pagesize = <64>;
spi-cpha;
spi-cpol;
pl022,interface = <0>;
};
&nand {
- nandcs@0 {
+ nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-ecc-mode = "hw";
};
&nand {
- nandcs@0 {
+ nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-ecc-mode = "hw";
<&A57_3>;
};
+ osc: clock-25000000 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ };
+
+ iprocmed: iprocmed {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ iprocslow: iprocslow {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+
pcie0: pcie@20020000 {
compatible = "brcm,iproc-pcie";
reg = <0 0x20020000 0 0x1000>;
ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
brcm,pcie-ob;
- brcm,pcie-ob-oarr-size;
brcm,pcie-ob-axi-offset = <0x00000000>;
status = "disabled";
ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
brcm,pcie-ob;
- brcm,pcie-ob-oarr-size;
brcm,pcie-ob-axi-offset = <0x30000000>;
status = "disabled";
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
- #include "ns2-clock.dtsi"
-
enet: ethernet@61000000 {
compatible = "brcm,ns2-amac";
reg = <0x61000000 0x1000>,
#iommu-cells = <1>;
};
+ lcpll_ddr: clock-controller@6501d058 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-lcpll-ddr";
+ reg = <0x6501d058 0x20>,
+ <0x6501c020 0x4>,
+ <0x6501d04c 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "lcpll_ddr", "pcie_sata_usb",
+ "ddr", "ddr_ch2_unused",
+ "ddr_ch3_unused", "ddr_ch4_unused",
+ "ddr_ch5_unused";
+ };
+
+ lcpll_ports: clock-controller@6501d078 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-lcpll-ports";
+ reg = <0x6501d078 0x20>,
+ <0x6501c020 0x4>,
+ <0x6501d054 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "lcpll_ports", "wan", "rgmii",
+ "ports_ch2_unused",
+ "ports_ch3_unused",
+ "ports_ch4_unused",
+ "ports_ch5_unused";
+ };
+
+ genpll_scr: clock-controller@6501d098 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-genpll-scr";
+ reg = <0x6501d098 0x32>,
+ <0x6501c020 0x4>,
+ <0x6501d044 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "genpll_scr", "scr", "fs",
+ "audio_ref", "scr_ch3_unused",
+ "scr_ch4_unused", "scr_ch5_unused";
+ };
+
+ genpll_sw: clock-controller@6501d0c4 {
+ #clock-cells = <1>;
+ compatible = "brcm,ns2-genpll-sw";
+ reg = <0x6501d0c4 0x32>,
+ <0x6501c020 0x4>,
+ <0x6501d044 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "genpll_sw", "rpe", "250", "nic",
+ "chimp", "port", "sdio";
+ };
pinctrl: pinctrl@6501d130 {
compatible = "brcm,ns2-pinmux";
reg = <0x6501d130 0x08>,
ranges = <0 0x65590000 0x10000>;
pmu@9000 {
- compatible = "arm,cci-400-pmu,r1",
- "arm,cci-400-pmu";
+ compatible = "arm,cci-400-pmu,r1";
reg = <0x9000 0x4000>;
interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
reg = <0x66220000 0x28>;
};
- sata_phy: sata_phy@663f0100 {
+ sata_phy: sata-phy@663f0100 {
compatible = "brcm,iproc-ns2-sata-phy";
reg = <0x663f0100 0x1f00>,
<0x663f004c 0x10>;
};
};
- sdio0: sdhci@66420000 {
+ sdio0: mmc@66420000 {
compatible = "brcm,sdhci-iproc-cygnus";
reg = <0x66420000 0x100>;
interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- sdio1: sdhci@66430000 {
+ sdio1: mmc@66430000 {
compatible = "brcm,sdhci-iproc-cygnus";
reg = <0x66430000 0x100>;
interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- nand: nand@66460000 {
+ nand: nand-controller@66460000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x66460000 0x600>,
<0x67015408 0x600>,
interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "spi_l1_intr";
clocks = <&iprocmed>;
- clock-names = "iprocmed";
num-cs = <2>;
#address-cells = <1>;
#size-cells = <0>;
&nand {
status = "okay";
- nandcs@0 {
+ nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-ecc-mode = "hw";
+++ /dev/null
-/*
- * BSD LICENSE
- *
- * Copyright(c) 2016-2017 Broadcom. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Broadcom nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <dt-bindings/clock/bcm-sr.h>
-
- osc: oscillator {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
-
- crmu_ref25m: crmu_ref25m {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&osc>;
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- genpll0: genpll0@1d104 {
- #clock-cells = <1>;
- compatible = "brcm,sr-genpll0";
- reg = <0x0001d104 0x32>,
- <0x0001c854 0x4>;
- clocks = <&osc>;
- clock-output-names = "genpll0", "clk_125m", "clk_scr",
- "clk_250", "clk_pcie_axi",
- "clk_paxc_axi_x2",
- "clk_paxc_axi";
- };
-
- genpll2: genpll2@1d1ac {
- #clock-cells = <1>;
- compatible = "brcm,sr-genpll2";
- reg = <0x0001d1ac 0x32>,
- <0x0001c854 0x4>;
- clocks = <&osc>;
- clock-output-names = "genpll2", "clk_nic",
- "clk_ts_500_ref", "clk_125_nitro",
- "clk_chimp", "clk_nic_flash",
- "clk_fs";
- };
-
- genpll3: genpll3@1d1e0 {
- #clock-cells = <1>;
- compatible = "brcm,sr-genpll3";
- reg = <0x0001d1e0 0x32>,
- <0x0001c854 0x4>;
- clocks = <&osc>;
- clock-output-names = "genpll3", "clk_hsls",
- "clk_sdio";
- };
-
- genpll4: genpll4@1d214 {
- #clock-cells = <1>;
- compatible = "brcm,sr-genpll4";
- reg = <0x0001d214 0x32>,
- <0x0001c854 0x4>;
- clocks = <&osc>;
- clock-output-names = "genpll4", "clk_ccn",
- "clk_tpiu_pll", "clk_noc",
- "clk_chclk_fs4",
- "clk_bridge_fscpu";
- };
-
- genpll5: genpll5@1d248 {
- #clock-cells = <1>;
- compatible = "brcm,sr-genpll5";
- reg = <0x0001d248 0x32>,
- <0x0001c870 0x4>;
- clocks = <&osc>;
- clock-output-names = "genpll5", "clk_fs4_hf",
- "clk_crypto_ae", "clk_raid_ae";
- };
-
- lcpll0: lcpll0@1d0c4 {
- #clock-cells = <1>;
- compatible = "brcm,sr-lcpll0";
- reg = <0x0001d0c4 0x3c>,
- <0x0001c870 0x4>;
- clocks = <&osc>;
- clock-output-names = "lcpll0", "clk_sata_refp",
- "clk_sata_refn", "clk_sata_350",
- "clk_sata_500";
- };
-
- lcpll1: lcpll1@1d138 {
- #clock-cells = <1>;
- compatible = "brcm,sr-lcpll1";
- reg = <0x0001d138 0x3c>,
- <0x0001c870 0x4>;
- clocks = <&osc>;
- clock-output-names = "lcpll1", "clk_wan",
- "clk_usb_ref",
- "clk_crmu_ts";
- };
-
- hsls_clk: hsls_clk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&genpll3 1>;
- clock-div = <1>;
- clock-mult = <1>;
- };
-
- hsls_div2_clk: hsls_div2_clk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>;
- clock-div = <2>;
- clock-mult = <1>;
-
- };
-
- hsls_div4_clk: hsls_div4_clk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>;
- clock-div = <4>;
- clock-mult = <1>;
- };
-
- hsls_25m_clk: hsls_25m_clk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&crmu_ref25m>;
- clock-div = <1>;
- clock-mult = <1>;
- };
-
- hsls_25m_div2_clk: hsls_25m_div2_clk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&hsls_25m_clk>;
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- sdio0_clk: sdio0_clk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>;
- clock-div = <1>;
- clock-mult = <1>;
- };
-
- sdio1_clk: sdio1_clk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>;
- clock-div = <1>;
- clock-mult = <1>;
- };
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
- fs4: fs4 {
+ fs4: fs4-bus@67000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
msi-parent = <&gic_its 0x4300>;
#mbox-cells = <3>;
};
+ };
- raid0: raid@0 {
- compatible = "brcm,iproc-sba-v2";
- mboxes = <&raid_mbox 0 0x1 0xff00>,
- <&raid_mbox 1 0x1 0xff00>,
- <&raid_mbox 2 0x1 0xff00>,
- <&raid_mbox 3 0x1 0xff00>;
- };
+ raid0: raid-0 {
+ compatible = "brcm,iproc-sba-v2";
+ mboxes = <&raid_mbox 0 0x1 0xff00>,
+ <&raid_mbox 1 0x1 0xff00>,
+ <&raid_mbox 2 0x1 0xff00>,
+ <&raid_mbox 3 0x1 0xff00>;
+ };
- raid1: raid@1 {
- compatible = "brcm,iproc-sba-v2";
- mboxes = <&raid_mbox 4 0x1 0xff00>,
- <&raid_mbox 5 0x1 0xff00>,
- <&raid_mbox 6 0x1 0xff00>,
- <&raid_mbox 7 0x1 0xff00>;
- };
+ raid1: raid-1 {
+ compatible = "brcm,iproc-sba-v2";
+ mboxes = <&raid_mbox 4 0x1 0xff00>,
+ <&raid_mbox 5 0x1 0xff00>,
+ <&raid_mbox 6 0x1 0xff00>,
+ <&raid_mbox 7 0x1 0xff00>;
+ };
- raid2: raid@2 {
- compatible = "brcm,iproc-sba-v2";
- mboxes = <&raid_mbox 8 0x1 0xff00>,
- <&raid_mbox 9 0x1 0xff00>,
- <&raid_mbox 10 0x1 0xff00>,
- <&raid_mbox 11 0x1 0xff00>;
- };
+ raid2: raid-2 {
+ compatible = "brcm,iproc-sba-v2";
+ mboxes = <&raid_mbox 8 0x1 0xff00>,
+ <&raid_mbox 9 0x1 0xff00>,
+ <&raid_mbox 10 0x1 0xff00>,
+ <&raid_mbox 11 0x1 0xff00>;
+ };
- raid3: raid@3 {
- compatible = "brcm,iproc-sba-v2";
- mboxes = <&raid_mbox 12 0x1 0xff00>,
- <&raid_mbox 13 0x1 0xff00>,
- <&raid_mbox 14 0x1 0xff00>,
- <&raid_mbox 15 0x1 0xff00>;
- };
+ raid3: raid-3 {
+ compatible = "brcm,iproc-sba-v2";
+ mboxes = <&raid_mbox 12 0x1 0xff00>,
+ <&raid_mbox 13 0x1 0xff00>,
+ <&raid_mbox 14 0x1 0xff00>,
+ <&raid_mbox 15 0x1 0xff00>;
+ };
- raid4: raid@4 {
- compatible = "brcm,iproc-sba-v2";
- mboxes = <&raid_mbox 16 0x1 0xff00>,
- <&raid_mbox 17 0x1 0xff00>,
- <&raid_mbox 18 0x1 0xff00>,
- <&raid_mbox 19 0x1 0xff00>;
- };
+ raid4: raid-4 {
+ compatible = "brcm,iproc-sba-v2";
+ mboxes = <&raid_mbox 16 0x1 0xff00>,
+ <&raid_mbox 17 0x1 0xff00>,
+ <&raid_mbox 18 0x1 0xff00>,
+ <&raid_mbox 19 0x1 0xff00>;
+ };
- raid5: raid@5 {
- compatible = "brcm,iproc-sba-v2";
- mboxes = <&raid_mbox 20 0x1 0xff00>,
- <&raid_mbox 21 0x1 0xff00>,
- <&raid_mbox 22 0x1 0xff00>,
- <&raid_mbox 23 0x1 0xff00>;
- };
+ raid5: raid-5 {
+ compatible = "brcm,iproc-sba-v2";
+ mboxes = <&raid_mbox 20 0x1 0xff00>,
+ <&raid_mbox 21 0x1 0xff00>,
+ <&raid_mbox 22 0x1 0xff00>,
+ <&raid_mbox 23 0x1 0xff00>;
+ };
- raid6: raid@6 {
- compatible = "brcm,iproc-sba-v2";
- mboxes = <&raid_mbox 24 0x1 0xff00>,
- <&raid_mbox 25 0x1 0xff00>,
- <&raid_mbox 26 0x1 0xff00>,
- <&raid_mbox 27 0x1 0xff00>;
- };
+ raid6: raid-6 {
+ compatible = "brcm,iproc-sba-v2";
+ mboxes = <&raid_mbox 24 0x1 0xff00>,
+ <&raid_mbox 25 0x1 0xff00>,
+ <&raid_mbox 26 0x1 0xff00>,
+ <&raid_mbox 27 0x1 0xff00>;
+ };
- raid7: raid@7 {
- compatible = "brcm,iproc-sba-v2";
- mboxes = <&raid_mbox 28 0x1 0xff00>,
- <&raid_mbox 29 0x1 0xff00>,
- <&raid_mbox 30 0x1 0xff00>,
- <&raid_mbox 31 0x1 0xff00>;
- };
+ raid7: raid-7 {
+ compatible = "brcm,iproc-sba-v2";
+ mboxes = <&raid_mbox 28 0x1 0xff00>,
+ <&raid_mbox 29 0x1 0xff00>,
+ <&raid_mbox 30 0x1 0xff00>,
+ <&raid_mbox 31 0x1 0xff00>;
};
phy-names = "pcie-phy";
};
-pcie-ss {
+pcie-ss-bus@40000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
#include <dt-bindings/pinctrl/brcm,pinctrl-stingray.h>
- pinconf: pinconf@140000 {
+ pinconf: pinctrl@140000 {
compatible = "pinconf-single";
reg = <0x00140000 0x250>;
pinctrl-single,register-width = <32>;
/*
*Copyright(c) 2018 Broadcom
*/
- usb {
+ usb-bus@68500000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
status = "disabled";
};
- bdc0: usb@2000 {
- compatible = "brcm,bdc-v0.16";
- reg = <0x0 0x00002000 0x0 0x1000>;
- interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usbphy0 0>, <&usbphy0 1>;
- phy-names = "phy0", "phy1";
- dma-coherent;
- status = "disabled";
- };
-
usbphy1: usb-phy@10000 {
compatible = "brcm,sr-usb-combo-phy";
reg = <0x0 0x00010000 0x0 0x100>;
status = "disabled";
};
- bdc1: usb@21000 {
- compatible = "brcm,bdc-v0.16";
- reg = <0x0 0x00021000 0x0 0x1000>;
- interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usbphy2>;
- phy-names = "phy0";
- dma-coherent;
- status = "disabled";
- };
};
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include <dt-bindings/clock/bcm-sr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
reg = <0 0x60401000 0 0x38c>;
};
- scr {
+ osc: clock-50000000 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+
+ crmu_ref25m: hsls_25m_clk: clock-25000000 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&osc>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ hsls_div2_clk: hsls_div2_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>;
+ clock-div = <2>;
+ clock-mult = <1>;
+
+ };
+
+ hsls_div4_clk: hsls_div4_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+
+ hsls_25m_div2_clk: clock-12500000 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&hsls_25m_clk>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ scr-bus@61000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
- crmu: crmu {
+ crmu: crmu-bus@66400000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x66400000 0x100000>;
- #include "stingray-clock.dtsi"
-
otp: otp@1c400 {
compatible = "brcm,ocotp-v2";
reg = <0x0001c400 0x68>;
reg = <0x0001d000 0x400>;
};
+ lcpll0: clock-controller@1d0c4 {
+ #clock-cells = <1>;
+ compatible = "brcm,sr-lcpll0";
+ reg = <0x0001d0c4 0x3c>,
+ <0x0001c870 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "lcpll0", "clk_sata_refp",
+ "clk_sata_refn", "clk_sata_350",
+ "clk_sata_500";
+ };
+
+ genpll0: clock-controller@1d104 {
+ #clock-cells = <1>;
+ compatible = "brcm,sr-genpll0";
+ reg = <0x0001d104 0x32>,
+ <0x0001c854 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "genpll0", "clk_125m", "clk_scr",
+ "clk_250", "clk_pcie_axi",
+ "clk_paxc_axi_x2",
+ "clk_paxc_axi";
+ };
+
+ lcpll1: clock-controller@1d138 {
+ #clock-cells = <1>;
+ compatible = "brcm,sr-lcpll1";
+ reg = <0x0001d138 0x3c>,
+ <0x0001c870 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "lcpll1", "clk_wan",
+ "clk_usb_ref",
+ "clk_crmu_ts";
+ };
+
+ genpll2: clock-controller@1d1ac {
+ #clock-cells = <1>;
+ compatible = "brcm,sr-genpll2";
+ reg = <0x0001d1ac 0x32>,
+ <0x0001c854 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "genpll2", "clk_nic",
+ "clk_ts_500_ref", "clk_125_nitro",
+ "clk_chimp", "clk_nic_flash",
+ "clk_fs";
+ };
+
+ genpll3: clock-controller@1d1e0 {
+ #clock-cells = <1>;
+ compatible = "brcm,sr-genpll3";
+ reg = <0x0001d1e0 0x32>,
+ <0x0001c854 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "genpll3", "clk_hsls",
+ "clk_sdio";
+ };
+
+ genpll4: clock-controller@1d214 {
+ #clock-cells = <1>;
+ compatible = "brcm,sr-genpll4";
+ reg = <0x0001d214 0x32>,
+ <0x0001c854 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "genpll4", "clk_ccn",
+ "clk_tpiu_pll", "clk_noc",
+ "clk_chclk_fs4",
+ "clk_bridge_fscpu";
+ };
+
+ genpll5: clock-controller@1d248 {
+ #clock-cells = <1>;
+ compatible = "brcm,sr-genpll5";
+ reg = <0x0001d248 0x32>,
+ <0x0001c870 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "genpll5", "clk_fs4_hf",
+ "clk_crypto_ae", "clk_raid_ae";
+ };
+
gpio_crmu: gpio@24800 {
compatible = "brcm,iproc-gpio";
reg = <0x00024800 0x4c>;
#include "stingray-pcie.dtsi"
#include "stingray-usb.dtsi"
- hsls {
+ hsls-bus@68900000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
};
- nand: nand@360000 {
+ nand: nand-controller@360000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x00360000 0x600>,
<0x0050a408 0x600>,
status = "disabled";
};
- sdio0: sdhci@3f1000 {
+ sdio0: mmc@3f1000 {
compatible = "brcm,sdhci-iproc";
reg = <0x003f1000 0x100>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <8>;
- clocks = <&sdio0_clk>;
+ clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>;
iommus = <&smmu 0x6002 0x0000>;
status = "disabled";
};
- sdio1: sdhci@3f2000 {
+ sdio1: mmc@3f2000 {
compatible = "brcm,sdhci-iproc";
reg = <0x003f2000 0x100>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <8>;
- clocks = <&sdio1_clk>;
+ clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>;
iommus = <&smmu 0x6003 0x0000>;
status = "disabled";
};
};
- tmons {
+ tmons-bus@8f100000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
- nic-hsls {
+ nic-hsls-bus@60800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x0 0x0 0x0 0x7fffffff>;
+ ranges = <0x0 0x0 0x60800000 0x6fffff>;
- nic_i2c0: i2c@60826100 {
+ nic_i2c0: i2c@26100 {
compatible = "brcm,iproc-nic-i2c";
#address-cells = <1>;
#size-cells = <0>;
- reg = <0x60826100 0x100>,
- <0x60e00408 0x1000>;
+ reg = <0x026100 0x100>,
+ <0x600408 0x1000>;
brcm,ape-hsls-addr-mask = <0x03400000>;
clock-frequency = <100000>;
status = "disabled";
compatible = "arm,pl011", "arm,primecell";
reg = <0x87e0 0x24000000 0x0 0x1000>;
interrupts = <1 21 4>;
- clocks = <&refclk50mhz>;
- clock-names = "apb_pclk";
+ clocks = <&refclk50mhz>, <&refclk50mhz>;
+ clock-names = "uartclk", "apb_pclk";
};
uaa1: serial@87e025000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x87e0 0x25000000 0x0 0x1000>;
interrupts = <1 22 4>;
- clocks = <&refclk50mhz>;
- clock-names = "apb_pclk";
+ clocks = <&refclk50mhz>, <&refclk50mhz>;
+ clock-names = "uartclk", "apb_pclk";
};
};
};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * dts file for Cavium ThunderX2 CN99XX Evaluation Platform
- *
- * Copyright (c) 2017 Cavium Inc.
- * Copyright (c) 2013-2016 Broadcom
- */
-
-/dts-v1/;
-
-#include "thunder2-99xx.dtsi"
-
-/ {
- model = "Cavium ThunderX2 CN99XX";
- compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */
- <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */
- };
-
- aliases {
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * dtsi file for Cavium ThunderX2 CN99XX processor
- *
- * Copyright (c) 2017 Cavium Inc.
- * Copyright (c) 2013-2016 Broadcom
- * Author: Zi Shen Lim <zlim@broadcom.com>
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
- model = "Cavium ThunderX2 CN99XX";
- compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- /* just 4 cpus now, 128 needed in full config */
- cpus {
- #address-cells = <0x2>;
- #size-cells = <0x0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "cavium,thunder2", "brcm,vulcan";
- reg = <0x0 0x0>;
- enable-method = "psci";
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "cavium,thunder2", "brcm,vulcan";
- reg = <0x0 0x1>;
- enable-method = "psci";
- };
-
- cpu@2 {
- device_type = "cpu";
- compatible = "cavium,thunder2", "brcm,vulcan";
- reg = <0x0 0x2>;
- enable-method = "psci";
- };
-
- cpu@3 {
- device_type = "cpu";
- compatible = "cavium,thunder2", "brcm,vulcan";
- reg = <0x0 0x3>;
- enable-method = "psci";
- };
- };
-
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
- };
-
- gic: interrupt-controller@4000080000 {
- compatible = "arm,gic-v3";
- #interrupt-cells = <3>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- interrupt-controller;
- #redistributor-regions = <1>;
- reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */
- <0x04 0x01000000 0x0 0x1000000>; /* GICR */
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-
- gicits: msi-controller@4000100000 {
- compatible = "arm,gic-v3-its";
- msi-controller;
- reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pmu {
- compatible = "brcm,vulcan-pmu";
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */
- };
-
- clk125mhz: uart_clk125mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <125000000>;
- clock-output-names = "clk125mhz";
- };
-
- pcie@30000000 {
- compatible = "pci-host-ecam-generic";
- device_type = "pci";
- #interrupt-cells = <1>;
- #address-cells = <3>;
- #size-cells = <2>;
-
- /* ECAM at 0x3000_0000 - 0x4000_0000 */
- reg = <0x0 0x30000000 0x0 0x10000000>;
-
- /*
- * PCI ranges:
- * IO no supported
- * MEM 0x4000_0000 - 0x6000_0000
- * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000
- */
- ranges =
- <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000
- 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>;
- bus-range = <0 0xff>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map =
- /* addr pin ic icaddr icintr */
- <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
- 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
- 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
- 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- msi-parent = <&gicits>;
- dma-coherent;
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- uart0: serial@402020000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0x04 0x02020000 0x0 0x1000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk125mhz>, <&clk125mhz>;
- clock-names = "uartclk", "apb_pclk";
- };
- };
-
-};
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2025 Cix Technology Group Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "sky1.dtsi"
+#include "sky1-pinfunc.h"
+
+/ {
+ model = "Xunlong,OrangePi 6 Plus";
+ compatible = "xunlong,orangepi-6-plus", "cix,sky1";
+
+ aliases {
+ serial2 = &uart2;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x28000000>;
+ linux,cma-default;
+ };
+ };
+
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hog-cfg {
+ pins {
+ pinmux = <CIX_PAD_GPIO144_FUNC_GPIO144>,
+ <CIX_PAD_GPIO145_FUNC_GPIO145>,
+ <CIX_PAD_GPIO146_FUNC_GPIO146>,
+ <CIX_PAD_GPIO147_FUNC_GPIO147>;
+ bias-pull-down;
+ drive-strength = <8>;
+ };
+ };
+};
+
+&iomuxc_s5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog_s5>;
+
+ pinctrl_hog_s5: hog-s5-cfg {
+ pins {
+ pinmux = <CIX_PAD_GPIO014_FUNC_GPIO014>;
+ bias-pull-up;
+ drive-strength = <8>;
+
+ };
+ };
+};
+
+&pcie_x8_rc {
+ status = "okay";
+};
+
+&pcie_x2_rc {
+ status = "okay";
+};
+
+&pcie_x1_1_rc {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
ranges = <0x01000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>,
<0x02000000 0x0 0x38200000 0x0 0x38200000 0x0 0x07e00000>,
- <0x43000000 0x0C 0x00000000 0x0C 0x00000000 0x04 0x00000000>;
+ <0x43000000 0x0c 0x00000000 0x0c 0x00000000 0x04 0x00000000>;
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x30 0x5f>;
"wfd";
};
+ cmu_mfd: clock-controller@19e00000 {
+ compatible = "samsung,exynosautov920-cmu-mfd";
+ reg = <0x19e00000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>,
+ <&cmu_top DOUT_CLKCMU_MFD_NOC>;
+ clock-names = "oscclk",
+ "noc";
+ };
+
pinctrl_aud: pinctrl@1a460000 {
compatible = "samsung,exynosautov920-pinctrl";
reg = <0x1a460000 0x10000>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x40000000>;
+ efuse@10000000 {
+ compatible = "google,gs101-otp";
+ reg = <0x10000000 0xf084>;
+ clocks = <&cmu_misc CLK_GOUT_MISC_OTP_CON_TOP_PCLK>;
+ clock-names = "pclk";
+ interrupts = <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
cmu_misc: clock-controller@10010000 {
compatible = "google,gs101-cmu-misc";
reg = <0x10010000 0x10000>;
clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>,
<&cmu_top CLK_DOUT_CMU_MISC_SSS>;
clock-names = "bus", "sss";
+ samsung,sysreg = <&sysreg_misc>;
};
sysreg_misc: syscon@10030000 {
status = "disabled";
};
+ trng: rng@10141400 {
+ compatible = "google,gs101-trng",
+ "samsung,exynos850-trng";
+ reg = <0x10141400 0x100>;
+ clocks = <&cmu_misc CLK_GOUT_MISC_SSS_I_ACLK>,
+ <&cmu_misc CLK_GOUT_MISC_SSS_I_PCLK>;
+ clock-names = "secss", "pclk";
+ };
+
gic: interrupt-controller@10400000 {
compatible = "arm,gic-v3";
#address-cells = <0>;
<&cmu_top CLK_DOUT_CMU_PERIC0_BUS>,
<&cmu_top CLK_DOUT_CMU_PERIC0_IP>;
clock-names = "oscclk", "bus", "ip";
+ samsung,sysreg = <&sysreg_peric0>;
};
sysreg_peric0: syscon@10820000 {
<&cmu_top CLK_DOUT_CMU_PERIC1_BUS>,
<&cmu_top CLK_DOUT_CMU_PERIC1_IP>;
clock-names = "oscclk", "bus", "ip";
+ samsung,sysreg = <&sysreg_peric1>;
};
sysreg_peric1: syscon@10c20000 {
<&cmu_top CLK_DOUT_CMU_HSI0_USBDPDBG>;
clock-names = "oscclk", "bus", "dpgtc", "usb31drd",
"usbdpdbg";
+ samsung,sysreg = <&sysreg_hsi0>;
};
sysreg_hsi0: syscon@11020000 {
<&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>,
<&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>;
clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";
+ samsung,sysreg = <&sysreg_hsi2>;
};
sysreg_hsi2: syscon@14420000 {
clocks = <&ext_24_5m>;
clock-names = "oscclk";
+ samsung,sysreg = <&sysreg_apm>;
};
sysreg_apm: syscon@17420000 {
};
pmu_system_controller: system-controller@17460000 {
- compatible = "google,gs101-pmu", "syscon";
+ compatible = "google,gs101-pmu";
reg = <0x17460000 0x10000>;
google,pmu-intr-gen-syscon = <&pmu_intr_gen>;
status = "disabled";
};
+ cmu_dpu: clock-controller@1c000000 {
+ compatible = "google,gs101-cmu-dpu";
+ reg = <0x1c000000 0x10000>;
+ #clock-cells = <1>;
+
+ clocks = <&ext_24_5m>,
+ <&cmu_top CLK_DOUT_CMU_DPU_BUS>;
+ clock-names = "oscclk", "bus";
+ samsung,sysreg = <&sysreg_dpu>;
+ };
+
+ sysreg_dpu: syscon@1c020000 {
+ compatible = "google,gs101-dpu-sysreg", "syscon";
+ reg = <0x1c020000 0x10000>;
+ clocks = <&cmu_dpu CLK_GOUT_DPU_SYSREG_DPU_PCLK>;
+ };
+
cmu_top: clock-controller@1e080000 {
compatible = "google,gs101-cmu-top";
reg = <0x1e080000 0x10000>;
clock-names = "sfp";
};
- sec_mon: sec_mon@1e90000 {
+ sec_mon: sec-mon@1e90000 {
compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
"fsl,sec-v4.0-mon";
reg = <0x0 0x1e90000 0x0 0x10000>;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2019-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Michael Krummsdorf
+ * Author: Matthias Schiffer
+ * Author: Alexander Stein
+ */
+
+/dts-v1/;
+
+#include "fsl-ls1028a-tqmls1028a-mbls1028a.dtsi"
+
+/ {
+ model = "MBLS1028A-IND starterkit";
+ compatible = "tq,ls1028a-tqmls1028a-mbls1028a-ind", "tq,ls1028a-tqmls1028a", "fsl,ls1028a";
+};
+
+&i2c5 {
+ gpio_exp_3v3: gpio@71 {
+ compatible = "nxp,pca9538";
+ reg = <0x71>;
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ clk-intn-hog {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "CLK_INT#";
+ };
+
+ mpcie-waken-hog {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "MPCIE_WAKE#";
+ };
+
+ mpcie-disn-hog {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "MPCIE_DIS#";
+ };
+
+ mpcie-rstn-hog {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "MPCIE_RST#";
+ };
+
+ sata-perstn-hog {
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "SATA_PERST#";
+ };
+
+ dcdc-reset-hog {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "DCDC_RESET";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2019-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Michael Krummsdorf
+ * Author: Matthias Schiffer
+ * Author: Alexander Stein
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include "fsl-ls1028a-tqmls1028a-mbls1028a.dtsi"
+
+/ {
+ model = "MBLS1028A starterkit";
+ compatible = "tq,ls1028a-tqmls1028a-mbls1028a", "tq,ls1028a-tqmls1028a", "fsl,ls1028a";
+
+ gpio-beeper {
+ compatible = "gpio-beeper";
+ gpios = <&gpio_exp_3v3 15 GPIO_ACTIVE_HIGH>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ button-0 {
+ label = "S4";
+ linux,code = <BTN_0>;
+ gpios = <&gpio_exp_3v3 11 GPIO_ACTIVE_LOW>;
+ };
+
+ button-1 {
+ label = "S5";
+ linux,code = <BTN_1>;
+ gpios = <&gpio_exp_3v3 12 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <1>;
+ gpios = <&gpio_exp_3v3 14 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+
+ led-2 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpio_exp_3v3 13 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&gpio_exp_1v8 {
+ dcdc-reset-hog {
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ line-name = "DCDC_RESET";
+ output-low;
+ };
+};
+
+&i2c5 {
+ gpio_exp_3v3: gpio@25 {
+ compatible = "nxp,pca9555";
+ reg = <0x25>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gpio1>;
+ interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
+ vcc-supply = <®_3p3v>;
+
+ clk-intn-hog {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "CLK_INT#";
+ };
+
+ mpcie-waken-hog {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "MPCIE_WAKE#";
+ };
+
+ mpcie-disn-hog {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "MPCIE_DIS#";
+ };
+
+ mpcie-rstn-hog {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "MPCIE_RST#";
+ };
+
+ sata-perstn-hog {
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "SATA_PERST#";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2019-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Michael Krummsdorf
+ * Author: Matthias Schiffer
+ * Author: Alexander Stein
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include "fsl-ls1028a-tqmls1028a.dtsi"
+
+/ {
+ aliases {
+ crypto = &crypto;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ mmc0 = &esdhc; /* SD-Card */
+ mmc1 = &esdhc1; /* eMMC */
+ serial0 = &duart0;
+ serial1 = &duart1;
+ };
+
+ chosen {
+ stdout-path = &duart0;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "V_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "V_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ /* 256 MiB */
+ size = <0 0x10000000>;
+ linux,cma-default;
+ };
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&dspi2 {
+ bus-num = <2>;
+ status = "okay";
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&duart1 {
+ status = "okay";
+};
+
+&esdhc {
+ cd-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ no-mmc;
+ no-sdio;
+ no-1-8-v;
+ bus-width = <4>;
+ status = "okay";
+};
+
+/* When switched to baseboard-internal i2c bus,
+ * IIC5 has access to the following devices.
+ */
+&i2c4 {
+ /* TUSB8041 only supports 100 KHz, but it is not connected */
+ clock-frequency = <400000>;
+ status = "okay";
+
+ /* SI5338 - set up in U-Boot */
+ /* clockgen@70 */
+};
+
+&i2c5 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ gpio_exp_1v8: gpio@70 {
+ compatible = "nxp,pca9538";
+ reg = <0x70>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gpio1>;
+ interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
+ vcc-supply = <®_1p8v>;
+
+ ec1-intn-hog {
+ gpio-hog;
+ gpios = <0 0>;
+ input;
+ line-name = "EC1_INT#";
+ };
+
+ sgmii-intn-hog {
+ gpio-hog;
+ gpios = <2 0>;
+ input;
+ line-name = "SGMII_INT#";
+ };
+
+ qsgmii-intn-hog {
+ gpio-hog;
+ gpios = <4 0>;
+ input;
+ line-name = "QSGMII_INT#";
+ };
+
+ qsgmii-rstn-hog {
+ gpio-hog;
+ gpios = <5 0>;
+ output-high;
+ line-name = "QSGMII_RESET#";
+ };
+ };
+};
+
+&enetc_mdio_pf3 {
+ mdio0_rgmii_phy00: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x00>;
+ reset-gpios = <&gpio_exp_1v8 1 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <1>;
+ reset-deassert-us = <200>;
+ interrupt-parent = <&gpio_exp_1v8>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+
+ mdio0_sgmii_phy03: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x03>;
+ reset-gpios = <&gpio_exp_1v8 3 GPIO_ACTIVE_LOW>;
+ /*
+ * Long reset to work around PHY incorrect strap pin sampling
+ * due to external capacitors for SGMII
+ */
+ reset-assert-us = <2500>;
+ reset-deassert-us = <200>;
+ interrupt-parent = <&gpio_exp_1v8>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+
+ qsgmii_phy1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+
+ qsgmii_phy2: ethernet-phy@1d {
+ reg = <0x1d>;
+ };
+
+ qsgmii_phy3: ethernet-phy@1e {
+ reg = <0x1e>;
+ };
+
+ qsgmii_phy4: ethernet-phy@1f {
+ reg = <0x1f>;
+ };
+};
+
+&enetc_port0 {
+ phy-handle = <&mdio0_sgmii_phy03>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ status = "okay";
+};
+
+&enetc_port1 {
+ phy-handle = <&mdio0_rgmii_phy00>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&enetc_port2 {
+ status = "okay";
+};
+
+&mscc_felix {
+ status = "okay";
+};
+
+/* l2switch ports */
+&mscc_felix_port0 {
+ phy-handle = <&qsgmii_phy1>;
+ phy-mode = "qsgmii";
+ status = "okay";
+};
+
+&mscc_felix_port1 {
+ phy-handle = <&qsgmii_phy2>;
+ phy-mode = "qsgmii";
+ status = "okay";
+};
+
+&mscc_felix_port2 {
+ phy-handle = <&qsgmii_phy3>;
+ phy-mode = "qsgmii";
+ status = "okay";
+};
+
+&mscc_felix_port3 {
+ phy-handle = <&qsgmii_phy4>;
+ phy-mode = "qsgmii";
+ status = "okay";
+};
+
+&mscc_felix_port4 {
+ ethernet = <&enetc_port2>;
+ status = "okay";
+};
+
+&pcie2 {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&usb0 {
+ /* dual role is implemented, but not a full featured OTG */
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb1 {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ hub_2_0: hub@1 {
+ compatible = "usb451,8142";
+ reg = <1>;
+ peer-hub = <&hub_3_0>;
+ reset-gpios = <&gpio_exp_3v3 1 GPIO_ACTIVE_LOW>;
+ vdd-supply = <®_3p3v>;
+ };
+
+ hub_3_0: hub@2 {
+ compatible = "usb451,8140";
+ reg = <2>;
+ peer-hub = <&hub_2_0>;
+ reset-gpios = <&gpio_exp_3v3 1 GPIO_ACTIVE_LOW>;
+ vdd-supply = <®_3p3v>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright 2019-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Michael Krummsdorf
+ * Author: Matthias Schiffer
+ * Author: Alexander Stein
+ */
+
+#include "fsl-ls1028a.dtsi"
+
+/ {
+ compatible = "tq,ls1028a-tqmls1028a", "fsl,ls1028a";
+
+ reg_1p8v_som: regulator-1p8v-som {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V_SOM";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v_som: regulator-3p3v-som {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V_SOM";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ thermal-zones {
+ /*
+ * TQMLS1028A uses an external temperature sensor
+ * instead of TMU
+ */
+ /delete-node/ ddr-controller;
+
+ cluster-thermal {
+ thermal-sensors = <&sa56004_4c 1>;
+ };
+ };
+};
+
+&esdhc1 {
+ no-sdio;
+ no-sd;
+ non-removable;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-ddr-1_8v;
+ bus-width = <8>;
+ vmmc-supply = <®_3p3v_som>;
+ vqmmc-supply = <®_1p8v_som>;
+ status = "okay";
+};
+
+&fspi {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ vcc-supply = <®_1p8v_som>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ js42_18: temperature-sensor@18 {
+ compatible = "nxp,se97b", "jedec,jc-42.4-temp";
+ reg = <0x18>;
+ };
+
+ sa56004_4c: temperature-sensor@4c {
+ compatible = "nxp,sa56004";
+ reg = <0x4c>;
+ #thermal-sensor-cells = <1>;
+ vcc-supply = <®_3p3v_som>;
+ };
+
+ se97_50: eeprom@50 {
+ compatible = "nxp,se97b", "atmel,24c02";
+ read-only;
+ reg = <0x50>;
+ pagesize = <16>;
+ vcc-supply = <®_3p3v_som>;
+ };
+
+ rtc1: rtc@51 {
+ compatible = "nxp,pcf85063a";
+ reg = <0x51>;
+ quartz-load-femtofarads = <12500>;
+ };
+
+ m24c256_57: eeprom@57 {
+ compatible = "atmel,24c256";
+ reg = <0x57>;
+ pagesize = <32>;
+ vcc-supply = <®_3p3v_som>;
+ };
+};
+
+/*
+ * We use a separate sensor IC to measure core temperature. Disable the TMU
+ * as its driver can cause log spam outside of its measurement range (0-125C).
+ *
+ * Will have to be reevaluated if this DTS is ported to a mainline kernel,
+ * as both sensors of the TMU are referenced by the default LS1028A
+ * thermal-zones definitions there.
+ */
+&tmu {
+ status = "disabled";
+};
#include "fsl-ls1046a.dtsi"
#include "tqmls10xxa.dtsi"
+&bman_fbpr {
+ alloc-ranges = <0 0x88000000 1 0x00000000>;
+};
+
+&qman_fqd {
+ alloc-ranges = <0 0x88000000 1 0x00000000>;
+};
+
+&qman_pfdr {
+ alloc-ranges = <0 0x88000000 1 0x00000000>;
+};
+
&qspi {
num-cs = <2>;
status = "okay";
status = "disabled";
};
- pcie_ep1: pcie_ep@3400000 {
+ pcie_ep1: pcie-ep@3400000 {
compatible = "fsl,ls1046a-pcie-ep";
reg = <0x00 0x03400000 0x0 0x00100000>,
<0x40 0x00000000 0x8 0x00000000>;
status = "disabled";
};
- pcie_ep2: pcie_ep@3500000 {
+ pcie_ep2: pcie-ep@3500000 {
compatible = "fsl,ls1046a-pcie-ep";
reg = <0x00 0x03500000 0x0 0x00100000>,
<0x48 0x00000000 0x8 0x00000000>;
status = "disabled";
};
- pcie_ep3: pcie_ep@3600000 {
+ pcie_ep3: pcie-ep@3600000 {
compatible = "fsl,ls1046a-pcie-ep";
reg = <0x00 0x03600000 0x0 0x00100000>,
<0x50 0x00000000 0x8 0x00000000>;
/* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */
partition@2800000 {
label = "ubia";
- reg = <0x2800000 0x6C00000>;
+ reg = <0x2800000 0x6c00000>;
};
/* ubib (second OpenWrt) */
partition@9400000 {
label = "ubib";
- reg = <0x9400000 0x6C00000>;
+ reg = <0x9400000 0x6c00000>;
};
};
};
compatible = "arm,mmu-500";
reg = <0 0x5000000 0 0x800000>;
#iommu-cells = <1>;
- stream-match-mask = <0x7C00>;
+ stream-match-mask = <0x7c00>;
dma-coherent;
#global-interrupts = <12>;
// global secure fault
reg = <0 0x5000000 0 0x800000>;
#global-interrupts = <12>;
#iommu-cells = <1>;
- stream-match-mask = <0x7C00>;
+ stream-match-mask = <0x7c00>;
dma-coherent;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* global secure fault */
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* combined secure interrupt */
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster0_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster0_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster1_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster1_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster2_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster2_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster3_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster3_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster4_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster4_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster5_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster5_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster6_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster6_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster7_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster7_l2>;
#include <dt-bindings/pwm/pwm.h>
/ {
+ aliases {
+ ethernet0 = &fec1;
+ };
+
chosen {
stdout-path = &lpuart1;
};
ranges = <0x5c000000 0x0 0x5c000000 0x1000000>;
ddr_pmu0: ddr-pmu@5c020000 {
- compatible = "fsl,imx8-ddr-pmu";
+ compatible = "fsl,imx8qxp-ddr-pmu", "fsl,imx8-ddr-pmu";
reg = <0x5c020000 0x10000>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
};
compatible = "fsl,imx8dxl-ddr-pmu", "fsl,imx8-ddr-pmu";
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
};
+
+&ddr_subsys {
+ db_pmu0: db-pmu@5ca40000 {
+ compatible = "fsl,imx8dxl-db-pmu";
+ reg = <0x5ca40000 0x10000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&db_pmu0_lpcg IMX_LPCG_CLK_4>, <&db_pmu0_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg", "cnt";
+ };
+
+ db_pmu0_lpcg: clock-controller@5cae0000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5cae0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&db_ipg_clk>, <&db_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "perf_lpcg_cnt_clk",
+ "perf_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_PERF>;
+ };
+};
clock-output-names = "xtal_24MHz";
};
+ db_ipg_clk: clock-db-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <456000000>;
+ clock-output-names = "db_ipg_clk";
+ };
+
/* sorted in register address */
#include "imx8-ss-cm40.dtsi"
#include "imx8-ss-adma.dtsi"
no-map;
};
- rsc_table: rsc_table@b80ff000 {
+ rsc_table: rsc-table@b80ff000 {
reg = <0 0xb80ff000 0 0x1000>;
no-map;
};
enet-phy-lane-no-swap;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,min-output-impedance;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
reg = <0>;
status = "okay";
};
+®_usdhc2_vqmmc {
+ status = "okay";
+};
+
&sai3 {
assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>,
<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>,
<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>,
- <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>,
- <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>;
+ <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>,
<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>,
<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>,
- <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>,
- <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>;
+ <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>,
<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>,
<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>,
- <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>,
- <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>;
+ <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>;
};
};
reg = <0x00000000 0x40000000 0 0x40000000>;
};
- /* e-MMC IO, needed for HS modes */
- reg_vcc1v8: regulator-vcc1v8 {
- compatible = "regulator-fixed";
- regulator-name = "TQMA8MXML_VCC1V8";
+ reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>;
+ regulator-name = "V_SD2";
regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- /* identical to buck4_reg, but should never change */
- reg_vcc3v3: regulator-vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "TQMA8MXML_VCC3V3";
- regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1>,
+ <3300000 0x0>;
+ vin-supply = <&ldo5_reg>;
+ status = "disabled";
};
reserved-memory {
};
};
-
pcf85063: rtc@51 {
compatible = "nxp,pcf85063a";
reg = <0x51>;
read-only;
reg = <0x53>;
pagesize = <16>;
- vcc-supply = <®_vcc3v3>;
+ vcc-supply = <&buck4_reg>;
};
eeprom0: eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
pagesize = <32>;
- vcc-supply = <®_vcc3v3>;
+ vcc-supply = <&buck4_reg>;
};
};
fsl,clkreq-unsupported;
};
+&usdhc2 {
+ vqmmc-supply = <®_usdhc2_vqmmc>;
+};
+
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
non-removable;
no-sd;
no-sdio;
- vmmc-supply = <®_vcc3v3>;
- vqmmc-supply = <®_vcc1v8>;
+ vmmc-supply = <&buck4_reg>;
+ vqmmc-supply = <&buck5_reg>;
status = "okay";
};
fsl,pins = <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>;
};
+ pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp {
+ fsl,pins = <MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc0>;
+ };
+
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>,
<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
interrupt-parent = <&gpio4>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
};
+
+ magnetometer@1e {
+ compatible = "st,lis2mdl";
+ reg = <0x1e>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mag>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+ };
};
/* off-board header */
>;
};
+ pinctrl_mag: maggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x159
+ >;
+ };
+
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
arm,no-tick-in-suspend;
};
- thermal-zones {
+ thermal_zones: thermal-zones {
cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
samsung,esc-clock-frequency = <20000000>;
};
+®_usdhc2_vqmmc {
+ status = "okay";
+};
+
&sai3 {
assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
};
pinctrl_i2c2: i2c2grp {
- fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001C4>,
- <MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001C4>;
+ fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c4>,
+ <MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c4>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
- fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001C4>,
- <MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001C4>;
+ fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c4>,
+ <MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c4>;
};
pinctrl_i2c3: i2c3grp {
- fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001C4>,
- <MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001C4>;
+ fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c4>,
+ <MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c4>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
- fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001C4>,
- <MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001C4>;
+ fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c4>,
+ <MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c4>;
};
pinctrl_pwm3: pwm3grp {
<MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>,
<MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>,
<MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>,
- <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>,
- <MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>;
+ <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
<MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>,
<MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>,
<MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>,
- <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>,
- <MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>;
+ <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
<MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>,
<MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>,
<MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>,
- <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>,
- <MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>;
+ <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>;
};
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
reg = <0x00000000 0x40000000 0 0x40000000>;
};
- /* e-MMC IO, needed for HS modes */
- reg_vcc1v8: regulator-vcc1v8 {
- compatible = "regulator-fixed";
- regulator-name = "TQMA8MXNL_VCC1V8";
+ reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>;
+ regulator-name = "V_SD2";
regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- reg_vcc3v3: regulator-vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "TQMA8MXNL_VCC3V3";
- regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1>,
+ <3300000 0x0>;
+ vin-supply = <&ldo5_reg>;
+ status = "disabled";
};
reserved-memory {
read-only;
reg = <0x53>;
pagesize = <16>;
- vcc-supply = <®_vcc3v3>;
+ vcc-supply = <&buck4_reg>;
};
eeprom0: eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
pagesize = <32>;
- vcc-supply = <®_vcc3v3>;
+ vcc-supply = <&buck4_reg>;
};
};
vddio-supply = <&ldo3_reg>;
};
+&usdhc2 {
+ vqmmc-supply = <®_usdhc2_vqmmc>;
+};
+
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
non-removable;
no-sd;
no-sdio;
- vmmc-supply = <®_vcc3v3>;
- vqmmc-supply = <®_vcc1v8>;
+ vmmc-supply = <&buck4_reg>;
+ vqmmc-supply = <&buck5_reg>;
status = "okay";
};
fsl,pins = <MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>;
};
+ pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp {
+ fsl,pins = <MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc0>;
+ };
+
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>,
<MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020-2024 Fedor Ross <fedor.ross@ifm.com>
+ */
+
+#include "imx8mn.dtsi"
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "ifm i.MX8MNano VHIP4 Evaluation Board";
+ compatible = "ifm,imx8mn-vhip4-evalboard", "ifm,imx8mn-vhip4", "fsl,imx8mn";
+
+ aliases {
+ mmc0 = &usdhc3;
+ mmc1 = &usdhc1;
+ mmc2 = &usdhc2;
+ rtc0 = &hw_rtc;
+ rtc1 = &snvs_rtc;
+ };
+
+ chosen {
+ bootargs = "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200 rootwait";
+ stdout-path = &uart3;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0x40000000>;
+ };
+
+ can_clk20m: can-clk20m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <20000000>;
+ };
+
+ can_clk40m: can-clk40m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <40000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&pinctrl_gpio_button>;
+ pinctrl-names = "default";
+
+ button-2 {
+ label = "Button2";
+ gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_2>;
+ };
+
+ button-3 {
+ label = "Button3";
+ gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_3>;
+ };
+ };
+
+ ifm_led: led {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pinctrl_gpio_led>;
+ pinctrl-names = "default", "extended";
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <1>;
+ color = <LED_COLOR_ID_YELLOW>;
+ gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+ default-state = "keep";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
+ default-state = "keep";
+ };
+ };
+};
+
+&A53_0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25000000 {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ };
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_cs>;
+ /delete-property/ dmas;
+ /delete-property/ dma-names;
+};
+
+&ecspi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3>, <&pinctrl_ecspi3_cs>;
+ /delete-property/ dmas;
+ /delete-property/ dma-names;
+};
+
+&gpu {
+ /* SoC has GPU fused off. */
+ status = "disabled";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ hw_rtc: rtc@52 {
+ compatible = "microcrystal,rv3028";
+ reg = <0x52>;
+ };
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+
+ ifm_pmic: pmic@4b {
+ compatible = "rohm,bd71847";
+ reg = <0x4b>;
+ pinctrl-0 = <&pinctrl_pmic>;
+ rohm,reset-snvs-powered;
+
+ regulators {
+ buck1_reg: BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <790000>;
+ regulator-max-microvolt = <860000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <840000>;
+ regulator-max-microvolt = <960000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ buck3_reg: BUCK3 {
+ // BUCK5 in datasheet
+ regulator-name = "buck3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ buck4_reg: BUCK4 {
+ // BUCK6 in datasheet
+ regulator-name = "buck4";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5_reg: BUCK5 {
+ // BUCK7 in datasheet
+ regulator-name = "buck5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6_reg: BUCK6 {
+ // BUCK8 in datasheet
+ regulator-name = "buck6";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: LDO1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl_ecspi1: ecspi1-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x110
+ MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x110
+ MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x190
+ >;
+ };
+
+ pinctrl_ecspi3: ecspi3-grp {
+ fsl,pins = <
+ /* SPI3_CAN_CLK */
+ MX8MN_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x110
+ /* SPI3_CAN_MOSI */
+ MX8MN_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x110
+ /* SPI3_CAN_MISO */
+ MX8MN_IOMUXC_UART2_RXD_ECSPI3_MISO 0x190
+ >;
+ };
+
+ pinctrl_gpio_button: gpiobutton-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_DATA1_GPIO2_IO16 0x96
+ MX8MN_IOMUXC_SD2_DATA3_GPIO2_IO18 0x96
+ >;
+ };
+
+ pinctrl_gpio_led: gpioled-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CLK_GPIO2_IO13 0x116
+ MX8MN_IOMUXC_SD2_DATA0_GPIO2_IO15 0x116
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000110
+ MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x150
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000114
+ MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x150
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000116
+ MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x150
+ >;
+ };
+
+ pinctrl_wdog: wdog-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x64
+ >;
+ };
+};
+
+&pgc_gpumix {
+ /* SoC has GPU fused off. */
+ status = "disabled";
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
+&uart3 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usbotg1 {
+ status = "okay";
+};
+
+&usdhc3 {
+ assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
+ assigned-clock-rates = <400000000>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2025 Fedor Ross <fedor.ross@ifm.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mn-pinfunc.h"
+
+&ecspi1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ ksz8794: ethernet-switch@1 {
+ compatible = "microchip,ksz8794";
+ pinctrl-names = "default", "reset";
+ pinctrl-0 = <&pinctrl_ks8794>;
+ pinctrl-1 = <&pinctrl_ks8794>;
+ reg = <1>;
+ reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
+ spi-max-frequency = <5000000>;
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "cpu";
+ ethernet = <&fec1>;
+ phy-mode = "rgmii-id";
+ rx-internal-delay-ps = <2000>;
+ tx-internal-delay-ps = <2000>;
+ fixed-link {
+ full-duplex;
+ speed = <1000>;
+ };
+ };
+ };
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ fixed-link {
+ full-duplex;
+ speed = <1000>;
+ };
+};
+
+&iomuxc {
+ pinctrl_fec1: fec1-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x16
+ MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x96
+ MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16
+ MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16
+ MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16
+ MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16
+ MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x96
+ MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x96
+ MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x96
+ MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x96
+ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x10
+ MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x96
+ MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x96
+ MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16
+ MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1d6
+ >;
+ };
+
+ pinctrl_ks8794: ks8794-grp {
+ fsl,pins = <
+ /* KSZ8794 reset line */
+ MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x16
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mn-pinfunc.h"
+
+&pinctrl_ecspi1 {
+ fsl,pins = <
+ MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x10
+ MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x10
+ MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x90
+ /* KS8794 nCS */
+ MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x150
+ /* ANV32C81 nCS */
+ MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x150
+ >;
+};
+
+#include "imx8mn-vhip4-evalboard-ksz8794-common.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include "imx8mn-pinfunc.h"
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-handle = <ðphy0>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl_fec1: fec1-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x16
+ MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x96
+ MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16
+ MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16
+ MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16
+ MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16
+ MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x96
+ MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x96
+ MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x96
+ MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x96
+ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16
+ MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x96
+ MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x96
+ MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16
+ MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1d6
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020-2024 Fedor Ross <fedor.ross@ifm.com>
+ */
+
+/dts-v1/;
+
+#include "imx8mn-vhip4-evalboard-common.dtsi"
+
+/ {
+ model = "ifm i.MX8MNano VHIP4 Evaluation Board v1";
+ compatible = "ifm,imx8mn-vhip4-evalboard-v1", "ifm,imx8mn-vhip4-evalboard",
+ "ifm,imx8mn-vhip4", "fsl,imx8mn";
+};
+
+&ifm_led {
+ pinctrl-1 = <&pinctrl_gpio_led_v1>;
+
+ led-2 {
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <3>;
+ color = <LED_COLOR_ID_YELLOW>;
+ gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
+ default-state = "keep";
+ };
+
+ led-3 {
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <4>;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ default-state = "keep";
+ };
+};
+
+&ecspi1 {
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio5 21 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ eeprom@0 {
+ compatible = "anvo,anv32c81w", "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ spi-cpha;
+ spi-cpol;
+ pagesize = <1>;
+ size = <32768>;
+ address-width = <16>;
+ };
+};
+
+&ecspi3 {
+ cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, <&gpio5 4 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ can0: can@0 {
+ compatible = "microchip,mcp25625";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mcp25625>;
+ reg = <0>;
+ clocks = <&can_clk20m>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ can1: can@1 {
+ compatible = "microchip,mcp2518fd";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mcp2518>;
+ reg = <1>;
+ clocks = <&can_clk40m>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ microchip,rx-int-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
+ spi-max-frequency = <20000000>;
+ };
+};
+
+&i2c1 {
+ scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ temperature-sensor@48 {
+ compatible = "national,lm75";
+ reg = <0x48>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&i2c3 {
+ scl-gpios = <&gpio2 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&ifm_pmic {
+ interrupt-parent = <&gpio2>;
+ interrupts = <0 GPIO_ACTIVE_LOW>;
+};
+
+&iomuxc {
+ pinctrl_ecspi1_cs: ecspi1-cs-grp {
+ fsl,pins = <
+ /* KS8794 nCS */
+ MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x150
+ /* ANV32C81 nCS */
+ MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x150
+ >;
+ };
+
+ pinctrl_ecspi3_cs: ecspi3-cs-grp {
+ fsl,pins = <
+ /* MCP25625 nCS */
+ MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25 0x150
+ /* MCP2518FD nCS */
+ MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x150
+ >;
+ };
+
+ pinctrl_gpio_5: gpio5-grp {
+ fsl,pins = <
+ /* CFG_EEPROM_WP */
+ MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x140
+ >;
+ };
+
+ pinctrl_gpio_led_v1: gpioled-v1-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_DATA2_GPIO2_IO17 0x116
+ MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x116
+ >;
+ };
+
+ pinctrl_i2c1: i2c1-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000056
+ MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000d6
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x56
+ MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0xd6
+ >;
+ };
+
+ pinctrl_i2c2: i2c2-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000056
+ MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000d6
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2-gpio-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x56
+ MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0xd6
+ >;
+ };
+
+ pinctrl_i2c3: i2c3-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_RESET_B_I2C3_SCL 0x40000056
+ MX8MN_IOMUXC_SD1_STROBE_I2C3_SDA 0x400000d6
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3-gpio-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x56
+ MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0xd6
+ >;
+ };
+
+ pinctrl_mcp2518: mcp2518-grp {
+ fsl,pins = <
+ /* MCP2518 nINT line */
+ MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x116
+ /* MCP2518 nINT1/GPIO1 line */
+ MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1 0x116
+ >;
+ };
+
+ pinctrl_mcp25625: mcp25625-grp {
+ fsl,pins = <
+ /* MCP25625 nINT line */
+ MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x156
+ >;
+ };
+
+ pinctrl_pmic: pmic-irq-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x16
+ >;
+ };
+
+ pinctrl_uart3: uart3-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x142
+ MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x142
+ >;
+ };
+
+ pinctrl_usb_nreset: usbnreset-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x14a
+ >;
+ };
+
+ pinctrl_wdog: wdog-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x64
+ >;
+ };
+};
+
+&gpio5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_5>;
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "",
+ "ifm_device_info_eeprom_wp",
+ "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_nreset>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb-hub@1 {
+ compatible = "usb424,2512", "usb424,2514";
+ reg = <1>;
+ reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 Fedor Ross <fedor.ross@ifm.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "imx8mn-pinfunc.h"
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-handle = <ðphy0>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+
+ adi,rx-internal-delay-ps = <1800>;
+ adi,tx-internal-delay-ps = <2200>;
+ interrupts-extended = <&gpio4 31 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <10000>;
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl_fec1: fec1-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x16
+ MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x96
+ MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16
+ MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16
+ MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16
+ MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16
+ MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x96
+ MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x96
+ MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x96
+ MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x96
+ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16
+ MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x96
+ MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x96
+ MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16
+ /* nRST */
+ MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x156
+ /* nIRQ */
+ MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1d6
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 Marek Vasut
+ */
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mn-pinfunc.h"
+
+&pinctrl_ecspi1 {
+ fsl,pins = <
+ MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x10
+ MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x10
+ MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x90
+ /* KS8794 nCS */
+ MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x150
+ /* ANV32C81 nCS */
+ MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x150
+ >;
+};
+
+#include "imx8mn-vhip4-evalboard-ksz8794-common.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 Fedor Ross <fedor.ross@ifm.com>
+ */
+
+/dts-v1/;
+
+#include "imx8mn-vhip4-evalboard-common.dtsi"
+
+/ {
+ model = "ifm i.MX8MNano VHIP4 Evaluation Board v2";
+ compatible = "ifm,imx8mn-vhip4-evalboard-v2", "ifm,imx8mn-vhip4-evalboard",
+ "ifm,imx8mn-vhip4", "fsl,imx8mn";
+
+ multi-led {
+ compatible = "leds-group-multicolor";
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_INDICATOR;
+ leds = <&rgb_0>, <&rgb_1>, <&rgb_2>;
+ };
+};
+
+&ifm_led {
+ pinctrl-1 = <&pinctrl_gpio_led_v2>;
+
+ rgb_0: rgb-led-red {
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
+ default-state = "keep";
+ };
+
+ rgb_1: rgb-led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ default-state = "keep";
+ };
+
+ rgb_2: rgb-led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+ default-state = "keep";
+ };
+};
+
+&ecspi1 {
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio1 11 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ eeprom@0 {
+ compatible = "fujitsu,mb85rs64", "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ spi-cpha;
+ spi-cpol;
+ pagesize = <1>;
+ size = <32768>;
+ address-width = <16>;
+ };
+};
+
+&ecspi3 {
+ cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ can0: can@0 {
+ compatible = "microchip,mcp2518fd";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mcp2518>;
+ reg = <0>;
+ clocks = <&can_clk40m>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+ microchip,rx-int-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ spi-max-frequency = <20000000>;
+ };
+};
+
+&i2c1 {
+ scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ temperature-sensor@48 {
+ compatible = "ti,tmp1075";
+ reg = <0x48>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+};
+
+&i2c3 {
+ scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&ifm_pmic {
+ interrupt-parent = <&gpio5>;
+ interrupts = <17 GPIO_ACTIVE_LOW>;
+};
+
+&iomuxc {
+ pinctrl_ecspi1_cs: ecspi1-cs-grp {
+ fsl,pins = <
+ /* KS8794 nCS */
+ MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x150
+ /* Retain memory nCS (FRAM or MRAM) */
+ MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x150
+ /* RETAIN_nHOLD */
+ MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x140
+ >;
+ };
+
+ pinctrl_ecspi3_cs: ecspi3-cs-grp {
+ fsl,pins = <
+ /* MCP2518FD nCS */
+ MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25 0x150
+ >;
+ };
+
+ pinctrl_gpio_led_v2: gpioled-v2-grp {
+ fsl,pins = <
+ /* LED_RGB_RED */
+ MX8MN_IOMUXC_SD2_DATA2_GPIO2_IO17 0x116
+ /* LED_RGB_GREEN */
+ MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x116
+ /* LED_RGB_BLUE */
+ MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x116
+ >;
+ };
+
+ pinctrl_i2c1: i2c1-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_DATA4_I2C1_SCL 0x40000056
+ MX8MN_IOMUXC_SD1_DATA5_I2C1_SDA 0x400000d6
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x56
+ MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0xd6
+ /* CFG_EEPROM_WP */
+ MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140
+ /* RTC_nIRQ */
+ MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x116
+ /* LOG_EE_WP */
+ MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x140
+ >;
+ };
+
+ pinctrl_i2c3: i2c3-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000056
+ MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000d6
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3-gpio-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x56
+ MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0xd6
+ >;
+ };
+
+ pinctrl_mcp2518: mcp2518-grp {
+ fsl,pins = <
+ /* CAN0_CLKO */
+ MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x116
+ /* CAN0_nINT0 */
+ MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x116
+ /* CAN0_nINT1 */
+ MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x116
+ /* CAN0_nINT */
+ MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x116
+ >;
+ };
+
+ pinctrl_pmic: pmic-irq-grp {
+ fsl,pins = <
+ /* PMIC_nIRQ */
+ MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1d6
+ >;
+ };
+
+ pinctrl_uart3: uart3-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD1_DATA6_UART3_DCE_TX 0x142
+ MX8MN_IOMUXC_SD1_DATA7_UART3_DCE_RX 0x142
+ >;
+ };
+
+ pinctrl_wdog: wdog-grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x64
+ >;
+ };
+};
+
+&gpio2 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "",
+ "ifm_device_info_eeprom_wp",
+ "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio5 {
+ gpio-line-names =
+ "", "", "",
+ "ifm_logging_eeprom_wp",
+ "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
wakeup-source;
status = "disabled";
};
+
+ snvs_lpgpr: snvs-lpgpr {
+ compatible = "fsl,imx8mn-snvs-lpgpr",
+ "fsl,imx7d-snvs-lpgpr";
+ };
};
clk: clock-controller@30380000 {
status = "disabled";
};
+ reg_pcie0: regulator-pcie {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi>;
+ regulator-name = "WIFI_BT_RST#";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
&eqos { /* First ethernet */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
- phy-handle = <&phy_eqos>;
+ phy-handle = <&phy_eqos_bcm>;
phy-mode = "rgmii-id";
status = "okay";
#size-cells = <0>;
/* Atheros AR8031 PHY */
- phy_eqos: ethernet-phy@0 {
+ phy_eqos_ath: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
/*
reset-deassert-us = <10000>;
qca,keep-pll-enabled;
vddio-supply = <&vddio_eqos>;
+ status = "disabled";
vddio_eqos: vddio-regulator {
regulator-name = "VDDIO_EQOS";
regulator-name = "VDDH_EQOS";
};
};
+
+ /* Broadcom BCM54213PE PHY */
+ phy_eqos_bcm: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ /*
+ * Dedicated ENET_INT# and ENET_WOL# signals are
+ * unused, the PHY does not provide cable detect
+ * interrupt.
+ */
+ reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <10000>;
+ };
};
};
&fec { /* Second ethernet */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
- phy-handle = <&phy_fec>;
+ phy-handle = <&phy_fec_bcm>;
phy-mode = "rgmii-id";
fsl,magic-packet;
status = "okay";
#size-cells = <0>;
/* Atheros AR8031 PHY */
- phy_fec: ethernet-phy@0 {
+ phy_fec_ath: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
/*
reset-deassert-us = <10000>;
qca,keep-pll-enabled;
vddio-supply = <&vddio_fec>;
+ status = "disabled";
vddio_fec: vddio-regulator {
regulator-name = "VDDIO_FEC";
regulator-name = "VDDH_FEC";
};
};
+
+ /* Broadcom BCM54213PE PHY */
+ phy_fec_bcm: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ /*
+ * Dedicated ENET_INT# and ENET_WOL# signals are
+ * unused, the PHY does not provide cable detect
+ * interrupt.
+ */
+ reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <10000>;
+ };
};
};
self-powered;
};
- eeprom: eeprom@50 {
+ tpm: tpm@2e {
+ compatible = "st,st33tphf2ei2c", "tcg,tpm-tis-i2c";
+ reg = <0x2e>;
+ };
+
+ eeprom900: eeprom@50 { /* board rev.900 */
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
+ status = "disabled";
+ };
+
+ eeprom902: eeprom@51 { /* board rev.902 */
+ compatible = "atmel,24c32";
+ reg = <0x51>;
+ pagesize = <32>;
};
rtc: rtc@68 {
+ #clock-cells = <1>;
compatible = "st,m41t62";
reg = <0x68>;
pinctrl-names = "default";
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
+
+ gpiolvds: io-expander@20 {
+ compatible = "nxp,pca9554";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names =
+ "BL_ENABLE_V", "SEL_BL_12V",
+ "SEL_PANEL_5V", "SEL_PANEL_12V",
+ "SEL_BL_PWM", "SEL_BL_EN",
+ "REVERSE_SCAN_PANEL", "GND_REV903";
+ };
+
+ gpiowifi: io-expander@21 {
+ compatible = "nxp,pca9554";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names =
+ "BL_LVDS_ENABLE_3V3", "BL_LVDS_PWM_3V3",
+ "M2_BT_WAKE_3V3#", "M2_W_DISABLE2_3V3#",
+ "TFT_PANEL_ENABLE_3V3", "TPM_RESET_3V3#",
+ "CSI2_PD_3V3", "CSI2_RESET_3V3#";
+
+ /* BL_LVDS_PWM_3V3 is patch-wired to BL_PWM_3V3 on rev.903 */
+ pwm-input-hog {
+ gpio-hog;
+ gpios = <1 0>;
+ input;
+ line-name = "BL_LVDS_PWM_3V3_HOG";
+ };
+ };
+
+ eepromlvds: eeprom@51 {
+ compatible = "atmel,24c32";
+ reg = <0x51>;
+ pagesize = <32>;
+ /* Optional EEPROM, disabled by default. */
+ status = "disabled";
+ };
};
&i2c3 {
pinctrl-0 = <&pinctrl_pcie0>;
fsl,max-link-speed = <3>;
reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
+ vpcie-supply = <®_pcie0>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
- status = "disabled";
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "infineon,cyw55572-bt";
+ brcm,requires-autobaud-mode;
+ clocks = <&rtc 0>;
+ clock-names = "txco";
+ max-speed = <921600>;
+ shutdown-gpios = <&gpiowifi 3 GPIO_ACTIVE_HIGH>;
+ };
};
&usb3_phy0 {
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
/* ENET_RST# */
MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x6
- /* ENET_INT# */
- MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000090
>;
};
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
/* ENET2_RST# */
MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x6
- /* ENET2_INT# */
- MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x40000090
>;
};
/* PG_V_IN_VAR# */
MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x40000000
- /* CSI2_PD_1V8 */
- MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x0
- /* CSI2_RESET_1V8# */
- MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x0
/* DIS_USB_DN1 */
MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x0
/* GRAPHICS_PRSNT_1V8# */
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000000
+ /* TOUCH_RESET_3V3# */
+ MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x2
+ /* TOUCH_INT# */
+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x40000140
/* CLK_CCM_CLKO1_3V3 */
MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x10
+ /* ENET_INT# (rev.900,901) or M2_WDIS_BTIRQ_3V3# (rev.903) */
+ MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000092
>;
};
fsl,pins = <
/* M2_PCIE_RST# */
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2
- /* M2_W_DISABLE1_1V8# */
+ /* M2_PCIE_WAKE_1V8# */
MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x2
- /* M2_W_DISABLE2_1V8# */
- MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x2
- /* CLK_M2_32K768 */
- MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x14
+ /* M2_UART_WAKE_1V8# */
+ MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x40000002
/* M2_PCIE_WAKE# */
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x40000140
/* M2_PCIE_CLKREQ# */
fsl,pins = <
MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
+ MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x149
+ MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RTS 0x149
>;
};
MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x26
>;
};
+
+ pinctrl_wifi: wifi-grp {
+ fsl,pins = <
+ /* WIFI_BT_RST_3V3# */
+ MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x40000090
+ >;
+ };
};
};
&easrc {
- fsl,asrc-rate = <48000>;
+ fsl,asrc-rate = <48000>;
status = "okay";
};
<0x1 0x00000000 0 0xc0000000>;
};
+ flexcan_phy: can-phy {
+ compatible = "nxp,tja1048";
+ #phy-cells = <1>;
+ max-bitrate = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan_phy>;
+ standby-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>,
+ <&gpio4 27 GPIO_ACTIVE_LOW>;
+ };
+
native-hdmi-connector {
compatible = "hdmi-connector";
label = "HDMI OUT";
clock-frequency = <100000000>;
};
+ reg_1v5: regulator-1v5 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v5";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ };
+
+ reg_1v8: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reg_2v8: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "2v8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
reg_audio_3v3: regulator-audio-3v3 {
compatible = "regulator-fixed";
regulator-name = "audio-3v3";
enable-active-high;
};
- reg_can1_stby: regulator-can1-stby {
- compatible = "regulator-fixed";
- regulator-name = "can1-stby";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1_reg>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_can2_stby: regulator-can2-stby {
- compatible = "regulator-fixed";
- regulator-name = "can2-stby";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2_reg>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
reg_pcie0: regulator-pcie {
compatible = "regulator-fixed";
pinctrl-names = "default";
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
- xceiver-supply = <®_can1_stby>;
+ phys = <&flexcan_phy 0>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
- xceiver-supply = <®_can2_stby>;
+ phys = <&flexcan_phy 1>;
status = "disabled";/* can2 pin conflict with pdm */
};
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
+ camera@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>;
+ clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
+ clock-names = "xclk";
+ assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+ assigned-clock-rates = <24000000>;
+ powerdown-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+ AVDD-supply = <®_2v8>;
+ DVDD-supply = <®_1v5>;
+ DOVDD-supply = <®_1v8>;
+ status = "okay";
+
+ port {
+ ov5640_mipi_0_ep: endpoint {
+ remote-endpoint = <&mipi_csi0_ep>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
hdmi@3d {
compatible = "adi,adv7535";
reg = <0x3d>;
*/
};
+&isi_0 {
+ status = "okay";
+};
+
&lcdif1 {
status = "okay";
};
status = "okay";
};
+&mipi_csi_0 {
+ status = "okay";
+
+ ports {
+ port@0 {
+ mipi_csi0_ep: endpoint {
+ remote-endpoint = <&ov5640_mipi_0_ep>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
&mipi_dsi {
samsung,esc-clock-frequency = <10000000>;
status = "okay";
>;
};
+ pinctrl_csi_mclk: csi_mclk_grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x50
+ >;
+ };
+
+ pinctrl_csi0_pwn: csi0_pwn_grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x10
+ >;
+ };
+
+ pinctrl_csi0_rst: csi0_rst_grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10
+ >;
+ };
+
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
>;
};
- pinctrl_flexcan1_reg: flexcan1reggrp {
+ pinctrl_flexcan_phy: flexcanphygrp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */
- >;
- };
-
- pinctrl_flexcan2_reg: flexcan2reggrp {
- fsl,pins = <
MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */
>;
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mp.dtsi"
+
+/ {
+ model = "NXP i.MX8MPlus FRDM board";
+ compatible = "fsl,imx8mp-frdm", "fsl,imx8mp";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ label = "red";
+ gpios = <&pcal6416_0 13 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-1 {
+ label = "green";
+ gpios = <&pcal6416_0 14 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ led-2 {
+ label = "blue";
+ gpios = <&pcal6416_0 15 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0xc0000000>,
+ <0x1 0x00000000 0 0x40000000>;
+ };
+};
+
+&A53_0 {
+ cpu-supply = <®_arm>;
+};
+
+&A53_1 {
+ cpu-supply = <®_arm>;
+};
+
+&A53_2 {
+ cpu-supply = <®_arm>;
+};
+
+&A53_3 {
+ cpu-supply = <®_arm>;
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic@25 {
+ compatible = "nxp,pca9450c";
+ reg = <0x25>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ reg_arm: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1025000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <950000>;
+ nxp,dvs-standby-voltage = <850000>;
+ };
+
+ BUCK4 {
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_buck5: BUCK5 {
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <1045000>;
+ regulator-max-microvolt = <1155000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <1710000>;
+ regulator-max-microvolt = <1890000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ pcal6416_0: gpio@20 {
+ compatible = "nxp,pcal6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcal6416_0_int>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+ gpio-line-names = "CSI1_nRST",
+ "CSI2_nRST",
+ "DSI_CTP_RST",
+ "EXT_PWREN1",
+ "CAN_STBY",
+ "EXP_P0_5",
+ "EXP_P0_6",
+ "P0_7",
+ "LVDS0_BLT_EN",
+ "LVDS1_BLT_EN",
+ "LVDS0_CTP_RST",
+ "LVDS1_CTP_RST",
+ "SPK_PWREN",
+ "RLED_GPIO",
+ "GLED_GPIO",
+ "BLED_GPIO";
+ };
+
+ pcal6416_1: gpio@21 {
+ compatible = "nxp,pcal6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcal6416_1_int>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ gpio-line-names = "P0_0",
+ "P0_1",
+ "AUD_nINT",
+ "RTC_nINTA",
+ "USB1_SS_SEL",
+ "USB2_PWR_EN",
+ "SPI_EXP_SEL",
+ "P0_7",
+ "W2_HOST_WAKE_SD_3V3",
+ "W2_HOST_WAKE_BT_3V3",
+ "EXP_WIFI_BT_PDN_3V3",
+ "EXP_BT_RST_3V3",
+ "W2_RST_IND_3V3",
+ "SPI_nINT_3V3",
+ "KEYM_PCIE_nWAKE",
+ "P1_7";
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ assigned-clocks = <&clk IMX8MP_CLK_UART3>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usdhc3 {
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
+ assigned-clock-rates = <400000000>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
+ >;
+ };
+
+ pinctrl_pcal6416_0_int: pcal6416-0-int-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x146
+ >;
+ };
+
+ pinctrl_pcal6416_1_int: pcal6416-1-int-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x146
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
+ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
+ MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
+ MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
+ MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
+ >;
+ };
+};
};
&i2c3 {
- carrier_eeprom: eeprom@57{
+ carrier_eeprom: eeprom@57 {
compatible = "st,24c02", "atmel,24c02";
reg = <0x57>;
pagesize = <16>;
status = "okay";
};
-&panel0_lvds {
+&panel_lvds0 {
compatible = "edt,etml1010g3dra";
status = "okay";
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/imx8mp-clock.h>
+#include "imx8mp-pinfunc.h"
+
+&{/} {
+
+ backlight_lvds1: backlight-lvds1 {
+ compatible = "pwm-backlight";
+ pinctrl-0 = <&pinctrl_lvds1>;
+ pinctrl-names = "default";
+ power-supply = <®_vcc_12v>;
+ status = "disabled";
+ };
+
+ panel_lvds1: panel-lvds1 {
+ backlight = <&backlight_lvds1>;
+ power-supply = <®_vdd_3v3>;
+ status = "disabled";
+
+ port {
+ panel1_in: endpoint {
+ remote-endpoint = <&ldb_lvds_ch1>;
+ };
+ };
+ };
+
+ reg_vcc_12v: regulator-12v {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <12000000>;
+ regulator-min-microvolt = <12000000>;
+ regulator-name = "VCC_12V";
+ };
+
+ reg_vcc_1v8_audio: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "VCC_1V8_Audio";
+ };
+
+ reg_vcc_3v3_analog: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "VCC_3V3_Analog";
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "snd-peb-av-10";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,frame-master = <&dailink_master>;
+ simple-audio-card,mclk-fs = <32>;
+ simple-audio-card,widgets =
+ "Line", "Line In",
+ "Speaker", "Speaker",
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack";
+ simple-audio-card,routing =
+ "Speaker", "SPOP",
+ "Speaker", "SPOM",
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT",
+ "LINE1L", "Line In",
+ "LINE1R", "Line In",
+ "MIC3R", "Microphone Jack",
+ "Microphone Jack", "Mic Bias";
+
+ simple-audio-card,codec {
+ sound-dai = <&codec>;
+ };
+
+ dailink_master: simple-audio-card,cpu {
+ sound-dai = <&sai5>;
+ };
+ };
+};
+
+&i2c5 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_i2c5>;
+ pinctrl-1 = <&pinctrl_i2c5_gpio>;
+ pinctrl-names = "default", "gpio";
+ scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ codec: audio-codec@18 {
+ compatible = "ti,tlv320aic3007";
+ reg = <0x18>;
+ pinctrl-0 = <&pinctrl_tlv320>;
+ pinctrl-names = "default";
+ #sound-dai-cells = <0>;
+ ai3x-gpio-func = <0xd 0x0>;
+ ai3x-micbias-vg = <2>;
+ AVDD-supply = <®_vcc_3v3_analog>;
+ DRVDD-supply = <®_vcc_3v3_analog>;
+ DVDD-supply = <®_vcc_1v8_audio>;
+ IOVDD-supply = <®_vdd_3v3>;
+ };
+
+ eeprom@57 {
+ compatible = "atmel,24c32";
+ reg = <0x57>;
+ pagesize = <32>;
+ vcc-supply = <®_vdd_3v3>;
+ };
+};
+
+&ldb_lvds_ch1 {
+ remote-endpoint = <&panel1_in>;
+};
+
+&pwm2 {
+ pinctrl-0 = <&pinctrl_pwm2>;
+ pinctrl-names = "default";
+};
+
+&sai5 {
+ pinctrl-0 = <&pinctrl_sai5>;
+ pinctrl-names = "default";
+ assigned-clocks = <&clk IMX8MP_CLK_SAI5>;
+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <12288000>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>,
+ <&clk IMX8MP_CLK_DUMMY>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>,
+ <&clk IMX8MP_CLK_DUMMY>,
+ <&clk IMX8MP_CLK_DUMMY>,
+ <&clk IMX8MP_AUDIO_PLL1_OUT>,
+ <&clk IMX8MP_AUDIO_PLL2_OUT>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k",
+ "pll11k";
+ #sound-dai-cells = <0>;
+ fsl,sai-mclk-direction-output;
+ fsl,sai-synchronous-rx;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_i2c5: i2c5grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x400001c2
+ MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_i2c5_gpio: i2c5gpiogrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x1e2
+ MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1e2
+ >;
+ };
+
+ pinctrl_lvds1: lvds1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x12
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x12
+ >;
+ };
+
+ pinctrl_sai5: sai5grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0xd6
+ MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 0xd6
+ MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0xd6
+ MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0xd6
+ MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0xd6
+ >;
+ };
+
+ pinctrl_tlv320: tlv320grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x16
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/imx8mp-clock.h>
+
+/dts-v1/;
+/plugin/;
+
+&backlight_lvds0 {
+ brightness-levels = <0 8 16 32 64 128 255>;
+ default-brightness-level = <8>;
+ enable-gpios = <&gpio5 23 GPIO_ACTIVE_LOW>;
+ num-interpolated-steps = <2>;
+ pwms = <&pwm1 0 66667 0>;
+ status = "okay";
+};
+
+&lcdif2 {
+ status = "okay";
+};
+
+&lvds_bridge {
+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>;
+ assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
+ /*
+ * The LVDS panel uses 66.5 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to
+ * 66.5 * 7 = 465.5 MHz so the LDB serializer and LCDIFv3 scanout
+ * engine can reach accurate pixel clock of exactly 66.5 MHz.
+ */
+ assigned-clock-rates = <0>, <465500000>;
+ status = "okay";
+};
+
+&panel_lvds0 {
+ compatible = "powertip,ph128800t006-zhc01";
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
"phytec,imx8mp-phycore-fpsc", "fsl,imx8mp";
model = "PHYTEC i.MX8MP Libra RDK FPSC";
- backlight_lvds0: backlight0 {
+ backlight_lvds0: backlight-lvds0 {
compatible = "pwm-backlight";
pinctrl-0 = <&pinctrl_lvds0>;
pinctrl-names = "default";
stdout-path = &uart4;
};
- panel0_lvds: panel-lvds {
+ panel_lvds0: panel-lvds0 {
/* compatible panel in overlay */
backlight = <&backlight_lvds0>;
power-supply = <®_vdd_3v3>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
- MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1C0
+ MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1c0
>;
};
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH
+ */
+
+#include <dt-bindings/clock/imx8mp-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx8mp-pinfunc.h"
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ wlbt_clock: clock-32768 {
+ compatible = "fixed-clock";
+ clock-accuracy = <20000>;
+ clock-frequency = <32768>;
+ clock-output-names = "WIFIBT_SLOW_CLK";
+ #clock-cells = <0>;
+ };
+
+ usdhc1_pwrseq: pwr-seq {
+ compatible = "mmc-pwrseq-simple";
+ post-power-on-delay-ms = <250>;
+ reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&iomuxc {
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x140 /* RTS */
+ MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x140 /* CTS */
+ MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 /* RX */
+ MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 /* TX */
+ >;
+ };
+
+ pinctrl_bluetooth: bluetoothgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x106 /* BT_DEV_WAKE_EXP */
+ MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x106 /* BT_REG_ON_EXP */
+ MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x106 /* BT_HOST_WAKE_EXP */
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 /* SDIO_CLK */
+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 /* SDIO_CMD */
+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 /* SDIO_D0 */
+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 /* SDIO_D1 */
+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 /* SDIO_D2 */
+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 /* SDIO_D3 */
+ >;
+ };
+
+ pinctrl_wifi: wifigrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x106 /* WL_REG_ON_EXP */
+ >;
+ };
+};
+
+&uart3 {
+ assigned-clocks = <&clk IMX8MP_CLK_UART3>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+ pinctrl-0 = <&pinctrl_uart3>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ pinctrl-0 = <&pinctrl_bluetooth>;
+ pinctrl-names = "default";
+ clock-names = "lpo";
+ clocks = <&wlbt_clock>;
+ device-wakeup-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
+ max-speed = <3000000>;
+ shutdown-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+ vbat-supply = <®_vcc_3v3_sw>;
+ vddio-supply = <®_vcc_1v8_exp_con>;
+ };
+};
+
+&usdhc1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-names = "default";
+ bus-width = <4>;
+ max-frequency = <50000000>;
+ mmc-pwrseq = <&usdhc1_pwrseq>;
+ non-removable;
+ vmmc-supply = <®_vcc_3v3_sw>;
+ status = "okay";
+
+ wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ pinctrl-0 = <&pinctrl_wifi>;
+ pinctrl-names = "default";
+ reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
+ };
+};
compatible = "gpio-fan";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fan>;
+ fan-supply = <®_vcc_5v_sw>;
gpio-fan,speed-map = <0 0
13000 1>;
gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
regulator-max-microvolt = <3300000>;
};
+ reg_vcc_1v8_exp_con: regulator-vcc-1v8 {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "VCC_1V8_EXP_CON";
+ };
+
thermal-zones {
soc-thermal {
trips {
};
};
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ sda-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
&ldb_lvds_ch1 {
remote-endpoint = <&panel1_in>;
};
>;
};
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3gpiogrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1e2
+ MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1e2
+ >;
+ };
+
pinctrl_lvds1: lvds1grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x12
pinctrl_rtc: rtcgrp {
fsl,pins = <
- MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1C0
+ MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c0
>;
};
regulator-min-microvolt = <3300000>;
regulator-name = "VDD_IO";
};
+
+ reg_vdd_1v8: regulator-vdd-1v8 {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "VDD_1V8";
+ };
};
&A53_0 {
spi-max-frequency = <80000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
+ vcc-supply = <®_vdd_1v8>;
};
};
nxp,dvs-standby-voltage = <850000>;
};
- buck4: BUCK4{
+ buck4: BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-always-on;
};
- buck5: BUCK5{
+ buck5: BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
};
};
- som_eeprom: eeprom@50{
+ som_eeprom: eeprom@50 {
compatible = "st,24c01", "atmel,24c01";
reg = <0x50>;
pagesize = <16>;
pinctrl-0 = <&pinctrl_gpio4>, <&pinctrl_gpio6>;
};
+&hdmi_pai {
+ status = "okay";
+};
+
&hdmi_pvi {
status = "okay";
};
};
pinctrl_mcu_int: mcuintgrp {
- fsl,pins = <MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x1C0>; /* MCU_INT# */
+ fsl,pins = <MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x1c0>; /* MCU_INT# */
};
/* SMARC LCD1_BKLT_PWM */
/* SMARC SLEEP# */
pinctrl_sleep: sleepgrp {
- fsl,pins = <MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x1C0>; /* SMARC S149 - SLEEP# */
+ fsl,pins = <MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x1c0>; /* SMARC S149 - SLEEP# */
};
/* SMARC SMB_ALERT# */
pinctrl_smb_alert: smbalertgrp {
- fsl,pins = <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x1C0>; /* SMARC P1 - SMB_ALERT# */
+ fsl,pins = <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x1c0>; /* SMARC P1 - SMB_ALERT# */
};
/* TPM_CS# */
compatible = "shared-dma-pool";
reusable;
size = <0 0x38000000>;
- alloc-ranges = <0 0x40000000 0 0xB0000000>;
+ alloc-ranges = <0 0x40000000 0 0xb0000000>;
linux,cma-default;
};
};
"Headphone Jack", "HPL",
"Headphone Jack", "HPR";
};
+
+ sound-hdmi {
+ compatible = "fsl,imx-audio-hdmi";
+ model = "audio-hdmi";
+ audio-cpu = <&aud2htx>;
+ hdmi-out;
+ };
+};
+
+&aud2htx {
+ status = "okay";
};
&ecspi3 {
reset-deassert-us = <50000>;
enet-phy-lane-no-swap;
interrupt-parent = <&gpio4>;
- interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
reset-deassert-us = <50000>;
enet-phy-lane-no-swap;
interrupt-parent = <&gpio4>;
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
status = "disabled";
};
+&hdmi_pai {
+ status = "okay";
+};
+
&hdmi_pvi {
status = "okay";
};
fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>,
<MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>,
<MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>,
- <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000154>;
+ <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000030>;
};
pinctrl_gpt1: gpt1grp {
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2021-2022 TQ-Systems GmbH
- * Author: Alexander Stein <alexander.stein@tq-group.com>
+ * Copyright 2021-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Alexander Stein
*/
/dts-v1/;
compatible = "shared-dma-pool";
reusable;
size = <0 0x38000000>;
- alloc-ranges = <0 0x40000000 0 0xB0000000>;
+ alloc-ranges = <0 0x40000000 0 0xb0000000>;
linux,cma-default;
};
};
"Line Out Jack", "LOR";
};
+ sound-hdmi {
+ compatible = "fsl,imx-audio-hdmi";
+ model = "audio-hdmi";
+ audio-cpu = <&aud2htx>;
+ hdmi-out;
+ };
+
thermal-zones {
soc-thermal {
trips {
};
};
+&aud2htx {
+ status = "okay";
+};
+
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
reset-deassert-us = <50000>;
enet-phy-lane-no-swap;
interrupt-parent = <&gpio4>;
- interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
};
};
};
reset-deassert-us = <50000>;
enet-phy-lane-no-swap;
interrupt-parent = <&gpio4>;
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
};
};
};
"", "", "", "";
};
+&hdmi_pai {
+ status = "okay";
+};
+
&hdmi_pvi {
status = "okay";
};
<MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12>,
<MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12>,
<MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12>,
- <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>;
+ <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>,
+ <MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x16>;
};
pinctrl_eqos_event: eqosevtgrp {
fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>,
<MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>,
<MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>,
- <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000010>;
+ <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000030>;
};
pinctrl_hoggpio2: hoggpio2grp {
/ {
model = "Variscite VAR-SOM-MX8M-PLUS on Symphony-Board";
compatible = "variscite,var-som-mx8mp-symphony", "variscite,var-som-mx8mp", "fsl,imx8mp";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_POWER;
+ gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ off-on-delay-us = <12000>;
+ };
+
+ reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
+ compatible = "regulator-gpio";
+ regulator-name = "VSD_VSEL";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ states = <3300000 0x0 1800000 0x1>;
+ vin-supply = <&ldo5>;
+ };
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ /* GPIO expander */
+ pca9534: gpio@20 {
+ compatible = "nxp,pca9534";
+ reg = <0x20>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pca9534>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
+
+ usb3-sata-sel-hog {
+ gpio-hog;
+ gpios = <4 0>;
+ output-low;
+ line-name = "usb3_sata_sel";
+ };
+ };
+};
+
+/* Console */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+/* SD-card */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ vqmmc-supply = <®_usdhc2_vqmmc>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_pca9534: pca9534grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0xc0
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40
+ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c4
+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0xc0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
+ >;
+ };
};
/ {
model = "Variscite VAR-SOM-MX8M Plus module";
- chosen {
- stdout-path = &uart2;
- };
-
- gpio-leds {
- compatible = "gpio-leds";
-
- led-0 {
- function = LED_FUNCTION_POWER;
- gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0xc0000000>,
<0x1 0x00000000 0 0xc0000000>;
};
- reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
- compatible = "regulator-fixed";
- regulator-name = "VSD_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- startup-delay-us = <100>;
- off-on-delay-us = <12000>;
+ iw61x_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ post-power-on-delay-ms = <100>;
+ power-off-delay-us = <10000>;
+ reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
+ <&gpio2 19 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
};
- reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
- compatible = "regulator-gpio";
- regulator-name = "VSD_VSEL";
- regulator-min-microvolt = <1800000>;
+ reg_audio_supply: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "wm8904-supply";
+ regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
- states = <3300000 0x0 1800000 0x1>;
- vin-supply = <&ldo5>;
+ regulator-always-on;
};
reg_phy_supply: regulator-phy-supply {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,bitclock-master = <&codec_dai>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <&codec_dai>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,name = "wm8904-audio";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPOUTL",
+ "Headphone Jack", "HPOUTR",
+ "IN2L", "Line In Jack",
+ "IN2R", "Line In Jack",
+ "IN1L", "Microphone Jack",
+ "IN1R", "Microphone Jack";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack",
+ "Line", "Line In Jack";
+
+ codec_dai: simple-audio-card,codec {
+ sound-dai = <&wm8904>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai3>;
+ };
+ };
};
&A53_0 {
cpu-supply = <&buck2>;
};
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ /* Resistive touch controller */
+ tsc2046: touchscreen@0 {
+ compatible = "ti,tsc2046";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_restouch>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
+ spi-max-frequency = <1500000>;
+ pendown-gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
+ ti,x-min = /bits/ 16 <125>;
+ ti,x-max = /bits/ 16 <4008>;
+ ti,y-min = /bits/ 16 <282>;
+ ti,y-max = /bits/ 16 <3864>;
+ ti,x-plate-ohms = /bits/ 16 <180>;
+ ti,pressure-max = /bits/ 16 <255>;
+ ti,debounce-max = /bits/ 16 <10>;
+ ti,debounce-tol = /bits/ 16 <3>;
+ ti,debounce-rep = /bits/ 16 <1>;
+ ti,settle-delay-usec = /bits/ 16 <150>;
+ ti,keep-vref-on;
+ wakeup-source;
+ };
+};
+
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
};
};
};
-};
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
-
- /* GPIO expander */
- pca9534: gpio@20 {
- compatible = "nxp,pca9534";
- reg = <0x20>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pca9534>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&gpio1>;
- interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
- wakeup-source;
-
- usb3-sata-sel-hog {
- gpio-hog;
- gpios = <4 0>;
- output-low;
- line-name = "usb3_sata_sel";
- };
+ wm8904: audio-codec@1a {
+ compatible = "wlf,wm8904";
+ reg = <0x1a>;
+ #sound-dai-cells = <0>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
+ clock-names = "mclk";
+ AVDD-supply = <®_audio_supply>;
+ CPVDD-supply = <®_audio_supply>;
+ DBVDD-supply = <®_audio_supply>;
+ DCVDD-supply = <®_audio_supply>;
+ MICVDD-supply = <®_audio_supply>;
+ wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
+ "soft", "music";
+ /*
+ * Config registers per name, respectively:
+ * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
+ * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
+ * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1
+ * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1
+ * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
+ */
+ wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
+ /bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
+ /bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
+ /bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
+ /bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
+ /* GPIO1 = DMIC_CLK, don't touch others */
+ wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
};
};
-/* Console */
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
+&sai3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3>;
+ assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <11536000>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>,
+ <&clk IMX8MP_CLK_DUMMY>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>,
+ <&clk IMX8MP_CLK_DUMMY>,
+ <&clk IMX8MP_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ fsl,sai-mclk-direction-output;
+ status = "okay";
};
-/* SD-card */
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
- vmmc-supply = <®_usdhc2_vmmc>;
- vqmmc-supply = <®_usdhc2_vqmmc>;
- bus-width = <4>;
- status = "okay";
+/* BT */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bluetooth>;
+ assigned-clocks = <&clk IMX8MP_CLK_UART3>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "nxp,88w8987-bt";
+ };
+};
+
+/* WIFI */
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>;
+ bus-width = <4>;
+ non-removable;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&iw61x_pwrseq>;
+ status = "okay";
};
/* eMMC */
&iomuxc {
+ pinctrl_bluetooth: bluetoothgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0xc0
+ MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0xc0
+ MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0xc0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x12
+ MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x12
+ MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x12
+ MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x12
+ >;
+ };
+
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
>;
};
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
- MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
- >;
- };
-
- pinctrl_pca9534: pca9534grp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0xc0
- >;
- };
-
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1c0
>;
};
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40
- MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40
+ pinctrl_restouch: restouchgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0xc0
>;
};
- pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c4
- MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
- MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0xc0
- >;
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
+ MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
+ MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
+ MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
+ MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
+ MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0xd6
+ MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0xd6
+ >;
};
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
- >;
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
+ MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
+ MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
+ MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
+ >;
};
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
- >;
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
+ >;
};
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
- >;
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
+ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
+ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
+ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
+ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
+ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
+ >;
};
pinctrl_usdhc3: usdhc3grp {
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
>;
};
+
+ pinctrl_wifi: wifigrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0xc0
+ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0xc0
+ >;
+ };
};
interrupt-parent = <&gpio4>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
};
+
+ magnetometer@1e {
+ compatible = "st,lis2mdl";
+ reg = <0x1e>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mag>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
+ };
};
&pcie_phy {
>;
};
+ pinctrl_mag: maggrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x150 /* IRQ */
+ >;
+ };
+
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */
};
/* Verdin HDMI_1 */
+&hdmi_pai {
+ status = "okay";
+};
+
&hdmi_pvi {
status = "okay";
};
};
/* Verdin HDMI_1 */
+&hdmi_pai {
+ status = "okay";
+};
+
&hdmi_pvi {
status = "okay";
};
};
/* Verdin HDMI_1 */
+&hdmi_pai {
+ status = "okay";
+};
+
&hdmi_pvi {
status = "okay";
};
};
/* Verdin HDMI_1 */
+&hdmi_pai {
+ status = "okay";
+};
+
&hdmi_pvi {
status = "okay";
};
#pwm-cells = <3>;
};
-/* TODO: Verdin I2S_1 */
-
-/* TODO: Verdin I2S_2 */
-
&snvs_pwrkey {
status = "okay";
};
pinctrl_hpdet: hpdetgrp {
fsl,pins = <
- MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0xC0 /* HP_DET */
+ MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0xc0 /* HP_DET */
>;
};
&a53_opp_table {
opp-1000000000 {
- opp-microvolt = <950000>;
+ opp-microvolt = <1000000>;
};
};
compatible = "purism,librem5", "fsl,imx8mq";
chassis-type = "handset";
+ aliases {
+ rtc0 = &rtc;
+ rtc1 = &snvs_rtc;
+ };
+
backlight_dsi: backlight-dsi {
compatible = "led-backlight";
leds = <&led_backlight>;
vibrator {
compatible = "pwm-vibrator";
- pwms = <&pwm1 0 1000000000 0>;
+ pwms = <&pwm1 0 50000 0>;
pwm-names = "enable";
vcc-supply = <®_vdd_3v3>;
};
>;
};
+ pinctrl_i2c1_gpio: i2c1-gpiogrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x26
+ MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x26
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000026
>;
};
+ pinctrl_i2c2_gpio: i2c2-gpiogrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x26
+ MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x26
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000026
>;
};
+ pinctrl_i2c3_gpio: i2c3-gpiogrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x26
+ MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x26
+ >;
+ };
+
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000026
>;
};
+ pinctrl_i2c4_gpio: i2c4-gpiogrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x26
+ MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x26
+ >;
+ };
+
pinctrl_keys: keysgrp {
fsl,pins = <
/* VOL- */
- MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x01C0
+ MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x01c0
/* VOL+ */
- MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x01C0
+ MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x01c0
>;
};
pinctrl_tcpc: tcpcgrp {
fsl,pins = <
/* TCPC_INT */
- MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x01C0
+ MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x01c0
>;
};
&i2c1 {
clock-frequency = <384000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
typec_pd: usb-pd@3f {
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-ramp-delay = <1250>;
- rohm,dvs-run-voltage = <880000>;
- rohm,dvs-idle-voltage = <820000>;
- rohm,dvs-suspend-voltage = <810000>;
+ rohm,dvs-run-voltage = <900000>;
+ rohm,dvs-idle-voltage = <850000>;
+ rohm,dvs-suspend-voltage = <850000>;
regulator-always-on;
};
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-ramp-delay = <1250>;
- rohm,dvs-run-voltage = <950000>;
- rohm,dvs-idle-voltage = <850000>;
+ rohm,dvs-run-voltage = <1000000>;
+ rohm,dvs-idle-voltage = <900000>;
regulator-always-on;
};
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
- rohm,dvs-run-voltage = <850000>;
+ rohm,dvs-run-voltage = <900000>;
};
buck4_reg: BUCK4 {
regulator-name = "buck4";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
- rohm,dvs-run-voltage = <930000>;
+ rohm,dvs-run-voltage = <1000000>;
};
buck5_reg: BUCK5 {
};
};
- rtc@68 {
+ rtc: rtc@68 {
compatible = "microcrystal,rv4162";
reg = <0x68>;
pinctrl-names = "default";
&i2c2 {
clock-frequency = <384000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
magnetometer: magnetometer@1e {
&i2c3 {
clock-frequency = <384000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
codec: audio-codec@1a {
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
#sound-dai-cells = <0>;
- mic-cfg = <0x200>;
DCVDD-supply = <®_aud_1v8>;
DBVDD-supply = <®_aud_1v8>;
AVDD-supply = <®_aud_1v8>;
&i2c4 {
clock-frequency = <384000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
vcm@c {
status = "okay";
};
-&snvs_rtc {
- status = "disabled";
-};
-
&uart1 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
&usdhc2 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
- assigned-clock-rates = <200000000>;
+ assigned-clock-rates = <50000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
mmc-pwrseq = <&usdhc2_pwrseq>;
post-power-on-delay-ms = <20>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- max-frequency = <100000000>;
+ max-frequency = <50000000>;
disable-wp;
cap-sdio-irq;
+ cap-power-off-card;
keep-power-in-suspend;
wakeup-source;
status = "okay";
fsl,ext-reset-output;
status = "okay";
};
-
-&a53_opp_table {
- opp-1000000000 {
- opp-microvolt = <850000>;
- };
-
- opp-1500000000 {
- opp-microvolt = <950000>;
- };
-};
<&clk IMX8MQ_GPU_PLL_OUT>,
<&clk IMX8MQ_GPU_PLL>;
assigned-clock-rates = <800000000>, <800000000>,
- <800000000>, <800000000>, <0>;
+ <800000000>, <400000000>, <0>;
power-domains = <&pgc_gpu>;
};
pinctrl_mipi_csi0: mipi-csi0grp {
fsl,pins = <
- IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xC0000041
- IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xC0000041
- IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041
+ IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xc0000041
+ IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xc0000041
+ IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xc0000041
>;
};
pinctrl_mipi_csi1: mipi-csi1grp {
fsl,pins = <
- IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xC0000041
- IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xC0000041
- IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xC0000041
+ IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xc0000041
+ IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xc0000041
+ IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xc0000041
>;
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+&ddr_pmu0 {
+ compatible = "fsl,imx8qm-ddr-pmu", "fsl,imx8-ddr-pmu";
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&ddr_subsys {
+ ddr_pmu1: ddr-pmu@5c120000 {
+ compatible = "fsl,imx8qm-ddr-pmu", "fsl,imx8-ddr-pmu";
+ reg = <0x5c120000 0x10000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
#size-cells = <0>;
cpu-map {
- cluster0 {
+ cluster0: cluster0 {
core0 {
cpu = <&A53_0>;
};
};
};
- cluster1 {
+ cluster1: cluster1 {
core0 {
cpu = <&A72_0>;
};
reg = <0x0 0x100>;
clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>;
enable-method = "psci";
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
gic: interrupt-controller@51a00000 {
compatible = "arm,gic-v3";
reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
- <0x0 0x51b00000 0 0xC0000>, /* GICR */
+ <0x0 0x51b00000 0 0xc0000>, /* GICR */
<0x0 0x52000000 0 0x2000>, /* GICC */
<0x0 0x52010000 0 0x1000>, /* GICH */
<0x0 0x52020000 0 0x20000>; /* GICV */
#include "imx8-ss-img.dtsi"
#include "imx8-ss-dma.dtsi"
#include "imx8-ss-conn.dtsi"
+ #include "imx8-ss-ddr.dtsi"
#include "imx8-ss-lsio.dtsi"
#include "imx8-ss-hsio.dtsi"
};
#include "imx8qm-ss-lvds.dtsi"
#include "imx8qm-ss-mipi.dtsi"
#include "imx8qm-ss-hsio.dtsi"
+#include "imx8qm-ss-ddr.dtsi"
/delete-node/ &dsp;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2024 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx8qp-apalis-v1.1.dtsi"
+#include "imx8-apalis-eval-v1.2.dtsi"
+
+/ {
+ model = "Toradex Apalis iMX8QP V1.1 on Apalis Evaluation Board V1.2";
+ compatible = "toradex,apalis-imx8-v1.1-eval-v1.2",
+ "toradex,apalis-imx8-v1.1",
+ "fsl,imx8qp";
+};
+
+/* Apalis MMC1 */
+&usdhc2 {
+ /delete-property/ no-1-8-v;
+};
+
+/* Apalis SD1 */
+&usdhc3 {
+ /delete-property/ no-1-8-v;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx8qp-apalis-v1.1.dtsi"
+#include "imx8-apalis-eval-v1.1.dtsi"
+
+/ {
+ model = "Toradex Apalis iMX8QP V1.1 on Apalis Evaluation Board";
+ compatible = "toradex,apalis-imx8-v1.1-eval",
+ "toradex,apalis-imx8-v1.1",
+ "fsl,imx8qp";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx8qp-apalis-v1.1.dtsi"
+#include "imx8-apalis-ixora-v1.1.dtsi"
+
+/ {
+ model = "Toradex Apalis iMX8QP V1.1 on Apalis Ixora V1.1 Carrier Board";
+ compatible = "toradex,apalis-imx8-v1.1-ixora-v1.1",
+ "toradex,apalis-imx8-v1.1",
+ "fsl,imx8qp";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx8qp-apalis-v1.1.dtsi"
+#include "imx8-apalis-ixora-v1.2.dtsi"
+
+/ {
+ model = "Toradex Apalis iMX8QP V1.1 on Apalis Ixora V1.2 Carrier Board";
+ compatible = "toradex,apalis-imx8-v1.1-ixora-v1.2",
+ "toradex,apalis-imx8-v1.1",
+ "fsl,imx8qp";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+#include "imx8qp.dtsi"
+#include "imx8-apalis-v1.1.dtsi"
+
+&cooling_maps_map0 {
+ cooling-device =
+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
+
+#include "imx8qm.dtsi"
+
+/delete-node/ &A72_1;
+
+&cluster1 {
+ /delete-node/ core1;
+};
+
+&gpu_3d0 {
+ assigned-clock-rates = <625000000>, <625000000>;
+};
+
+&thermal_zones {
+ cpu1-thermal {
+ cooling-maps {
+ map0 {
+ cooling-device =
+ <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+};
#size-cells = <0>;
reg = <2>;
+ accelerometer@1e {
+ compatible = "nxp,fxos8700";
+ reg = <0x1e>;
+ };
+
+ gyroscope@21 {
+ compatible = "nxp,fxas21002c";
+ reg = <0x21>;
+ };
+
pressure-sensor@60 {
compatible = "fsl,mpl3115";
reg = <0x60>;
vdd-supply = <®_3v3>;
vddio-supply = <®_3v3>;
};
+
+ /* Ref SCH-54536 */
+ inertial-meter@68 {
+ compatible = "invensense,icm20602";
+ reg = <0x68>;
+ };
+
+ inertial-meter@69 {
+ compatible = "invensense,iam20380";
+ reg = <0x69>;
+ };
+
+ pressure-sensor@77 {
+ compatible = "meas,ms5611";
+ reg = <0x77>;
+ };
};
i2c@3 {
interrupt-parent = <&lsio_gpio1>;
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
};
+
+ /* Ref SCH-54536 */
+ light-sensort@60 {
+ compatible = "vishay,vcnl4035";
+ reg = <0x60>;
+ };
};
};
pinctrl_mipi_csi0: mipi-csi0grp {
fsl,pins = <
- IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041
- IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041
- IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041
+ IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xc0000041
+ IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xc0000041
+ IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xc0000041
>;
};
"ch28", "ch29", "ch30", "ch31";
};
+ sim_lpav: clock-controller@2da50000 {
+ compatible = "fsl,imx8ulp-sim-lpav";
+ reg = <0x2da50000 0x10000>;
+ clocks = <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>,
+ <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>,
+ <&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>;
+ clock-names = "bus", "core", "plat";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+
+ sim_lpav_mux: mux-controller {
+ compatible = "reg-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x8 0x00000200>;
+ };
+ };
+
cgc2: clock-controller@2da60000 {
compatible = "fsl,imx8ulp-cgc2";
reg = <0x2da60000 0x10000>;
* Copyright 2019 Toradex
*/
+#include "dt-bindings/pwm/pwm.h"
+
/ {
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_bl_on>;
+ brightness-levels = <0 45 63 88 119 158 203 255>;
+ default-brightness-level = <4>;
+ enable-gpios = <&lsio_gpio3 12 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
+ power-supply = <®_module_3v3>;
+ pwms = <&adma_pwm 0 6666667 PWM_POLARITY_INVERTED>;
+ status = "disabled";
+ };
+
chosen {
stdout-path = &lpuart3;
};
regulator-name = "usbh_vbus";
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ linux,cma-default;
+ reusable;
+ size = <0 0x1a000000>;
+ };
+ };
+
sound-card {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&dailink_master>;
/* On-module PCIe for Wi-Fi */
&pcieb {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcieb>;
+ pinctrl-0 = <&pinctrl_pcieb>, <&pinctrl_wifi>;
phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
phy-names = "pcie-phy";
reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
};
pinctrl_csi_mclk: csimclkgrp {
- fsl,pins = <IMX8QXP_CSI_MCLK_CI_PI_MCLK 0xC0000041>; /* SODIMM 75 / X3-12 */
+ fsl,pins = <IMX8QXP_CSI_MCLK_CI_PI_MCLK 0xc0000041>; /* SODIMM 75 / X3-12 */
};
pinctrl_ext_io0: extio0grp {
serial4 = &lpuart5;
};
+ bt_sco_codec: bt-sco-codec {
+ compatible = "linux,bt-sco";
+ #sound-dai-cells = <1>;
+ };
+
chosen {
stdout-path = &lpuart1;
};
linux,cma-default;
};
};
+
+ sound-wm8962 {
+ compatible = "fsl,imx-audio-wm8962";
+ model = "wm8962-audio";
+ audio-cpu = <&sai3>;
+ audio-codec = <&wm8962>;
+ hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>;
+ audio-routing =
+ "Headphone Jack", "HPOUTL",
+ "Headphone Jack", "HPOUTR",
+ "Ext Spk", "SPKOUTL",
+ "Ext Spk", "SPKOUTR",
+ "AMIC", "MICBIAS",
+ "IN3R", "AMIC",
+ "IN1R", "AMIC";
+ };
+
+ sound-bt-sco {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "bt-sco-audio";
+ simple-audio-card,format = "dsp_a";
+ simple-audio-card,bitclock-inversion;
+ simple-audio-card,frame-master = <&btcpu>;
+ simple-audio-card,bitclock-master = <&btcpu>;
+
+ simple-audio-card,codec {
+ sound-dai = <&bt_sco_codec 1>;
+ };
+
+ btcpu: simple-audio-card,cpu {
+ sound-dai = <&sai1>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <16>;
+ };
+ };
+
+ sound-micfil {
+ compatible = "fsl,imx-audio-card";
+ model = "micfil-audio";
+
+ pri-dai-link {
+ link-name = "micfil hifi";
+ format = "i2s";
+
+ cpu {
+ sound-dai = <&micfil>;
+ };
+ };
+ };
+
+ sound-xcvr {
+ compatible = "fsl,imx-audio-card";
+ model = "imx-audio-xcvr";
+
+ pri-dai-link {
+ link-name = "XCVR PCM";
+
+ cpu {
+ sound-dai = <&xcvr>;
+ };
+ };
+ };
};
&adc1 {
pinctrl-names = "default";
status = "okay";
- audio_codec: wm8962@1a {
+ wm8962: audio-codec@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clk IMX93_CLK_SAI3_GATE>;
};
};
+&micfil {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_pdm>;
+ pinctrl-1 = <&pinctrl_pdm_sleep>;
+ assigned-clocks = <&clk IMX93_CLK_PDM>;
+ assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
+ assigned-clock-rates = <49152000>;
+ status = "okay";
+};
+
+&sai1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_sai1>;
+ pinctrl-1 = <&pinctrl_sai1_sleep>;
+ assigned-clocks = <&clk IMX93_CLK_SAI1>;
+ assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
+ assigned-clock-rates = <12288000>;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
+&sai3 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_sai3>;
+ pinctrl-1 = <&pinctrl_sai3_sleep>;
+ assigned-clocks = <&clk IMX93_CLK_SAI3>;
+ assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
+ assigned-clock-rates = <12288000>;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
&usbotg1 {
adp-disable;
disable-over-current;
status = "okay";
};
+&xcvr {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_spdif>;
+ pinctrl-1 = <&pinctrl_spdif_sleep>;
+ assigned-clocks = <&clk IMX93_CLK_SPDIF>,
+ <&clk IMX93_CLK_AUDIO_XCVR>;
+ assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>,
+ <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+ assigned-clock-rates = <12288000>, <200000000>;
+ status = "okay";
+};
+
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
>;
};
+ pinctrl_pdm: pdmgrp {
+ fsl,pins = <
+ MX91_PAD_PDM_CLK__PDM_CLK 0x31e
+ MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x31e
+ MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x31e
+ >;
+ };
+
+ pinctrl_pdm_sleep: pdmsleepgrp {
+ fsl,pins = <
+ MX91_PAD_PDM_CLK__GPIO1_IO8 0x51e
+ MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x51e
+ MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x51e
+ >;
+ };
+
+ pinctrl_sai1: sai1grp {
+ fsl,pins = <
+ MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e
+ MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e
+ MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e
+ MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x31e
+ >;
+ };
+
+ pinctrl_sai1_sleep: sai1sleepgrp {
+ fsl,pins = <
+ MX91_PAD_SAI1_TXC__GPIO1_IO12 0x51e
+ MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x51e
+ MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x51e
+ MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x51e
+ >;
+ };
+
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ MX91_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e
+ MX91_PAD_GPIO_IO17__SAI3_MCLK 0x31e
+ MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 0x31e
+ MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 0x31e
+ MX91_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e
+ >;
+ };
+
+ pinctrl_sai3_sleep: sai3sleepgrp {
+ fsl,pins = <
+ MX91_PAD_GPIO_IO16__GPIO2_IO16 0x51e
+ MX91_PAD_GPIO_IO17__GPIO2_IO17 0x51e
+ MX91_PAD_GPIO_IO19__GPIO2_IO19 0x51e
+ MX91_PAD_GPIO_IO20__GPIO2_IO20 0x51e
+ MX91_PAD_GPIO_IO26__GPIO2_IO26 0x51e
+ >;
+ };
+
+ pinctrl_spdif: spdifgrp {
+ fsl,pins = <
+ MX91_PAD_GPIO_IO22__SPDIF_IN 0x31e
+ MX91_PAD_GPIO_IO23__SPDIF_OUT 0x31e
+ >;
+ };
+
+ pinctrl_spdif_sleep: spdifsleepgrp {
+ fsl,pins = <
+ MX91_PAD_GPIO_IO22__GPIO2_IO22 0x51e
+ MX91_PAD_GPIO_IO23__GPIO2_IO23 0x51e
+ >;
+ };
+
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 NXP
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/usb/pd.h>
+#include "imx91.dtsi"
+
+/ {
+ compatible = "fsl,imx91-11x11-frdm", "fsl,imx91";
+ model = "NXP i.MX91 11x11 FRDM Board";
+
+ aliases {
+ ethernet0 = &fec;
+ ethernet1 = &eqos;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ i2c0 = &lpi2c1;
+ i2c1 = &lpi2c2;
+ i2c2 = &lpi2c3;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc3;
+ rtc0 = &bbnsm_rtc;
+ rtc1 = &pcf2131;
+ serial0 = &lpuart1;
+ serial4 = &lpuart5;
+ };
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ flexcan_phy: can-phy {
+ compatible = "nxp,tja1051";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ silent-gpios = <&pcal6524 23 GPIO_ACTIVE_HIGH>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ button-k2 {
+ interrupt-parent = <&pcal6524>;
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+ label = "Button K2";
+ gpios = <&pcal6524 5 GPIO_PULL_UP>;
+ linux,code = <BTN_1>;
+ };
+
+ button-k3 {
+ interrupt-parent = <&pcal6524>;
+ interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+ label = "Button K3";
+ gpios = <&pcal6524 6 GPIO_PULL_UP>;
+ linux,code = <BTN_2>;
+ };
+ };
+
+ reg_vref_1v8: regulator-adc-vref {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "vref_1v8";
+ };
+
+ reg_m2_pwr: regulator-m2-pwr {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "M.2-power";
+ gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ off-on-delay-us = <12000>;
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ pinctrl-names = "default";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "VSD_3V3";
+ gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+
+ reg_usdhc3_vmmc: regulator-usdhc3 {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "WLAN_EN";
+ vin-supply = <®_m2_pwr>;
+ gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ /*
+ * This regulator defined as PDn pin of the IW610 wifi module.
+ * IW610 wifi chip needs more delay than other wifi chips to complete
+ * the host interface initialization after power up, otherwise the
+ * internal state of IW610 may be unstable, resulting in the failure of
+ * the SDIO3.0 switch voltage.
+ */
+ startup-delay-us = <20000>;
+ };
+
+ reg_vdd_12v: regulator-vdd-12v {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <12000000>;
+ regulator-min-microvolt = <12000000>;
+ regulator-name = "reg_vdd_12v";
+ gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_vexp_3v3: regulator-vexp-3v3 {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "VEXP_3V3";
+ vin-supply = <&buck4>;
+ gpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_vexp_5v: regulator-vexp-5v {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "VEXP_5V";
+ gpio = <&pcal6524 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x80000000 0 0x30000000>;
+ reusable;
+ size = <0 0x10000000>;
+ linux,cma-default;
+ };
+ };
+
+ soc@0 {
+ bootph-all;
+ bootph-pre-ram;
+ };
+
+ sound-mqs {
+ compatible = "fsl,imx6sx-sdb-mqs",
+ "fsl,imx-audio-mqs";
+ audio-codec = <&mqs1>;
+ audio-cpu = <&sai1>;
+ model = "mqs-audio";
+ };
+
+ usdhc3_pwrseq: usdhc3-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&adc1 {
+ vref-supply = <®_vref_1v8>;
+ status = "okay";
+};
+
+&aips1 {
+ bootph-pre-ram;
+ bootph-all;
+};
+
+&aips2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&aips3 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&clk {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&clk_ext1 {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&eqos {
+ phy-handle = <ðphy1>;
+ phy-mode = "rgmii-id";
+ pinctrl-0 = <&pinctrl_eqos>;
+ pinctrl-1 = <&pinctrl_eqos_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <5000000>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <15000>;
+ reset-deassert-us = <100000>;
+ };
+ };
+};
+
+&fec {
+ phy-handle = <ðphy2>;
+ phy-mode = "rgmii-id";
+ pinctrl-0 = <&pinctrl_fec>;
+ pinctrl-1 = <&pinctrl_fec_sleep>;
+ pinctrl-names = "default", "sleep";
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <5000000>;
+
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
+ reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <15000>;
+ reset-deassert-us = <100000>;
+ };
+ };
+};
+
+&flexcan2 {
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ pinctrl-1 = <&pinctrl_flexcan2_sleep>;
+ pinctrl-names = "default", "sleep";
+ phys = <&flexcan_phy>;
+ status = "okay";
+};
+
+&gpio1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio3 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio4 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&lpi2c1 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+ pinctrl-names = "default";
+ bootph-pre-ram;
+ bootph-some-ram;
+ status = "okay";
+
+ pcal6408: gpio@20 {
+ compatible = "nxp,pcal9554b";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ vcc-supply = <®_usdhc3_vmmc>;
+ status = "okay";
+ };
+};
+
+&lpi2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ pinctrl-names = "default";
+ bootph-pre-ram;
+ bootph-some-ram;
+ status = "okay";
+
+ pcal6524: gpio@22 {
+ compatible = "nxp,pcal6524";
+ reg = <0x22>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-parent = <&gpio3>;
+ pinctrl-0 = <&pinctrl_pcal6524>;
+ pinctrl-names = "default";
+ };
+
+ pmic@25 {
+ compatible = "nxp,pca9451a";
+ reg = <0x25>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&pcal6524>;
+ bootph-pre-ram;
+ bootph-some-ram;
+
+ regulators {
+ bootph-pre-ram;
+ bootph-some-ram;
+
+ buck1: BUCK1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <2237500>;
+ regulator-min-microvolt = <650000>;
+ regulator-name = "BUCK1";
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2: BUCK2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <2187500>;
+ regulator-min-microvolt = <600000>;
+ regulator-name = "BUCK2";
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4: BUCK4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3400000>;
+ regulator-min-microvolt = <600000>;
+ regulator-name = "BUCK4";
+ };
+
+ buck5: BUCK5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3400000>;
+ regulator-min-microvolt = <600000>;
+ regulator-name = "BUCK5";
+ };
+
+ buck6: BUCK6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3400000>;
+ regulator-min-microvolt = <600000>;
+ regulator-name = "BUCK6";
+ };
+
+ ldo1: LDO1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1600000>;
+ regulator-name = "LDO1";
+ };
+
+ ldo4: LDO4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <800000>;
+ regulator-name = "LDO4";
+ };
+
+ ldo5: LDO5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "LDO5";
+ };
+ };
+ };
+};
+
+&lpi2c3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c3>;
+ pinctrl-names = "default";
+ bootph-pre-ram;
+ bootph-some-ram;
+ status = "okay";
+
+ ptn5110: tcpc@50 {
+ compatible = "nxp,ptn5110", "tcpci";
+ reg = <0x50>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio3>;
+
+ typec1_con: connector {
+ compatible = "usb-c-connector";
+ data-role = "dual";
+ label = "USB-C";
+ op-sink-microwatt = <15000000>;
+ power-role = "dual";
+ self-powered;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 20000, 3000)>;
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ try-power-role = "sink";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ typec1_dr_sw: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+ };
+ };
+ };
+
+ pcf2131: rtc@53 {
+ compatible = "nxp,pcf2131";
+ reg = <0x53>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&pcal6524>;
+ status = "okay";
+ };
+};
+
+&lpuart1 {
+ pinctrl-0 = <&pinctrl_uart1>;
+ pinctrl-names = "default";
+ bootph-pre-ram;
+ bootph-some-ram;
+ status = "okay";
+};
+
+&lpuart5 {
+ pinctrl-0 = <&pinctrl_uart5>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ bluetooth {
+ compatible = "nxp,88w8987-bt";
+ };
+};
+
+&mqs1 {
+ clocks = <&clk IMX93_CLK_MQS1_GATE>;
+ clock-names = "mclk";
+ pinctrl-0 = <&pinctrl_mqs1>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&osc_32k {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&osc_24m {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&sai1 {
+ clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k";
+ assigned-clocks = <&clk IMX93_CLK_SAI1>;
+ assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
+ assigned-clock-rates = <24576000>;
+ #sound-dai-cells = <0>;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
+&usbotg1 {
+ adp-disable;
+ disable-over-current;
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ usb-role-switch;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ status = "okay";
+
+ port {
+ usb1_drd_sw: endpoint {
+ remote-endpoint = <&typec1_dr_sw>;
+ };
+ };
+};
+
+&usbotg2 {
+ disable-over-current;
+ dr_mode = "host";
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ status = "okay";
+};
+
+&usdhc1 {
+ bus-width = <8>;
+ non-removable;
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ bootph-pre-ram;
+ bootph-some-ram;
+ status = "okay";
+};
+
+&usdhc2 {
+ bus-width = <4>;
+ cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
+ no-mmc;
+ no-sdio;
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ vmmc-supply = <®_usdhc2_vmmc>;
+ bootph-pre-ram;
+ bootph-some-ram;
+ status = "okay";
+};
+
+&usdhc3 {
+ bus-width = <4>;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&usdhc3_pwrseq>;
+ non-removable;
+ pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>;
+ pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ vmmc-supply = <®_usdhc3_vmmc>;
+ wakeup-source;
+ status = "okay";
+};
+
+&wdog3 {
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ bootph-pre-ram;
+ bootph-some-ram;
+
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e
+ MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
+ MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
+ MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
+ MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
+ MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
+ MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe
+ MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
+ MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
+ MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e
+ MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
+ MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
+ MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
+ MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_eqos_sleep: eqossleepgrp {
+ fsl,pins = <
+ MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e
+ MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e
+ MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e
+ MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e
+ MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e
+ MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e
+ MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e
+ MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e
+ MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e
+ MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e
+ MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e
+ MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e
+ MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e
+ MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX91_PAD_ENET2_MDC__ENET2_MDC 0x57e
+ MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x57e
+ MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e
+ MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e
+ MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e
+ MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e
+ MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe
+ MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e
+ MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e
+ MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e
+ MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e
+ MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e
+ MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe
+ MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_fec_sleep: fecsleepgrp {
+ fsl,pins = <
+ MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e
+ MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
+ MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e
+ MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e
+ MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e
+ MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e
+ MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e
+ MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e
+ MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e
+ MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e
+ MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e
+ MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e
+ MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e
+ MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX91_PAD_GPIO_IO25__CAN2_TX 0x139e
+ MX91_PAD_GPIO_IO27__CAN2_RX 0x139e
+ >;
+ };
+
+ pinctrl_flexcan2_sleep: flexcan2sleepgrp {
+ fsl,pins = <
+ MX91_PAD_GPIO_IO25__GPIO2_IO25 0x31e
+ MX91_PAD_GPIO_IO27__GPIO2_IO27 0x31e
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
+ MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
+ >;
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <
+ MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
+ MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
+ >;
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+
+ pinctrl_lpi2c3: lpi2c3grp {
+ fsl,pins = <
+ MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
+ MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
+ >;
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+
+ pinctrl_lpspi3: lpspi3grp {
+ fsl,pins = <
+ MX91_PAD_GPIO_IO08__GPIO2_IO8 0x3fe
+ MX91_PAD_GPIO_IO09__LPSPI3_SIN 0x3fe
+ MX91_PAD_GPIO_IO10__LPSPI3_SOUT 0x3fe
+ MX91_PAD_GPIO_IO11__LPSPI3_SCK 0x3fe
+ >;
+ };
+
+ pinctrl_mqs1: mqs1grp {
+ fsl,pins = <
+ MX91_PAD_PDM_CLK__MQS1_LEFT 0x31e
+ MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x31e
+ >;
+ };
+
+ pinctrl_pcal6524: pcal6524grp {
+ fsl,pins = <
+ MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e
+ >;
+ bootph-pre-ram;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX91_PAD_UART1_RXD__LPUART1_RX 0x31e
+ MX91_PAD_UART1_TXD__LPUART1_TX 0x31e
+ >;
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
+ MX91_PAD_DAP_TDI__LPUART5_RX 0x31e
+ MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
+ MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582
+ MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382
+ MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382
+ MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382
+ MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382
+ MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382
+ MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382
+ MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382
+ MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382
+ MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382
+ MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
+ >;
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e
+ MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e
+ MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
+ MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
+ MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
+ MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
+ MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
+ MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
+ MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
+ MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
+ MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe
+ MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe
+ MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
+ MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
+ MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
+ MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
+ MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
+ MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
+ MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
+ MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
+ MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e
+ >;
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+
+ pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
+ fsl,pins = <
+ MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582
+ MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382
+ MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382
+ MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382
+ MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382
+ MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382
+ MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+
+ pinctrl_usdhc2_sleep: usdhc2sleepgrp {
+ fsl,pins = <
+ MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e
+ MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e
+ MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e
+ MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e
+ MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e
+ MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e
+ MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e
+ MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e
+ MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
+ MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
+ MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
+ MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
+ MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe
+ MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe
+ MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
+ MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
+ MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
+ MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
+ MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582
+ MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382
+ MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382
+ MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382
+ MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382
+ MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382
+ >;
+ };
+
+ pinctrl_usdhc3_sleep: usdhc3sleepgrp {
+ fsl,pins = <
+ MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e
+ MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e
+ MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e
+ MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e
+ MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e
+ MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e
+ >;
+ };
+
+ pinctrl_usdhc3_wlan: usdhc3wlangrp {
+ fsl,pins = <
+ MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e
+ MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e
+ MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e
+ MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e
+ MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e
+ MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe
+ MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe
+ MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
+ MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
+ MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
+ MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
+ >;
+ };
+};
/* enable SION for data and cmd pad due to ERR052021 */
pinctrl_usdhc1: usdhc1grp {
fsl,pins = /* PD | FSEL 3 | DSE X5 */
- <MX91_PAD_SD1_CLK__USDHC1_CLK 0x5be>,
+ <MX91_PAD_SD1_CLK__USDHC1_CLK 0x59e>,
/* HYS | FSEL 0 | no drive */
<MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1000>,
/* HYS | FSEL 3 | X5 */
- <MX91_PAD_SD1_CMD__USDHC1_CMD 0x400011be>,
+ <MX91_PAD_SD1_CMD__USDHC1_CMD 0x4000139e>,
/* HYS | FSEL 3 | X4 */
- <MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x4000119e>,
- <MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x4000119e>,
- <MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x4000119e>,
- <MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x4000119e>,
- <MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x4000119e>,
- <MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x4000119e>,
- <MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x4000119e>,
- <MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x4000119e>;
+ <MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e>,
+ <MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e>,
+ <MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x4000139e>,
+ <MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e>,
+ <MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e>,
+ <MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e>,
+ <MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e>,
+ <MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e>;
};
pinctrl_wdog: wdoggrp {
#include "imx91-pinfunc.h"
#include "imx91_93_common.dtsi"
+/{
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tmu 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <80000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu-crit {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+};
+
+&aips1 {
+ tmu: thermal-sensor@44482000 {
+ compatible = "fsl,imx91-tmu";
+ reg = <0x44482000 0x1000>;
+ #thermal-sensor-cells = <0>;
+ clocks = <&clk IMX93_CLK_TMC_GATE>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "thr1", "thr2", "ready";
+ nvmem-cells = <&tmu_trim1>, <&tmu_trim2>;
+ nvmem-cell-names = "trim1", "trim2";
+ };
+};
+
&clk {
compatible = "fsl,imx91-ccm";
};
clock-names = "apb", "axi", "nic", "disp", "cam",
"lcdif", "isi", "csi";
};
+
+&ocotp {
+ tmu_trim1: tmu-trim@a0 {
+ reg = <0xa0 0x4>;
+ };
+
+ tmu_trim2: tmu-trim@a4 {
+ reg = <0xa4 0x4>;
+ };
+};
};
+ flexcan_phy: can-phy {
+ compatible = "nxp,tja1057";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ silent-gpios = <&adp5585 6 GPIO_ACTIVE_HIGH>;
+ };
+
reg_vdd_12v: regulator-vdd-12v {
compatible = "regulator-fixed";
regulator-name = "VDD_12V";
enable-active-high;
};
- reg_can2_standby: regulator-can2-standby {
- compatible = "regulator-fixed";
- regulator-name = "can2-stby";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&adp5585 6 GPIO_ACTIVE_LOW>;
- };
-
reg_m2_pwr: regulator-m2-pwr {
compatible = "regulator-fixed";
regulator-name = "M.2-power";
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
- xceiver-supply = <®_can2_standby>;
+ phys = <&flexcan_phy>;
status = "okay";
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/dts-v1/;
+
+#include <dt-bindings/usb/pd.h>
+#include "imx93.dtsi"
+
+/ {
+ compatible = "fsl,imx93-11x11-frdm", "fsl,imx93";
+ model = "NXP i.MX93 11X11 FRDM board";
+
+ aliases {
+ can0 = &flexcan2;
+ ethernet0 = &fec;
+ ethernet1 = &eqos;
+ i2c0 = &lpi2c1;
+ i2c1 = &lpi2c2;
+ i2c2 = &lpi2c3;
+ mmc0 = &usdhc1; /* EMMC */
+ mmc1 = &usdhc2; /* uSD */
+ rtc0 = &pcf2131;
+ serial0 = &lpuart1;
+ serial4 = &lpuart5;
+ };
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ flexcan2_phy: can-phy {
+ compatible = "nxp,tja1051";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ silent-gpios = <&pcal6524 23 GPIO_ACTIVE_HIGH>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ button-k2 {
+ label = "Button K2";
+ linux,code = <BTN_1>;
+ gpios = <&pcal6524 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ interrupt-parent = <&pcal6524>;
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ button-k3 {
+ label = "Button K3";
+ linux,code = <BTN_2>;
+ gpios = <&pcal6524 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ interrupt-parent = <&pcal6524>;
+ interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ off-on-delay-us = <12000>;
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ pinctrl-names = "default";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "VSD_3V3";
+ vin-supply = <&buck4>;
+ gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usdhc3_vmmc: regulator-usdhc3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VPCIe_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <20000>;
+ gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x80000000 0 0x30000000>;
+ reusable;
+ size = <0 0x10000000>;
+ linux,cma-default;
+ };
+
+ rsc_table: rsc-table@2021e000 {
+ reg = <0 0x2021e000 0 0x1000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@a4000000 {
+ reg = <0 0xa4000000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@a4008000 {
+ reg = <0 0xa4008000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring0: vdev1vring0@a4010000 {
+ reg = <0 0xa4010000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring1: vdev1vring1@a4018000 {
+ reg = <0 0xa4018000 0 0x8000>;
+ no-map;
+ };
+
+ vdevbuffer: vdevbuffer@a4020000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xa4020000 0 0x100000>;
+ no-map;
+ };
+ };
+
+ sound-mqs {
+ compatible = "fsl,imx-audio-mqs";
+ model = "mqs-audio";
+ audio-cpu = <&sai1>;
+ audio-codec = <&mqs1>;
+ };
+
+ usdhc3_pwrseq: mmc-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&adc1 {
+ vref-supply = <&buck5>;
+ status = "okay";
+};
+
+&mu1 {
+ status = "okay";
+};
+
+&cm33 {
+ mboxes = <&mu1 0 1>,
+ <&mu1 1 1>,
+ <&mu1 3 1>;
+ mbox-names = "tx", "rx", "rxdb";
+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
+ <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
+ status = "okay";
+};
+
+&eqos {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_eqos>;
+ pinctrl-1 = <&pinctrl_eqos_sleep>;
+ phy-handle = <ðphy1>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <5000000>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
+ realtek,clkout-disable;
+ };
+ };
+};
+
+&fec {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_fec>;
+ pinctrl-1 = <&pinctrl_fec_sleep>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy2>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <5000000>;
+
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
+ realtek,clkout-disable;
+ };
+ };
+};
+
+&flexcan2 {
+ phys = <&flexcan2_phy>;
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ pinctrl-1 = <&pinctrl_flexcan2_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+};
+
+&lpi2c1 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ pcal6408: gpio@20 {
+ compatible = "nxp,pcal6408";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&lpi2c2 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ pcal6524: gpio@22 {
+ compatible = "nxp,pcal6524";
+ reg = <0x22>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gpio3>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ pinctrl-0 = <&pinctrl_pcal6524>;
+ pinctrl-names = "default";
+ /* does not boot with supplier set, because it is the bucks interrupt parent */
+ /* vcc-supply = <&buck4>; */
+ };
+
+ pmic@25 {
+ compatible = "nxp,pca9451a";
+ reg = <0x25>;
+ interrupt-parent = <&pcal6524>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+
+ regulators {
+
+ buck1: BUCK1 {
+ regulator-name = "VDD_SOC_0V8";
+ regulator-min-microvolt = <610000>;
+ regulator-max-microvolt = <950000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2: BUCK2 {
+ regulator-name = "LPD4_x_VDDQ_0V6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <670000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4: BUCK4 {
+ regulator-name = "VDD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ buck5: BUCK5 {
+ regulator-name = "VDD_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ buck6: BUCK6 {
+ regulator-name = "LPD4_x_VDD2_1V1";
+ regulator-min-microvolt = <1060000>;
+ regulator-max-microvolt = <1140000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo1: LDO1 {
+ regulator-name = "NVCC_BBSM_1V8";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <1980000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4: LDO4 {
+ regulator-name = "VDD_ANA_0V8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <840000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo5: LDO5 {
+ regulator-name = "NVCC_SD";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ pagesize = <64>;
+ vcc-supply = <&buck4>;
+ };
+};
+
+&lpi2c3 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c3>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ ptn5110: tcpc@50 {
+ compatible = "nxp,ptn5110", "tcpci";
+ reg = <0x50>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+
+ typec1_con: connector {
+ compatible = "usb-c-connector";
+ data-role = "dual";
+ label = "USB-C";
+ op-sink-microwatt = <15000000>;
+ power-role = "dual";
+ self-powered;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 20000, 3000)>;
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ try-power-role = "sink";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ typec1_dr_sw: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+ };
+ };
+ };
+
+ pcf2131: rtc@53 {
+ compatible = "nxp,pcf2131";
+ reg = <0x53>;
+ interrupt-parent = <&pcal6524>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&lpuart1 { /* console */
+ pinctrl-0 = <&pinctrl_uart1>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&lpuart5 {
+ pinctrl-0 = <&pinctrl_uart5>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "nxp,88w8987-bt";
+ device-wakeup-gpios = <&pcal6408 3 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pcal6524 19 GPIO_ACTIVE_LOW>;
+ vcc-supply = <®_usdhc3_vmmc>;
+ };
+};
+
+&mqs1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mqs1>;
+ clocks = <&clk IMX93_CLK_MQS1_GATE>;
+ clock-names = "mclk";
+ status = "okay";
+};
+
+&sai1 {
+ #sound-dai-cells = <0>;
+ clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k";
+ assigned-clocks = <&clk IMX93_CLK_SAI1>;
+ assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
+ assigned-clock-rates = <24576000>;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
+&usbotg1 {
+ adp-disable;
+ disable-over-current;
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ usb-role-switch;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ status = "okay";
+
+ port {
+ usb1_drd_sw: endpoint {
+ remote-endpoint = <&typec1_dr_sw>;
+ };
+ };
+};
+
+&usbotg2 {
+ disable-over-current;
+ dr_mode = "host";
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ status = "okay";
+};
+
+&usdhc1 {
+ bus-width = <8>;
+ non-removable;
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ vmmc-supply = <&buck4>;
+ status = "okay";
+};
+
+&usdhc2 {
+ bus-width = <4>;
+ cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
+ no-mmc;
+ no-sdio;
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&usdhc3 {
+ bus-width = <4>;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&usdhc3_pwrseq>;
+ non-removable;
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc3_sleep>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ vmmc-supply = <®_usdhc3_vmmc>;
+ status = "okay";
+};
+
+&wdog3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
+ MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
+ MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
+ MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
+ MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
+ MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
+ MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e
+ MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
+ MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
+ MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
+ MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
+ MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
+ MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
+ MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_eqos_sleep: eqossleepgrp {
+ fsl,pins = <
+ MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e
+ MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e
+ MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e
+ MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e
+ MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e
+ MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e
+ MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e
+ MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e
+ MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e
+ MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e
+ MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e
+ MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e
+ MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e
+ MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
+ MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
+ MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
+ MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
+ MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
+ MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
+ MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e
+ MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
+ MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
+ MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
+ MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
+ MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
+ MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e
+ MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_fec_sleep: fecsleepgrp {
+ fsl,pins = <
+ MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e
+ MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
+ MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e
+ MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e
+ MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e
+ MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e
+ MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e
+ MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e
+ MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e
+ MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e
+ MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e
+ MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e
+ MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e
+ MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
+ MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
+ >;
+ };
+
+ pinctrl_flexcan2_sleep: flexcan2sleepgrp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO25__GPIO2_IO25 0x31e
+ MX93_PAD_GPIO_IO27__GPIO2_IO27 0x31e
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
+ MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <
+ MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
+ MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c3: lpi2c3grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
+ MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
+ >;
+ };
+
+ pinctrl_mqs1: mqs1grp {
+ fsl,pins = <
+ MX93_PAD_PDM_CLK__MQS1_LEFT 0x31e
+ MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x31e
+ >;
+ };
+
+ pinctrl_pcal6524: pcal6524grp {
+ fsl,pins = <
+ MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
+ MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
+ MX93_PAD_DAP_TDI__LPUART5_RX 0x31e
+ MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
+ MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_sleep: usdhc2-sleepgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e
+ MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e
+ MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e
+ MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e
+ MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e
+ MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e
+ MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582
+ MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382
+ MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382
+ MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382
+ MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382
+ MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e
+ MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e
+ MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e
+ MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e
+ MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e
+ MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe
+ MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe
+ MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe
+ MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe
+ MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe
+ MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe
+ >;
+ };
+
+ pinctrl_usdhc3_sleep: usdhc3grpsleepgrp {
+ fsl,pins = <
+ MX93_PAD_SD3_CLK__GPIO3_IO20 0x31e
+ MX93_PAD_SD3_CMD__GPIO3_IO21 0x31e
+ MX93_PAD_SD3_DATA0__GPIO3_IO22 0x31e
+ MX93_PAD_SD3_DATA1__GPIO3_IO23 0x31e
+ MX93_PAD_SD3_DATA2__GPIO3_IO24 0x31e
+ MX93_PAD_SD3_DATA3__GPIO3_IO25 0x31e
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e
+ >;
+ };
+};
serial0 = &lpuart1;
};
+ bt_sco_codec: bt-sco-codec {
+ compatible = "linux,bt-sco";
+ #sound-dai-cells = <1>;
+ };
+
chosen {
stdout-path = &lpuart1;
};
regulator-max-microvolt = <1800000>;
};
+ sound-bt-sco {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "bt-sco-audio";
+ simple-audio-card,format = "dsp_a";
+ simple-audio-card,bitclock-inversion;
+ simple-audio-card,frame-master = <&btcpu>;
+ simple-audio-card,bitclock-master = <&btcpu>;
+
+ simple-audio-card,codec {
+ sound-dai = <&bt_sco_codec 1>;
+ };
+
+ btcpu: simple-audio-card,cpu {
+ sound-dai = <&sai1>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <16>;
+ };
+ };
+
+ sound-xcvr {
+ compatible = "fsl,imx-audio-card";
+ model = "imx-audio-xcvr";
+
+ pri-dai-link {
+ link-name = "XCVR PCM";
+
+ cpu {
+ sound-dai = <&xcvr>;
+ };
+ };
+ };
+
usdhc3_pwrseq: usdhc3_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>;
status = "okay";
};
+&sai1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai1>;
+ assigned-clocks = <&clk IMX93_CLK_SAI1>;
+ assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
+ assigned-clock-rates = <12288000>;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
&usbotg1 {
dr_mode = "otg";
hnp-disable;
status = "okay";
};
+&xcvr {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spdif>;
+ assigned-clocks = <&clk IMX93_CLK_SPDIF>,
+ <&clk IMX93_CLK_AUDIO_XCVR>;
+ assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>,
+ <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+ assigned-clock-rates = <12288000>, <200000000>;
+ status = "okay";
+};
+
&iomuxc {
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
>;
};
+ pinctrl_sai1: sai1grp {
+ fsl,pins = <
+ MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e
+ MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e
+ MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e
+ MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e
+ >;
+ };
+
+ pinctrl_spdif: spdifgrp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO22__SPDIF_IN 0x31e
+ MX93_PAD_GPIO_IO23__SPDIF_OUT 0x31e
+ >;
+ };
+
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 NXP
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx93-pinfunc.h"
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ flexcan_phy: can-phy {
+ compatible = "nxp,tja1057";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ silent-gpios = <&pcal6524 23 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&flexcan1 {
+ phys = <&flexcan_phy>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX93_PAD_PDM_CLK__CAN1_TX 0x139e
+ MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
+ >;
+ };
+};
+
+/* micfi1 use the A port, conflict with can1 */
+&micfil {
+ status = "disabled";
+};
+
+&pcal6524 {
+ /*
+ * mic-can-sel-hog have property 'output-low', dt overlay don't
+ * support /delete-property/. Both 'output-low' and 'output-high'
+ * will be exist under hog nodes if overlay file set 'output-high'.
+ * Workaround is disable this hog and create new hog with
+ * 'output-high'.
+ */
+ mic-can-sel-hog {
+ status = "disabled";
+ };
+
+ /*
+ * Config the MIC/CAN_SEL to high, chose B
+ * port, connect to CAN.
+ */
+ mic-can-high-sel-hog {
+ gpio-hog;
+ gpios = <0x11 0x00>;
+ output-high;
+ };
+};
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
+ fsl,tuning-step = <1>;
status = "okay";
};
vmmc-supply = <®_usdhc2_vmmc>;
bus-width = <4>;
no-mmc;
+ fsl,tuning-step = <1>;
status = "okay";
};
/* enable SION for data and cmd pad due to ERR052021 */
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
- /* PD | FSEL 3 | DSE X5 */
- MX93_PAD_SD1_CLK__USDHC1_CLK 0x5be
+ /* PD | FSEL 3 | DSE X4 */
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x59e
/* HYS | FSEL 0 | no drive */
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1000
- /* HYS | FSEL 3 | X5 */
- MX93_PAD_SD1_CMD__USDHC1_CMD 0x400011be
- /* HYS | FSEL 3 | X4 */
- MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000119e
- MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000119e
- MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000119e
- MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000119e
- MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000119e
- MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000119e
- MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000119e
- MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000119e
+ /* HYS | PU | FSEL 3 | DSE X4 */
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
+ /* HYS | PU | FSEL 3 | DSE X4 */
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000139e
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e
>;
};
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &pca9534;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
status = "okay";
+ /* Capacitive touch controller */
+ ft5x06_ts: touchscreen@38 {
+ compatible = "edt,edt-ft5206";
+ reg = <0x38>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_captouch>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+ touchscreen-size-x = <800>;
+ touchscreen-size-y = <480>;
+ touchscreen-inverted-x;
+ touchscreen-inverted-y;
+ wakeup-source;
+ };
+
/* DS1337 RTC module */
rtc@68 {
compatible = "dallas,ds1337";
#gpio-cells = <2>;
wakeup-source;
};
+
+ /* USB Type-C Controller */
+ ptn5150: typec@3d {
+ compatible = "nxp,ptn5150";
+ reg = <0x3d>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ptn5150>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <10 IRQ_TYPE_NONE>;
+
+ port {
+ typec1_dr_sw: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+ };
};
/* Console */
status = "okay";
};
+&lpspi6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpspi6>;
+ cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
/* J18.7, J18.9 */
&lpuart6 {
pinctrl-names = "default";
status = "okay";
};
+&usbotg1 {
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ usb-role-switch;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ status = "okay";
+
+ port {
+ usb1_drd_sw: endpoint {
+ remote-endpoint = <&typec1_dr_sw>;
+ };
+ };
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
/* SD */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
};
&iomuxc {
+ pinctrl_captouch: captouchgrp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO25__GPIO2_IO25 0x31e
+ >;
+ };
+
pinctrl_fec: fecgrp {
fsl,pins = <
MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
>;
};
+ pinctrl_lpspi6: lpspi6grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO00__GPIO2_IO00 0x31e
+ MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x31e
+ MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x31e
+ MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x31e
+ >;
+ };
+
pinctrl_pca9534: pca9534grp {
fsl,pins = <
MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
>;
};
+ pinctrl_ptn5150: ptn5150grp {
+ fsl,pins = <
+ MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
regulator-ramp-delay = <3125>;
};
- buck4: BUCK4{
+ buck4: BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-always-on;
};
- buck5: BUCK5{
+ buck5: BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
compatible = "fsl,aips-bus", "simple-bus";
reg = <0 0x42800000 0 0x800000>;
ranges = <0x42800000 0x0 0x42800000 0x800000>,
- <0x28000000 0x0 0x28000000 0x1000000>;
+ <0x24000000 0x0 0x24000000 0xc000000>;
#address-cells = <1>;
#size-cells = <1>;
#mbox-cells = <2>;
status = "disabled";
};
+
+ xspi1: spi@42b90000 {
+ compatible = "nxp,imx94-xspi";
+ reg = <0x42b90000 0x50000>, <0x28000000 0x08000000>;
+ reg-names = "base", "mmap";
+ interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, // EENV0
+ <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, // EENV1
+ <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, // EENV2
+ <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, // EENV3
+ <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; // EENV4
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk IMX94_CLK_XSPI1>;
+ clock-names = "per";
+ status = "disabled";
+ };
+
+ xspi2: spi@42be0000 {
+ compatible = "nxp,imx94-xspi";
+ reg = <0x42be0000 0x50000>, <0x24000000 0x04000000>;
+ reg-names = "base", "mmap";
+ interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, // EENV0
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, // EENV1
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, // EENV2
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, // EENV3
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; // EENV4
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk IMX94_CLK_XSPI2>;
+ clock-names = "per";
+ status = "disabled";
+ };
};
gpio2: gpio@43810000 {
};
};
+ netc_blk_ctrl: system-controller@4ceb0000 {
+ compatible = "nxp,imx94-netc-blk-ctrl";
+ reg = <0x0 0x4ceb0000 0x0 0x10000>,
+ <0x0 0x4cec0000 0x0 0x10000>,
+ <0x0 0x4c810000 0x0 0x7C>;
+ reg-names = "ierb", "prb", "netcmix";
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ clocks = <&scmi_clk IMX94_CLK_ENET>;
+ clock-names = "ipg";
+ power-domains = <&scmi_devpd IMX94_PD_NETC>;
+ status = "disabled";
+
+ netc_bus0: pcie@4ca00000 {
+ compatible = "pci-host-ecam-generic";
+ reg = <0x0 0x4ca00000 0x0 0x100000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x0 0x0>;
+ msi-map = <0x00 &its 0x68 0x1>, //ENETC3 PF
+ <0x01 &its 0x61 0x1>, //Timer0
+ <0x02 &its 0x64 0x1>, //Switch
+ <0x40 &its 0x69 0x1>, //ENETC3 VF0
+ <0x80 &its 0x6a 0x1>, //ENETC3 VF1
+ <0xC0 &its 0x6b 0x1>; //ENETC3 VF2
+ /* Switch BAR0 - non-prefetchable memory */
+ ranges = <0x02000000 0x0 0x4cc00000 0x0 0x4cc00000 0x0 0x80000
+ /* ENETC 3 and Timer 0 BAR0 - non-prefetchable memory */
+ 0x02000000 0x0 0x4cd40000 0x0 0x4cd40000 0x0 0x60000
+ /* Switch and Timer 0 BAR2 - prefetchable memory */
+ 0x42000000 0x0 0x4ce00000 0x0 0x4ce00000 0x0 0x20000
+ /* ENETC 3 VF0-2 BAR0 - non-prefetchable memory */
+ 0x02000000 0x0 0x4ce50000 0x0 0x4ce50000 0x0 0x30000
+ /* ENETC 3 VF0-2 BAR2 - prefetchable memory */
+ 0x42000000 0x0 0x4ce80000 0x0 0x4ce80000 0x0 0x30000>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0
+ GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+
+ enetc3: ethernet@0,0 {
+ compatible = "pci1131,e110";
+ reg = <0x0 0 0 0 0>;
+ phy-mode = "internal";
+ status = "disabled";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+
+ netc_timer0: ptp-timer@0,1 {
+ compatible = "pci1131,ee02";
+ reg = <0x100 0 0 0 0>;
+ status = "disabled";
+ };
+
+ rcec@1,0 {
+ reg = <0x800 0 0 0 0>;
+ interrupts = <1>;
+ };
+ };
+
+ netc_bus1: pcie@4cb00000 {
+ compatible = "pci-host-ecam-generic";
+ reg = <0x0 0x4cb00000 0x0 0x100000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ bus-range = <0x1 0x1>;
+ msi-map = <0x100 &its 0x65 0x1>, //ENETC0 PF
+ <0x101 &its 0x62 0x1>, //Timer1
+ <0x140 &its 0x66 0x1>, //ENETC1 PF
+ <0x180 &its 0x67 0x1>, //ENETC2 PF
+ <0x181 &its 0x63 0x1>, //Timer2
+ <0x1C0 &its 0x60 0x1>; //EMDIO
+ /* ENETC 0-2 BAR0 - non-prefetchable memory */
+ ranges = <0x02000000 0x0 0x4cC80000 0x0 0x4cc80000 0x0 0xc0000
+ /* Timer 1-2 and EMDIO BAR0 - non-prefetchable memory */
+ 0x02000000 0x0 0x4cda0000 0x0 0x4cda0000 0x0 0x60000
+ /* Timer 1-2 and EMDIO BAR2 - prefetchable memory */
+ 0x42000000 0x0 0x4ce20000 0x0 0x4ce20000 0x0 0x30000>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0
+ GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+
+ enetc0: ethernet@0,0 {
+ compatible = "pci1131,e101";
+ reg = <0x10000 0 0 0 0>;
+ status = "disabled";
+ };
+
+ netc_timer1: ptp-timer@0,1 {
+ compatible = "pci1131,ee02";
+ reg = <0x10100 0 0 0 0>;
+ status = "disabled";
+ };
+
+ rcec@1,0 {
+ reg = <0x10800 0 0 0 0>;
+ interrupts = <1>;
+ };
+
+ enetc1: ethernet@8,0 {
+ compatible = "pci1131,e101";
+ reg = <0x14000 0 0 0 0>;
+ status = "disabled";
+ };
+
+ enetc2: ethernet@10,0 {
+ compatible = "pci1131,e101";
+ reg = <0x18000 0 0 0 0>;
+ status = "disabled";
+ };
+
+ netc_timer2: ptp-timer@10,1 {
+ compatible = "pci1131,ee02";
+ reg = <0x18100 0 0 0 0>;
+ status = "disabled";
+ };
+
+ netc_emdio: mdio@18,0 {
+ compatible = "pci1131,ee00";
+ reg = <0x1c000 0 0 0 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
ddr-pmu@4e090dc0 {
compatible = "fsl,imx94-ddr-pmu", "fsl,imx93-ddr-pmu";
reg = <0x0 0x4e090dc0 0x0 0x200>;
model = "NXP i.MX943 EVK board";
aliases {
+ ethernet0 = &enetc3;
+ ethernet1 = &enetc1;
+ ethernet2 = &enetc2;
i2c2 = &lpi2c3;
i2c3 = &lpi2c4;
i2c5 = &lpi2c6;
#sound-dai-cells = <1>;
};
+ flexcan2_phy: can-phy0 {
+ compatible = "nxp,tjr1443";
+ #phy-cells = <0>;
+ enable-gpios = <&pcal6416_i2c6_u50 3 GPIO_ACTIVE_HIGH>;
+ max-bitrate = <8000000>;
+ standby-gpios = <&pcal6416_i2c6_u50 4 GPIO_ACTIVE_LOW>;
+ };
+
+ flexcan4_phy: can-phy1 {
+ compatible = "nxp,tjr1443";
+ #phy-cells = <0>;
+ enable-gpios = <&pcal6416_i2c3_u171 0 GPIO_ACTIVE_HIGH>;
+ max-bitrate = <8000000>;
+ standby-gpios = <&pcal6416_i2c3_u171 1 GPIO_ACTIVE_LOW>;
+ };
+
chosen {
stdout-path = &lpuart1;
};
};
};
+&enetc1 {
+ clocks = <&scmi_clk IMX94_CLK_MAC4>;
+ clock-names = "ref";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eth3>;
+ phy-handle = <ðphy3>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&enetc2 {
+ clocks = <&scmi_clk IMX94_CLK_MAC5>;
+ clock-names = "ref";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eth4>;
+ phy-handle = <ðphy4>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&enetc3 {
+ status = "okay";
+};
+
+&flexcan2 {
+ phys = <&flexcan2_phy>;
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&flexcan4 {
+ phys = <&flexcan4_phy>;
+ pinctrl-0 = <&pinctrl_flexcan4>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&lpi2c3 {
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_lpi2c3>;
status = "okay";
};
+&netc_blk_ctrl {
+ assigned-clocks = <&scmi_clk IMX94_CLK_MAC4>,
+ <&scmi_clk IMX94_CLK_MAC5>;
+ assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD0>,
+ <&scmi_clk IMX94_CLK_SYSPLL1_PFD0>;
+ assigned-clock-rates = <250000000>, <250000000>;
+ status = "okay";
+};
+
+&netc_emdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_emdio>;
+ status = "okay";
+
+ ethphy3: ethernet-phy@6 {
+ reg = <0x6>;
+ realtek,clkout-disable;
+ };
+
+ ethphy4: ethernet-phy@7 {
+ reg = <0x7>;
+ realtek,clkout-disable;
+ };
+};
+
+&netc_timer0 {
+ status = "okay";
+};
+
+&netc_timer1 {
+ status = "okay";
+};
+
&sai1 {
assigned-clocks = <&scmi_clk IMX94_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX94_CLK_AUDIOPLL2_VCO>,
};
&scmi_iomuxc {
+ pinctrl_emdio: emdiogrp {
+ fsl,pins = <
+ IMX94_PAD_ETH4_MDC_GPIO1__NETC_EMDC 0x57e
+ IMX94_PAD_ETH4_MDIO_GPIO2__NETC_EMDIO 0x97e
+ >;
+ };
+
+ pinctrl_eth3: eth3grp {
+ fsl,pins = <
+ IMX94_PAD_ETH3_TXD3__NETC_PINMUX_ETH3_TXD3 0x50e
+ IMX94_PAD_ETH3_TXD2__NETC_PINMUX_ETH3_TXD2 0x50e
+ IMX94_PAD_ETH3_TXD1__NETC_PINMUX_ETH3_TXD1 0x50e
+ IMX94_PAD_ETH3_TXD0__NETC_PINMUX_ETH3_TXD0 0x50e
+ IMX94_PAD_ETH3_TX_CTL__NETC_PINMUX_ETH3_TX_CTL 0x51e
+ IMX94_PAD_ETH3_TX_CLK__NETC_PINMUX_ETH3_TX_CLK 0x59e
+ IMX94_PAD_ETH3_RX_CTL__NETC_PINMUX_ETH3_RX_CTL 0x51e
+ IMX94_PAD_ETH3_RX_CLK__NETC_PINMUX_ETH3_RX_CLK 0x59e
+ IMX94_PAD_ETH3_RXD0__NETC_PINMUX_ETH3_RXD0 0x51e
+ IMX94_PAD_ETH3_RXD1__NETC_PINMUX_ETH3_RXD1 0x51e
+ IMX94_PAD_ETH3_RXD2__NETC_PINMUX_ETH3_RXD2 0x51e
+ IMX94_PAD_ETH3_RXD3__NETC_PINMUX_ETH3_RXD3 0x51e
+ >;
+ };
+
+ pinctrl_eth4: eth4grp {
+ fsl,pins = <
+ IMX94_PAD_ETH4_TXD3__NETC_PINMUX_ETH4_TXD3 0x50e
+ IMX94_PAD_ETH4_TXD2__NETC_PINMUX_ETH4_TXD2 0x50e
+ IMX94_PAD_ETH4_TXD1__NETC_PINMUX_ETH4_TXD1 0x50e
+ IMX94_PAD_ETH4_TXD0__NETC_PINMUX_ETH4_TXD0 0x50e
+ IMX94_PAD_ETH4_TX_CTL__NETC_PINMUX_ETH4_TX_CTL 0x51e
+ IMX94_PAD_ETH4_TX_CLK__NETC_PINMUX_ETH4_TX_CLK 0x59e
+ IMX94_PAD_ETH4_RX_CTL__NETC_PINMUX_ETH4_RX_CTL 0x51e
+ IMX94_PAD_ETH4_RX_CLK__NETC_PINMUX_ETH4_RX_CLK 0x59e
+ IMX94_PAD_ETH4_RXD0__NETC_PINMUX_ETH4_RXD0 0x51e
+ IMX94_PAD_ETH4_RXD1__NETC_PINMUX_ETH4_RXD1 0x51e
+ IMX94_PAD_ETH4_RXD2__NETC_PINMUX_ETH4_RXD2 0x51e
+ IMX94_PAD_ETH4_RXD3__NETC_PINMUX_ETH4_RXD3 0x51e
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ IMX94_PAD_GPIO_IO34__CAN2_TX 0x39e
+ IMX94_PAD_GPIO_IO35__CAN2_RX 0x39e
+ >;
+ };
+
+ pinctrl_flexcan4: flexcan4grp {
+ fsl,pins = <
+ IMX94_PAD_GPIO_IO36__CAN4_TX 0x39e
+ IMX94_PAD_GPIO_IO37__CAN4_RX 0x39e
+ >;
+ };
pinctrl_ioexpander_int2: ioexpanderint2grp {
fsl,pins = <
IMX94_PAD_SD2_RESET_B__GPIO4_IO27 0x31e
>;
};
+
+ pinctrl_xspi1: xspi1grp {
+ fsl,pins = <
+ IMX94_PAD_XSPI1_SCLK__XSPI1_A_SCLK 0x3fe
+ IMX94_PAD_XSPI1_SS0_B__XSPI1_A_SS0_B 0x3fe
+ IMX94_PAD_XSPI1_DATA0__XSPI1_A_DATA0 0x3fe
+ IMX94_PAD_XSPI1_DATA1__XSPI1_A_DATA1 0x3fe
+ IMX94_PAD_XSPI1_DATA2__XSPI1_A_DATA2 0x3fe
+ IMX94_PAD_XSPI1_DATA3__XSPI1_A_DATA3 0x3fe
+ IMX94_PAD_XSPI1_DATA4__XSPI1_A_DATA4 0x3fe
+ IMX94_PAD_XSPI1_DATA5__XSPI1_A_DATA5 0x3fe
+ IMX94_PAD_XSPI1_DATA6__XSPI1_A_DATA6 0x3fe
+ IMX94_PAD_XSPI1_DATA7__XSPI1_A_DATA7 0x3fe
+ IMX94_PAD_XSPI1_DQS__XSPI1_A_DQS 0x3fe
+ >;
+ };
};
&usdhc1 {
fsl,ext-reset-output;
status = "okay";
};
+
+&xspi1 {
+ pinctrl-0 = <&pinctrl_xspi1>;
+ pinctrl-1 = <&pinctrl_xspi1>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+
+ mt35xu512aba: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reset-gpios = <&pcal6416_i2c6_u50 15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+ spi-max-frequency = <200000000>;
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <8>;
+ };
+};
gpio = <&pcal6524 0 GPIO_ACTIVE_LOW>;
};
- reg_can2_stby: regulator-can2-stby {
- compatible = "regulator-fixed";
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "can2-stby";
- gpio = <&pcal6524 14 GPIO_ACTIVE_LOW>;
+ flexcan2_phy: can-phy {
+ compatible = "nxp,tja1051";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ silent-gpios = <&pcal6524 14 GPIO_ACTIVE_HIGH>;
};
reg_m2_pwr: regulator-m2-pwr {
linux_cma: linux,cma {
compatible = "shared-dma-pool";
- alloc-ranges = <0 0x80000000 0 0x7F000000>;
+ alloc-ranges = <0 0x80000000 0 0x7f000000>;
reusable;
size = <0 0x3c000000>;
linux,cma-default;
no-map;
};
- vpu_boot: vpu_boot@a0000000 {
+ vpu_boot: vpu-boot@a0000000 {
reg = <0 0xa0000000 0 0x100000>;
no-map;
};
&flexcan2 {
pinctrl-0 = <&pinctrl_flexcan2>;
pinctrl-names = "default";
- xceiver-supply = <®_can2_stby>;
+ phys = <&flexcan2_phy>;
status = "okay";
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 NXP
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/usb/pd.h>
+#include "imx95.dtsi"
+
+#define BRD_SM_CTRL_SD3_WAKE 0x8000 /*!< PCAL6408A-0 */
+#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /*!< PCAL6408A-4 */
+#define BRD_SM_CTRL_BT_WAKE 0x8002 /*!< PCAL6408A-5 */
+#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /*!< PCAL6408A-6 */
+#define BRD_SM_CTRL_BUTTON 0x8004 /*!< PCAL6408A-7 */
+
+/ {
+ compatible = "fsl,imx95-15x15-frdm", "fsl,imx95";
+ model = "NXP i.MX95 15X15 FRDM board";
+
+ aliases {
+ ethernet0 = &enetc_port0;
+ ethernet1 = &enetc_port1;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ i2c0 = &lpi2c1;
+ i2c1 = &lpi2c2;
+ i2c2 = &lpi2c3;
+ i2c3 = &lpi2c4;
+ i2c4 = &lpi2c5;
+ i2c5 = &lpi2c6;
+ i2c6 = &lpi2c7;
+ i2c7 = &lpi2c8;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc3;
+ serial0 = &lpuart1;
+ serial4 = &lpuart5;
+ };
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ stdout-path = &lpuart1;
+ };
+
+ dmic: dmic {
+ compatible = "dmic-codec";
+ #sound-dai-cells = <0>;
+ num-channels = <2>;
+ };
+
+ flexcan2_phy: can-phy {
+ compatible = "nxp,tja1051";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ /*
+ * Shared SILENT GPIO: CAN PHYs enter silent mode
+ * together (hardware design).
+ */
+ silent-gpios = <&pcal6524 7 GPIO_ACTIVE_HIGH>;
+ };
+
+ flexcan5_phy: can-phy {
+ compatible = "nxp,tja1051";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ silent-gpios = <&pcal6524 7 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "+V1.8_SW";
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "+V3.3_SW";
+ };
+
+ reg_5p0v: regulator-5p0v {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "+V5.0_SW";
+ };
+
+ reg_ext_3v3: regulator-ext-3v3 {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "VCCEXT_3V3";
+ };
+
+ reg_ext_5v: regulator-ext-5v {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "VCCEXT_5V";
+ gpio = <&pcal6524 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_m2_ekey_pwr: regulator-m2-pwr {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "M.2-power-ekey";
+ gpio = <&pcal6524 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_m2_mkey_pwr: regulator-m2-mkey-pwr {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "M.2-mkey-power";
+ gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ off-on-delay-us = <12000>;
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ pinctrl-names = "default";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "VDD_SD2_3V3";
+ gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usdhc3_vmmc: regulator-usdhc3 {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "WLAN_EN";
+ vin-supply = <®_m2_ekey_pwr>;
+ gpio = <&pcal6524 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ /*
+ * IW612 wifi chip needs more delay than other wifi chips to complete
+ * the host interface initialization after power up, otherwise the
+ * internal state of IW612 may be unstable, resulting in the failure of
+ * the SDIO3.0 switch voltage.
+ */
+ startup-delay-us = <20000>;
+ };
+
+ reg_usb_vbus: regulator-vbus {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "USB_VBUS";
+ gpio = <&pcal6524 15 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_vref_1v8: regulator-adc-vref {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "vref_1v8";
+ };
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ linux_cma: linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x80000000 0 0x7F000000>;
+ reusable;
+ size = <0 0x3c000000>;
+ linux,cma-default;
+ };
+
+ vdev0vring0: memory@88000000 {
+ reg = <0 0x88000000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: memory@88008000 {
+ reg = <0 0x88008000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring0: memory@88010000 {
+ reg = <0 0x88010000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring1: memory@88018000 {
+ reg = <0 0x88018000 0 0x8000>;
+ no-map;
+ };
+
+ vdevbuffer: memory@88020000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x88020000 0 0x100000>;
+ no-map;
+ };
+
+ rsc_table: memory@88220000 {
+ reg = <0 0x88220000 0 0x1000>;
+ no-map;
+ };
+
+ vpu_boot: memory@a0000000 {
+ reg = <0 0xa0000000 0 0x100000>;
+ no-map;
+ };
+ };
+
+ sound-micfil {
+ compatible = "fsl,imx-audio-card";
+ model = "micfil-audio";
+
+ pri-dai-link {
+ link-name = "micfil hifi";
+ format = "i2s";
+
+ cpu {
+ sound-dai = <&micfil>;
+ };
+
+ codec {
+ sound-dai = <&dmic>;
+ };
+ };
+ };
+
+ usdhc3_pwrseq: usdhc3-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pcal6524 8 GPIO_ACTIVE_LOW>;
+ };
+
+ memory@80000000 {
+ reg = <0x0 0x80000000 0 0x80000000>;
+ device_type = "memory";
+ };
+};
+
+&adc1 {
+ vref-supply = <®_vref_1v8>;
+ status = "okay";
+};
+
+&enetc_port0 {
+ phy-handle = <ðphy0>;
+ phy-mode = "rgmii-id";
+ pinctrl-0 = <&pinctrl_enetc0>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&enetc_port1 {
+ phy-handle = <ðphy1>;
+ phy-mode = "rgmii-id";
+ pinctrl-0 = <&pinctrl_enetc1>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&flexcan2 {
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ pinctrl-names = "default";
+ phys = <&flexcan2_phy>;
+ status = "okay";
+};
+
+&flexcan5 {
+ pinctrl-0 = <&pinctrl_flexcan5>;
+ pinctrl-names = "default";
+ phys = <&flexcan5_phy>;
+ status = "okay";
+};
+
+&lpi2c2 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ pcal6524: gpio@22 {
+ compatible = "nxp,pcal6524";
+ reg = <0x22>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gpio5>;
+ interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ pinctrl-0 = <&pinctrl_pcal6524>;
+ pinctrl-names = "default";
+ gpio-line-names = "ENET1 PHY reset",
+ "ENET2 PHY reset",
+ "SPI3/GPIO select",
+ "UART3/GPIO select",
+ "CAN2&5/GPIO select",
+ "PWM/GPIO select",
+ "Watch dog enable",
+ "CAN1&2&5 silent",
+ "SDIO_nRST",
+ "WL_nDISABLE1",
+ "WL_nDISABLE2",
+ "M.2 Mkey NC06",
+ "EXT_5V0_PWR_EN",
+ "EXT_3V3_PWR_EN",
+ "Mkey power control",
+ "USB2 power control",
+ "Ekey power control",
+ "MIPI-DSICSI reset",
+ "MIPI-DSI IO2",
+ "MIPI-CSI reset",
+ "LVDS TP reset",
+ "LVDS BL enable",
+ "LVDS BL power enable",
+ "IT6263 reset";
+
+ lpspi-gpio-sel-hog {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+
+ lpuart-gpio-sel-hog {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+
+ can-gpio-sel-hog {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+
+ pwm-gpio-sel-hog {
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
+ };
+};
+
+&lpi2c3 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c3>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ ptn5110: tcpc@50 {
+ compatible = "nxp,ptn5110", "tcpci";
+ reg = <0x50>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&pinctrl_ptn5110>;
+ pinctrl-names = "default";
+
+ typec_con: connector {
+ compatible = "usb-c-connector";
+ data-role = "dual";
+ label = "USB-C";
+ op-sink-microwatt = <15000000>;
+ power-role = "dual";
+ self-powered;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 20000, 3000)>;
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ try-power-role = "sink";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ typec_con_hs: endpoint {
+ remote-endpoint = <&usb3_data_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ typec_con_ss: endpoint {
+ remote-endpoint = <&usb3_data_ss>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&lpi2c4 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c4>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ pca9632: led-controller@62 {
+ compatible = "nxp,pca9632";
+ reg = <0x62>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nxp,inverted-out;
+
+ led_backlight0: led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_BACKLIGHT;
+ function-enumerator = <0>;
+ };
+
+ led_backlight1: led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_BACKLIGHT;
+ function-enumerator = <1>;
+ };
+ };
+};
+
+&lpuart1 {
+ pinctrl-0 = <&pinctrl_uart1>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&lpuart5 {
+ pinctrl-0 = <&pinctrl_uart5>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ bluetooth {
+ compatible = "nxp,88w8987-bt";
+ };
+};
+
+&micfil {
+ assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL1>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL2>,
+ <&scmi_clk IMX95_CLK_PDM>;
+ assigned-clock-parents = <0>, <0>, <0>, <0>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL1>;
+ assigned-clock-rates = <3932160000>,
+ <3612672000>, <393216000>,
+ <361267200>, <49152000>;
+ #sound-dai-cells = <0>;
+ pinctrl-0 = <&pinctrl_pdm>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&mu7 {
+ status = "okay";
+};
+
+&netc_blk_ctrl {
+ status = "okay";
+};
+
+/* Configure MSI and IOMMU mappings specific to the i.MX95 15x15 FRDM board. */
+&netc_bus0 {
+ msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF
+ <0x10 &its 0x61 0x1>, //ENETC0 VF0
+ <0x20 &its 0x62 0x1>, //ENETC0 VF1
+ <0x40 &its 0x63 0x1>, //ENETC1 PF
+ <0x50 &its 0x65 0x1>, //ENETC1 VF0
+ <0x60 &its 0x66 0x1>, //ENETC1 VF1
+ <0x80 &its 0x64 0x1>, //ENETC2 PF
+ <0xc0 &its 0x67 0x1>; //NETC Timer
+ iommu-map = <0x0 &smmu 0x20 0x1>,
+ <0x10 &smmu 0x21 0x1>,
+ <0x20 &smmu 0x22 0x1>,
+ <0x40 &smmu 0x23 0x1>,
+ <0x50 &smmu 0x25 0x1>,
+ <0x60 &smmu 0x26 0x1>,
+ <0x80 &smmu 0x24 0x1>,
+ <0xc0 &smmu 0x27 0x1>;
+};
+
+&netc_emdio {
+ pinctrl-0 = <&pinctrl_emdio>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ ethphy0: ethernet-phy@1 {
+ reg = <1>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ reset-gpios = <&pcal6524 0 GPIO_ACTIVE_LOW>;
+ };
+
+ ethphy1: ethernet-phy@2 {
+ reg = <2>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ reset-gpios = <&pcal6524 1 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&netc_timer {
+ status = "okay";
+};
+
+&netcmix_blk_ctrl {
+ status = "okay";
+};
+
+&pcie0 {
+ pinctrl-0 = <&pinctrl_pcie0>;
+ pinctrl-names = "default";
+ reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ supports-clkreq;
+ vpcie-supply = <®_m2_mkey_pwr>;
+ status = "okay";
+};
+
+&scmi_iomuxc {
+ pinctrl_emdio: emdiogrp {
+ fsl,pins = <
+ IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x50e
+ IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e
+ >;
+ };
+
+ pinctrl_enetc0: enetc0grp {
+ fsl,pins = <
+ IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e
+ IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e
+ IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e
+ IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e
+ IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e
+ IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e
+ IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e
+ IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e
+ IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e
+ IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e
+ IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e
+ IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e
+ >;
+ };
+
+ pinctrl_enetc1: enetc1grp {
+ fsl,pins = <
+ IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x50e
+ IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x50e
+ IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x50e
+ IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x50e
+ IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e
+ IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e
+ IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e
+ IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e
+ IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e
+ IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e
+ IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e
+ IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e
+ IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e
+ >;
+ };
+
+ pinctrl_flexcan5: flexcan5grp {
+ fsl,pins = <
+ IMX95_PAD_GPIO_IO22__CAN5_TX 0x39e
+ IMX95_PAD_GPIO_IO23__CAN5_RX 0x39e
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x40000b9e
+ IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <
+ IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e
+ IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c3: lpi2c3grp {
+ fsl,pins = <
+ IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
+ IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c4: lpi2c4grp {
+ fsl,pins = <
+ IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e
+ IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e
+ >;
+ };
+
+ pinctrl_pcal6524: pcal6524grp {
+ fsl,pins = <
+ IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e
+ >;
+ };
+
+ pinctrl_pcie0: pcie0grp {
+ fsl,pins = <
+ IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x40000b1e
+ IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x31e
+ >;
+ };
+
+ pinctrl_pdm: pdmgrp {
+ fsl,pins = <
+ IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e
+ IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e
+ >;
+ };
+
+ pinctrl_ptn5110: ptn5110grp {
+ fsl,pins = <
+ IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 0x31e
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e
+ IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
+ IMX95_PAD_DAP_TDI__LPUART5_RX 0x31e
+ IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
+ IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
+ IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
+ IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
+ IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
+ IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
+ IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
+ IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
+ IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
+ IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
+ IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
+ IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
+ IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
+ IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
+ IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
+ IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
+ IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
+ IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
+ IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
+ IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
+ IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
+ IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe
+ IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe
+ IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
+ IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
+ IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
+ IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
+ IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
+ IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
+ IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
+ IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
+ IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
+ IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
+ IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
+ IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
+ IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
+ IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
+ IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
+ IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
+ IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
+ IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
+ IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
+ IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
+ IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
+ IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
+ IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
+ IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
+ IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
+ IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
+ IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e
+ IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e
+ IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e
+ IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e
+ IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e
+ IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e
+ IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e
+ IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e
+ IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e
+ IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e
+ IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe
+ IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe
+ IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
+ IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
+ IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
+ IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
+ >;
+ };
+};
+
+&scmi_misc {
+ nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE 1
+ BRD_SM_CTRL_PCIE1_WAKE 1
+ BRD_SM_CTRL_BT_WAKE 1
+ BRD_SM_CTRL_PCIE2_WAKE 1
+ BRD_SM_CTRL_BUTTON 1>;
+};
+
+&thermal_zones {
+ pf09-thermal {
+ polling-delay = <2000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&scmi_sensor 2>;
+
+ trips {
+ pf09_alert: trip0 {
+ hysteresis = <2000>;
+ temperature = <140000>;
+ type = "passive";
+ };
+
+ pf09_crit: trip1 {
+ hysteresis = <2000>;
+ temperature = <155000>;
+ type = "critical";
+ };
+ };
+ };
+
+ pf53arm-thermal {
+ polling-delay = <2000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&scmi_sensor 4>;
+
+ cooling-maps {
+ map0 {
+ cooling-device = <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ trip = <&pf5301_alert>;
+ };
+ };
+
+ trips {
+ pf5301_alert: trip0 {
+ hysteresis = <2000>;
+ temperature = <140000>;
+ type = "passive";
+ };
+
+ pf5301_crit: trip1 {
+ hysteresis = <2000>;
+ temperature = <155000>;
+ type = "critical";
+ };
+ };
+ };
+
+ pf53soc-thermal {
+ polling-delay = <2000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&scmi_sensor 3>;
+
+ trips {
+ pf5302_alert: trip0 {
+ hysteresis = <2000>;
+ temperature = <140000>;
+ type = "passive";
+ };
+
+ pf5302_crit: trip1 {
+ hysteresis = <2000>;
+ temperature = <155000>;
+ type = "critical";
+ };
+ };
+ };
+};
+
+&usb2 {
+ disable-over-current;
+ dr_mode = "host";
+ vbus-supply = <®_usb_vbus>;
+ status = "okay";
+};
+
+&usb3 {
+ status = "okay";
+};
+
+&usb3_dwc3 {
+ adp-disable;
+ dr_mode = "otg";
+ hnp-disable;
+ role-switch-default-mode = "peripheral";
+ srp-disable;
+ usb-role-switch;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ status = "okay";
+
+ port {
+ usb3_data_hs: endpoint {
+ remote-endpoint = <&typec_con_hs>;
+ };
+ };
+};
+
+&usb3_phy {
+ orientation-switch;
+ fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <17>;
+ fsl,phy-pcs-tx-swing-full-percent = <100>;
+ fsl,phy-tx-preemp-amp-tune-microamp = <600>;
+ fsl,phy-tx-vboost-level-microvolt = <1156>;
+ fsl,phy-tx-vref-tune-percent = <100>;
+ status = "okay";
+
+ port {
+ usb3_data_ss: endpoint {
+ remote-endpoint = <&typec_con_ss>;
+ };
+ };
+};
+
+&usdhc1 {
+ bus-width = <8>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc1>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ fsl,tuning-step = <1>;
+ status = "okay";
+};
+
+&usdhc2 {
+ bus-width = <4>;
+ cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ vmmc-supply = <®_usdhc2_vmmc>;
+ fsl,tuning-step = <1>;
+ status = "okay";
+};
+
+&usdhc3 {
+ bus-width = <4>;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&usdhc3_pwrseq>;
+ non-removable;
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc3>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ vmmc-supply = <®_usdhc3_vmmc>;
+ wakeup-source;
+ status = "okay";
+};
+
+&wdog3 {
+ status = "okay";
+};
#define IMX95_CLK_SEL_A55P (IMX95_CCM_NUM_CLK_SRC + 123 + 7)
#define IMX95_CLK_SEL_DRAM (IMX95_CCM_NUM_CLK_SRC + 123 + 8)
#define IMX95_CLK_SEL_TEMPSENSE (IMX95_CCM_NUM_CLK_SRC + 123 + 9)
+#define IMX95_CLK_GPU_CGC (IMX95_CCM_NUM_CLK_SRC + 123 + 10)
#endif /* __CLOCK_IMX95_H */
compatible = "shared-dma-pool";
reusable;
size = <0 0x3c000000>;
- alloc-ranges = <0 0x80000000 0 0x7F000000>;
+ alloc-ranges = <0 0x80000000 0 0x7f000000>;
linux,cma-default;
};
};
linux,cma-default;
};
- vpu_boot: vpu_boot@a0000000 {
+ vpu_boot: vpu-boot@a0000000 {
reg = <0 0xa0000000 0 0x100000>;
no-map;
};
gpu: gpu@4d900000 {
compatible = "nxp,imx95-mali", "arm,mali-valhall-csf";
reg = <0 0x4d900000 0 0x480000>;
- clocks = <&scmi_clk IMX95_CLK_GPU>, <&scmi_clk IMX95_CLK_GPUAPB>;
+ clocks = <&scmi_clk IMX95_CLK_GPU_CGC>, <&scmi_clk IMX95_CLK_GPUAPB>;
clock-names = "core", "coregroup";
interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+/*
+ * Copyright 2025 NXP
+ */
+
+#ifndef __CLOCK_IMX952_H__
+#define __CLOCK_IMX952_H__
+
+/* Clock Source */
+#define IMX952_CLK_EXT 0
+#define IMX952_CLK_OSC32K 1
+#define IMX952_CLK_OSC24M 2
+#define IMX952_CLK_FRO 3
+#define IMX952_CLK_SYSPLL1_VCO 4
+#define IMX952_CLK_SYSPLL1_PFD0_UNGATED 5
+#define IMX952_CLK_SYSPLL1_PFD0 6
+#define IMX952_CLK_SYSPLL1_PFD0_DIV2 7
+#define IMX952_CLK_SYSPLL1_PFD1_UNGATED 8
+#define IMX952_CLK_SYSPLL1_PFD1 9
+#define IMX952_CLK_SYSPLL1_PFD1_DIV2 10
+#define IMX952_CLK_SYSPLL1_PFD2_UNGATED 11
+#define IMX952_CLK_SYSPLL1_PFD2 12
+#define IMX952_CLK_SYSPLL1_PFD2_DIV2 13
+#define IMX952_CLK_AUDIOPLL1_VCO 14
+#define IMX952_CLK_AUDIOPLL1 15
+#define IMX952_CLK_AUDIOPLL2_VCO 16
+#define IMX952_CLK_AUDIOPLL2 17
+#define IMX952_CLK_VIDEOPLL1_VCO 18
+#define IMX952_CLK_VIDEOPLL1 19
+#define IMX952_CLK_SRC_RESERVED20 20
+#define IMX952_CLK_SYSPLL1_PFD3_UNGATED 21
+#define IMX952_CLK_SYSPLL1_PFD3 22
+#define IMX952_CLK_SYSPLL1_PFD3_DIV2 23
+#define IMX952_CLK_ARMPLL_VCO 24
+#define IMX952_CLK_ARMPLL_PFD0_UNGATED 25
+#define IMX952_CLK_ARMPLL_PFD0 26
+#define IMX952_CLK_ARMPLL_PFD1_UNGATED 27
+#define IMX952_CLK_ARMPLL_PFD1 28
+#define IMX952_CLK_ARMPLL_PFD2_UNGATED 29
+#define IMX952_CLK_ARMPLL_PFD2 30
+#define IMX952_CLK_ARMPLL_PFD3_UNGATED 31
+#define IMX952_CLK_ARMPLL_PFD3 32
+#define IMX952_CLK_DRAMPLL_VCO 33
+#define IMX952_CLK_DRAMPLL 34
+#define IMX952_CLK_HSIOPLL_VCO 35
+#define IMX952_CLK_HSIOPLL 36
+#define IMX952_CLK_LDBPLL_VCO 37
+#define IMX952_CLK_LDBPLL 38
+#define IMX952_CLK_EXT1 39
+#define IMX952_CLK_EXT2 40
+
+/* Clock ROOT */
+#define IMX952_CLK_ADC 41
+#define IMX952_CLK_RESERVED1 42
+#define IMX952_CLK_BUSAON 43
+#define IMX952_CLK_CAN1 44
+#define IMX952_CLK_RESERVED4 45
+#define IMX952_CLK_I3C1SLOW 46
+#define IMX952_CLK_LPI2C1 47
+#define IMX952_CLK_LPI2C2 48
+#define IMX952_CLK_LPSPI1 49
+#define IMX952_CLK_LPSPI2 50
+#define IMX952_CLK_LPTMR1 51
+#define IMX952_CLK_LPUART1 52
+#define IMX952_CLK_LPUART2 53
+#define IMX952_CLK_M33 54
+#define IMX952_CLK_M33SYSTICK 55
+#define IMX952_CLK_RESERVED15 56
+#define IMX952_CLK_PDM 57
+#define IMX952_CLK_SAI1 58
+#define IMX952_CLK_RESERVED18 59
+#define IMX952_CLK_TPM2 60
+#define IMX952_CLK_RESERVED20 61
+#define IMX952_CLK_CAMAPB 62
+#define IMX952_CLK_CAMAXI 63
+#define IMX952_CLK_CAMCM0 64
+#define IMX952_CLK_CAMISI 65
+#define IMX952_CLK_CAMPHYCFG 66
+#define IMX952_CLK_MIPIPHYPLLBYPASS 67
+#define IMX952_CLK_RESERVED27 68
+#define IMX952_CLK_MIPITESTBYTE 69
+#define IMX952_CLK_A55 70
+#define IMX952_CLK_A55MTRBUS 71
+#define IMX952_CLK_A55PERIPH 72
+#define IMX952_CLK_DRAMALT 73
+#define IMX952_CLK_DRAMAPB 74
+#define IMX952_CLK_DISPAPB 75
+#define IMX952_CLK_DISPAXI 76
+#define IMX952_CLK_DISPLPSPI 77
+#define IMX952_CLK_DISPOCRAM 78
+#define IMX952_CLK_DISPPHYCFG 79
+#define IMX952_CLK_DISP1PIX 80
+#define IMX952_CLK_DISPCDPHYAPB 81
+#define IMX952_CLK_RESERVED41 82
+#define IMX952_CLK_GPUAPB 83
+#define IMX952_CLK_GPU 84
+#define IMX952_CLK_HSIOACSCAN480M 85
+#define IMX952_CLK_HSIOACSCAN80M 86
+#define IMX952_CLK_HSIO 87
+#define IMX952_CLK_HSIOPCIEAUX 88
+#define IMX952_CLK_HSIOPCIETEST160M 89
+#define IMX952_CLK_HSIOPCIETEST400M 90
+#define IMX952_CLK_HSIOPCIETEST500M 91
+#define IMX952_CLK_HSIOUSBTEST50M 92
+#define IMX952_CLK_HSIOUSBTEST60M 93
+#define IMX952_CLK_BUSM7 94
+#define IMX952_CLK_M7 95
+#define IMX952_CLK_M7SYSTICK 96
+#define IMX952_CLK_BUSNETCMIX 97
+#define IMX952_CLK_ENET 98
+#define IMX952_CLK_ENETPHYTEST200M 99
+#define IMX952_CLK_ENETPHYTEST500M 100
+#define IMX952_CLK_ENETPHYTEST667M 101
+#define IMX952_CLK_ENETREF 102
+#define IMX952_CLK_ENETTIMER1 103
+#define IMX952_CLK_RESERVED63 104
+#define IMX952_CLK_SAI2 105
+#define IMX952_CLK_NOCAPB 106
+#define IMX952_CLK_NOC 107
+#define IMX952_CLK_NPUAPB 108
+#define IMX952_CLK_NPU 109
+#define IMX952_CLK_CCMCKO1 110
+#define IMX952_CLK_CCMCKO2 111
+#define IMX952_CLK_CCMCKO3 112
+#define IMX952_CLK_CCMCKO4 113
+#define IMX952_CLK_VPUAPB 114
+#define IMX952_CLK_VPU 115
+#define IMX952_CLK_RESERVED75 116
+#define IMX952_CLK_RESERVED76 117
+#define IMX952_CLK_AUDIOXCVR 118
+#define IMX952_CLK_BUSWAKEUP 119
+#define IMX952_CLK_CAN2 120
+#define IMX952_CLK_CAN3 121
+#define IMX952_CLK_CAN4 122
+#define IMX952_CLK_CAN5 123
+#define IMX952_CLK_FLEXIO1 124
+#define IMX952_CLK_FLEXIO2 125
+#define IMX952_CLK_XSPI1 126
+#define IMX952_CLK_RESERVED86 127
+#define IMX952_CLK_I3C2SLOW 128
+#define IMX952_CLK_LPI2C3 129
+#define IMX952_CLK_LPI2C4 130
+#define IMX952_CLK_LPI2C5 131
+#define IMX952_CLK_LPI2C6 132
+#define IMX952_CLK_LPI2C7 133
+#define IMX952_CLK_LPI2C8 134
+#define IMX952_CLK_LPSPI3 135
+#define IMX952_CLK_LPSPI4 136
+#define IMX952_CLK_LPSPI5 137
+#define IMX952_CLK_LPSPI6 138
+#define IMX952_CLK_LPSPI7 139
+#define IMX952_CLK_LPSPI8 140
+#define IMX952_CLK_LPTMR2 141
+#define IMX952_CLK_LPUART3 142
+#define IMX952_CLK_LPUART4 143
+#define IMX952_CLK_LPUART5 144
+#define IMX952_CLK_LPUART6 145
+#define IMX952_CLK_LPUART7 146
+#define IMX952_CLK_LPUART8 147
+#define IMX952_CLK_SAI3 148
+#define IMX952_CLK_SAI4 149
+#define IMX952_CLK_SAI5 150
+#define IMX952_CLK_SPDIF 151
+#define IMX952_CLK_SWOTRACE 152
+#define IMX952_CLK_TPM4 153
+#define IMX952_CLK_TPM5 154
+#define IMX952_CLK_TPM6 155
+#define IMX952_CLK_MIPIPHYDFT400 156
+#define IMX952_CLK_MIPIPHYDFT540 157
+#define IMX952_CLK_USDHC1 158
+#define IMX952_CLK_USDHC2 159
+#define IMX952_CLK_USDHC3 160
+#define IMX952_CLK_V2XPK 161
+#define IMX952_CLK_WAKEUPAXI 162
+#define IMX952_CLK_XSPISLVROOT 163
+#define IMX952_CLK_AUDMIX1 164
+#define IMX952_CLK_ASRC1 165
+#define IMX952_CLK_ASRC2 166
+#define IMX952_CLK_GPT1 167
+#define IMX952_CLK_GPT2 168
+#define IMX952_CLK_GPT3 169
+#define IMX952_CLK_GPT4 170
+
+/* Clock GPR SEL */
+#define IMX952_CLK_GPR_SEL_EXT 171
+#define IMX952_CLK_GPR_SEL_A55C0 172
+#define IMX952_CLK_GPR_SEL_A55C1 173
+#define IMX952_CLK_GPR_SEL_A55C2 174
+#define IMX952_CLK_GPR_SEL_A55C3 175
+#define IMX952_CLK_GPR_SEL_A55P 176
+#define IMX952_CLK_GPR_SEL_DRAM 177
+#define IMX952_CLK_GPR_SEL_TEMPSENSE 178
+
+/* Clock CGC */
+#define IMX952_CLK_CGC_NPU 179
+#define IMX952_CLK_CGC_GPU 180
+#define IMX952_CLK_CGC_CAMISI 181
+#define IMX952_CLK_CGC_CAMISP 182
+#define IMX952_CLK_CGC_CAMCSI0 183
+#define IMX952_CLK_CGC_CAMCSI1 184
+#define IMX952_CLK_CGC_CAMOCRAM 185
+#define IMX952_CLK_CGC_HSIOUSB 186
+#define IMX952_CLK_CGC_HSIOPCIE 187
+#define IMX952_CLK_CGC_DISPOCRAM 188
+#define IMX952_CLK_CGC_DISPSEERIS 189
+#define IMX952_CLK_CGC_DISPDSI 190
+#define IMX952_CLK_CGC_NOCGIC 191
+#define IMX952_CLK_CGC_NOCOCRAM 192
+#define IMX952_CLK_CGC_NETC 193
+#define IMX952_CLK_CGC_VPUENC 194
+#define IMX952_CLK_CGC_VPUJPEGENC 195
+#define IMX952_CLK_CGC_VPUJPEGDEC 196
+#define IMX952_CLK_CGC_VPUDEC 197
+
+#endif
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025-2026 NXP
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/usb/pd.h>
+#include "imx952.dtsi"
+
+#define FALLING_EDGE BIT(0)
+#define RISING_EDGE BIT(1)
+
+#define BRD_SM_CTRL_SD3_WAKE 0x8000U /*!< PCAL6408A-0 */
+#define BRD_SM_CTRL_M2E_WAKE 0x8001U /*!< PCAL6408A-4 */
+#define BRD_SM_CTRL_BT_WAKE 0x8002U /*!< PCAL6408A-5 */
+#define BRD_SM_CTRL_M2M_WAKE 0x8003U /*!< PCAL6408A-6 */
+#define BRD_SM_CTRL_BUTTON 0x8004U /*!< PCAL6408A-7 */
+
+/ {
+ model = "NXP i.MX952 EVK board";
+ compatible = "fsl,imx952-evk", "fsl,imx952";
+
+ aliases {
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ i2c0 = &lpi2c1;
+ i2c1 = &lpi2c2;
+ i2c2 = &lpi2c3;
+ i2c3 = &lpi2c4;
+ i2c4 = &lpi2c5;
+ i2c5 = &lpi2c6;
+ i2c6 = &lpi2c7;
+ i2c7 = &lpi2c8;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ serial0 = &lpuart1;
+ serial4 = &lpuart5;
+ spi6 = &lpspi7;
+ };
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0 0x80000000>;
+ };
+
+ fan0: pwm-fan {
+ compatible = "pwm-fan";
+ #cooling-cells = <2>;
+ pwms = <&tpm6 2 4000000 PWM_POLARITY_INVERTED>;
+ cooling-levels = <64 128 192 255>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux_cma: linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x80000000 0 0x7f000000>;
+ size = <0 0x3c000000>;
+ linux,cma-default;
+ reusable;
+ };
+ };
+
+ flexcan1_phy: can-phy0 {
+ compatible = "nxp,tjr1443";
+ #phy-cells = <0>;
+ max-bitrate = <8000000>;
+ enable-gpios = <&pcal6416 6 GPIO_ACTIVE_HIGH>;
+ standby-gpios = <&pcal6416 5 GPIO_ACTIVE_LOW>;
+ };
+
+ flexcan2_phy: can-phy1 {
+ compatible = "nxp,tjr1443";
+ #phy-cells = <0>;
+ max-bitrate = <8000000>;
+ enable-gpios = <&i2c4_pcal6408 4 GPIO_ACTIVE_HIGH>;
+ standby-gpios = <&i2c4_pcal6408 3 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "+V3.3_SW";
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "+V1.8_SW";
+ };
+
+ reg_vref_1v8: regulator-adc-vref {
+ compatible = "regulator-fixed";
+ regulator-name = "vref_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-name = "VDD_SD2_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ off-on-delay-us = <12000>;
+ };
+
+ reg_usb_vbus: regulator-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_VBUS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pcal6524 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+};
+
+/* pin conflict with PDM */
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ phys = <&flexcan1_phy>;
+ status = "disabled";
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ phys = <&flexcan2_phy>;
+ status = "okay";
+};
+
+&lpi2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ status = "okay";
+
+ adp5585: io-expander@34 {
+ compatible = "adi,adp5585-00", "adi,adp5585";
+ reg = <0x34>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-reserved-ranges = <5 1>;
+ #pwm-cells = <3>;
+ };
+};
+
+&lpi2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c3>;
+ status = "okay";
+
+ i2c3_pcal6408: gpio@20 {
+ compatible = "nxp,pcal6408";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ vcc-supply = <®_3p3v>;
+ };
+};
+
+&lpi2c4 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c4>;
+ status = "okay";
+
+ i2c4_pcal6408: gpio@21 {
+ compatible = "nxp,pcal6408";
+ reg = <0x21>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4_pcal6408>;
+ vcc-supply = <®_3p3v>;
+ };
+};
+
+&lpi2c6 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c6>;
+ status = "okay";
+
+ pcal6416: gpio@21 {
+ compatible = "nxp,pcal6416";
+ #gpio-cells = <2>;
+ gpio-controller;
+ reg = <0x21>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcal6416>;
+ vcc-supply = <®_3p3v>;
+
+ pdm-can-sel-hog {
+ gpio-hog;
+ gpios = <10 GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+
+ mqs-en-hog {
+ gpio-hog;
+ gpios = <15 GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+ };
+};
+
+&lpi2c7 {
+ clock-frequency = <1000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c7>;
+ status = "okay";
+
+ pcal6524: gpio@22 {
+ compatible = "nxp,pcal6524";
+ reg = <0x22>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcal6524>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ ptn5110: tcpc@50 {
+ compatible = "nxp,ptn5110", "tcpci";
+ reg = <0x50>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ptn5110>;
+
+ typec_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>;
+ op-sink-microwatt = <0>;
+ self-powered;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ typec1_dr_sw: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&lpuart1 {
+ /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&lpuart5 {
+ /* BT */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "nxp,88w8987-bt";
+ };
+};
+
+&lpspi7 {
+ cs-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpspi7>;
+ status = "okay";
+};
+
+&scmi_misc {
+ nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE 1
+ BRD_SM_CTRL_M2E_WAKE 1
+ BRD_SM_CTRL_BT_WAKE 1
+ BRD_SM_CTRL_M2M_WAKE 1
+ BRD_SM_CTRL_BUTTON 1>;
+};
+
+&tpm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tpm3>;
+ status = "okay";
+};
+
+&tpm6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tpm6>;
+ status = "okay";
+};
+
+&usb1 {
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ usb-role-switch;
+ disable-over-current;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ status = "okay";
+
+ port {
+ usb1_drd_sw: endpoint {
+ remote-endpoint = <&typec1_dr_sw>;
+ };
+ };
+};
+
+&usb2 {
+ dr_mode = "host";
+ disable-over-current;
+ vbus-supply = <®_usb_vbus>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ non-removable;
+ no-sdio;
+ no-sd;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&wdog3 {
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&scmi_iomuxc {
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ IMX952_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e
+ IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_CAN2_TX 0x39e
+ IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_CAN2_RX 0x39e
+ >;
+ };
+
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <
+ IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e
+ IMX952_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c3: lpi2c3grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPI2C3_SDA 0x40000b9e
+ IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPI2C3_SCL 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c4: lpi2c4grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_LPI2C4_SDA 0x40000b9e
+ IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_LPI2C4_SCL 0x40000b9e
+ >;
+ };
+
+ pinctrl_i2c4_pcal6408: i2c4pcal6408grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_GPIO2_IO_18 0x31e
+ >;
+ };
+
+ pinctrl_lpi2c6: lpi2c6grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPI2C6_SDA 0x40000b9e
+ IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPI2C6_SCL 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c7: lpi2c7grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPI2C7_SDA 0x40000b9e
+ IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPI2C7_SCL 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpspi7: lpspi7grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_GPIO2_IO_4 0x39e
+ IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPSPI7_SIN 0x39e
+ IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPSPI7_SOUT 0x39e
+ IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPSPI7_SCK 0x39e
+ >;
+ };
+
+ pinctrl_pcal6416: pcal6416grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPIO2_IO_10 0x31e
+ >;
+ };
+
+ pinctrl_pcal6524: pcal6524grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_GPIO5_IO_16 0x31e
+ >;
+ };
+
+ pinctrl_ptn5110: ptn5110grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_GPIO5_IO_14 0x31e
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x31e
+ >;
+ };
+
+ pinctrl_tpm3: tpm3grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2 0x51e
+ >;
+ };
+
+ pinctrl_tpm6: tpm6grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_TPM6_CH2 0x51e
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ IMX952_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e
+ IMX952_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_LPUART5_TX 0x31e
+ IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_LPUART5_RX 0x31e
+ IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_LPUART5_RTS_B 0x31e
+ IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_LPUART5_CTS_B 0x31e
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x158e
+ IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x138e
+ IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x138e
+ IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x138e
+ IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x138e
+ IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x138e
+ IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x138e
+ IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x138e
+ IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x138e
+ IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x138e
+ IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x158e
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x158e
+ IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x138e
+ IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x138e
+ IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x138e
+ IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x138e
+ IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x138e
+ IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x138e
+ IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x138e
+ IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x138e
+ IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x138e
+ IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x158e
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x159e
+ IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x139e
+ IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x139e
+ IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x139e
+ IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x139e
+ IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x139e
+ IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x139e
+ IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x139e
+ IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x139e
+ IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x139e
+ IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x159e
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e
+ IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e
+ IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e
+ IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e
+ IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e
+ IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e
+ IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e
+ IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e
+ IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e
+ IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e
+ IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e
+ IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e
+ IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e
+ IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e
+ IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e
+ IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e
+ IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e
+ IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e
+ IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_GPIO3_IO_0 0x31e
+ >;
+ };
+};
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright 2025 NXP
+ */
+
+#ifndef __DTS_IMX952_PINFUNC_H__
+#define __DTS_IMX952_PINFUNC_H__
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_TDI 0x0000 0x0230 0x05FC 0x00 0x00
+#define IMX952_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0230 0x0000 0x01 0x00
+#define IMX952_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0230 0x0000 0x02 0x00
+#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_CAN2_TX 0x0000 0x0230 0x0000 0x03 0x00
+#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_30 0x0000 0x0230 0x0000 0x04 0x00
+#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_GPIO3_IO_28 0x0000 0x0230 0x0000 0x05 0x00
+#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_LPUART5_RX 0x0000 0x0230 0x059C 0x06 0x00
+
+#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_TMS 0x0004 0x0234 0x0600 0x00 0x00
+#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_31 0x0004 0x0234 0x0000 0x04 0x00
+#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_GPIO3_IO_29 0x0004 0x0234 0x0000 0x05 0x00
+#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_LPUART5_RTS_B 0x0004 0x0234 0x0000 0x06 0x00
+
+#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_TCK 0x0008 0x0238 0x05F8 0x00 0x00
+#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_30 0x0008 0x0238 0x04B4 0x04 0x00
+#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_GPIO3_IO_30 0x0008 0x0238 0x0000 0x05 0x00
+#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_LPUART5_CTS_B 0x0008 0x0238 0x0598 0x06 0x00
+
+#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_TDO 0x000C 0x023C 0x0000 0x00 0x00
+#define IMX952_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_MQS2_RIGHT 0x000C 0x023C 0x0000 0x01 0x00
+#define IMX952_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_NETC_TMR_1588_ALARM2 0x000C 0x023C 0x0000 0x02 0x00
+#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_CAN2_RX 0x000C 0x023C 0x04A4 0x03 0x00
+#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_31 0x000C 0x023C 0x04B8 0x04 0x00
+#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_GPIO3_IO_31 0x000C 0x023C 0x0000 0x05 0x00
+#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_LPUART5_TX 0x000C 0x023C 0x05A0 0x06 0x00
+
+#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_GPIO2_IO_0 0x0010 0x0240 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPI2C3_SDA 0x0010 0x0240 0x0530 0x01 0x00
+#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_GPTMUX_INOUT0 0x0010 0x0240 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPSPI6_PCS0 0x0010 0x0240 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPUART5_TX 0x0010 0x0240 0x05A0 0x05 0x01
+#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPI2C5_SDA 0x0010 0x0240 0x0540 0x06 0x00
+#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_0 0x0010 0x0240 0x04BC 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_GPIO2_IO_1 0x0014 0x0244 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPI2C3_SCL 0x0014 0x0244 0x052C 0x01 0x00
+#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_GPTMUX_INOUT1 0x0014 0x0244 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPSPI6_SIN 0x0014 0x0244 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPUART5_RX 0x0014 0x0244 0x059C 0x05 0x01
+#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPI2C5_SCL 0x0014 0x0244 0x053C 0x06 0x00
+#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_1 0x0014 0x0244 0x04C0 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_GPIO2_IO_2 0x0018 0x0248 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPI2C4_SDA 0x0018 0x0248 0x0538 0x01 0x00
+#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_GPTMUX_INOUT2 0x0018 0x0248 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPSPI6_SOUT 0x0018 0x0248 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPUART5_CTS_B 0x0018 0x0248 0x0598 0x05 0x01
+#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPI2C6_SDA 0x0018 0x0248 0x0548 0x06 0x00
+#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_2 0x0018 0x0248 0x04C4 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_GPIO2_IO_3 0x001C 0x024C 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPI2C4_SCL 0x001C 0x024C 0x0534 0x01 0x00
+#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_GPTMUX_INOUT3 0x001C 0x024C 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPSPI6_SCK 0x001C 0x024C 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPUART5_RTS_B 0x001C 0x024C 0x0000 0x05 0x00
+#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPI2C6_SCL 0x001C 0x024C 0x0544 0x06 0x00
+#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_3 0x001C 0x024C 0x04C8 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_GPIO2_IO_4 0x0020 0x0250 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_TPM3_CH0 0x0020 0x0250 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO04__AONMIX_TOP_PDM_CLK 0x0020 0x0250 0x0000 0x02 0x00
+#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_GPTMUX_INOUT4 0x0020 0x0250 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_LPSPI7_PCS0 0x0020 0x0250 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_LPUART6_TX 0x0020 0x0250 0x05AC 0x05 0x00
+#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_LPI2C6_SDA 0x0020 0x0250 0x0548 0x06 0x01
+#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_4 0x0020 0x0250 0x04CC 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_GPIO2_IO_5 0x0024 0x0254 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_TPM4_CH0 0x0024 0x0254 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO05__AONMIX_TOP_PDM_BIT_STREAM_0 0x0024 0x0254 0x0464 0x02 0x01
+#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_GPTMUX_INOUT5 0x0024 0x0254 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPSPI7_SIN 0x0024 0x0254 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPUART6_RX 0x0024 0x0254 0x05A8 0x05 0x00
+#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPI2C6_SCL 0x0024 0x0254 0x0544 0x06 0x01
+#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_5 0x0024 0x0254 0x04D0 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_GPIO2_IO_6 0x0028 0x0258 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_TPM5_CH0 0x0028 0x0258 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO06__AONMIX_TOP_PDM_BIT_STREAM_1 0x0028 0x0258 0x0468 0x02 0x01
+#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_GPTMUX_INOUT6 0x0028 0x0258 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPSPI7_SOUT 0x0028 0x0258 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPUART6_CTS_B 0x0028 0x0258 0x05A4 0x05 0x00
+#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPI2C7_SDA 0x0028 0x0258 0x0550 0x06 0x00
+#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_6 0x0028 0x0258 0x04D4 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_GPIO2_IO_7 0x002C 0x025C 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPSPI3_PCS1 0x002C 0x025C 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_GPTMUX_INOUT7 0x002C 0x025C 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPSPI7_SCK 0x002C 0x025C 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPUART6_RTS_B 0x002C 0x025C 0x0000 0x05 0x00
+#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPI2C7_SCL 0x002C 0x025C 0x054C 0x06 0x00
+#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_7 0x002C 0x025C 0x04D8 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_GPIO2_IO_8 0x0030 0x0260 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPSPI3_PCS0 0x0030 0x0260 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_GPTMUX_INOUT8 0x0030 0x0260 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_TPM6_CH0 0x0030 0x0260 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPUART7_TX 0x0030 0x0260 0x05B4 0x05 0x00
+#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPI2C7_SDA 0x0030 0x0260 0x0550 0x06 0x01
+#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_8 0x0030 0x0260 0x04DC 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_GPIO2_IO_9 0x0034 0x0264 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPSPI3_SIN 0x0034 0x0264 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_GPTMUX_INOUT9 0x0034 0x0264 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_TPM3_EXTCLK 0x0034 0x0264 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPUART7_RX 0x0034 0x0264 0x05B0 0x05 0x00
+#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPI2C7_SCL 0x0034 0x0264 0x054C 0x06 0x01
+#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_9 0x0034 0x0264 0x04E0 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPIO2_IO_10 0x0038 0x0268 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_LPSPI3_SOUT 0x0038 0x0268 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPTMUX_INOUT10 0x0038 0x0268 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_TPM4_EXTCLK 0x0038 0x0268 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_LPUART7_CTS_B 0x0038 0x0268 0x0000 0x05 0x00
+#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_LPI2C8_SDA 0x0038 0x0268 0x0558 0x06 0x00
+#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_10 0x0038 0x0268 0x04E4 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_GPIO2_IO_11 0x003C 0x026C 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_LPSPI3_SCK 0x003C 0x026C 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_GPTMUX_INOUT11 0x003C 0x026C 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_TPM5_EXTCLK 0x003C 0x026C 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_LPUART7_RTS_B 0x003C 0x026C 0x0000 0x05 0x00
+#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_LPI2C8_SCL 0x003C 0x026C 0x0554 0x06 0x00
+#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_11 0x003C 0x026C 0x04E8 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_GPIO2_IO_12 0x0040 0x0270 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2 0x0040 0x0270 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO12__AONMIX_TOP_PDM_BIT_STREAM_2 0x0040 0x0270 0x046C 0x02 0x00
+#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_12 0x0040 0x0270 0x04EC 0x03 0x00
+#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_LPSPI8_PCS0 0x0040 0x0270 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_LPUART8_TX 0x0040 0x0270 0x0000 0x05 0x00
+#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_LPI2C8_SDA 0x0040 0x0270 0x0558 0x06 0x01
+#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_SAI3_RX_SYNC 0x0040 0x0270 0x05BC 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_GPIO2_IO_13 0x0044 0x0274 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_TPM4_CH2 0x0044 0x0274 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO13__AONMIX_TOP_PDM_BIT_STREAM_3 0x0044 0x0274 0x0470 0x02 0x00
+#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_LPSPI8_SIN 0x0044 0x0274 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_LPUART8_RX 0x0044 0x0274 0x0000 0x05 0x00
+#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_LPI2C8_SCL 0x0044 0x0274 0x0554 0x06 0x01
+#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_13 0x0044 0x0274 0x04F0 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_GPIO2_IO_14 0x0048 0x0278 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPUART3_TX 0x0048 0x0278 0x0588 0x01 0x01
+#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPSPI8_SOUT 0x0048 0x0278 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPUART8_CTS_B 0x0048 0x0278 0x0000 0x05 0x00
+#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPUART4_TX 0x0048 0x0278 0x0594 0x06 0x01
+#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_14 0x0048 0x0278 0x04F4 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_GPIO2_IO_15 0x004C 0x027C 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPUART3_RX 0x004C 0x027C 0x0584 0x01 0x01
+#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_XSPI1_INTFA_B 0x004C 0x027C 0x0624 0x03 0x00
+#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPSPI8_SCK 0x004C 0x027C 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPUART8_RTS_B 0x004C 0x027C 0x0000 0x05 0x00
+#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPUART4_RX 0x004C 0x027C 0x0590 0x06 0x01
+#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_15 0x004C 0x027C 0x04F8 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_GPIO2_IO_16 0x0050 0x0280 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXBCLK 0x0050 0x0280 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO16__AONMIX_TOP_PDM_BIT_STREAM_2 0x0050 0x0280 0x046C 0x02 0x01
+#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_LPUART3_CTS_B 0x0050 0x0280 0x0580 0x04 0x01
+#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_LPSPI4_PCS2 0x0050 0x0280 0x0564 0x05 0x00
+#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_LPUART4_CTS_B 0x0050 0x0280 0x058C 0x06 0x01
+#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_16 0x0050 0x0280 0x04FC 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_GPIO2_IO_17 0x0054 0x0284 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_SAI3_MCLK 0x0054 0x0284 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_LPUART3_RTS_B 0x0054 0x0284 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_LPSPI4_PCS1 0x0054 0x0284 0x0560 0x05 0x00
+#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_LPUART4_RTS_B 0x0054 0x0284 0x0000 0x06 0x00
+#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_17 0x0054 0x0284 0x0500 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_GPIO2_IO_18 0x0058 0x0288 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_SAI3_RX_BCLK 0x0058 0x0288 0x05B8 0x01 0x00
+#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_LPSPI5_PCS0 0x0058 0x0288 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_LPSPI4_PCS0 0x0058 0x0288 0x055C 0x05 0x00
+#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_TPM5_CH2 0x0058 0x0288 0x0000 0x06 0x00
+#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_18 0x0058 0x0288 0x0504 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_GPIO2_IO_19 0x005C 0x028C 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_SAI3_RX_SYNC 0x005C 0x028C 0x05BC 0x01 0x01
+#define IMX952_PAD_GPIO_IO19__AONMIX_TOP_PDM_BIT_STREAM_3 0x005C 0x028C 0x0470 0x02 0x01
+#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_19 0x005C 0x028C 0x0508 0x03 0x00
+#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_LPSPI5_SIN 0x005C 0x028C 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_LPSPI4_SIN 0x005C 0x028C 0x056C 0x05 0x00
+#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_TPM6_CH2 0x005C 0x028C 0x0000 0x06 0x00
+#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXDATA 0x005C 0x028C 0x05F4 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_GPIO2_IO_20 0x0060 0x0290 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_SAI3_RX_DATA_0 0x0060 0x0290 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO20__AONMIX_TOP_PDM_BIT_STREAM_0 0x0060 0x0290 0x0464 0x02 0x02
+#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_LPSPI5_SOUT 0x0060 0x0290 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_LPSPI4_SOUT 0x0060 0x0290 0x0570 0x05 0x00
+#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_TPM3_CH1 0x0060 0x0290 0x0000 0x06 0x00
+#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_20 0x0060 0x0290 0x050C 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_GPIO2_IO_21 0x0064 0x0294 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXDATA 0x0064 0x0294 0x05F4 0x01 0x01
+#define IMX952_PAD_GPIO_IO21__AONMIX_TOP_PDM_CLK 0x0064 0x0294 0x0000 0x02 0x00
+#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_21 0x0064 0x0294 0x0510 0x03 0x00
+#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_LPSPI5_SCK 0x0064 0x0294 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_LPSPI4_SCK 0x0064 0x0294 0x0568 0x05 0x00
+#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_TPM4_CH1 0x0064 0x0294 0x0000 0x06 0x00
+#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_SAI3_RX_BCLK 0x0064 0x0294 0x05B8 0x07 0x01
+
+#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_GPIO2_IO_22 0x0068 0x0298 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_USDHC3_CLK 0x0068 0x0298 0x0604 0x01 0x00
+#define IMX952_PAD_GPIO_IO22__HSIOMIX_TOP_USB1_OTG_OC 0x0068 0x0298 0x047C 0x03 0x01
+#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_TPM5_CH1 0x0068 0x0298 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_TPM6_EXTCLK 0x0068 0x0298 0x0000 0x05 0x00
+#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_LPI2C5_SDA 0x0068 0x0298 0x0540 0x06 0x01
+#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_22 0x0068 0x0298 0x0514 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_GPIO2_IO_23 0x006C 0x029C 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_USDHC3_CMD 0x006C 0x029C 0x0608 0x01 0x00
+#define IMX952_PAD_GPIO_IO23__HSIOMIX_TOP_USB2_OTG_OC 0x006C 0x029C 0x0480 0x03 0x01
+#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_TPM6_CH1 0x006C 0x029C 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_LPI2C5_SCL 0x006C 0x029C 0x053C 0x06 0x01
+#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_23 0x006C 0x029C 0x0518 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_GPIO2_IO_24 0x0070 0x02A0 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_USDHC3_DATA0 0x0070 0x02A0 0x060C 0x01 0x00
+#define IMX952_PAD_GPIO_IO24__HSIOMIX_TOP_USB1_OTG_PWR 0x0070 0x02A0 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_TPM3_CH3 0x0070 0x02A0 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_TDO 0x0070 0x02A0 0x0000 0x05 0x00
+#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_LPSPI6_PCS1 0x0070 0x02A0 0x0000 0x06 0x00
+#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_24 0x0070 0x02A0 0x051C 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_GPIO2_IO_25 0x0074 0x02A4 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_USDHC3_DATA1 0x0074 0x02A4 0x0610 0x01 0x00
+#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_CAN2_TX 0x0074 0x02A4 0x0000 0x02 0x00
+#define IMX952_PAD_GPIO_IO25__HSIOMIX_TOP_USB2_OTG_PWR 0x0074 0x02A4 0x0000 0x03 0x00
+#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_TPM4_CH3 0x0074 0x02A4 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_TCK 0x0074 0x02A4 0x05F8 0x05 0x01
+#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_LPSPI7_PCS1 0x0074 0x02A4 0x0000 0x06 0x00
+#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_25 0x0074 0x02A4 0x0520 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_GPIO2_IO_26 0x0078 0x02A8 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_USDHC3_DATA2 0x0078 0x02A8 0x0614 0x01 0x00
+#define IMX952_PAD_GPIO_IO26__AONMIX_TOP_PDM_BIT_STREAM_1 0x0078 0x02A8 0x0468 0x02 0x02
+#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_26 0x0078 0x02A8 0x04AC 0x03 0x01
+#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_TPM5_CH3 0x0078 0x02A8 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_TDI 0x0078 0x02A8 0x05FC 0x05 0x01
+#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_LPSPI8_PCS1 0x0078 0x02A8 0x0000 0x06 0x00
+#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXSYNC 0x0078 0x02A8 0x0000 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_GPIO2_IO_27 0x007C 0x02AC 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_USDHC3_DATA3 0x007C 0x02AC 0x0618 0x01 0x00
+#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_CAN2_RX 0x007C 0x02AC 0x04A4 0x02 0x02
+#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_TPM6_CH3 0x007C 0x02AC 0x0000 0x04 0x00
+#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_TMS 0x007C 0x02AC 0x0600 0x05 0x01
+#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_LPSPI5_PCS1 0x007C 0x02AC 0x0000 0x06 0x00
+#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_27 0x007C 0x02AC 0x04B0 0x07 0x01
+
+#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_GPIO2_IO_28 0x0080 0x02B0 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_LPI2C3_SDA 0x0080 0x02B0 0x0530 0x01 0x01
+#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_CAN3_TX 0x0080 0x02B0 0x0000 0x02 0x00
+#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_28 0x0080 0x02B0 0x0000 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_GPIO2_IO_29 0x0084 0x02B4 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_LPI2C3_SCL 0x0084 0x02B4 0x052C 0x01 0x01
+#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_CAN3_RX 0x0084 0x02B4 0x04A8 0x02 0x01
+#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_29 0x0084 0x02B4 0x0000 0x07 0x00
+
+#define IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_GPIO2_IO_30 0x0088 0x02B8 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_LPI2C4_SDA 0x0088 0x02B8 0x0538 0x01 0x01
+#define IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_30 0x0088 0x02B8 0x04B4 0x07 0x01
+
+#define IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_GPIO2_IO_31 0x008C 0x02BC 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_LPI2C4_SCL 0x008C 0x02BC 0x0534 0x01 0x01
+#define IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_31 0x008C 0x02BC 0x04B8 0x07 0x01
+
+#define IMX952_PAD_GPIO_IO32__WAKEUPMIX_TOP_GPIO5_IO_12 0x0090 0x02C0 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x0090 0x02C0 0x0000 0x01 0x00
+#define IMX952_PAD_GPIO_IO32__WAKEUPMIX_TOP_LPUART6_TX 0x0090 0x02C0 0x05AC 0x02 0x01
+#define IMX952_PAD_GPIO_IO32__WAKEUPMIX_TOP_LPSPI4_PCS2 0x0090 0x02C0 0x0564 0x04 0x01
+
+#define IMX952_PAD_GPIO_IO33__WAKEUPMIX_TOP_GPIO5_IO_13 0x0094 0x02C4 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO33__WAKEUPMIX_TOP_LPUART6_RX 0x0094 0x02C4 0x05A8 0x02 0x01
+#define IMX952_PAD_GPIO_IO33__WAKEUPMIX_TOP_LPSPI4_PCS1 0x0094 0x02C4 0x0560 0x04 0x01
+
+#define IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_GPIO5_IO_14 0x0098 0x02C8 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_LPUART6_CTS_B 0x0098 0x02C8 0x05A4 0x02 0x01
+#define IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_LPSPI4_PCS0 0x0098 0x02C8 0x055C 0x04 0x01
+
+#define IMX952_PAD_GPIO_IO35__WAKEUPMIX_TOP_GPIO5_IO_15 0x009C 0x02CC 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO35__WAKEUPMIX_TOP_LPUART6_RTS_B 0x009C 0x02CC 0x0000 0x02 0x00
+#define IMX952_PAD_GPIO_IO35__WAKEUPMIX_TOP_LPSPI4_SIN 0x009C 0x02CC 0x056C 0x04 0x01
+
+#define IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_LPSPI4_SOUT 0x00A0 0x02D0 0x0570 0x04 0x01
+#define IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_GPIO5_IO_16 0x00A0 0x02D0 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_LPUART7_TX 0x00A0 0x02D0 0x05B4 0x02 0x01
+
+#define IMX952_PAD_GPIO_IO37__WAKEUPMIX_TOP_GPIO5_IO_17 0x00A4 0x02D4 0x0000 0x00 0x00
+#define IMX952_PAD_GPIO_IO37__WAKEUPMIX_TOP_LPUART7_RX 0x00A4 0x02D4 0x05B0 0x02 0x01
+#define IMX952_PAD_GPIO_IO37__WAKEUPMIX_TOP_LPSPI4_SCK 0x00A4 0x02D4 0x0568 0x04 0x01
+
+#define IMX952_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1 0x00D4 0x0304 0x0000 0x00 0x00
+#define IMX952_PAD_CCM_CLKO1__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x00D4 0x0304 0x0494 0x01 0x00
+#define IMX952_PAD_CCM_CLKO1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_26 0x00D4 0x0304 0x04AC 0x04 0x00
+#define IMX952_PAD_CCM_CLKO1__WAKEUPMIX_TOP_GPIO3_IO_26 0x00D4 0x0304 0x0000 0x05 0x00
+
+#define IMX952_PAD_CCM_CLKO2__WAKEUPMIX_TOP_GPIO3_IO_27 0x00D8 0x0308 0x0000 0x05 0x00
+#define IMX952_PAD_CCM_CLKO2__CCMSRCGPCMIX_TOP_CLKO_2 0x00D8 0x0308 0x0000 0x00 0x00
+#define IMX952_PAD_CCM_CLKO2__NETCMIX_TOP_NETC_TMR_1588_PP1 0x00D8 0x0308 0x0000 0x01 0x00
+#define IMX952_PAD_CCM_CLKO2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_27 0x00D8 0x0308 0x04B0 0x04 0x00
+
+#define IMX952_PAD_CCM_CLKO3__CCMSRCGPCMIX_TOP_CLKO_3 0x00DC 0x030C 0x0000 0x00 0x00
+#define IMX952_PAD_CCM_CLKO3__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x00DC 0x030C 0x0498 0x01 0x00
+#define IMX952_PAD_CCM_CLKO3__WAKEUPMIX_TOP_CAN3_TX 0x00DC 0x030C 0x0000 0x02 0x00
+#define IMX952_PAD_CCM_CLKO3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_28 0x00DC 0x030C 0x0000 0x04 0x00
+#define IMX952_PAD_CCM_CLKO3__WAKEUPMIX_TOP_GPIO4_IO_28 0x00DC 0x030C 0x0000 0x05 0x00
+
+#define IMX952_PAD_CCM_CLKO4__CCMSRCGPCMIX_TOP_CLKO_4 0x00E0 0x0310 0x0000 0x00 0x00
+#define IMX952_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2 0x00E0 0x0310 0x0000 0x01 0x00
+#define IMX952_PAD_CCM_CLKO4__WAKEUPMIX_TOP_CAN3_RX 0x00E0 0x0310 0x04A8 0x02 0x00
+#define IMX952_PAD_CCM_CLKO4__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_29 0x00E0 0x0310 0x0000 0x04 0x00
+#define IMX952_PAD_CCM_CLKO4__WAKEUPMIX_TOP_GPIO4_IO_29 0x00E0 0x0310 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x00E4 0x0314 0x0484 0x00 0x00
+#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_LPUART3_DCD_B 0x00E4 0x0314 0x0000 0x01 0x00
+#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_I3C2_SCL 0x00E4 0x0314 0x0524 0x02 0x00
+#define IMX952_PAD_ENET1_MDC__HSIOMIX_TOP_USB1_OTG_ID 0x00E4 0x0314 0x0000 0x03 0x00
+#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_0 0x00E4 0x0314 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_GPIO4_IO_0 0x00E4 0x0314 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x00E8 0x0318 0x0488 0x00 0x00
+#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_LPUART3_RIN_B 0x00E8 0x0318 0x0000 0x01 0x00
+#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_I3C2_SDA 0x00E8 0x0318 0x0528 0x02 0x00
+#define IMX952_PAD_ENET1_MDIO__HSIOMIX_TOP_USB1_OTG_PWR 0x00E8 0x0318 0x0000 0x03 0x00
+#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_1 0x00E8 0x0318 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_GPIO4_IO_1 0x00E8 0x0318 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x00EC 0x031C 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_TD3__WAKEUPMIX_TOP_CAN2_TX 0x00EC 0x031C 0x0000 0x02 0x00
+#define IMX952_PAD_ENET1_TD3__HSIOMIX_TOP_USB2_OTG_ID 0x00EC 0x031C 0x0000 0x03 0x00
+#define IMX952_PAD_ENET1_TD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_2 0x00EC 0x031C 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_TD3__WAKEUPMIX_TOP_GPIO4_IO_2 0x00EC 0x031C 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x00F0 0x0320 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RMII_REF50_CLK 0x00F0 0x0320 0x0000 0x01 0x00
+#define IMX952_PAD_ENET1_TD2__WAKEUPMIX_TOP_CAN2_RX 0x00F0 0x0320 0x04A4 0x02 0x01
+#define IMX952_PAD_ENET1_TD2__HSIOMIX_TOP_USB2_OTG_OC 0x00F0 0x0320 0x0480 0x03 0x00
+#define IMX952_PAD_ENET1_TD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_3 0x00F0 0x0320 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_TD2__WAKEUPMIX_TOP_GPIO4_IO_3 0x00F0 0x0320 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x00F4 0x0324 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_LPUART3_RTS_B 0x00F4 0x0324 0x0000 0x01 0x00
+#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_I3C2_PUR 0x00F4 0x0324 0x0000 0x02 0x00
+#define IMX952_PAD_ENET1_TD1__HSIOMIX_TOP_USB1_OTG_OC 0x00F4 0x0324 0x047C 0x03 0x00
+#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_4 0x00F4 0x0324 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_GPIO4_IO_4 0x00F4 0x0324 0x0000 0x05 0x00
+#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_I3C2_PUR_B 0x00F4 0x0324 0x0000 0x06 0x00
+#define IMX952_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RMII_TXD1 0x00F4 0x0324 0x0000 0x07 0x00
+
+#define IMX952_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x00F8 0x0328 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_TD0__WAKEUPMIX_TOP_LPUART3_TX 0x00F8 0x0328 0x0588 0x01 0x00
+#define IMX952_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RMII_TXD0 0x00F8 0x0328 0x0000 0x02 0x00
+#define IMX952_PAD_ENET1_TD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_5 0x00F8 0x0328 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_TD0__WAKEUPMIX_TOP_GPIO4_IO_5 0x00F8 0x0328 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x00FC 0x032C 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_TX_CTL__WAKEUPMIX_TOP_LPUART3_DTR_B 0x00FC 0x032C 0x0000 0x01 0x00
+#define IMX952_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RMII_TX_EN 0x00FC 0x032C 0x0000 0x02 0x00
+#define IMX952_PAD_ENET1_TX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_6 0x00FC 0x032C 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_TX_CTL__WAKEUPMIX_TOP_GPIO4_IO_6 0x00FC 0x032C 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x0100 0x0330 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RMII_REF50_CLK_OUT 0x0100 0x0330 0x0000 0x01 0x00
+#define IMX952_PAD_ENET1_TXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_7 0x0100 0x0330 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_TXC__WAKEUPMIX_TOP_GPIO4_IO_7 0x0100 0x0330 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x0104 0x0334 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_RX_CTL__WAKEUPMIX_TOP_LPUART3_DSR_B 0x0104 0x0334 0x0000 0x01 0x00
+#define IMX952_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RMII_CRS_DV 0x0104 0x0334 0x0000 0x02 0x00
+#define IMX952_PAD_ENET1_RX_CTL__HSIOMIX_TOP_USB2_OTG_PWR 0x0104 0x0334 0x0000 0x03 0x00
+#define IMX952_PAD_ENET1_RX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_8 0x0104 0x0334 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_RX_CTL__WAKEUPMIX_TOP_GPIO4_IO_8 0x0104 0x0334 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x0108 0x0338 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RMII_RX_ER 0x0108 0x0338 0x048C 0x01 0x00
+#define IMX952_PAD_ENET1_RXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_9 0x0108 0x0338 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_RXC__WAKEUPMIX_TOP_GPIO4_IO_9 0x0108 0x0338 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x010C 0x033C 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_RD0__WAKEUPMIX_TOP_LPUART3_RX 0x010C 0x033C 0x0584 0x01 0x00
+#define IMX952_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RMII_RXD0 0x010C 0x033C 0x0000 0x02 0x00
+#define IMX952_PAD_ENET1_RD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_10 0x010C 0x033C 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_RD0__WAKEUPMIX_TOP_GPIO4_IO_10 0x010C 0x033C 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x0110 0x0340 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_LPUART3_CTS_B 0x0110 0x0340 0x0580 0x01 0x00
+#define IMX952_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RMII_RXD1 0x0110 0x0340 0x0000 0x02 0x00
+#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_LPTMR2_ALT0 0x0110 0x0340 0x0574 0x03 0x00
+#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_11 0x0110 0x0340 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_GPIO4_IO_11 0x0110 0x0340 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x0114 0x0344 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RMII_RX_ER 0x0114 0x0344 0x048C 0x02 0x01
+#define IMX952_PAD_ENET1_RD2__WAKEUPMIX_TOP_LPTMR2_ALT1 0x0114 0x0344 0x0578 0x03 0x00
+#define IMX952_PAD_ENET1_RD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_12 0x0114 0x0344 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_RD2__WAKEUPMIX_TOP_GPIO4_IO_12 0x0114 0x0344 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x0118 0x0348 0x0000 0x00 0x00
+#define IMX952_PAD_ENET1_RD3__WAKEUPMIX_TOP_LPTMR2_ALT2 0x0118 0x0348 0x057C 0x03 0x00
+#define IMX952_PAD_ENET1_RD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_13 0x0118 0x0348 0x0000 0x04 0x00
+#define IMX952_PAD_ENET1_RD3__WAKEUPMIX_TOP_GPIO4_IO_13 0x0118 0x0348 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x011C 0x034C 0x0484 0x00 0x01
+#define IMX952_PAD_ENET2_MDC__WAKEUPMIX_TOP_LPUART4_DCD_B 0x011C 0x034C 0x0000 0x01 0x00
+#define IMX952_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x011C 0x034C 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_MDC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_14 0x011C 0x034C 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_MDC__WAKEUPMIX_TOP_GPIO4_IO_14 0x011C 0x034C 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x0120 0x0350 0x0488 0x00 0x01
+#define IMX952_PAD_ENET2_MDIO__WAKEUPMIX_TOP_LPUART4_RIN_B 0x0120 0x0350 0x0000 0x01 0x00
+#define IMX952_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x0120 0x0350 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_MDIO__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_15 0x0120 0x0350 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_MDIO__WAKEUPMIX_TOP_GPIO4_IO_15 0x0120 0x0350 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_0 0x0124 0x0354 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_TD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_16 0x0124 0x0354 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_TD3__WAKEUPMIX_TOP_GPIO4_IO_16 0x0124 0x0354 0x0000 0x05 0x00
+#define IMX952_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x0124 0x0354 0x0000 0x00 0x00
+
+#define IMX952_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x0128 0x0358 0x0000 0x00 0x00
+#define IMX952_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RMII_REF50_CLK 0x0128 0x0358 0x0000 0x01 0x00
+#define IMX952_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_1 0x0128 0x0358 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_TD2__WAKEUPMIX_TOP_SAI4_TX_SYNC 0x0128 0x0358 0x05D0 0x03 0x00
+#define IMX952_PAD_ENET2_TD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_17 0x0128 0x0358 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_TD2__WAKEUPMIX_TOP_GPIO4_IO_17 0x0128 0x0358 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x012C 0x035C 0x0000 0x00 0x00
+#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_LPUART4_RTS_B 0x012C 0x035C 0x0000 0x01 0x00
+#define IMX952_PAD_ENET2_TD1__NETCMIX_TOP_SAI2_RX_DATA_2 0x012C 0x035C 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_SAI4_TX_BCLK 0x012C 0x035C 0x05CC 0x03 0x00
+#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_18 0x012C 0x035C 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_GPIO4_IO_18 0x012C 0x035C 0x0000 0x05 0x00
+#define IMX952_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RMII_TXD1 0x012C 0x035C 0x0000 0x06 0x00
+
+#define IMX952_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x0130 0x0360 0x0000 0x00 0x00
+#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_LPUART4_TX 0x0130 0x0360 0x0594 0x01 0x00
+#define IMX952_PAD_ENET2_TD0__NETCMIX_TOP_SAI2_RX_DATA_3 0x0130 0x0360 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_SAI4_TX_DATA_0 0x0130 0x0360 0x0000 0x03 0x00
+#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_19 0x0130 0x0360 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_GPIO4_IO_19 0x0130 0x0360 0x0000 0x05 0x00
+#define IMX952_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RMII_TXD0 0x0130 0x0360 0x0000 0x06 0x00
+
+#define IMX952_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x0134 0x0364 0x0000 0x00 0x00
+#define IMX952_PAD_ENET2_TX_CTL__WAKEUPMIX_TOP_LPUART4_DTR_B 0x0134 0x0364 0x0000 0x01 0x00
+#define IMX952_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x0134 0x0364 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RMII_TX_EN 0x0134 0x0364 0x0000 0x03 0x00
+#define IMX952_PAD_ENET2_TX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_20 0x0134 0x0364 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_TX_CTL__WAKEUPMIX_TOP_GPIO4_IO_20 0x0134 0x0364 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x0138 0x0368 0x0000 0x00 0x00
+#define IMX952_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RMII_REF50_CLK_OUT 0x0138 0x0368 0x0000 0x01 0x00
+#define IMX952_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x0138 0x0368 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_TXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_21 0x0138 0x0368 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_TXC__WAKEUPMIX_TOP_GPIO4_IO_21 0x0138 0x0368 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x013C 0x036C 0x0000 0x00 0x00
+#define IMX952_PAD_ENET2_RX_CTL__WAKEUPMIX_TOP_LPUART4_DSR_B 0x013C 0x036C 0x0000 0x01 0x00
+#define IMX952_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_0 0x013C 0x036C 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_RX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_22 0x013C 0x036C 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_RX_CTL__WAKEUPMIX_TOP_GPIO4_IO_22 0x013C 0x036C 0x0000 0x05 0x00
+#define IMX952_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RMII_CRS_DV 0x013C 0x036C 0x0000 0x06 0x00
+
+#define IMX952_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x0140 0x0370 0x0000 0x00 0x00
+#define IMX952_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RMII_RX_ER 0x0140 0x0370 0x0490 0x01 0x00
+#define IMX952_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_1 0x0140 0x0370 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_RXC__WAKEUPMIX_TOP_SAI4_RX_SYNC 0x0140 0x0370 0x05C8 0x03 0x00
+#define IMX952_PAD_ENET2_RXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_23 0x0140 0x0370 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_RXC__WAKEUPMIX_TOP_GPIO4_IO_23 0x0140 0x0370 0x0000 0x05 0x00
+
+#define IMX952_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x0144 0x0374 0x0000 0x00 0x00
+#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_LPUART4_RX 0x0144 0x0374 0x0590 0x01 0x00
+#define IMX952_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_2 0x0144 0x0374 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_SAI4_RX_BCLK 0x0144 0x0374 0x05C0 0x03 0x00
+#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_24 0x0144 0x0374 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_GPIO4_IO_24 0x0144 0x0374 0x0000 0x05 0x00
+#define IMX952_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RMII_RXD0 0x0144 0x0374 0x0000 0x06 0x00
+
+#define IMX952_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x0148 0x0378 0x0000 0x00 0x00
+#define IMX952_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_3 0x0148 0x0378 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_RD1__WAKEUPMIX_TOP_SAI4_RX_DATA_0 0x0148 0x0378 0x05C4 0x03 0x00
+#define IMX952_PAD_ENET2_RD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_25 0x0148 0x0378 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_RD1__WAKEUPMIX_TOP_GPIO4_IO_25 0x0148 0x0378 0x0000 0x05 0x00
+#define IMX952_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RMII_RXD1 0x0148 0x0378 0x0000 0x06 0x00
+
+#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x014C 0x037C 0x0000 0x00 0x00
+#define IMX952_PAD_ENET2_RD2__WAKEUPMIX_TOP_LPUART4_CTS_B 0x014C 0x037C 0x058C 0x01 0x00
+#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x014C 0x037C 0x0000 0x02 0x00
+#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_MQS2_RIGHT 0x014C 0x037C 0x0000 0x03 0x00
+#define IMX952_PAD_ENET2_RD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_26 0x014C 0x037C 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_RD2__WAKEUPMIX_TOP_GPIO4_IO_26 0x014C 0x037C 0x0000 0x05 0x00
+#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RMII_RX_ER 0x014C 0x037C 0x0490 0x06 0x01
+
+#define IMX952_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x0150 0x0380 0x0000 0x00 0x00
+#define IMX952_PAD_ENET2_RD3__NETCMIX_TOP_MQS2_LEFT 0x0150 0x0380 0x0000 0x03 0x00
+#define IMX952_PAD_ENET2_RD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_27 0x0150 0x0380 0x0000 0x04 0x00
+#define IMX952_PAD_ENET2_RD3__WAKEUPMIX_TOP_GPIO4_IO_27 0x0150 0x0380 0x0000 0x05 0x00
+
+#define IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_8 0x0154 0x0384 0x04DC 0x04 0x01
+#define IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_GPIO3_IO_8 0x0154 0x0384 0x0000 0x05 0x00
+#define IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x0154 0x0384 0x0000 0x00 0x00
+
+#define IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x0158 0x0388 0x0000 0x00 0x00
+#define IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_9 0x0158 0x0388 0x04E0 0x04 0x01
+#define IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_GPIO3_IO_9 0x0158 0x0388 0x0000 0x05 0x00
+
+#define IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x015C 0x038C 0x0000 0x00 0x00
+#define IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_10 0x015C 0x038C 0x04E4 0x04 0x01
+#define IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_GPIO3_IO_10 0x015C 0x038C 0x0000 0x05 0x00
+
+#define IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x0160 0x0390 0x0000 0x00 0x00
+#define IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_11 0x0160 0x0390 0x04E8 0x04 0x01
+#define IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_GPIO3_IO_11 0x0160 0x0390 0x0000 0x05 0x00
+
+#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x0164 0x0394 0x0000 0x00 0x00
+#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_XSPI1_INTFA_B 0x0164 0x0394 0x0624 0x01 0x01
+#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_12 0x0164 0x0394 0x04EC 0x04 0x01
+#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_GPIO3_IO_12 0x0164 0x0394 0x0000 0x05 0x00
+#define IMX952_PAD_SD1_DATA2__CCMSRCGPCMIX_TOP_PMIC_READY 0x0164 0x0394 0x0000 0x06 0x00
+
+#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x0168 0x0398 0x0000 0x00 0x00
+#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_XSPI1_A_SS1_B 0x0168 0x0398 0x064C 0x01 0x00
+#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_13 0x0168 0x0398 0x04F0 0x04 0x01
+#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_GPIO3_IO_13 0x0168 0x0398 0x0000 0x05 0x00
+
+#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x016C 0x039C 0x0000 0x00 0x00
+#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_XSPI1_A_DATA_4 0x016C 0x039C 0x0638 0x01 0x00
+#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_14 0x016C 0x039C 0x04F4 0x04 0x01
+#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_GPIO3_IO_14 0x016C 0x039C 0x0000 0x05 0x00
+#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_XSPI_SLV_DATA_4 0x016C 0x039C 0x066C 0x06 0x00
+
+#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x0170 0x03A0 0x0000 0x00 0x00
+#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_XSPI1_A_DATA_5 0x0170 0x03A0 0x063C 0x01 0x00
+#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_RESET_B 0x0170 0x03A0 0x0000 0x02 0x00
+#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_15 0x0170 0x03A0 0x04F8 0x04 0x01
+#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_GPIO3_IO_15 0x0170 0x03A0 0x0000 0x05 0x00
+#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_XSPI_SLV_DATA_5 0x0170 0x03A0 0x0670 0x06 0x00
+
+#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x0174 0x03A4 0x0000 0x00 0x00
+#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_XSPI1_A_DATA_6 0x0174 0x03A4 0x0640 0x01 0x00
+#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_CD_B 0x0174 0x03A4 0x0000 0x02 0x00
+#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_16 0x0174 0x03A4 0x04FC 0x04 0x01
+#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_GPIO3_IO_16 0x0174 0x03A4 0x0000 0x05 0x00
+#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_XSPI_SLV_DATA_6 0x0174 0x03A4 0x0674 0x06 0x00
+
+#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x0178 0x03A8 0x0000 0x00 0x00
+#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_XSPI1_A_DATA_7 0x0178 0x03A8 0x0644 0x01 0x00
+#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_WP 0x0178 0x03A8 0x0000 0x02 0x00
+#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_17 0x0178 0x03A8 0x0500 0x04 0x01
+#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_GPIO3_IO_17 0x0178 0x03A8 0x0000 0x05 0x00
+#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_XSPI_SLV_DATA_7 0x0178 0x03A8 0x0678 0x06 0x00
+
+#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x017C 0x03AC 0x0000 0x00 0x00
+#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_XSPI1_A_DQS 0x017C 0x03AC 0x0620 0x01 0x00
+#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_18 0x017C 0x03AC 0x0504 0x04 0x01
+#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_GPIO3_IO_18 0x017C 0x03AC 0x0000 0x05 0x00
+#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_XSPI_SLV_DQS 0x017C 0x03AC 0x0654 0x06 0x00
+
+#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x0180 0x03B0 0x0000 0x00 0x00
+#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_WP 0x0180 0x03B0 0x0000 0x01 0x00
+#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_LPTMR2_ALT2 0x0180 0x03B0 0x057C 0x02 0x01
+#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_19 0x0180 0x03B0 0x0508 0x04 0x01
+#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_GPIO3_IO_19 0x0180 0x03B0 0x0000 0x05 0x00
+#define IMX952_PAD_SD2_VSELECT__CCMSRCGPCMIX_TOP_EXT_CLK1 0x0180 0x03B0 0x0478 0x06 0x01
+
+#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_USDHC3_CLK 0x0184 0x03B4 0x0604 0x00 0x01
+#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_XSPI1_A_SCLK 0x0184 0x03B4 0x061C 0x01 0x00
+#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_SAI5_TX_DATA_1 0x0184 0x03B4 0x0000 0x02 0x00
+#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_SAI5_RX_DATA_0 0x0184 0x03B4 0x05D8 0x03 0x00
+#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_20 0x0184 0x03B4 0x050C 0x04 0x01
+#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_GPIO3_IO_20 0x0184 0x03B4 0x0000 0x05 0x00
+#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_XSPI_SLV_CLK 0x0184 0x03B4 0x0658 0x06 0x00
+
+#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_USDHC3_CMD 0x0188 0x03B8 0x0608 0x00 0x01
+#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_XSPI1_A_SS0_B 0x0188 0x03B8 0x0648 0x01 0x00
+#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_SAI5_TX_DATA_2 0x0188 0x03B8 0x0000 0x02 0x00
+#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_SAI5_RX_SYNC 0x0188 0x03B8 0x05E8 0x03 0x00
+#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_21 0x0188 0x03B8 0x0510 0x04 0x01
+#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_GPIO3_IO_21 0x0188 0x03B8 0x0000 0x05 0x00
+#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_XSPI_SLV_CS 0x0188 0x03B8 0x0650 0x06 0x00
+
+#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_USDHC3_DATA0 0x018C 0x03BC 0x060C 0x00 0x01
+#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_XSPI1_A_DATA_0 0x018C 0x03BC 0x0628 0x01 0x00
+#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_SAI5_TX_DATA_3 0x018C 0x03BC 0x0000 0x02 0x00
+#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_SAI5_RX_BCLK 0x018C 0x03BC 0x05D4 0x03 0x00
+#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_22 0x018C 0x03BC 0x0514 0x04 0x01
+#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_GPIO3_IO_22 0x018C 0x03BC 0x0000 0x05 0x00
+#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_XSPI_SLV_DATA_0 0x018C 0x03BC 0x065C 0x06 0x00
+
+#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_USDHC3_DATA1 0x0190 0x03C0 0x0610 0x00 0x01
+#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_XSPI1_A_DATA_1 0x0190 0x03C0 0x062C 0x01 0x00
+#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_SAI5_RX_DATA_1 0x0190 0x03C0 0x05DC 0x02 0x00
+#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_SAI5_TX_DATA_0 0x0190 0x03C0 0x0000 0x03 0x00
+#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_23 0x0190 0x03C0 0x0518 0x04 0x01
+#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_GPIO3_IO_23 0x0190 0x03C0 0x0000 0x05 0x00
+#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_XSPI_SLV_DATA_1 0x0190 0x03C0 0x0660 0x06 0x00
+
+#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_USDHC3_DATA2 0x0194 0x03C4 0x0614 0x00 0x01
+#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_XSPI1_A_DATA_2 0x0194 0x03C4 0x0630 0x01 0x00
+#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_SAI5_RX_DATA_2 0x0194 0x03C4 0x05E0 0x02 0x00
+#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_SAI5_TX_SYNC 0x0194 0x03C4 0x05F0 0x03 0x00
+#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_24 0x0194 0x03C4 0x051C 0x04 0x01
+#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_GPIO3_IO_24 0x0194 0x03C4 0x0000 0x05 0x00
+#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_XSPI_SLV_DATA_2 0x0194 0x03C4 0x0664 0x06 0x00
+
+#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_USDHC3_DATA3 0x0198 0x03C8 0x0618 0x00 0x01
+#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_XSPI1_A_DATA_3 0x0198 0x03C8 0x0634 0x01 0x00
+#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_SAI5_RX_DATA_3 0x0198 0x03C8 0x05E4 0x02 0x00
+#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_SAI5_TX_BCLK 0x0198 0x03C8 0x05EC 0x03 0x00
+#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_25 0x0198 0x03C8 0x0520 0x04 0x01
+#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_GPIO3_IO_25 0x0198 0x03C8 0x0000 0x05 0x00
+#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_XSPI_SLV_DATA_3 0x0198 0x03C8 0x0668 0x06 0x00
+
+#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_XSPI1_A_DATA_0 0x019C 0x03CC 0x0628 0x00 0x01
+#define IMX952_PAD_XSPI1_DATA0__NETCMIX_TOP_SAI2_TX_DATA_4 0x019C 0x03CC 0x0000 0x01 0x00
+#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_SAI4_TX_BCLK 0x019C 0x03CC 0x05CC 0x02 0x01
+#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_SAI4_RX_DATA_1 0x019C 0x03CC 0x0000 0x03 0x00
+#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_XSPI_SLV_DATA_0 0x019C 0x03CC 0x065C 0x04 0x01
+#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_GPIO5_IO_0 0x019C 0x03CC 0x0000 0x05 0x00
+
+#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_XSPI1_A_DATA_1 0x01A0 0x03D0 0x062C 0x00 0x01
+#define IMX952_PAD_XSPI1_DATA1__NETCMIX_TOP_SAI2_TX_DATA_5 0x01A0 0x03D0 0x0000 0x01 0x00
+#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_SAI4_TX_SYNC 0x01A0 0x03D0 0x05D0 0x02 0x01
+#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_SAI4_TX_DATA_1 0x01A0 0x03D0 0x0000 0x03 0x00
+#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_XSPI_SLV_DATA_1 0x01A0 0x03D0 0x0660 0x04 0x01
+#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_GPIO5_IO_1 0x01A0 0x03D0 0x0000 0x05 0x00
+
+#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_XSPI1_A_DATA_2 0x01A4 0x03D4 0x0630 0x00 0x01
+#define IMX952_PAD_XSPI1_DATA2__NETCMIX_TOP_SAI2_TX_DATA_6 0x01A4 0x03D4 0x0000 0x01 0x00
+#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_SAI4_TX_DATA_0 0x01A4 0x03D4 0x0000 0x02 0x00
+#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_XSPI_SLV_DATA_2 0x01A4 0x03D4 0x0664 0x04 0x01
+#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_GPIO5_IO_2 0x01A4 0x03D4 0x0000 0x05 0x00
+
+#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_XSPI1_A_DATA_3 0x01A8 0x03D8 0x0634 0x00 0x01
+#define IMX952_PAD_XSPI1_DATA3__NETCMIX_TOP_SAI2_TX_DATA_7 0x01A8 0x03D8 0x0000 0x01 0x00
+#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_SAI4_RX_DATA_0 0x01A8 0x03D8 0x05C4 0x02 0x01
+#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_XSPI_SLV_DATA_3 0x01A8 0x03D8 0x0668 0x04 0x01
+#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_GPIO5_IO_3 0x01A8 0x03D8 0x0000 0x05 0x00
+
+#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_XSPI1_A_DATA_4 0x01AC 0x03DC 0x0638 0x00 0x01
+#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_SAI5_TX_DATA_0 0x01AC 0x03DC 0x0000 0x01 0x00
+#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_SAI5_RX_DATA_1 0x01AC 0x03DC 0x05DC 0x02 0x01
+#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_XSPI_SLV_DATA_4 0x01AC 0x03DC 0x066C 0x04 0x01
+#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_GPIO5_IO_4 0x01AC 0x03DC 0x0000 0x05 0x00
+
+#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_XSPI1_A_DATA_5 0x01B0 0x03E0 0x063C 0x00 0x01
+#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_SAI5_TX_SYNC 0x01B0 0x03E0 0x05F0 0x01 0x01
+#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_SAI5_RX_DATA_2 0x01B0 0x03E0 0x05E0 0x02 0x01
+#define IMX952_PAD_XSPI1_DATA5__NETCMIX_TOP_SAI2_RX_DATA_6 0x01B0 0x03E0 0x049C 0x03 0x00
+#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_XSPI_SLV_DATA_5 0x01B0 0x03E0 0x0670 0x04 0x01
+#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_GPIO5_IO_5 0x01B0 0x03E0 0x0000 0x05 0x00
+
+#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_XSPI1_A_DATA_6 0x01B4 0x03E4 0x0640 0x00 0x01
+#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_SAI5_TX_BCLK 0x01B4 0x03E4 0x05EC 0x01 0x01
+#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_SAI5_RX_DATA_3 0x01B4 0x03E4 0x05E4 0x02 0x01
+#define IMX952_PAD_XSPI1_DATA6__NETCMIX_TOP_SAI2_RX_DATA_7 0x01B4 0x03E4 0x04A0 0x03 0x00
+#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_XSPI_SLV_DATA_6 0x01B4 0x03E4 0x0674 0x04 0x01
+#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_GPIO5_IO_6 0x01B4 0x03E4 0x0000 0x05 0x00
+
+#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_XSPI1_A_DATA_7 0x01B8 0x03E8 0x0644 0x00 0x01
+#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_SAI5_RX_DATA_0 0x01B8 0x03E8 0x05D8 0x01 0x01
+#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_SAI5_TX_DATA_1 0x01B8 0x03E8 0x0000 0x02 0x00
+#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_XSPI_SLV_DATA_7 0x01B8 0x03E8 0x0678 0x04 0x01
+#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_GPIO5_IO_7 0x01B8 0x03E8 0x0000 0x05 0x00
+
+#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_XSPI1_A_DQS 0x01BC 0x03EC 0x0620 0x00 0x01
+#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_SAI5_RX_SYNC 0x01BC 0x03EC 0x05E8 0x01 0x01
+#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_SAI5_TX_DATA_2 0x01BC 0x03EC 0x0000 0x02 0x00
+#define IMX952_PAD_XSPI1_DQS__NETCMIX_TOP_SAI2_RX_DATA_6 0x01BC 0x03EC 0x049C 0x03 0x01
+#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_XSPI_SLV_DQS 0x01BC 0x03EC 0x0654 0x04 0x01
+#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_GPIO5_IO_8 0x01BC 0x03EC 0x0000 0x05 0x00
+
+#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_XSPI1_A_SCLK 0x01C0 0x03F0 0x061C 0x00 0x01
+#define IMX952_PAD_XSPI1_SCLK__NETCMIX_TOP_SAI2_RX_DATA_4 0x01C0 0x03F0 0x0000 0x01 0x00
+#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_SAI4_RX_SYNC 0x01C0 0x03F0 0x05C8 0x02 0x01
+#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_XSPI_SLV_CLK 0x01C0 0x03F0 0x0658 0x04 0x01
+#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_GPIO5_IO_9 0x01C0 0x03F0 0x0000 0x05 0x00
+
+#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_XSPI1_A_SS0_B 0x01C4 0x03F4 0x0648 0x00 0x01
+#define IMX952_PAD_XSPI1_SS0_B__NETCMIX_TOP_SAI2_RX_DATA_5 0x01C4 0x03F4 0x0000 0x01 0x00
+#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_SAI4_RX_BCLK 0x01C4 0x03F4 0x05C0 0x02 0x01
+#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_XSPI_SLV_CS 0x01C4 0x03F4 0x0650 0x04 0x01
+#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_GPIO5_IO_10 0x01C4 0x03F4 0x0000 0x05 0x00
+
+#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_XSPI1_A_SS1_B 0x01C8 0x03F8 0x064C 0x00 0x01
+#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_SAI5_RX_BCLK 0x01C8 0x03F8 0x05D4 0x01 0x01
+#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_SAI5_TX_DATA_3 0x01C8 0x03F8 0x0000 0x02 0x00
+#define IMX952_PAD_XSPI1_SS1_B__NETCMIX_TOP_SAI2_RX_DATA_7 0x01C8 0x03F8 0x04A0 0x03 0x01
+#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_GPIO5_IO_11 0x01C8 0x03F8 0x0000 0x05 0x00
+
+#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_USDHC2_CD_B 0x01CC 0x03FC 0x0000 0x00 0x00
+#define IMX952_PAD_SD2_CD_B__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x01CC 0x03FC 0x0494 0x01 0x01
+#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_I3C2_SCL 0x01CC 0x03FC 0x0524 0x02 0x01
+#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_0 0x01CC 0x03FC 0x04BC 0x04 0x01
+#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_GPIO3_IO_0 0x01CC 0x03FC 0x0000 0x05 0x00
+
+#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x01D0 0x0400 0x0000 0x00 0x00
+#define IMX952_PAD_SD2_CLK__NETCMIX_TOP_NETC_TMR_1588_PP1 0x01D0 0x0400 0x0000 0x01 0x00
+#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_I3C2_SDA 0x01D0 0x0400 0x0528 0x02 0x01
+#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_1 0x01D0 0x0400 0x04C0 0x04 0x01
+#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_GPIO3_IO_1 0x01D0 0x0400 0x0000 0x05 0x00
+#define IMX952_PAD_SD2_CLK__CCMSRCGPCMIX_TOP_OBSERVE_0 0x01D0 0x0400 0x0000 0x06 0x00
+
+#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x01D4 0x0404 0x0000 0x00 0x00
+#define IMX952_PAD_SD2_CMD__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x01D4 0x0404 0x0498 0x01 0x01
+#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_I3C2_PUR 0x01D4 0x0404 0x0000 0x02 0x00
+#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_I3C2_PUR_B 0x01D4 0x0404 0x0000 0x03 0x00
+#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_2 0x01D4 0x0404 0x04C4 0x04 0x01
+#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_GPIO3_IO_2 0x01D4 0x0404 0x0000 0x05 0x00
+#define IMX952_PAD_SD2_CMD__CCMSRCGPCMIX_TOP_OBSERVE_1 0x01D4 0x0404 0x0000 0x06 0x00
+
+#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x01D8 0x0408 0x0000 0x00 0x00
+#define IMX952_PAD_SD2_DATA0__NETCMIX_TOP_NETC_TMR_1588_PP2 0x01D8 0x0408 0x0000 0x01 0x00
+#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_CAN2_TX 0x01D8 0x0408 0x0000 0x02 0x00
+#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_3 0x01D8 0x0408 0x04C8 0x04 0x01
+#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_GPIO3_IO_3 0x01D8 0x0408 0x0000 0x05 0x00
+#define IMX952_PAD_SD2_DATA0__CCMSRCGPCMIX_TOP_OBSERVE_2 0x01D8 0x0408 0x0000 0x06 0x00
+
+#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x01DC 0x040C 0x0000 0x00 0x00
+#define IMX952_PAD_SD2_DATA1__NETCMIX_TOP_NETC_TMR_1588_CLK 0x01DC 0x040C 0x0000 0x01 0x00
+#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_CAN2_RX 0x01DC 0x040C 0x04A4 0x02 0x03
+#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_4 0x01DC 0x040C 0x04CC 0x04 0x01
+#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_GPIO3_IO_4 0x01DC 0x040C 0x0000 0x05 0x00
+
+#define IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x01E0 0x0410 0x0000 0x00 0x00
+#define IMX952_PAD_SD2_DATA2__NETCMIX_TOP_NETC_TMR_1588_PP3 0x01E0 0x0410 0x0000 0x01 0x00
+#define IMX952_PAD_SD2_DATA2__NETCMIX_TOP_MQS2_RIGHT 0x01E0 0x0410 0x0000 0x02 0x00
+#define IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_5 0x01E0 0x0410 0x04D0 0x04 0x01
+#define IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_GPIO3_IO_5 0x01E0 0x0410 0x0000 0x05 0x00
+
+#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x01E4 0x0414 0x0000 0x00 0x00
+#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_LPTMR2_ALT0 0x01E4 0x0414 0x0574 0x01 0x01
+#define IMX952_PAD_SD2_DATA3__NETCMIX_TOP_MQS2_LEFT 0x01E4 0x0414 0x0000 0x02 0x00
+#define IMX952_PAD_SD2_DATA3__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x01E4 0x0414 0x0000 0x03 0x00
+#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_6 0x01E4 0x0414 0x04D4 0x04 0x01
+#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_GPIO3_IO_6 0x01E4 0x0414 0x0000 0x05 0x00
+
+#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_USDHC2_RESET_B 0x01E8 0x0418 0x0000 0x00 0x00
+#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_LPTMR2_ALT1 0x01E8 0x0418 0x0578 0x01 0x01
+#define IMX952_PAD_SD2_RESET_B__NETCMIX_TOP_NETC_TMR_1588_GCLK 0x01E8 0x0418 0x0000 0x03 0x00
+#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_7 0x01E8 0x0418 0x04D8 0x04 0x01
+#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x01E8 0x0418 0x0000 0x05 0x00
+
+#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x01EC 0x041C 0x0000 0x00 0x00
+#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_I3C1_SCL 0x01EC 0x041C 0x0000 0x01 0x00
+#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_LPUART1_DCD_B 0x01EC 0x041C 0x0000 0x02 0x00
+#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_TPM2_CH0 0x01EC 0x041C 0x0000 0x03 0x00
+#define IMX952_PAD_I2C1_SCL__VPUMIX_TOP_UART_RX 0x01EC 0x041C 0x0000 0x04 0x00
+#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_GPIO1_IO_0 0x01EC 0x041C 0x0000 0x05 0x00
+
+#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x01F0 0x0420 0x0000 0x00 0x00
+#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_I3C1_SDA 0x01F0 0x0420 0x0000 0x01 0x00
+#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_LPUART1_RIN_B 0x01F0 0x0420 0x0000 0x02 0x00
+#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_TPM2_CH1 0x01F0 0x0420 0x0000 0x03 0x00
+#define IMX952_PAD_I2C1_SDA__VPUMIX_TOP_UART_TX 0x01F0 0x0420 0x0000 0x04 0x00
+#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_GPIO1_IO_1 0x01F0 0x0420 0x0000 0x05 0x00
+
+#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x01F4 0x0424 0x0000 0x00 0x00
+#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR 0x01F4 0x0424 0x0000 0x01 0x00
+#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPUART2_DCD_B 0x01F4 0x0424 0x0000 0x02 0x00
+#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_TPM2_CH2 0x01F4 0x0424 0x0000 0x03 0x00
+#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_SAI1_RX_SYNC 0x01F4 0x0424 0x0000 0x04 0x00
+#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_2 0x01F4 0x0424 0x0000 0x05 0x00
+#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR_B 0x01F4 0x0424 0x0000 0x06 0x00
+
+#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x01F8 0x0428 0x0000 0x00 0x00
+#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_LPUART2_RIN_B 0x01F8 0x0428 0x0000 0x02 0x00
+#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_TPM2_CH3 0x01F8 0x0428 0x0000 0x03 0x00
+#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_SAI1_RX_BCLK 0x01F8 0x0428 0x0000 0x04 0x00
+#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_3 0x01F8 0x0428 0x0000 0x05 0x00
+
+#define IMX952_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x01FC 0x042C 0x0000 0x00 0x00
+#define IMX952_PAD_UART1_RXD__AONMIX_TOP_UART_CSSI_RX 0x01FC 0x042C 0x0000 0x01 0x00
+#define IMX952_PAD_UART1_RXD__AONMIX_TOP_LPSPI2_SIN 0x01FC 0x042C 0x0000 0x02 0x00
+#define IMX952_PAD_UART1_RXD__AONMIX_TOP_TPM1_CH0 0x01FC 0x042C 0x0000 0x03 0x00
+#define IMX952_PAD_UART1_RXD__AONMIX_TOP_GPIO1_IO_4 0x01FC 0x042C 0x0000 0x05 0x00
+
+#define IMX952_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x0200 0x0430 0x0000 0x00 0x00
+#define IMX952_PAD_UART1_TXD__AONMIX_TOP_UART_CSSI_TX 0x0200 0x0430 0x0000 0x01 0x00
+#define IMX952_PAD_UART1_TXD__AONMIX_TOP_LPSPI2_PCS0 0x0200 0x0430 0x0000 0x02 0x00
+#define IMX952_PAD_UART1_TXD__AONMIX_TOP_TPM1_CH1 0x0200 0x0430 0x0000 0x03 0x00
+#define IMX952_PAD_UART1_TXD__AONMIX_TOP_GPIO1_IO_5 0x0200 0x0430 0x0000 0x05 0x00
+
+#define IMX952_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x0204 0x0434 0x0000 0x00 0x00
+#define IMX952_PAD_UART2_RXD__AONMIX_TOP_LPUART1_CTS_B 0x0204 0x0434 0x0000 0x01 0x00
+#define IMX952_PAD_UART2_RXD__AONMIX_TOP_LPSPI2_SOUT 0x0204 0x0434 0x0000 0x02 0x00
+#define IMX952_PAD_UART2_RXD__AONMIX_TOP_TPM1_CH2 0x0204 0x0434 0x0000 0x03 0x00
+#define IMX952_PAD_UART2_RXD__AONMIX_TOP_SAI1_MCLK 0x0204 0x0434 0x0474 0x04 0x00
+#define IMX952_PAD_UART2_RXD__AONMIX_TOP_GPIO1_IO_6 0x0204 0x0434 0x0000 0x05 0x00
+
+#define IMX952_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x0208 0x0438 0x0000 0x00 0x00
+#define IMX952_PAD_UART2_TXD__AONMIX_TOP_LPUART1_RTS_B 0x0208 0x0438 0x0000 0x01 0x00
+#define IMX952_PAD_UART2_TXD__AONMIX_TOP_LPSPI2_SCK 0x0208 0x0438 0x0000 0x02 0x00
+#define IMX952_PAD_UART2_TXD__AONMIX_TOP_TPM1_CH3 0x0208 0x0438 0x0000 0x03 0x00
+#define IMX952_PAD_UART2_TXD__AONMIX_TOP_GPIO1_IO_7 0x0208 0x0438 0x0000 0x05 0x00
+
+#define IMX952_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x020C 0x043C 0x0000 0x00 0x00
+#define IMX952_PAD_PDM_CLK__AONMIX_TOP_MQS1_LEFT 0x020C 0x043C 0x0000 0x01 0x00
+#define IMX952_PAD_PDM_CLK__AONMIX_TOP_LPTMR1_ALT0 0x020C 0x043C 0x0000 0x04 0x00
+#define IMX952_PAD_PDM_CLK__AONMIX_TOP_GPIO1_IO_8 0x020C 0x043C 0x0000 0x05 0x00
+#define IMX952_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x020C 0x043C 0x0000 0x06 0x00
+
+#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_0 0x0210 0x0440 0x0464 0x00 0x00
+#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_MQS1_RIGHT 0x0210 0x0440 0x0000 0x01 0x00
+#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPSPI1_PCS1 0x0210 0x0440 0x0000 0x02 0x00
+#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_TPM1_EXTCLK 0x0210 0x0440 0x0000 0x03 0x00
+#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPTMR1_ALT1 0x0210 0x0440 0x0000 0x04 0x00
+#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_GPIO1_IO_9 0x0210 0x0440 0x0000 0x05 0x00
+#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x0210 0x0440 0x0460 0x06 0x00
+
+#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_PDM_BIT_STREAM_1 0x0214 0x0444 0x0468 0x00 0x00
+#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_NMI 0x0214 0x0444 0x0000 0x01 0x00
+#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPSPI2_PCS1 0x0214 0x0444 0x0000 0x02 0x00
+#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_TPM2_EXTCLK 0x0214 0x0444 0x0000 0x03 0x00
+#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPTMR1_ALT2 0x0214 0x0444 0x0000 0x04 0x00
+#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_10 0x0214 0x0444 0x0000 0x05 0x00
+#define IMX952_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_TOP_EXT_CLK1 0x0214 0x0444 0x0478 0x06 0x00
+
+#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x0218 0x0448 0x0000 0x00 0x00
+#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_DATA_1 0x0218 0x0448 0x0000 0x01 0x00
+#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_LPSPI1_PCS0 0x0218 0x0448 0x0000 0x02 0x00
+#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_LPUART2_DTR_B 0x0218 0x0448 0x0000 0x03 0x00
+#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_LEFT 0x0218 0x0448 0x0000 0x04 0x00
+#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_11 0x0218 0x0448 0x0000 0x05 0x00
+
+#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x021C 0x044C 0x0000 0x00 0x00
+#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_LPUART2_CTS_B 0x021C 0x044C 0x0000 0x01 0x00
+#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_LPSPI1_SIN 0x021C 0x044C 0x0000 0x02 0x00
+#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_LPUART1_DSR_B 0x021C 0x044C 0x0000 0x03 0x00
+#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_CAN1_RX 0x021C 0x044C 0x0460 0x04 0x01
+#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_12 0x021C 0x044C 0x0000 0x05 0x00
+
+#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_0 0x0220 0x0450 0x0000 0x00 0x00
+#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_LPUART2_RTS_B 0x0220 0x0450 0x0000 0x01 0x00
+#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_LPSPI1_SCK 0x0220 0x0450 0x0000 0x02 0x00
+#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_LPUART1_DTR_B 0x0220 0x0450 0x0000 0x03 0x00
+#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_CAN1_TX 0x0220 0x0450 0x0000 0x04 0x00
+#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_13 0x0220 0x0450 0x0000 0x05 0x00
+
+#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_0 0x0224 0x0454 0x0000 0x00 0x00
+#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_MCLK 0x0224 0x0454 0x0474 0x01 0x01
+#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_LPSPI1_SOUT 0x0224 0x0454 0x0000 0x02 0x00
+#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_LPUART2_DSR_B 0x0224 0x0454 0x0000 0x03 0x00
+#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_RIGHT 0x0224 0x0454 0x0000 0x04 0x00
+#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_14 0x0224 0x0454 0x0000 0x05 0x00
+
+#define IMX952_PAD_WDOG_ANY__AONMIX_TOP_WDOG_ANY 0x0228 0x0458 0x0000 0x00 0x00
+#define IMX952_PAD_WDOG_ANY__AONMIX_TOP_FCCU_EOUT1 0x0228 0x0458 0x0000 0x01 0x00
+#define IMX952_PAD_WDOG_ANY__AONMIX_TOP_GPIO1_IO_15 0x0228 0x0458 0x0000 0x05 0x00
+#endif /* __DTS_IMX952_PINFUNC_H__ */
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright 2025 NXP
+ */
+
+#ifndef __IMX952_POWER_H__
+#define __IMX952_POWER_H__
+
+#define IMX952_PD_ANA 0
+#define IMX952_PD_AON 1
+#define IMX952_PD_BBSM 2
+#define IMX952_PD_CAMERA 3
+#define IMX952_PD_CCMSRCGPC 4
+#define IMX952_PD_A55C0 5
+#define IMX952_PD_A55C1 6
+#define IMX952_PD_A55C2 7
+#define IMX952_PD_A55C3 8
+#define IMX952_PD_A55P 9
+#define IMX952_PD_DDR 10
+#define IMX952_PD_DISPLAY 11
+#define IMX952_PD_GPU 12
+#define IMX952_PD_HSIO_TOP 13
+#define IMX952_PD_HSIO_WAON 14
+#define IMX952_PD_M7 15
+#define IMX952_PD_NETC 16
+#define IMX952_PD_NOC 17
+#define IMX952_PD_NPU 18
+#define IMX952_PD_VPU 19
+#define IMX952_PD_WAKEUP 20
+
+#define IMX952_PERF_M33 0
+#define IMX952_PERF_WAKEUP 1
+#define IMX952_PERF_M7 2
+#define IMX952_PERF_DRAM 3
+#define IMX952_PERF_HSIO 4
+#define IMX952_PERF_NPU 5
+#define IMX952_PERF_NOC 6
+#define IMX952_PERF_A55 7
+#define IMX952_PERF_GPU 8
+#define IMX952_PERF_VPU 9
+#define IMX952_PERF_CAM 10
+#define IMX952_PERF_DISP 11
+
+#endif
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
+/*
+ * Copyright 2025-2026 NXP
+ */
+
+#include <dt-bindings/dma/fsl-edma.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "imx952-clock.h"
+#include "imx952-pinfunc.h"
+#include "imx952-power.h"
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clk_ext1: clock-ext1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <133000000>;
+ clock-output-names = "clk_ext1";
+ };
+
+ clk_dummy: clock-dummy {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "dummy";
+ };
+
+ clk_ldb_pll_pixel: clock-ldb-pll-div7 {
+ compatible = "fixed-factor-clock";
+ clocks = <&scmi_clk IMX952_CLK_LDBPLL>;
+ #clock-cells = <0>;
+ clock-div = <7>;
+ clock-mult = <1>;
+ clock-output-names = "ldb_pll_div7";
+ };
+
+ clk_osc_24m: clock-osc-24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc_24m";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ idle-states {
+ entry-method = "psci";
+
+ cpu_pd_wait: cpu-pd-wait {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010033>;
+ local-timer-stop;
+ entry-latency-us = <1000>;
+ exit-latency-us = <700>;
+ min-residency-us = <2700>;
+ wakeup-latency-us = <1500>;
+ };
+ };
+
+ A55_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ cpu-idle-states = <&cpu_pd_wait>;
+ power-domains = <&scmi_perf IMX952_PERF_A55>;
+ power-domain-names = "perf";
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l0>;
+ };
+
+ A55_1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ cpu-idle-states = <&cpu_pd_wait>;
+ power-domains = <&scmi_perf IMX952_PERF_A55>;
+ power-domain-names = "perf";
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l1>;
+ };
+
+ A55_2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x200>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ cpu-idle-states = <&cpu_pd_wait>;
+ power-domains = <&scmi_perf IMX952_PERF_A55>;
+ power-domain-names = "perf";
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l2>;
+ };
+
+ A55_3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x300>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ cpu-idle-states = <&cpu_pd_wait>;
+ power-domains = <&scmi_perf IMX952_PERF_A55>;
+ power-domain-names = "perf";
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l3>;
+ };
+
+ l2_cache_l0: l2-cache-l0 {
+ compatible = "cache";
+ cache-size = <65536>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_l1: l2-cache-l1 {
+ compatible = "cache";
+ cache-size = <65536>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_l2: l2-cache-l2 {
+ compatible = "cache";
+ cache-size = <65536>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_l3: l2-cache-l3 {
+ compatible = "cache";
+ cache-size = <65536>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l3_cache: l3-cache {
+ compatible = "cache";
+ cache-size = <524288>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-level = <3>;
+ cache-unified;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&A55_0>;
+ };
+
+ core1 {
+ cpu = <&A55_1>;
+ };
+
+ core2 {
+ cpu = <&A55_2>;
+ };
+
+ core3 {
+ cpu = <&A55_3>;
+ };
+ };
+ };
+ };
+
+ firmware {
+ scmi {
+ compatible = "arm,scmi";
+ mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>;
+ shmem = <&scmi_buf0>, <&scmi_buf1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ arm,max-rx-timeout-ms = <5000>;
+
+ scmi_devpd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi_sys_power: protocol@12 {
+ reg = <0x12>;
+ };
+
+ scmi_perf: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+
+ scmi_sensor: protocol@15 {
+ reg = <0x15>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ scmi_iomuxc: protocol@19 {
+ reg = <0x19>;
+ };
+
+ scmi_lmm: protocol@80 {
+ reg = <0x80>;
+ };
+
+ scmi_bbm: protocol@81 {
+ reg = <0x81>;
+ };
+
+ scmi_cpu: protocol@82 {
+ reg = <0x82>;
+ };
+
+ scmi_misc: protocol@84 {
+ reg = <0x84>;
+ };
+ };
+ };
+
+ gic: interrupt-controller@48000000 {
+ compatible = "arm,gic-v3";
+ reg = <0 0x48000000 0 0x10000>,
+ <0 0x48060000 0 0xc0000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ dma-noncoherent;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ its: msi-controller@48040000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0 0x48040000 0 0x20000>;
+ msi-controller;
+ #msi-cells = <1>;
+ dma-noncoherent;
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a55-pmu";
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <24000000>;
+ arm,no-tick-in-suspend;
+ interrupt-parent = <&gic>;
+ };
+
+ usbphynop1: usbphynop1 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ clocks = <&clk_dummy>;
+ clock-names = "main_clk";
+ };
+
+ usbphynop2: usbphynop2 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ clocks = <&clk_dummy>;
+ clock-names = "main_clk";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x0 0x0 0x80000000>,
+ <0x0 0x28000000 0x0 0x28000000 0x0 0x10000000>;
+
+ aips2: bus@42000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x0 0x42000000 0x0 0x800000>;
+ ranges = <0x42000000 0x0 0x42000000 0x8000000>,
+ <0x28000000 0x0 0x28000000 0x10000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mu7: mailbox@42050000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x42050000 0x10000>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ wdog3: watchdog@420b0000 {
+ compatible = "fsl,imx93-wdt";
+ reg = <0x420b0000 0x10000>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ timeout-sec = <40>;
+ status = "disabled";
+ };
+
+ tpm3: pwm@42100000 {
+ compatible = "fsl,imx7ulp-pwm";
+ reg = <0x42100000 0x1000>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ tpm4: pwm@42110000 {
+ compatible = "fsl,imx7ulp-pwm";
+ reg = <0x42110000 0x1000>;
+ clocks = <&scmi_clk IMX952_CLK_TPM4>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ tpm5: pwm@42120000 {
+ compatible = "fsl,imx7ulp-pwm";
+ reg = <0x42120000 0x1000>;
+ clocks = <&scmi_clk IMX952_CLK_TPM5>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ tpm6: pwm@42130000 {
+ compatible = "fsl,imx7ulp-pwm";
+ reg = <0x42130000 0x1000>;
+ clocks = <&scmi_clk IMX952_CLK_TPM6>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ i3c2: i3c@42140000 {
+ compatible = "silvaco,i3c-master-v1";
+ reg = <0x42140000 0x10000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX952_CLK_I3C2SLOW>,
+ <&clk_dummy>;
+ clock-names = "pclk", "fast_clk", "slow_clk";
+ status = "disabled";
+ };
+
+ lpi2c3: i2c@42150000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x42150000 0x10000>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPI2C3>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpi2c4: i2c@42160000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x42160000 0x10000>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPI2C4>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpspi3: spi@42170000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x42170000 0x10000>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPSPI3>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpspi4: spi@42180000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x42180000 0x10000>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPSPI4>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpuart3: serial@42190000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x42190000 0x1000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPUART3>;
+ clock-names = "ipg";
+ dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ lpuart4: serial@421a0000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x421a0000 0x1000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPUART4>;
+ clock-names = "ipg";
+ dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ lpuart5: serial@421b0000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x421b0000 0x1000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPUART5>;
+ clock-names = "ipg";
+ dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ lpuart6: serial@421c0000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x421c0000 0x1000>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPUART6>;
+ clock-names = "ipg";
+ dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ flexcan2: can@421d0000 {
+ compatible = "fsl,imx95-flexcan";
+ reg = <0x421d0000 0x10000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX952_CLK_CAN2>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&scmi_clk IMX952_CLK_CAN2>;
+ assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>;
+ assigned-clock-rates = <40000000>;
+ fsl,clk-source = /bits/ 8 <0>;
+ status = "disabled";
+ };
+
+ flexcan3: can@42220000 {
+ compatible = "fsl,imx95-flexcan";
+ reg = <0x42220000 0x10000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX952_CLK_CAN3>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&scmi_clk IMX952_CLK_CAN3>;
+ assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>;
+ assigned-clock-rates = <40000000>;
+ fsl,clk-source = /bits/ 8 <0>;
+ status = "disabled";
+ };
+
+ lpuart7: serial@422b0000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x422b0000 0x1000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPUART7>;
+ clock-names = "ipg";
+ dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ lpuart8: serial@422c0000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x422c0000 0x1000>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPUART8>;
+ clock-names = "ipg";
+ dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ lpi2c5: i2c@422d0000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x422d0000 0x10000>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPI2C5>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpi2c6: i2c@422e0000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x422e0000 0x10000>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPI2C6>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpi2c7: i2c@422f0000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x422f0000 0x10000>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPI2C7>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpi2c8: i2c@42300000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x42300000 0x10000>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPI2C8>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpspi5: spi@42310000 {
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x42310000 0x10000>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk IMX952_CLK_LPSPI5>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpspi6: spi@42320000 {
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x42320000 0x10000>;
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk IMX952_CLK_LPSPI6>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpspi7: spi@42330000 {
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x42330000 0x10000>;
+ interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk IMX952_CLK_LPSPI7>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpspi8: spi@42340000 {
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x42340000 0x10000>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk IMX952_CLK_LPSPI8>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ mu8: mailbox@42350000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x42350000 0x10000>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+ };
+
+ aips3: bus@42800000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0 0x42800000 0 0x800000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x42800000 0x0 0x42800000 0x800000>;
+
+ edma2: dma-controller@42800000 {
+ compatible = "fsl,imx95-edma5";
+ reg = <0x42800000 0x210000>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "dma";
+ #dma-cells = <3>;
+ dma-channels = <64>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; //error irq
+ };
+
+ usdhc1: mmc@42c20000 {
+ compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
+ reg = <0x42c20000 0x10000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX952_CLK_WAKEUPAXI>,
+ <&scmi_clk IMX952_CLK_USDHC1>;
+ clock-names = "ipg", "ahb", "per";
+ assigned-clocks = <&scmi_clk IMX952_CLK_USDHC1>;
+ assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1>;
+ assigned-clock-rates = <400000000>;
+ bus-width = <8>;
+ fsl,tuning-start-tap = <1>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ usdhc2: mmc@42c30000 {
+ compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
+ reg = <0x42c30000 0x10000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX952_CLK_WAKEUPAXI>,
+ <&scmi_clk IMX952_CLK_USDHC2>;
+ clock-names = "ipg", "ahb", "per";
+ assigned-clocks = <&scmi_clk IMX952_CLK_USDHC2>;
+ assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1>;
+ assigned-clock-rates = <200000000>;
+ bus-width = <4>;
+ fsl,tuning-start-tap = <1>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ usdhc3: mmc@42c40000 {
+ compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
+ reg = <0x42c40000 0x10000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX952_CLK_WAKEUPAXI>,
+ <&scmi_clk IMX952_CLK_USDHC3>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ fsl,tuning-start-tap = <1>;
+ fsl,tuning-step = <2>;
+ status = "disabled";
+ };
+ };
+
+ gpio2: gpio@43810000 {
+ compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
+ reg = <0x0 0x43810000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&scmi_iomuxc 0 4 32>;
+ ngpios = <32>;
+ };
+
+ gpio3: gpio@43820000 {
+ compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
+ reg = <0x0 0x43820000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&scmi_iomuxc 0 115 8>, <&scmi_iomuxc 8 85 18>,
+ <&scmi_iomuxc 26 53 2>, <&scmi_iomuxc 28 0 4>;
+ ngpios = <32>;
+ };
+
+ gpio4: gpio@43840000 {
+ compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
+ reg = <0x0 0x43840000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&scmi_iomuxc 0 57 28>, <&scmi_iomuxc 28 55 2>;
+ ngpios = <30>;
+ };
+
+ gpio5: gpio@43850000 {
+ compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
+ reg = <0x0 0x43850000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX952_CLK_BUSWAKEUP>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&scmi_iomuxc 0 103 12>, <&scmi_iomuxc 12 36 6>;
+ ngpios = <18>;
+ };
+
+ aips1: bus@44000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x0 0x44000000 0x0 0x800000>;
+ ranges = <0x44000000 0x0 0x44000000 0x800000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ edma1: dma-controller@44000000 {
+ compatible = "fsl,imx93-edma3";
+ reg = <0x44000000 0x210000>;
+ clocks = <&scmi_clk IMX952_CLK_BUSAON>;
+ clock-names = "dma";
+ #dma-cells = <3>;
+ dma-channels = <32>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; //error irq
+ };
+
+ mu1: mailbox@44220000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x44220000 0x10000>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSAON>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ system_counter: timer@44290000 {
+ compatible = "nxp,imx95-sysctr-timer";
+ reg = <0x44290000 0x30000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_osc_24m>;
+ clock-names = "per";
+ nxp,no-divider;
+ };
+
+ i3c1: i3c@44330000 {
+ compatible = "silvaco,i3c-master-v1";
+ reg = <0x44330000 0x10000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk IMX952_CLK_BUSAON>,
+ <&scmi_clk IMX952_CLK_I3C1SLOW>,
+ <&clk_dummy>;
+ clock-names = "pclk", "fast_clk", "slow_clk";
+ status = "disabled";
+ };
+
+ lpi2c1: i2c@44340000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x44340000 0x10000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPI2C1>,
+ <&scmi_clk IMX952_CLK_BUSAON>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX> ;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpi2c2: i2c@44350000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x44350000 0x10000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPI2C2>,
+ <&scmi_clk IMX952_CLK_BUSAON>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX> ;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpspi1: spi@44360000 {
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x44360000 0x10000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPSPI1>,
+ <&scmi_clk IMX952_CLK_BUSAON>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&edma1 16 0 FSL_EDMA_RX>, <&edma1 17 0 0> ;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpspi2: spi@44370000 {
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x44370000 0x10000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPSPI2>,
+ <&scmi_clk IMX952_CLK_BUSAON>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&edma1 18 0 FSL_EDMA_RX>, <&edma1 19 0 0> ;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ lpuart1: serial@44380000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x44380000 0x1000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPUART1>;
+ clock-names = "ipg";
+ dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ lpuart2: serial@44390000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x44390000 0x1000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_LPUART2>;
+ clock-names = "ipg";
+ dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ flexcan1: can@443a0000 {
+ compatible = "fsl,imx95-flexcan";
+ reg = <0x443a0000 0x10000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSAON>,
+ <&scmi_clk IMX952_CLK_CAN1>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&scmi_clk IMX952_CLK_CAN1>;
+ assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>;
+ assigned-clock-rates = <40000000>;
+ fsl,clk-source = /bits/ 8 <0>;
+ status = "disabled";
+ };
+
+ adc1: adc@44530000 {
+ compatible = "nxp,imx93-adc";
+ reg = <0x44530000 0x10000>;
+ interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_ADC>;
+ clock-names = "ipg";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
+ mu2: mailbox@445b0000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x445b0000 0x1000>;
+ ranges;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #mbox-cells = <2>;
+
+ sram0: sram@445b1000 {
+ compatible = "mmio-sram";
+ reg = <0x445b1000 0x400>;
+ ranges = <0x0 0x445b1000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ scmi_buf0: scmi-sram-section@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x80>;
+ };
+
+ scmi_buf1: scmi-sram-section@80 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x80 0x80>;
+ };
+ };
+
+ };
+
+ mu3: mailbox@445d0000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x445d0000 0x10000>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSAON>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ mu4: mailbox@445f0000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x445f0000 0x10000>;
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSAON>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ mu5: mailbox@44610000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x44610000 0x10000>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSAON>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ mu6: mailbox@44630000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x44630000 0x10000>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_BUSAON>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+ };
+
+ v2x_mu0: mailbox@47300000 {
+ compatible = "fsl,imx95-mu-v2x";
+ reg = <0x0 0x47300000 0x0 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
+ v2x_mu2: mailbox@47320000 {
+ compatible = "fsl,imx95-mu-v2x";
+ reg = <0x0 0x47320000 0x0 0x10000>;
+ interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
+ v2x_mu3: mailbox@47330000 {
+ compatible = "fsl,imx95-mu-v2x";
+ reg = <0x0 0x47330000 0x0 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
+ v2x_mu4: mailbox@47340000 {
+ compatible = "fsl,imx95-mu-v2x";
+ reg = <0x0 0x47340000 0x0 0x10000>;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
+ v2x_mu: mailbox@47350000 {
+ compatible = "fsl,imx95-mu-v2x";
+ reg = <0x0 0x47350000 0x0 0x10000>;
+ interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
+ /* GPIO1 is under exclusive control of System Manager */
+ gpio1: gpio@47400000 {
+ compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
+ reg = <0x0 0x47400000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&scmi_clk IMX952_CLK_M33>,
+ <&scmi_clk IMX952_CLK_M33>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&scmi_iomuxc 0 123 16>;
+ ngpios = <16>;
+ status = "disabled";
+ };
+
+ elemu0: mailbox@47520000 {
+ compatible = "fsl,imx95-mu-ele";
+ reg = <0x0 0x47520000 0x0 0x10000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ elemu1: mailbox@47530000 {
+ compatible = "fsl,imx95-mu-ele";
+ reg = <0x0 0x47530000 0x0 0x10000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ elemu2: mailbox@47540000 {
+ compatible = "fsl,imx95-mu-ele";
+ reg = <0x0 0x47540000 0x0 0x10000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ elemu3: mailbox@47550000 {
+ compatible = "fsl,imx95-mu-ele";
+ reg = <0x0 0x47550000 0x0 0x10000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
+ elemu4: mailbox@47560000 {
+ compatible = "fsl,imx95-mu-ele";
+ reg = <0x0 0x47560000 0x0 0x10000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ elemu5: mailbox@47570000 {
+ compatible = "fsl,imx95-mu-ele";
+ reg = <0x0 0x47570000 0x0 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ usb1: usb@4c100000 {
+ compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
+ reg = <0x0 0x4c100000 0x0 0x200>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_CGC_HSIOUSB>,
+ <&scmi_clk IMX952_CLK_OSC32K>;
+ clock-names = "usb_ctrl_root", "usb_wakeup";
+ power-domains = <&scmi_devpd IMX952_PD_HSIO_TOP>;
+ phys = <&usbphynop1>;
+ fsl,usbmisc = <&usbmisc1 0>;
+ status = "disabled";
+ };
+
+ usbmisc1: usbmisc@4c100200 {
+ compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
+ #index-cells = <1>;
+ reg = <0x0 0x4c100200 0x0 0x200>,
+ <0x0 0x4c010010 0x0 0x4>;
+ };
+
+ usb2: usb@4c200000 {
+ compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
+ reg = <0x0 0x4c200000 0x0 0x200>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX952_CLK_CGC_HSIOUSB>,
+ <&scmi_clk IMX952_CLK_OSC32K>;
+ clock-names = "usb_ctrl_root", "usb_wakeup";
+ power-domains = <&scmi_devpd IMX952_PD_HSIO_TOP>;
+ phys = <&usbphynop2>;
+ fsl,usbmisc = <&usbmisc2 0>;
+ status = "disabled";
+ };
+
+ usbmisc2: usbmisc@4c200200 {
+ compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
+ #index-cells = <1>;
+ reg = <0x0 0x4c200200 0x0 0x200>,
+ <0x0 0x4c010014 0x0 0x4>;
+ };
+ };
+};
tlv320aic3x04: audio-codec@18 {
compatible = "ti,tlv320aic32x4";
reg = <0x18>;
- clocks = <&mclkout0_lpcg 0>;
+ clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
clock-names = "mclk";
iov-supply = <®_1v8>;
ldoin-supply = <®_3v3>;
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
- <&sai1_lpcg 0>;
+ <&sai1_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
status = "disabled";
};
- swt7: watchdog@4020C000 {
+ swt7: watchdog@4020c000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
- reg = <0x4020C000 0x1000>;
+ reg = <0x4020c000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
dspi1-grp3 {
- pinmux = <0x5F0>;
+ pinmux = <0x5f0>;
input-enable;
slew-rate = <150>;
bias-pull-up;
};
dspi1-grp4 {
- pinmux = <0x3D92>,
- <0x3DA2>,
- <0x3DB2>;
+ pinmux = <0x3d92>,
+ <0x3da2>,
+ <0x3db2>;
};
};
};
dspi5-grp1 {
- pinmux = <0xA0>;
+ pinmux = <0xa0>;
input-enable;
slew-rate = <150>;
bias-pull-up;
};
dspi5-grp2 {
- pinmux = <0x3ED2>,
- <0x3EE2>,
- <0x3EF2>;
+ pinmux = <0x3ed2>,
+ <0x3ee2>,
+ <0x3ef2>;
};
dspi5-grp3 {
- pinmux = <0xB3>;
+ pinmux = <0xb3>;
output-enable;
slew-rate = <150>;
};
dspi5-grp4 {
- pinmux = <0xC3>;
+ pinmux = <0xc3>;
output-enable;
input-enable;
slew-rate = <150>;
};
dspi1-grp3 {
- pinmux = <0x5F0>;
+ pinmux = <0x5f0>;
input-enable;
slew-rate = <150>;
bias-pull-up;
};
dspi1-grp4 {
- pinmux = <0x3D92>,
- <0x3DA2>,
- <0x3DB2>;
+ pinmux = <0x3d92>,
+ <0x3da2>,
+ <0x3db2>;
};
};
};
dspi5-grp1 {
- pinmux = <0xA0>;
+ pinmux = <0xa0>;
input-enable;
slew-rate = <150>;
bias-pull-up;
};
dspi5-grp2 {
- pinmux = <0x3ED2>,
- <0x3EE2>,
- <0x3EF2>;
+ pinmux = <0x3ed2>,
+ <0x3ee2>,
+ <0x3ef2>;
};
dspi5-grp3 {
- pinmux = <0xB3>;
+ pinmux = <0xb3>;
output-enable;
slew-rate = <150>;
};
dspi5-grp4 {
- pinmux = <0xC3>;
+ pinmux = <0xc3>;
output-enable;
input-enable;
slew-rate = <150>;
status = "okay";
};
+&hsio_phy {
+ fsl,hsio-cfg = "pciea-x2-pcieb";
+ fsl,refclk-pad-mode = "input";
+ status = "okay";
+};
+
&i2c0 {
tlv320aic3x04: audio-codec@18 {
compatible = "ti,tlv320aic32x4";
reg = <0x18>;
- clocks = <&mclkout0_lpcg 0>;
+ clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
clock-names = "mclk";
iov-supply = <®_1v8>;
ldoin-supply = <®_3v3>;
status = "okay";
};
+&pcieb {
+ status = "okay";
+};
+
®_sdvmmc {
off-on-delay-us = <200000>;
status = "okay";
status = "okay";
};
+&pcieb {
+ phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
+ phy-names = "pcie-phy";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcieb>;
+ reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
+};
+
&sai1 {
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
- <&sai1_lpcg 0>;
+ <&sai1_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
};
pinctrl_pcieb: pcieagrp {
- fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000041>,
- <IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000041>,
- <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000041>;
+ fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000041>,
+ <IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B 0x06000041>,
+ <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000041>;
};
pinctrl_pwm_mipi_lvds0: mipi-lvds0-pwmgrp {
};
&pcie {
- reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
vpcie-supply = <®_pcie>;
status = "okay";
};
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xf0000000 0x10000000>;
+ dma-ranges = <0x0 0x0 0x0 0x40000000>;
crg: clock-reset-controller@8a22000 {
compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
clock-names = "nf_clk";
cdns,board-delay-ps = <4830>;
iommus = <&smmu 4>;
+ dma-coherent;
status = "disabled";
};
#size-cells = <1>;
};
- dmac0: dma-controller@10db0000 {
- compatible = "snps,axi-dma-1.01a";
- reg = <0x10db0000 0x500>;
- clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
- <&clkmgr AGILEX5_L4_MP_CLK>;
- clock-names = "core-clk", "cfgr-clk";
- interrupt-parent = <&intc>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- dma-channels = <4>;
- snps,dma-masters = <1>;
- snps,data-width = <2>;
- snps,block-size = <32767 32767 32767 32767>;
- snps,priority = <0 1 2 3>;
- snps,axi-max-burst-len = <8>;
- iommus = <&smmu 8>;
- };
-
- dmac1: dma-controller@10dc0000 {
- compatible = "snps,axi-dma-1.01a";
- reg = <0x10dc0000 0x500>;
- clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
- <&clkmgr AGILEX5_L4_MP_CLK>;
- clock-names = "core-clk", "cfgr-clk";
- interrupt-parent = <&intc>;
- interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- dma-channels = <4>;
- snps,dma-masters = <1>;
- snps,data-width = <2>;
- snps,block-size = <32767 32767 32767 32767>;
- snps,priority = <0 1 2 3>;
- snps,axi-max-burst-len = <8>;
- iommus = <&smmu 9>;
+ dma: dma-bus@10db0000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <2>;
+ ranges = <0x00 0x10db0000 0x00 0x20000>;
+ dma-ranges = <0x00 0x00 0x100 0x00>;
+
+ dmac0: dma-controller@0 {
+ compatible = "altr,agilex5-axi-dma",
+ "snps,axi-dma-1.01a";
+ reg = <0x0 0x0 0x500>;
+ clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
+ <&clkmgr AGILEX5_L4_MP_CLK>;
+ clock-names = "core-clk", "cfgr-clk";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ snps,dma-masters = <1>;
+ snps,data-width = <2>;
+ snps,block-size = <32767 32767 32767 32767>;
+ snps,priority = <0 1 2 3>;
+ snps,axi-max-burst-len = <8>;
+ iommus = <&smmu 8>;
+ };
+
+ dmac1: dma-controller@10000 {
+ compatible = "altr,agilex5-axi-dma",
+ "snps,axi-dma-1.01a";
+ reg = <0x10000 0x0 0x500>;
+ clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
+ <&clkmgr AGILEX5_L4_MP_CLK>;
+ clock-names = "core-clk", "cfgr-clk";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ snps,dma-masters = <1>;
+ snps,data-width = <2>;
+ snps,block-size = <32767 32767 32767 32767>;
+ snps,priority = <0 1 2 3>;
+ snps,axi-max-burst-len = <8>;
+ iommus = <&smmu 9>;
+ };
};
rst: rstmgr@10d11000 {
snps,tso;
altr,sysmgr-syscon = <&sysmgr 0x44 0>;
snps,clk-csr = <0>;
+ iommus = <&smmu 1>;
status = "disabled";
stmmac_axi_emac0_setup: stmmac-axi-config {
snps,dcb-algorithm;
};
queue1 {
- snps,weight = <0x0A>;
+ snps,weight = <0x0a>;
snps,dcb-algorithm;
};
queue2 {
- snps,weight = <0x0B>;
+ snps,weight = <0x0b>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue3 {
- snps,weight = <0x0C>;
+ snps,weight = <0x0c>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue4 {
- snps,weight = <0x0D>;
+ snps,weight = <0x0d>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue5 {
- snps,weight = <0x0E>;
+ snps,weight = <0x0e>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue6 {
- snps,weight = <0x0F>;
+ snps,weight = <0x0f>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
snps,tso;
altr,sysmgr-syscon = <&sysmgr 0x48 0>;
snps,clk-csr = <0>;
+ iommus = <&smmu 2>;
status = "disabled";
stmmac_axi_emac1_setup: stmmac-axi-config {
snps,dcb-algorithm;
};
queue1 {
- snps,weight = <0x0A>;
+ snps,weight = <0x0a>;
snps,dcb-algorithm;
};
queue2 {
- snps,weight = <0x0B>;
+ snps,weight = <0x0b>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue3 {
- snps,weight = <0x0C>;
+ snps,weight = <0x0c>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue4 {
- snps,weight = <0x0D>;
+ snps,weight = <0x0d>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue5 {
- snps,weight = <0x0E>;
+ snps,weight = <0x0e>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue6 {
- snps,weight = <0x0F>;
+ snps,weight = <0x0f>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
snps,tso;
altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
snps,clk-csr = <0>;
+ iommus = <&smmu 3>;
status = "disabled";
stmmac_axi_emac2_setup: stmmac-axi-config {
snps,dcb-algorithm;
};
queue1 {
- snps,weight = <0x0A>;
+ snps,weight = <0x0a>;
snps,dcb-algorithm;
};
queue2 {
- snps,weight = <0x0B>;
+ snps,weight = <0x0b>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue3 {
- snps,weight = <0x0C>;
+ snps,weight = <0x0c>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue4 {
- snps,weight = <0x0D>;
+ snps,weight = <0x0d>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue5 {
- snps,weight = <0x0E>;
+ snps,weight = <0x0e>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue6 {
- snps,weight = <0x0F>;
+ snps,weight = <0x0f>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
pmu0_tbu3: pmu@160a2000 {
compatible = "arm,smmu-v3-pmcg";
- reg = <0x160A2000 0x1000>,
- <0x160B2000 0x1000>;
+ reg = <0x160a2000 0x1000>,
+ <0x160b2000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
};
pmu0_tbu4: pmu@160c2000 {
compatible = "arm,smmu-v3-pmcg";
- reg = <0x160C2000 0x1000>,
- <0x160D2000 0x1000>;
+ reg = <0x160c2000 0x1000>,
+ <0x160d2000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
};
pmu0_tbu5: pmu@160e2000 {
compatible = "arm,smmu-v3-pmcg";
- reg = <0x160E2000 0x1000>,
- <0x160F2000 0x1000>;
+ reg = <0x160e2000 0x1000>,
+ <0x160f2000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2025, Altera Corporation
+ */
+#include "socfpga_agilex5.dtsi"
+
+/ {
+ model = "SoCFPGA Agilex5 SoCDK - Modular development kit";
+ compatible = "intel,socfpga-agilex5-socdk-modular", "intel,socfpga-agilex5";
+
+ aliases {
+ serial0 = &uart0;
+ ethernet2 = &gmac2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led0 {
+ label = "hps_led0";
+ gpios = <&porta 0x0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0x0 0x80000000 0x0 0x0>;
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gmac2 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <&emac2_phy0>;
+ max-frame-size = <9000>;
+
+ mdio0 {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ emac2_phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&osc1 {
+ clock-frequency = <25000000>;
+};
+
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "micron,mt25qu02g", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+ m25p,fast-read;
+ cdns,read-delay = <2>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qspi_boot: partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x04200000>;
+ };
+
+ root: partition@4200000 {
+ label = "root";
+ reg = <0x04200000 0x0be00000>;
+ };
+ };
+ };
+};
+
+&smmu {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
root: partition@4200000 {
label = "Root Filesystem - UBIFS";
- reg = <0x04200000 0x0BE00000>;
+ reg = <0x04200000 0x0be00000>;
};
};
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026, Altera Corporation
+ */
+#include "socfpga_agilex.dtsi"
+
+/ {
+ model = "SoCFPGA Agilex SoCDK eMMC daughter board";
+ compatible = "intel,socfpga-agilex-socdk-emmc", "intel,socfpga-agilex";
+
+ aliases {
+ serial0 = &uart0;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ ethernet2 = &gmac2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led0 {
+ label = "hps_led0";
+ gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
+ };
+
+ led1 {
+ label = "hps_led1";
+ gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
+ };
+
+ led2 {
+ label = "hps_led2";
+ gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0 0x80000000 0 0>;
+ };
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gmac2 {
+ status = "okay";
+ /* PHY delays is configured via skew properties */
+ phy-mode = "rgmii";
+ phy-handle = <&phy0>;
+
+ max-frame-size = <9000>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy@4 {
+ reg = <4>;
+
+ txd0-skew-ps = <0>; /* -420ps */
+ txd1-skew-ps = <0>; /* -420ps */
+ txd2-skew-ps = <0>; /* -420ps */
+ txd3-skew-ps = <0>; /* -420ps */
+ rxd0-skew-ps = <420>; /* 0ps */
+ rxd1-skew-ps = <420>; /* 0ps */
+ rxd2-skew-ps = <420>; /* 0ps */
+ rxd3-skew-ps = <420>; /* 0ps */
+ txen-skew-ps = <0>; /* -420ps */
+ txc-skew-ps = <900>; /* 0ps */
+ rxdv-skew-ps = <420>; /* 0ps */
+ rxc-skew-ps = <1680>; /* 780ps */
+ };
+ };
+};
+
+&mmc {
+ status = "okay";
+ cap-mmc-highspeed;
+ broken-cd;
+ bus-width = <4>;
+ clk-phase-sd-hs = <0>, <135>;
+};
+
+&osc1 {
+ clock-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ disable-over-current;
+};
+
+&watchdog0 {
+ status = "okay";
+};
qspi_boot: partition@0 {
label = "Boot and fpga data";
- reg = <0x0 0x03FE0000>;
+ reg = <0x0 0x03fe0000>;
};
qspi_rootfs: partition@3fe0000 {
label = "Root Filesystem - JFFS2";
- reg = <0x03FE0000 0x0C020000>;
+ reg = <0x03fe0000 0x0c020000>;
};
};
};
clock-output-names = "BUSCLK";
};
- amba {
+ amba-bus {
#address-cells = <2>;
#size-cells = <1>;
usb3_phy: usb3-phy {
compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
vcc-supply = <&exp_usb3_vbus>;
};
usb3_phy: usb3-phy {
compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
vcc-supply = <®_usb3_vbus>;
};
gpio-leds {
- pinctrl-names = "default";
compatible = "gpio-leds";
/* No assigned functions to the LEDs by default */
led1 {
};
vcc_sd_reg1: regulator {
- compatible = "regulator-gpio";
+ compatible = "regulator-fixed";
regulator-name = "vcc_sd1";
- regulator-min-microvolt = <1800000>;
+ regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
-
- gpios-states = <0>;
- states = <1800000 0x1
- 3300000 0x0>;
- enable-active-high;
};
keys {
};
crypto: crypto@90000 {
- compatible = "inside-secure,safexcel-eip97ies";
+ compatible = "marvell,armada-3700-crypto",
+ "inside-secure,safexcel-eip97ies";
reg = <0x90000 0x20000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for Marvell Armada 7020 Com Express CPU module board.
+ */
+
+#include "armada-7020.dtsi"
+
+/ {
+ model = "Marvell Armada-7020 COMEXPRESS board setup";
+ compatible = "marvell,armada7020-cpu-module", "marvell,armada7020",
+ "marvell,armada-ap806-dual", "marvell,armada-ap806";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x2 0x00000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ ethernet0 = &cp0_eth0;
+ ethernet1 = &cp0_eth1;
+ };
+};
+
+&ap_clk {
+ status = "okay";
+};
+
+&gic {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&spi0 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&cp0_mdio {
+ status = "okay";
+
+ phy0: ethernet-phy@10 {
+ reg = <0x10>;
+ };
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+&cp0_eth0 {
+ status = "okay";
+ phy-mode = "10gbase-r";
+ managed = "in-band-status";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy4 0>;
+};
+
+&cp0_eth1 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+};
+
+&cp0_clk {
+ status = "okay";
+};
+
+&cp0_i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&cp0_nand_controller {
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ label = "main-storage";
+ nand-rb = <0>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x400000>;
+ };
+ partition@200000 {
+ label = "Linux";
+ reg = <0x400000 0x100000>;
+ };
+ partition@1000000 {
+ label = "Filesystem";
+ reg = <0x500000 0x1e00000>;
+ };
+ };
+ };
+};
+
+&cp0_pcie0 {
+ status = "okay";
+ num-lanes = <4>;
+ num-viewport = <8>;
+
+ ranges = <0x81000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x00010000
+ 0x82000000 0x0 0x00000000 0x0 0xc0000000 0x0 0x30000000>;
+
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy0 0
+ &cp0_comphy1 0
+ &cp0_comphy2 0
+ &cp0_comphy3 0>;
+};
+
+&cp0_sata0 {
+ /* CPM Lane 0 - U29 */
+ status = "okay";
+
+ sata-port@1 {
+ status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy5 1>;
+ };
+};
+
+&cp0_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhci_pins>;
+ status = "okay";
+ bus-width = <4>;
+ no-1-8-v;
+ broken-cd;
+};
+
cp0_pinctrl: pinctrl {
compatible = "marvell,armada-7k-pinctrl";
+
+ sdhci_pins: sdhci-pins {
+ marvell,pins = "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61", "mpp62";
+ marvell,function = "sdio";
+ };
+
nand_pins: nand-pins {
marvell,pins =
"mpp15", "mpp16", "mpp17", "mpp18",
cp0_usb3_0_phy: cp0-usb3-0-phy {
compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
vcc-supply = <&cp0_reg_usb3_0_vbus>;
};
cp1_usb3_0_phy: cp1-usb3-0-phy {
compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
vcc-supply = <&cp1_reg_usb3_0_vbus>;
};
};
};
thermal-zones {
- /delete-node/ ap-thermal-cpu2;
- /delete-node/ ap-thermal-cpu3;
+ /delete-node/ ap-cpu2-thermal;
+ /delete-node/ ap-cpu3-thermal;
};
};
};
CP11X_LABEL(crypto): crypto@800000 {
- compatible = "inside-secure,safexcel-eip197b";
+ compatible = "marvell,armada-cp110-crypto",
+ "inside-secure,safexcel-eip197b";
reg = <0x800000 0x200000>;
interrupts = <88 IRQ_TYPE_LEVEL_HIGH>,
<89 IRQ_TYPE_LEVEL_HIGH>,
&cp0_pinctrl {
pinctrl-0 = <&sim_select_pins>;
- pintrl-names = "default";
+ pinctrl-names = "default";
rear_button_pins: cp0-rear-button-pins {
marvell,pins = "mpp31";
cp0_usb3_0_phy0: usb-phy-1 {
compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
};
cp0_usb3_0_phy1: usb-phy-2 {
compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
vcc-supply = <&cp0_reg_usb3_vbus1>;
};
/* on-board eMMC U6 */
&ap_sdhci0 {
- pinctrl-names = "default";
bus-width = <8>;
status = "okay";
mmc-ddr-1_8v;
cp0_usb3_0_phy0: usb-phy-1 {
compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
vcc-supply = <&cp0_reg_usb3_vbus0>;
};
cp0_usb3_0_phy1: usb-phy-2 {
compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
vcc-supply = <&cp0_reg_usb3_vbus1>;
};
/* on-board eMMC - U9 */
&ap_sdhci0 {
- pinctrl-names = "default";
bus-width = <8>;
vqmmc-supply = <&ap0_reg_sd_vccq>;
status = "okay";
/* U36 */
expander0: pca953x@21 {
compatible = "nxp,pca9555";
- pinctrl-names = "default";
gpio-controller;
#gpio-cells = <2>;
reg = <0x21>;
expander0: gpio@41 {
compatible = "nxp,pca9536";
reg = <0x41>;
+ gpio-controller;
+ #gpio-cells = <2>;
usb-a-vbus0-ilimit-hog {
gpio-hog;
};
&ap0_reg_sd_vccq {
+ compatible = "regulator-fixed";
regulator-max-microvolt = <1800000>;
- states = <1800000 0x1 1800000 0x0>;
+ /delete-property/ states;
/delete-property/ gpios;
};
cp1_usb3_0_phy0: usb-phy-3 {
compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
vcc-supply = <&cp1_reg_usb3_vbus0>;
};
cp2_usb3_0_phy0: usb-phy-4 {
compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
vcc-supply = <&cp2_reg_usb3_vbus0>;
};
cp2_usb3_0_phy1: usb-phy-5 {
compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
vcc-supply = <&cp2_reg_usb3_vbus1>;
};
/* U12 */
cp2_module_expander1: pca9555@21 {
compatible = "nxp,pca9555";
- pinctrl-names = "default";
gpio-controller;
#gpio-cells = <2>;
reg = <0x21>;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 Marvell International Ltd.
+ *
+ * Device tree for the Falcon DB Type 7 Com Express carrier board,
+ * Utilizing the Armada 7020 COM Express CPU module board.
+ * This specific carrier board (DB-98CX8540/80)
+ * only maintains a PCIe link with the CPU module,
+ * which does not require any special DTS definitions.
+ *
+ * There is no Linux CPU booting in this mode on the carrier, only on the
+ * Armada 7020 COM Express CPU module.
+ * What runs the Linux is the Armada 7020 on the COM Express CPU module,
+ * And it accesses the switch end-point on the Falcon DB portion of the carrier
+ * via PCIe.
+ */
+
+#include "armada-7020-comexpress.dtsi"
+#include "db-falcon-carrier.dtsi"
+
+/ {
+ model = "Marvell Falcon DB COM EXPRESS type 7 carrier board with Armada 7020 CPU module";
+ compatible = "marvell,armada7020-falcon-carrier", "marvell,db-falcon-carrier",
+ "marvell,armada7020-cpu-module", "marvell,armada7020",
+ "marvell,armada-ap806-dual", "marvell,armada-ap806";
+
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 Marvell International Ltd.
+ *
+ * Device tree for the Falcon DB Type 7 Com Express carrier board,
+ * This (DB-98CX8540/80) specific carrier board only maintains
+ * a PCIe link with the COM Express CPU module, which does not
+ * require any special DTS definitions.
+ *
+ * The board contains the 98CX8540/80 Switch, which connects by
+ * PCIe to the COM Express CPU module.
+ * This CPU module can be any standard COM Express CPU module with
+ * PCIe support.
+ *
+ * There is no Linux CPU booting in this mode on the carrier,
+ * only on the COM Express CPU module.
+ */
+
+/ {
+ model = "Marvell Armada Falcon DB COM EXPRESS type 7 carrier board";
+ compatible = "marvell,db-falcon-carrier";
+};
};
mt6331_vcamio_reg: ldo-vcamio {
- regulator-name = "vcam_io";
+ regulator-name = "vcamio";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <0>;
&mmc1 {
/* MicroSD card slot */
- pinctrl-names = "default";
+ pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_uhs>;
vmmc-supply = <&mt6331_vmc_reg>;
vqmmc-supply = <&mt6331_vmch_reg>;
status = "okay";
&mmc2 {
/* SDIO WiFi on MMC2 */
- pinctrl-names = "default";
+ pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_uhs>;
vmmc-supply = <&mt6331_vmc_reg>;
vqmmc-supply = <&mt6331_vmch_reg>;
status = "okay";
<PINMUX_GPIO170__FUNC_MSDC1_CMD>;
input-enable;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ drive-strength = <4>;
};
pins-clk {
pinmux = <PINMUX_GPIO175__FUNC_MSDC1_CLK>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ drive-strength = <4>;
+ };
+ };
+
+ mmc1_pins_uhs: microsd-uhs-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO171__FUNC_MSDC1_DAT0>,
+ <PINMUX_GPIO172__FUNC_MSDC1_DAT1>,
+ <PINMUX_GPIO173__FUNC_MSDC1_DAT2>,
+ <PINMUX_GPIO174__FUNC_MSDC1_DAT3>,
+ <PINMUX_GPIO170__FUNC_MSDC1_CMD>;
+ input-enable;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ drive-strength = <6>;
+ };
+
+ pins-clk {
+ pinmux = <PINMUX_GPIO175__FUNC_MSDC1_CLK>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ drive-strength = <8>;
};
};
<PINMUX_GPIO105__FUNC_MSDC2_CMD>;
input-enable;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ drive-strength = <4>;
+ };
+
+ pins-clk {
+ pinmux = <PINMUX_GPIO104__FUNC_MSDC2_CLK>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ drive-strength = <4>;
+ };
+ };
+
+ mmc2_pins_uhs: sdio-uhs-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO100__FUNC_MSDC2_DAT0>,
+ <PINMUX_GPIO101__FUNC_MSDC2_DAT1>,
+ <PINMUX_GPIO102__FUNC_MSDC2_DAT2>,
+ <PINMUX_GPIO103__FUNC_MSDC2_DAT3>,
+ <PINMUX_GPIO105__FUNC_MSDC2_CMD>;
+ input-enable;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ drive-strength = <8>;
};
pins-clk {
pinmux = <PINMUX_GPIO104__FUNC_MSDC2_CLK>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ drive-strength = <8>;
};
};
*/
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
- mt6332-led {
+ leds {
compatible = "mediatek,mt6332-led";
#address-cells = <1>;
#size-cells = <0>;
};
scpsys: syscon@10006000 {
- compatible = "syscon", "simple-mfd";
+ compatible = "mediatek,mt6795-scpsys", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
- #power-domain-cells = <1>;
/* System Power Manager */
spm: power-controller {
model = "OpenWrt One";
aliases {
+ ethernet0 = &gmac1;
+ ethernet1 = &gmac0;
serial0 = &uart0;
};
linux,default-trigger = "netdev";
};
};
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+ð {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ /* WAN interface */
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ nvmem-cells = <&wan_factory_mac 0>;
+ nvmem-cell-names = "mac-address";
+ phy-mode = "2500base-x";
+ phy-handle = <&phy15>;
+ };
+
+ /* LAN interface */
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ phy-mode = "gmii";
+ phy-handle = <&int_gbe_phy>;
+ };
+};
+
+&mdio_bus {
+ phy15: ethernet-phy@f {
+ compatible = "ethernet-phy-id03a2.a411";
+ reg = <0xf>;
+ interrupt-parent = <&pio>;
+ interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <20000>;
+ airoha,pnswap-rx;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_AMBER>;
+ };
+
+ led@1 {
+ reg = <1>;
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pins>;
+ status = "okay";
};
&pio {
+ pcie_pins: pcie-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie_pereset";
+ };
+ };
+
pwm_pins: pwm-pins {
mux {
function = "pwm";
pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
};
};
+
+ wifi_dbdc_pins: wifi-dbdc-pins {
+ mux {
+ function = "eth";
+ groups = "wf0_mode1";
+ };
+
+ conf {
+ pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
+ "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
+ "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
+ "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
+ "WF_CBA_RESETB", "WF_DIG_RESETB";
+ drive-strength = <4>;
+ };
+ };
};
&pwm {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
- #address-cells = <1>;
- #size-cells = <1>;
partitions {
compatible = "fixed-partitions";
};
};
+&sgmiisys0 {
+ mediatek,pnswap;
+};
+
&uart0 {
status = "okay";
};
+
+&usb_phy {
+ status = "okay";
+};
+
+&wifi {
+ nvmem-cells = <&wifi_factory_calibration>;
+ nvmem-cell-names = "eeprom";
+ pinctrl-names = "dbdc";
+ pinctrl-0 = <&wifi_dbdc_pins>;
+ status = "okay";
+};
+
+&xhci {
+ phys = <&u2port0 PHY_TYPE_USB2>;
+ vusb33-supply = <®_3p3v>;
+ vbus-supply = <®_5v>;
+ mediatek,u3p-dis-msk = <0x01>;
+ status = "okay";
+};
#include <dt-bindings/clock/mediatek,mt7981-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/mt7986-resets.h>
/ {
#size-cells = <2>;
ranges;
+ wo_boot: wo-boot@15194000 {
+ reg = <0 0x15194000 0 0x1000>;
+ no-map;
+ };
+
+ wo_ilm0: wo-ilm@151e0000 {
+ reg = <0 0x151e0000 0 0x8000>;
+ no-map;
+ };
+
+ wo_dlm0: wo-dlm@151e8000 {
+ reg = <0 0x151e8000 0 0x2000>;
+ no-map;
+ };
+
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
secmon_reserved: secmon@43000000 {
reg = <0 0x43000000 0 0x30000>;
no-map;
};
+
+ wmcpu_emi: wmcpu-reserved@47c80000 {
+ reg = <0 0x47c80000 0 0x100000>;
+ no-map;
+ };
+
+ wo_emi0: wo-emi@47d80000 {
+ reg = <0 0x47d80000 0 0x40000>;
+ no-map;
+ };
+
+ wo_data: wo-data@47dc0000 {
+ reg = <0 0x47dc0000 0 0x240000>;
+ no-map;
+ };
};
soc {
#pwm-cells = <2>;
};
+ sgmiisys0: syscon@10060000 {
+ compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
+ reg = <0 0x10060000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ sgmiisys1: syscon@10070000 {
+ compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
+ reg = <0 0x10070000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x100>;
status = "disabled";
};
+ xhci: usb@11200000 {
+ compatible = "mediatek,mt7986-xhci", "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x2e00>, <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
+ <&infracfg CLK_INFRA_IUSB_CK>,
+ <&infracfg CLK_INFRA_IUSB_133_CK>,
+ <&infracfg CLK_INFRA_IUSB_66M_CK>,
+ <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
+ status = "disabled";
+ };
+
+ pcie: pcie@11280000 {
+ compatible = "mediatek,mt7981-pcie",
+ "mediatek,mt8192-pcie";
+ reg = <0 0x11280000 0 0x4000>;
+ reg-names = "pcie-mac";
+ ranges = <0x82000000 0 0x20000000
+ 0x0 0x20000000 0 0x10000000>;
+ bus-range = <0x00 0xff>;
+ clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
+ <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
+ <&infracfg CLK_INFRA_IPCIER_CK>,
+ <&infracfg CLK_INFRA_IPCIEB_CK>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
+ device_type = "pci";
+ phys = <&u3port0 PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ #address-cells = <3>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ pcie_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
pio: pinctrl@11d00000 {
compatible = "mediatek,mt7981-pinctrl";
reg = <0 0x11d00000 0 0x1000>,
};
};
+ topmisc: topmisc@11d10000 {
+ compatible = "mediatek,mt7981-topmisc", "syscon";
+ reg = <0 0x11d10000 0 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ usb_phy: t-phy@11e10000 {
+ compatible = "mediatek,mt7981-tphy",
+ "mediatek,generic-tphy-v2";
+ ranges = <0 0 0x11e10000 0x1700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ u2port0: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+
+ u3port0: usb-phy@700 {
+ reg = <0x700 0x900>;
+ clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ mediatek,syscon-type = <&topmisc 0x218 0>;
+ };
+ };
+
efuse@11f20000 {
compatible = "mediatek,mt7981-efuse", "mediatek,efuse";
reg = <0 0x11f20000 0 0x1000>;
thermal_calibration: thermal-calib@274 {
reg = <0x274 0xc>;
};
+
+ phy_calibration: phy-calib@8dc {
+ reg = <0x8dc 0x10>;
+ };
};
- clock-controller@15000000 {
+ ethsys: clock-controller@15000000 {
compatible = "mediatek,mt7981-ethsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
- wifi@18000000 {
+ wed: wed@15010000 {
+ compatible = "mediatek,mt7981-wed",
+ "syscon";
+ reg = <0 0x15010000 0 0x1000>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
+ <&wo_data>, <&wo_boot>;
+ memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
+ "wo-data", "wo-boot";
+ mediatek,wo-ccif = <&wo_ccif0>;
+ };
+
+ eth: ethernet@15100000 {
+ compatible = "mediatek,mt7981-eth";
+ reg = <0 0x15100000 0 0x40000>;
+ assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
+ <&topckgen CLK_TOP_SGM_325M_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
+ <&topckgen CLK_TOP_CB_SGM_325M>;
+ clocks = <ðsys CLK_ETH_FE_EN>,
+ <ðsys CLK_ETH_GP2_EN>,
+ <ðsys CLK_ETH_GP1_EN>,
+ <ðsys CLK_ETH_WOCPU0_EN>,
+ <&topckgen CLK_TOP_SGM_REG>,
+ <&sgmiisys0 CLK_SGM0_TX_EN>,
+ <&sgmiisys0 CLK_SGM0_RX_EN>,
+ <&sgmiisys0 CLK_SGM0_CK0_EN>,
+ <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
+ <&sgmiisys1 CLK_SGM1_TX_EN>,
+ <&sgmiisys1 CLK_SGM1_RX_EN>,
+ <&sgmiisys1 CLK_SGM1_CK1_EN>,
+ <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
+ <&topckgen CLK_TOP_NETSYS_SEL>,
+ <&topckgen CLK_TOP_NETSYS_500M_SEL>;
+ clock-names = "fe", "gp2", "gp1", "wocpu0",
+ "sgmii_ck",
+ "sgmii_tx250m", "sgmii_rx250m",
+ "sgmii_cdr_ref", "sgmii_cdr_fb",
+ "sgmii2_tx250m", "sgmii2_rx250m",
+ "sgmii2_cdr_ref", "sgmii2_cdr_fb",
+ "netsys0", "netsys1";
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0",
+ "pdma1", "pdma2", "pdma3";
+ sram = <ð_sram>;
+ mediatek,ethsys = <ðsys>;
+ mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
+ mediatek,infracfg = <&topmisc>;
+ mediatek,wed = <&wed>;
+ status = "disabled";
+
+ mdio_bus: mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ int_gbe_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ phy-mode = "gmii";
+ phy-is-integrated;
+ nvmem-cells = <&phy_calibration>;
+ nvmem-cell-names = "phy-cal-data";
+ };
+ };
+ };
+
+ eth_sram: sram@15140000 {
+ compatible = "mmio-sram";
+ reg = <0 0x15140000 0 0x40000>;
+ ranges = <0 0x15140000 0 0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ wo_ccif0: syscon@151a5000 {
+ compatible = "mediatek,mt7986-wo-ccif", "syscon";
+ reg = <0 0x151a5000 0 0x1000>;
+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ wifi: wifi@18000000 {
compatible = "mediatek,mt7981-wmac";
reg = <0 0x18000000 0 0x1000000>,
<0 0x10003000 0 0x1000>,
clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
<&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
clock-names = "mcu", "ap2conn";
+ memory-region = <&wmcpu_emi>;
resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
reset-names = "consys";
+ status = "disabled";
};
};
};
crypto: crypto@10320000 {
- compatible = "inside-secure,safexcel-eip97";
+ compatible = "mediatek,mt7986-crypto", "inside-secure,safexcel-eip97ies";
reg = <0 0x10320000 0 0x40000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
tphy: t-phy@11c50000 {
compatible = "mediatek,mt7986-tphy",
"mediatek,generic-tphy-v2";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11c50000 0x1000>;
status = "disabled";
- tphyu2port0: usb-phy@11c50000 {
- reg = <0 0x11c50000 0 0x700>;
+ tphyu2port0: usb-phy@0 {
+ reg = <0 0x700>;
clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
clock-names = "ref";
#phy-cells = <1>;
};
- tphyu3port0: usb-phy@11c50700 {
- reg = <0 0x11c50700 0 0x900>;
+ tphyu3port0: usb-phy@700 {
+ reg = <0x700 0x900>;
clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
clock-names = "ref";
#phy-cells = <1>;
xsphy: xs-phy@11e10000 {
compatible = "mediatek,mt7988-xsphy",
"mediatek,xsphy";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11e10000 0x3900>;
status = "disabled";
- xphyu2port0: usb-phy@11e10000 {
- reg = <0 0x11e10000 0 0x400>;
+ xphyu2port0: usb-phy@0 {
+ reg = <0 0x400>;
clocks = <&infracfg CLK_INFRA_USB_UTMI>;
clock-names = "ref";
#phy-cells = <1>;
};
- xphyu3port0: usb-phy@11e13000 {
- reg = <0 0x11e13400 0 0x500>;
+ xphyu3port0: usb-phy@3400 {
+ reg = <0x3400 0x500>;
clocks = <&infracfg CLK_INFRA_USB_PIPE>;
clock-names = "ref";
#phy-cells = <1>;
#include "mt8173-elm.dtsi"
+&hdmi_mux_pins {
+ pins-mux {
+ pinmux = <MT8173_PIN_98_URTS1__FUNC_GPIO98>;
+ bias-pull-up;
+ output-high;
+ };
+};
+
&i2c0 {
clock-frequency = <200000>;
};
};
};
-&mmc1 {
- wp-gpios = <&pio 42 GPIO_ACTIVE_HIGH>;
-};
-
-&pio {
- hdmi_mux_pins: hdmi_mux_pins {
- pins2 {
- pinmux = <MT8173_PIN_98_URTS1__FUNC_GPIO98>;
- bias-pull-up;
- output-high;
- };
+&mmc1_pins_default {
+ pins-wp {
+ pinmux = <MT8173_PIN_42_DSI_TE__FUNC_GPIO42>;
+ input-enable;
+ bias-pull-up;
};
+};
- mmc1_pins_default: mmc1default {
- pins_wp {
- pinmux = <MT8173_PIN_42_DSI_TE__FUNC_GPIO42>;
- input-enable;
- bias-pull-up;
- };
- };
+&mmc1 {
+ wp-gpios = <&pio 42 GPIO_ACTIVE_HIGH>;
};
&touchscreen {
&dsi0 {
status = "okay";
- ports {
- port {
- dsi0_out: endpoint {
- remote-endpoint = <&ps8640_in>;
- };
+ port {
+ dsi0_out: endpoint {
+ remote-endpoint = <&ps8640_in>;
};
};
};
#address-cells = <1>;
#size-cells = <0>;
- btmrvl: btmrvl@2 {
+ mwifiex: wifi@1 {
+ compatible = "marvell,sd8897";
+ reg = <1>;
+ interrupts-extended = <&pio 38 IRQ_TYPE_LEVEL_LOW>;
+ marvell,wakeup-pin = <3>;
+ };
+
+ btmrvl: bluetooth@2 {
compatible = "marvell,sd8897-bt";
reg = <2>;
interrupts-extended = <&pio 119 IRQ_TYPE_LEVEL_LOW>;
marvell,wakeup-pin = /bits/ 16 <0x0d>;
marvell,wakeup-gap-ms = /bits/ 16 <0x64>;
};
-
- mwifiex: mwifiex@1 {
- compatible = "marvell,sd8897";
- reg = <1>;
- interrupts-extended = <&pio 38 IRQ_TYPE_LEVEL_LOW>;
- marvell,wakeup-pin = <3>;
- };
};
&nor_flash {
"SOC_I2C4_1V8_SDA_400K",
"SOC_I2C4_1V8_SCL_400K";
- aud_i2s2: aud_i2s2 {
- pins1 {
+ aud_i2s2: aud-i2s2-pins {
+ pins-bus {
pinmux = <MT8173_PIN_128_I2S0_LRCK__FUNC_I2S1_WS>,
<MT8173_PIN_129_I2S0_BCK__FUNC_I2S1_BCK>,
<MT8173_PIN_130_I2S0_MCK__FUNC_I2S1_MCK>,
};
};
- bl_fixed_pins: bl_fixed_pins {
- pins1 {
+ bl_fixed_pins: backlight-pins {
+ pins-blon {
pinmux = <MT8173_PIN_32_UTXD2__FUNC_GPIO32>;
output-low;
};
};
- bt_wake_pins: bt_wake_pins {
- pins1 {
+ bt_wake_pins: bt-pins {
+ pins-wake {
pinmux = <MT8173_PIN_119_KPROW0__FUNC_GPIO119>;
bias-pull-up;
};
};
- disp_pwm0_pins: disp_pwm0_pins {
+ disp_pwm0_pins: disp-pwm0-pins {
pins1 {
pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>;
output-low;
};
};
- gpio_keys_pins: gpio_keys_pins {
- volume_pins {
+ gpio_keys_pins: gpio-keys-pins {
+ pins-volumeupdn {
pinmux = <MT8173_PIN_123_KPCOL1__FUNC_GPIO123>,
<MT8173_PIN_124_KPCOL2__FUNC_GPIO124>;
bias-pull-up;
};
- tablet_mode_pins {
+ pins-tabletmode {
pinmux = <MT8173_PIN_121_KPROW2__FUNC_GPIO121>;
bias-pull-up;
};
};
- hdmi_mux_pins: hdmi_mux_pins {
- pins1 {
+ hdmi_mux_pins: hdmi-pins {
+ pins-mux {
pinmux = <MT8173_PIN_36_DAISYNC__FUNC_GPIO36>;
};
};
- i2c1_pins_a: i2c1 {
- da9211_pins {
+ i2c1_pins_a: i2c1-pins {
+ pins-da9211 {
pinmux = <MT8173_PIN_15_EINT15__FUNC_GPIO15>;
bias-pull-up;
};
};
- mmc0_pins_default: mmc0default {
- pins_cmd_dat {
+ mmc0_pins_default: mmc0-default-pins {
+ pins-cmd-dat {
pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
<MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
<MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
bias-pull-up;
};
- pins_clk {
+ pins-clk {
pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
bias-pull-down;
};
- pins_rst {
+ pins-rst {
pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
bias-pull-up;
};
};
- mmc1_pins_default: mmc1default {
- pins_cmd_dat {
+ mmc1_pins_default: mmc1-default-pins {
+ pins-cmd-dat {
pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
<MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
<MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
<MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
<MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
input-enable;
- drive-strength = <MTK_DRIVE_4mA>;
+ drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
- pins_clk {
+ pins-clk {
pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
bias-pull-down;
- drive-strength = <MTK_DRIVE_4mA>;
+ drive-strength = <4>;
};
- pins_insert {
+ pins-insert {
pinmux = <MT8173_PIN_1_EINT1__FUNC_GPIO1>;
bias-pull-up;
};
};
- mmc3_pins_default: mmc3default {
- pins_dat {
+ mmc3_pins_default: mmc3-default-pins {
+ pins-dat {
pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>,
<MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>,
<MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>,
<MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>;
input-enable;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
- pins_cmd {
+ pins-cmd {
pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>;
input-enable;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
- pins_clk {
+ pins-clk {
pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>;
bias-pull-down;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
};
};
- mmc0_pins_uhs: mmc0 {
- pins_cmd_dat {
+ mmc0_pins_uhs: mmc0-uhs-pins {
+ pins-cmd-dat {
pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
<MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
<MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
<MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
<MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
input-enable;
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
- pins_clk {
+ pins-clk {
pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
};
- pins_ds {
+ pins-ds {
pinmux = <MT8173_PIN_67_MSDC0_DSL__FUNC_MSDC0_DSL>;
drive-strength = <MTK_DRIVE_10mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
};
- pins_rst {
+ pins-rst {
pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
bias-pull-up;
};
};
- mmc1_pins_uhs: mmc1 {
- pins_cmd_dat {
+ mmc1_pins_uhs: mmc1-pins {
+ pins-cmd-dat {
pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
<MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
<MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
<MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
<MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
input-enable;
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
- pins_clk {
+ pins-clk {
pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
};
- mmc3_pins_uhs: mmc3 {
- pins_dat {
+ mmc3_pins_uhs: mmc3-pins {
+ pins-dat {
pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>,
<MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>,
<MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>,
<MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>;
input-enable;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
- pins_cmd {
+ pins-cmd {
pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>;
input-enable;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
- pins_clk {
+ pins-clk {
pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
};
- nor_gpio1_pins: nor {
+ nor_gpio1_pins: nor-pins {
pins1 {
pinmux = <MT8173_PIN_6_EINT6__FUNC_SFCS0>,
<MT8173_PIN_7_EINT7__FUNC_SFHOLD>,
<MT8173_PIN_8_EINT8__FUNC_SFIN>;
input-enable;
- drive-strength = <MTK_DRIVE_4mA>;
+ drive-strength = <4>;
bias-pull-up;
};
pins2 {
pinmux = <MT8173_PIN_5_EINT5__FUNC_SFOUT>;
- drive-strength = <MTK_DRIVE_4mA>;
+ drive-strength = <4>;
bias-pull-up;
};
- pins_clk {
+ pins-clk {
pinmux = <MT8173_PIN_9_EINT9__FUNC_SFCK>;
input-enable;
- drive-strength = <MTK_DRIVE_4mA>;
+ drive-strength = <4>;
bias-pull-up;
};
};
- panel_backlight_en_pins: panel_backlight_en_pins {
+ panel_backlight_en_pins: panel-backlight-en-pins {
pins1 {
pinmux = <MT8173_PIN_95_PCM_TX__FUNC_GPIO95>;
};
};
- panel_fixed_pins: panel_fixed_pins {
+ panel_fixed_pins: panel-fixed-pins {
pins1 {
pinmux = <MT8173_PIN_41_CMMCLK__FUNC_GPIO41>;
};
};
- ps8640_pins: ps8640_pins {
+ ps8640_pins: ps8640-pins {
pins1 {
pinmux = <MT8173_PIN_92_PCM_CLK__FUNC_GPIO92>,
<MT8173_PIN_115_URTS0__FUNC_GPIO115>,
};
};
- ps8640_fixed_pins: ps8640_fixed_pins {
+ ps8640_fixed_pins: ps8640-fixed-pins {
pins1 {
pinmux = <MT8173_PIN_30_URTS2__FUNC_GPIO30>;
};
};
- rt5650_irq: rt5650_irq {
- pins1 {
+ rt5650_irq: rt5650-pins {
+ pins-intn {
pinmux = <MT8173_PIN_3_EINT3__FUNC_GPIO3>;
bias-pull-down;
};
};
- sdio_fixed_3v3_pins: sdio_fixed_3v3_pins {
+ sdio_fixed_3v3_pins: sdio-vreg-3v3-pins {
pins1 {
pinmux = <MT8173_PIN_85_AUD_DAT_MOSI__FUNC_GPIO85>;
output-low;
};
};
- spi_pins_a: spi1 {
+ spi_pins_a: spi1-pins {
pins1 {
pinmux = <MT8173_PIN_0_EINT0__FUNC_GPIO0>;
bias-pull-up;
};
- pins_spi {
+ pins-spi {
pinmux = <MT8173_PIN_102_MSDC2_DAT2__FUNC_SPI_CK_1_>,
<MT8173_PIN_103_MSDC2_DAT3__FUNC_SPI_MI_1_>,
<MT8173_PIN_104_MSDC2_CLK__FUNC_SPI_MO_1_>,
};
};
- trackpad_irq: trackpad_irq {
- pins1 {
+ trackpad_irq: trackpad-pins {
+ pins-intn {
pinmux = <MT8173_PIN_117_URXD3__FUNC_GPIO117>;
input-enable;
bias-pull-up;
};
};
- usb_pins: usb {
+ usb_pins: usb-pins {
pins1 {
pinmux = <MT8173_PIN_101_MSDC2_DAT1__FUNC_GPIO101>;
output-high;
};
};
- wifi_wake_pins: wifi_wake_pins {
- pins1 {
+ wifi_wake_pins: wifi-pins {
+ pins-wake {
pinmux = <MT8173_PIN_38_CONN_RST__FUNC_GPIO38>;
bias-pull-up;
};
status = "okay";
};
-&thermal {
- bank0-supply = <&mt6397_vpca15_reg>;
- bank1-supply = <&da9211_vcpu_reg>;
-};
-
&uart0 {
status = "okay";
};
buck: da9211@68 {
compatible = "dlg,da9211";
reg = <0x68>;
+ interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>;
regulators {
da9211_vcpu_reg: BUCKA {
};
&pio {
- disp_pwm0_pins: disp_pwm0_pins {
+ disp_pwm0_pins: disp-pwm0-pins {
pins1 {
pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>;
output-low;
};
};
- mmc0_pins_default: mmc0default {
- pins_cmd_dat {
+ i2c1_pins_a: i2c1-pins {
+ pins-da9211 {
+ pinmux = <MT8173_PIN_15_EINT15__FUNC_GPIO15>;
+ bias-pull-up;
+ };
+ };
+
+ mmc0_pins_default: mmc0-default-pins {
+ pins-cmd-dat {
pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
<MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
<MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
bias-pull-up;
};
- pins_clk {
+ pins-clk {
pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
bias-pull-down;
};
- pins_rst {
+ pins-rst {
pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
bias-pull-up;
};
};
- mmc1_pins_default: mmc1default {
- pins_cmd_dat {
+ mmc1_pins_default: mmc1-default-pins {
+ pins-cmd-dat {
pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
<MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
<MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
- pins_clk {
+ pins-clk {
pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
bias-pull-down;
drive-strength = <4>;
};
- pins_insert {
+ pins-insert {
pinmux = <MT8173_PIN_132_I2S0_DATA1__FUNC_GPIO132>;
bias-pull-up;
};
};
- mmc0_pins_uhs: mmc0 {
- pins_cmd_dat {
+ mmc0_pins_uhs: mmc0-uhs-pins {
+ pins-cmd-dat {
pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
<MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
<MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
- pins_clk {
+ pins-clk {
pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
drive-strength = <2>;
bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
};
- pins_rst {
+ pins-rst {
pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
bias-pull-up;
};
};
- mmc1_pins_uhs: mmc1 {
- pins_cmd_dat {
+ spi_pins_a: spi0-pins {
+ pins-bus {
+ pinmux = <MT8173_PIN_69_SPI_CK__FUNC_SPI_CK_0_>,
+ <MT8173_PIN_70_SPI_MI__FUNC_SPI_MI_0_>,
+ <MT8173_PIN_71_SPI_MO__FUNC_SPI_MO_0_>,
+ <MT8173_PIN_72_SPI_CS__FUNC_SPI_CS_0_>;
+ };
+ };
+
+ mmc1_pins_uhs: mmc1-uhs-pins {
+ pins-cmd-dat {
pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
<MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
<MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
- pins_clk {
+ pins-clk {
pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
drive-strength = <4>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
};
- usb_id_pins_float: usb_iddig_pull_up {
- pins_iddig {
+ usb_id_pins_float: usb-iddig-pu-pins {
+ pins-iddig-pu {
pinmux = <MT8173_PIN_16_IDDIG__FUNC_IDDIG>;
bias-pull-up;
};
};
- usb_id_pins_ground: usb_iddig_pull_down {
- pins_iddig {
+ usb_id_pins_ground: usb-iddig-pd-pins {
+ pins-iddig-pd {
pinmux = <MT8173_PIN_16_IDDIG__FUNC_IDDIG>;
bias-pull-down;
};
};
};
-&pio {
- spi_pins_a: spi0 {
- pins_spi {
- pinmux = <MT8173_PIN_69_SPI_CK__FUNC_SPI_CK_0_>,
- <MT8173_PIN_70_SPI_MI__FUNC_SPI_MI_0_>,
- <MT8173_PIN_71_SPI_MO__FUNC_SPI_MO_0_>,
- <MT8173_PIN_72_SPI_CS__FUNC_SPI_CS_0_>;
- };
- };
-};
-
&spi {
pinctrl-names = "default";
pinctrl-0 = <&spi_pins_a>;
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
- hdmi_pin: xxx {
+ hdmi_pin: hdmi-hotplug-pins {
/*hdmi htplg pin*/
- pins1 {
+ pins-htplg {
pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
input-enable;
bias-pull-down;
};
};
- i2c0_pins_a: i2c0 {
- pins1 {
+ i2c0_pins_a: i2c0-pins {
+ pins-bus {
pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
<MT8173_PIN_46_SCL0__FUNC_SCL0>;
bias-disable;
};
};
- i2c1_pins_a: i2c1 {
- pins1 {
+ i2c1_pins_a: i2c1-pins {
+ pins-bus {
pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
<MT8173_PIN_126_SCL1__FUNC_SCL1>;
bias-disable;
};
};
- i2c2_pins_a: i2c2 {
- pins1 {
+ i2c2_pins_a: i2c2-pins {
+ pins-bus {
pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
<MT8173_PIN_44_SCL2__FUNC_SCL2>;
bias-disable;
};
};
- i2c3_pins_a: i2c3 {
- pins1 {
+ i2c3_pins_a: i2c3-pins {
+ pins-bus {
pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
<MT8173_PIN_107_SCL3__FUNC_SCL3>;
bias-disable;
};
};
- i2c4_pins_a: i2c4 {
- pins1 {
+ i2c4_pins_a: i2c4-pins {
+ pins-bus {
pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
<MT8173_PIN_134_SCL4__FUNC_SCL4>;
bias-disable;
};
};
- i2c6_pins_a: i2c6 {
- pins1 {
+ i2c6_pins_a: i2c6-pins {
+ pins-bus {
pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
<MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
bias-disable;
};
};
- thermal-sensor {
+ thermistor {
compatible = "murata,ncp03wf104";
pullup-uv = <1800000>;
pullup-ohm = <390000>;
};
&pio {
- i2c_pins_0: i2c0 {
+ i2c_pins_0: i2c0-pins {
pins_i2c {
pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
<PINMUX_GPIO83__FUNC_SCL0>;
};
};
- i2c_pins_1: i2c1 {
+ i2c_pins_1: i2c1-pins {
pins_i2c {
pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
<PINMUX_GPIO84__FUNC_SCL1>;
};
};
- i2c_pins_2: i2c2 {
+ i2c_pins_2: i2c2-pins {
pins_i2c {
pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
<PINMUX_GPIO104__FUNC_SDA2>;
};
};
- i2c_pins_3: i2c3 {
+ i2c_pins_3: i2c3-pins {
pins_i2c {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
};
};
- i2c_pins_4: i2c4 {
+ i2c_pins_4: i2c4-pins {
pins_i2c {
pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
<PINMUX_GPIO106__FUNC_SDA4>;
};
};
- i2c_pins_5: i2c5 {
+ i2c_pins_5: i2c5-pins {
pins_i2c {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
};
};
- spi_pins_0: spi0 {
+ spi_pins_0: spi0-pins {
pins_spi {
pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
<PINMUX_GPIO86__FUNC_SPI0_CSB>,
};
};
- mmc0_pins_default: mmc0default {
+ mmc0_pins_default: mmc0-default-pins {
pins_cmd_dat {
pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
};
};
- mmc0_pins_uhs: mmc0 {
+ mmc0_pins_uhs: mmc0-uhs-pins {
pins_cmd_dat {
pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
};
};
- mmc1_pins_default: mmc1default {
+ mmc1_pins_default: mmc1-default-pins {
pins_cmd_dat {
pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
<PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
};
};
- mmc1_pins_uhs: mmc1 {
+ mmc1_pins_uhs: mmc1-pins {
pins_cmd_dat {
pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
<PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
};
};
- spi_pins_1: spi1 {
+ spi_pins_1: spi1-pins {
pins_spi {
pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
<PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
};
};
- spi_pins_2: spi2 {
+ spi_pins_2: spi2-pins {
pins_spi {
pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
<PINMUX_GPIO1__FUNC_SPI2_MO>,
};
};
- spi_pins_3: spi3 {
+ spi_pins_3: spi3-pins {
pins_spi {
pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
<PINMUX_GPIO22__FUNC_SPI3_CSB>,
};
};
- spi_pins_4: spi4 {
+ spi_pins_4: spi4-pins {
pins_spi {
pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
<PINMUX_GPIO18__FUNC_SPI4_CSB>,
};
};
- spi_pins_5: spi5 {
+ spi_pins_5: spi5-pins {
pins_spi {
pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
<PINMUX_GPIO14__FUNC_SPI5_CSB>,
};
};
- pwm_pins_1: pwm1 {
+ pwm_pins_1: pwm1-pins {
pins_pwm {
pinmux = <PINMUX_GPIO90__FUNC_PWM_A>;
};
&pio {
bt_pins_wakeup: bt-pins-wakeup {
- piins-bt-wakeup {
+ pins-bt-wakeup {
pinmux = <PINMUX_GPIO42__FUNC_GPIO42>;
input-enable;
};
clock-output-names = "clk32k";
};
- it6505_pp18_reg: regulator0 {
+ pp1800_it6505: regulator0 {
compatible = "regulator-fixed";
- regulator-name = "it6505_pp18";
- gpio = <&pio 178 0>;
+ regulator-name = "pp1800_it6505";
+ gpios = <&pio 178 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&pp1800_alw>;
};
};
&pio {
- i2c_pins_0: i2c0 {
+ i2c_pins_0: i2c0-pins {
pins_i2c {
pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
<PINMUX_GPIO83__FUNC_SCL0>;
};
};
- i2c_pins_1: i2c1 {
+ i2c_pins_1: i2c1-pins {
pins_i2c {
pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
<PINMUX_GPIO84__FUNC_SCL1>;
};
};
- i2c_pins_2: i2c2 {
+ i2c_pins_2: i2c2-pins {
pins_i2c {
pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
<PINMUX_GPIO104__FUNC_SDA2>;
};
};
- i2c_pins_3: i2c3 {
+ i2c_pins_3: i2c3-pins {
pins_i2c {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
};
};
- i2c_pins_4: i2c4 {
+ i2c_pins_4: i2c4-pins {
pins_i2c {
pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
<PINMUX_GPIO106__FUNC_SDA4>;
};
};
- i2c_pins_5: i2c5 {
+ i2c_pins_5: i2c5-pins {
pins_i2c {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
};
};
- i2c6_pins: i2c6 {
+ i2c6_pins: i2c6-pins {
pins_cmd_dat {
pinmux = <PINMUX_GPIO113__FUNC_SCL6>,
<PINMUX_GPIO114__FUNC_SDA6>;
};
};
- keyboard_pins: keyboard {
+ keyboard_pins: keyboard-pins {
pins_keyboard {
pinmux = <PINMUX_GPIO91__FUNC_KPROW1>,
<PINMUX_GPIO92__FUNC_KPROW0>,
#size-cells = <0>;
port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0>;
- ovl_2l1_in: endpoint {
+
+ ovl_2l1_in: endpoint@1 {
+ reg = <1>;
remote-endpoint = <&mmsys_ep_ext>;
};
};
port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <1>;
- ovl_2l1_out: endpoint {
+
+ ovl_2l1_out: endpoint@1 {
+ reg = <1>;
remote-endpoint = <&rdma1_in>;
};
};
#size-cells = <0>;
port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0>;
- rdma1_in: endpoint {
+
+ rdma1_in: endpoint@1 {
+ reg = <1>;
remote-endpoint = <&ovl_2l1_out>;
};
};
port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <1>;
- rdma1_out: endpoint {
+
+ rdma1_out: endpoint@1 {
+ reg = <1>;
remote-endpoint = <&dpi_in>;
};
};
#size-cells = <0>;
port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0>;
- dpi_in: endpoint {
+
+ dpi_in: endpoint@1 {
+ reg = <1>;
remote-endpoint = <&rdma1_out>;
};
};
port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <1>;
- dpi_out: endpoint { };
+
+ dpi_out: endpoint@1 {
+ reg = <1>;
+ };
};
};
};
device_type = "memory";
reg = <0 0x40000000 0 0x80000000>;
};
+
+ vproc: regulator-vproc12 {
+ compatible = "regulator-fixed";
+ regulator-name = "vproc12";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+};
+
+&cci {
+ proc-supply = <&vproc>;
};
&i2c0 {
&scp_c0 {
pinctrl-names = "default";
pinctrl-0 = <&scp_pins>;
- firmware-name = "mediatek/mt8188/scp.img";
memory-region = <&scp_mem_reserved>;
status = "okay";
};
aliases {
dp-intf0 = &dp_intf0;
dp-intf1 = &dp_intf1;
+ dpi1 = &dpi1;
dsc0 = &dsc0;
ethdr0 = ðdr0;
gce0 = &gce0;
compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
reg = <0 0x11230000 0 0x10000>,
<0 0x11f50000 0 0x1000>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupts-extended = <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MSDC50_0>,
<&infracfg_ao CLK_INFRA_AO_MSDC0>,
<&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>,
compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
reg = <0 0x11240000 0 0x1000>,
<0 0x11eb0000 0 0x1000>;
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupts-extended = <&gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MSDC30_1>,
<&infracfg_ao CLK_INFRA_AO_MSDC1>,
<&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
reg = <0 0x11250000 0 0x1000>,
<0 0x11e60000 0 0x1000>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupts-extended = <&gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MSDC30_2>,
<&infracfg_ao CLK_INFRA_AO_MSDC2>,
<&infracfg_ao CLK_INFRA_AO_MSDC30_2>;
};
};
+ hdmi_phy: hdmi-phy@11d5f000 {
+ compatible = "mediatek,mt8188-hdmi-phy", "mediatek,mt8195-hdmi-phy";
+ reg = <0 0x11d5f000 0 0x100>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_HDMI_26M>;
+ clock-names = "pll_ref";
+ clock-output-names = "hdmi_txpll";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ mediatek,ibias = <0xa>;
+ mediatek,ibias_up = <0x1c>;
+ status = "disabled";
+ };
+
mipi_tx_config0: dsi-phy@11c80000 {
compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx";
reg = <0 0x11c80000 0 0x1000>;
mediatek,merge-fifo-en;
};
+ dpi1: dpi@1c112000 {
+ compatible = "mediatek,mt8188-dpi", "mediatek,mt8195-dpi";
+ reg = <0 0x1c112000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DPI1>,
+ <&vdosys1 CLK_VDO1_DPI1_MM>,
+ <&vdosys1 CLK_VDO1_DPI1_HDMI>;
+ clock-names = "pixel", "engine", "pll";
+ interrupts = <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ resets = <&vdosys1 MT8188_VDO1_RST_DPI1_MM_CK>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpi1_in: endpoint { };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpi1_out: endpoint { };
+ };
+ };
+ };
+
dp_intf1: dp-intf@1c113000 {
compatible = "mediatek,mt8188-dp-intf";
reg = <0 0x1c113000 0 0x1000>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x4000 0x1000>;
};
+ hdmi: hdmi@1c300000 {
+ compatible = "mediatek,mt8188-hdmi-tx";
+ #sound-dai-cells = <1>;
+ reg = <0 0x1c300000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_HDMI_APB>,
+ <&topckgen CLK_TOP_HDCP>,
+ <&topckgen CLK_TOP_HDCP_24M>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>;
+ clock-names = "bus", "hdcp", "hdcp24m", "hdmi-split";
+ assigned-clocks = <&topckgen CLK_TOP_HDCP>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4_D8>;
+ interrupts = <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_HDMI_TX>;
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi";
+ status = "disabled";
+
+ hdmi_ddc: i2c {
+ compatible = "mediatek,mt8188-hdmi-ddc",
+ "mediatek,mt8195-hdmi-ddc";
+ clocks = <&clk26m>;
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ hdmi0_in: endpoint { };
+ };
+
+ port@1 {
+ reg = <1>;
+ hdmi0_out: endpoint { };
+ };
+ };
+ };
+
+
edp_tx: edp-tx@1c500000 {
compatible = "mediatek,mt8188-edp-tx";
reg = <0 0x1c500000 0 0x8000>;
status = "okay";
clock-frequency = <400000>;
- clock-stretch-ns = <12600>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
reg = <0 0x11210000 0 0x2000>;
#clock-cells = <1>;
- afe: mt8192-afe-pcm {
+ afe: audio-controller {
compatible = "mediatek,mt8192-audio";
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
resets = <&watchdog 17>;
aliases {
dp-intf0 = &dp_intf0;
dp-intf1 = &dp_intf1;
+ dpi1 = &dpi1;
gce0 = &gce0;
gce1 = &gce1;
+ hdmi0 = &hdmi;
ethdr0 = ðdr0;
mutex0 = &mutex;
mutex1 = &mutex1;
#clock-cells = <1>;
};
+ hdmi_phy: hdmi-phy@11d5f000 {
+ compatible = "mediatek,mt8195-hdmi-phy";
+ reg = <0 0x11d5f000 0 0x100>;
+ clocks = <&topckgen CLK_TOP_HDMI_XTAL>,
+ <&infracfg_ao CLK_INFRA_AO_HDMI_26M>,
+ <&apmixedsys CLK_APMIXED_HDMIPLL1>,
+ <&apmixedsys CLK_APMIXED_HDMIPLL2>;
+ clock-names = "pll_ref", "26m", "pll1", "pll2";
+ clock-output-names = "hdmi_txpll";
+
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ mediatek,ibias = <0xa>;
+ mediatek,ibias_up = <0x1c>;
+ status = "disabled";
+ };
+
i2c0: i2c@11e00000 {
compatible = "mediatek,mt8195-i2c",
"mediatek,mt8192-i2c";
resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
};
+ dpi1: dpi@1c112000 {
+ compatible = "mediatek,mt8195-dpi";
+ reg = <0 0x1c112000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DPI1>,
+ <&vdosys1 CLK_VDO1_DPI1_MM>,
+ <&vdosys1 CLK_VDO1_DPI1_HDMI>;
+ clock-names = "pixel", "engine", "pll";
+ interrupts = <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_DPI1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpi1_in: endpoint { };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpi1_out: endpoint { };
+ };
+ };
+ };
+
dp_intf1: dp-intf@1c113000 {
compatible = "mediatek,mt8195-dp-intf";
reg = <0 0x1c113000 0 0x1000>;
"gfx_fe1_async", "vdo_be_async";
};
+ hdmi: hdmi-tx@1c300000 {
+ compatible = "mediatek,mt8195-hdmi-tx";
+ #sound-dai-cells = <1>;
+ reg = <0 0x1c300000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_HDMI_APB>,
+ <&topckgen CLK_TOP_HDCP>,
+ <&topckgen CLK_TOP_HDCP_24M>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>;
+ clock-names = "bus", "hdcp", "hdcp24m", "hdmi-split";
+ assigned-clocks = <&topckgen CLK_TOP_HDCP>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4_D8>;
+ interrupts = <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>;
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi";
+ status = "disabled";
+
+ hdmitx_ddc: i2c {
+ compatible = "mediatek,mt8195-hdmi-ddc";
+ clocks = <&clk26m>;
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ hdmi0_in: endpoint { };
+ };
+
+ port@1 {
+ reg = <1>;
+ hdmi0_out: endpoint { };
+ };
+ };
+ };
+
edp_tx: edp-tx@1c500000 {
compatible = "mediatek,mt8195-edp-tx";
reg = <0 0x1c500000 0 0x8000>;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 Ezurio LLC
+ * Author: Gary Bisson <bisson.gary@gmail.com>
+ */
+/dts-v1/;
+#include "mt8370.dtsi"
+#include "mt8390-tungsten-smarc.dtsi"
+
+/ {
+ model = "Ezurio Tungsten510 SMARC (MT8370)";
+ compatible = "ezurio,mt8370-tungsten-smarc", "mediatek,mt8370",
+ "mediatek,mt8188";
+};
wakeup-delay-ms = <30>;
};
+ connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+ ddc-i2c-bus = <&hdmi_ddc>;
+ hdmi-pwr-supply = <&hdmi_phy>;
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi0_out>;
+ };
+ };
+ };
+
firmware {
optee {
compatible = "linaro,optee-tz";
remote-endpoint = <&dsi0_in>;
};
+&dpi1 {
+ status = "okay";
+};
+
+&dpi1_in {
+ remote-endpoint = <&merge5_out>;
+};
+
+&dpi1_out {
+ remote-endpoint = <&hdmi0_in>;
+};
+
&gamma0_out {
remote-endpoint = <&postmask0_in>;
};
status = "okay";
};
+ðdr0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ ethdr0_in: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vdosys1_ep_ext>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ ethdr0_out: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&merge5_in>;
+ };
+ };
+ };
+};
+
+&hdmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pins>;
+ status = "okay";
+};
+
+&hdmi0_in {
+ remote-endpoint = <&dpi1_out>;
+};
+
+&hdmi0_out {
+ remote-endpoint = <&hdmi_connector_in>;
+};
+
+&hdmi_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_vreg_pins>;
+ status = "okay";
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
};
+&merge5 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ merge5_in: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <ðdr0_out>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ merge5_out: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dpi1_in>;
+ };
+ };
+ };
+};
+
&mfg0 {
domain-supply = <&mt6359_vproc2_buck_reg>;
};
};
};
+ hdmi_vreg_pins: hdmi-vreg-pins {
+ pins-pwr {
+ pinmux = <PINMUX_GPIO50__FUNC_O_HDMITX20_PWR5V>;
+ bias-disable;
+ };
+ };
+
+ hdmi_pins: hdmi-pins {
+ pins-hotplug {
+ pinmux = <PINMUX_GPIO51__FUNC_I0_HDMITX20_HTPLG>;
+ bias-pull-down;
+ };
+
+ pins-cec {
+ pinmux = <PINMUX_GPIO52__FUNC_B1_HDMITX20_CEC>;
+ bias-disable;
+ };
+
+ pins-ddc {
+ pinmux = <PINMUX_GPIO53__FUNC_B1_HDMITX20_SCL>,
+ <PINMUX_GPIO54__FUNC_B1_HDMITX20_SDA>;
+ drive-strength = <10>;
+ };
+ };
+
i2c0_pins: i2c0-pins {
pins {
pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>,
sound-dai = <&dmic_codec>;
};
};
+
+ dai-link-2 {
+ link-name = "ETDM3_OUT_BE";
+
+ codec {
+ sound-dai = <&hdmi 0>;
+ };
+ };
+
};
&spi2 {
};
};
+&vdosys1 {
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdosys1_ep_ext: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <ðdr0_in>;
+ };
+ };
+};
+
&xhci0 {
status = "okay";
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 Ezurio LLC
+ * Author: Gary Bisson <bisson.gary@gmail.com>
+ */
+/dts-v1/;
+#include "mt8188.dtsi"
+#include "mt8390-tungsten-smarc.dtsi"
+
+/ {
+ model = "Ezurio Tungsten700 SMARC (MT8390)";
+ compatible = "ezurio,mt8390-tungsten-smarc", "mediatek,mt8390",
+ "mediatek,mt8188";
+};
+
+&cpu4 {
+ cpu-supply = <&mt6359_vcore_buck_reg>;
+};
+
+&cpu5 {
+ cpu-supply = <&mt6359_vcore_buck_reg>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 Ezurio LLC
+ * Author: Gary Bisson <bisson.gary@gmail.com>
+ */
+
+#include "mt6359.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/net/microchip-lan78xx.h>
+#include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/usb/pd.h>
+
+/ {
+ aliases {
+ dsi0 = &disp_dsi0;
+ ethernet0 = ð
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
+ mmc2 = &mmc2;
+ rtc0 = &rv3028;
+ rtc1 = &mt6359rtc;
+ serial0 = &uart0;
+ };
+
+ backlight_lcd0: backlight-lcd0 {
+ compatible = "pwm-backlight";
+ brightness-levels = <0 1023>;
+ default-brightness-level = <768>;
+ num-interpolated-steps = <1023>;
+ enable-gpios = <&pio 30 GPIO_ACTIVE_HIGH>;
+ pwms = <&disp_pwm0 0 30000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0x1 0x00000000>;
+ };
+
+ panel-dsi0 {
+ compatible = "tianma,tm070jdhg30";
+ backlight = <&backlight_lcd0>;
+ power-supply = <®_5v>;
+
+ port {
+ dsi0_panel_in: endpoint {
+ remote-endpoint = <&sn65dsi84_bridge_out>;
+ };
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /*
+ * 12 MiB reserved for OP-TEE (BL32)
+ * +-----------------------+ 0x43e0_0000
+ * | SHMEM 2MiB |
+ * +-----------------------+ 0x43c0_0000
+ * | | TA_RAM 8MiB |
+ * + TZDRAM +--------------+ 0x4340_0000
+ * | | TEE_RAM 2MiB |
+ * +-----------------------+ 0x4320_0000
+ */
+ optee_reserved: optee@43200000 {
+ no-map;
+ reg = <0 0x43200000 0 0x00c00000>;
+ };
+
+ scp_mem: memory@50000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x50000000 0 0x2900000>;
+ no-map;
+ };
+
+ /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: memory@54600000 {
+ no-map;
+ reg = <0 0x54600000 0x0 0x200000>;
+ };
+
+ apu_mem: memory@55000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x55000000 0 0x1400000>; /* 20 MB */
+ };
+
+ vpu_mem: memory@57000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x57000000 0 0x1400000>; /* 20 MB */
+ };
+
+ adsp_mem: memory@60000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x60000000 0 0xf00000>;
+ no-map;
+ };
+
+ afe_dma_mem: memory@60f00000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x60f00000 0 0x100000>;
+ no-map;
+ };
+
+ adsp_dma_mem: memory@61000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x61000000 0 0x100000>;
+ no-map;
+ };
+ };
+
+ regulator-efuse {
+ compatible = "regulator-output";
+ vout-supply = <&mt6359_vefuse_ldo_reg>;
+ };
+
+ reg_1v8: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "reg_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "reg_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "reg_5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ sdcard_en_3v3: regulator-sdcard-en {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-name = "sdcard_en_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pio 111 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ usb_p0_vbus: regulator-usb-p0-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus_p0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 84 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ usb_p1_vbus: regulator-usb-p1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_hub_pins>;
+ regulator-name = "vbus_p1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&pio 147 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ usb_p2_vbus: regulator-usb-p2-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_eth_pins>;
+ regulator-name = "vbus_p2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&pio 80 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_pwrseq_pins>;
+ post-power-on-delay-ms = <200>;
+ reset-gpios = <&pio 89 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&adsp {
+ memory-region = <&adsp_dma_mem>, <&adsp_mem>;
+ status = "okay";
+};
+
+&afe {
+ memory-region = <&afe_dma_mem>;
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&mt6359_vcore_buck_reg>;
+};
+
+&cpu1 {
+ cpu-supply = <&mt6359_vcore_buck_reg>;
+};
+
+&cpu2 {
+ cpu-supply = <&mt6359_vcore_buck_reg>;
+};
+
+&cpu3 {
+ cpu-supply = <&mt6359_vcore_buck_reg>;
+};
+
+&cpu6 {
+ cpu-supply = <&mt6315_6_vbuck1>;
+};
+
+&cpu7 {
+ cpu-supply = <&mt6315_6_vbuck1>;
+};
+
+&disp_pwm0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&disp_pwm0_pins>;
+ status = "okay";
+};
+
+&disp_dsi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dither0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ remote-endpoint = <&sn65dsi84_bridge_in>;
+ };
+ };
+ };
+};
+
+&dither0_in {
+ remote-endpoint = <&postmask0_out>;
+};
+
+&dither0_out {
+ remote-endpoint = <&dsi0_in>;
+};
+
+ð {
+ phy-mode ="rgmii-id";
+ phy-handle = <ðernet_phy0>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <ð_default_pins>;
+ pinctrl-1 = <ð_sleep_pins>;
+ mediatek,mac-wol;
+ snps,reset-gpio = <&pio 27 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 11000 1000>;
+ status = "okay";
+};
+
+ð_mdio {
+ ethernet_phy0: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x7>;
+ interrupts-extended = <&pio 148 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&gamma0_out {
+ remote-endpoint = <&postmask0_in>;
+};
+
+&gpu {
+ mali-supply = <&mt6359_vproc2_buck_reg>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ i2c-mux@73 {
+ compatible = "nxp,pca9546";
+ reg = <0x73>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_mux_pins>;
+ reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c_mux_gp_0: i2c@0 {
+ reg = <0>;
+ clock-frequency = <100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c_mux_gp_1: i2c@1 {
+ reg = <1>;
+ clock-frequency = <100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c_mux_gp_2: i2c@2 {
+ reg = <2>;
+ clock-frequency = <100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c_mux_gp_3: i2c@3 {
+ reg = <3>;
+ clock-frequency = <100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ i2c-mux@73 {
+ compatible = "nxp,pca9546";
+ reg = <0x73>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_mux_smarc_lcd_pins>;
+ reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c_mux_lcd_0: i2c@0 {
+ reg = <0>;
+ clock-frequency = <100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c_mux_lcd_1: i2c@1 {
+ reg = <1>;
+ clock-frequency = <100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c_mux_lcd_2: i2c@2 {
+ reg = <2>;
+ clock-frequency = <100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c_mux_lcd_3: i2c@3 {
+ reg = <3>;
+ clock-frequency = <100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c_mux_gp_0 {
+ rv3028: rtc@52 {
+ compatible = "microcrystal,rv3028";
+ reg = <0x52>;
+ interrupts-extended = <&pio 42 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rv3028_pins>;
+ #clock-cells = <0>;
+ wakeup-source;
+ };
+};
+
+&i2c_mux_gp_1 {
+ usb-typec@60 {
+ compatible = "ti,hd3ss3220";
+ reg = <0x60>;
+ interrupts-extended = <&pio 45 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hd3ss3220_pins>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ hd3ss3220_in_ep: endpoint {
+ remote-endpoint = <&ss_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ hd3ss3220_out_ep: endpoint {
+ remote-endpoint = <&usb_role_switch>;
+ };
+ };
+ };
+ };
+};
+
+&i2c_mux_gp_2 {
+ codec@1a {
+ compatible = "wlf,wm8962";
+ reg = <0x1a>;
+ clocks = <&topckgen CLK_TOP_I2SO1>;
+ AVDD-supply = <®_1v8>;
+ CPVDD-supply = <®_1v8>;
+ DBVDD-supply = <®_3v3>;
+ DCVDD-supply = <®_1v8>;
+ MICVDD-supply = <®_3v3>;
+ PLLVDD-supply = <®_1v8>;
+ SPKVDD1-supply = <®_5v>;
+ SPKVDD2-supply = <®_5v>;
+ gpio-cfg = <
+ 0x0000 /* n/c */
+ 0x0000 /* gpio2: */
+ 0x0000 /* gpio3: */
+ 0x0000 /* n/c */
+ 0x8081 /* gpio5:HP detect */
+ 0x8095 /* gpio6:Mic detect */
+ >;
+ };
+};
+
+&i2c_mux_lcd_2 {
+ bridge@2c {
+ compatible = "ti,sn65dsi84";
+ reg = <0x2c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dsi0_sn65dsi84_pins>;
+ enable-gpios = <&pio 25 GPIO_ACTIVE_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sn65dsi84_bridge_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ data-lanes = <1 2 3 4>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ sn65dsi84_bridge_out: endpoint {
+ remote-endpoint = <&dsi0_panel_in>;
+ };
+ };
+ };
+ };
+
+ touchscren@5d {
+ compatible = "goodix,gt911";
+ reg = <0x5d>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_dsi0_goodix_pins>;
+ interrupts-extended = <&pio 146 IRQ_TYPE_LEVEL_HIGH>;
+ irq-gpios = <&pio 146 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&mfg0 {
+ domain-supply = <&mt6359_vproc2_buck_reg>;
+};
+
+&mfg1 {
+ domain-supply = <&mt6359_vsram_others_ldo_reg>;
+};
+
+&mmc0 {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ cap-mmc-hw-reset;
+ hs400-ds-delay = <0x1481b>;
+ max-frequency = <200000000>;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ non-removable;
+ no-sd;
+ no-sdio;
+ supports-cqe;
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_default_pins>;
+ pinctrl-1 = <&mmc0_uhs_pins>;
+ vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
+ vqmmc-supply = <&mt6359_vufs_ldo_reg>;
+ status = "okay";
+};
+
+&mmc1 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <200000000>;
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc1_default_pins>;
+ pinctrl-1 = <&mmc1_uhs_pins>;
+ cd-gpios = <&pio 2 GPIO_ACTIVE_LOW>;
+ vqmmc-supply = <&mt6359_vsim1_ldo_reg>;
+ vmmc-supply = <&sdcard_en_3v3>;
+ status = "okay";
+};
+
+&mmc2 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ max-frequency = <200000000>;
+ no-mmc;
+ non-removable;
+ no-sd;
+ sd-uhs-sdr104;
+ wakeup-source;
+ pinctrl-names = "default", "state_uhs", "state_eint";
+ pinctrl-0 = <&mmc2_default_pins>;
+ pinctrl-1 = <&mmc2_uhs_pins>;
+ pinctrl-2 = <&mmc2_eint_pins>;
+ interrupt-names = "msdc", "sdio_wakeup";
+ interrupts-extended = <&gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&pio 172 IRQ_TYPE_LEVEL_LOW>;
+ vmmc-supply = <&mt6359_vcn33_2_bt_ldo_reg>;
+ vqmmc-supply = <&mt6359_vcn18_ldo_reg>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ status = "okay";
+};
+
+&mipi_tx_config0 {
+ status = "okay";
+};
+
+&mt6359codec {
+ mediatek,mic-type-0 = <1>;
+ mediatek,mic-type-1 = <3>;
+};
+
+&mt6359_vbbck_ldo_reg {
+ regulator-always-on;
+};
+
+&mt6359_vcn18_ldo_reg {
+ regulator-name = "vcn18_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+};
+
+&mt6359_vcn33_1_bt_ldo_reg {
+ regulator-name = "vcn33_1_pmu";
+ regulator-always-on;
+};
+
+&mt6359_vcn33_2_bt_ldo_reg {
+ regulator-name = "vcn33_2_pmu";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+};
+
+&mt6359_vcore_buck_reg {
+ regulator-name = "dvdd_proc_l";
+ regulator-always-on;
+};
+
+&mt6359_vemc_1_ldo_reg {
+ regulator-always-on;
+};
+
+&mt6359_vgpu11_buck_reg {
+ regulator-name = "dvdd_core";
+ regulator-always-on;
+};
+
+&mt6359_vmodem_buck_reg {
+ regulator-always-on;
+};
+
+&mt6359_vpa_buck_reg {
+ regulator-name = "vpa_pmu";
+ regulator-always-on;
+};
+
+&mt6359_vproc2_buck_reg {
+ /* The name "vgpu" is required by mtk-regulator-coupler */
+ regulator-name = "vgpu";
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <800000>;
+ regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>;
+ regulator-coupled-max-spread = <225000>;
+};
+
+&mt6359_vs2_buck_reg {
+ regulator-min-microvolt = <1600000>;
+ regulator-boot-on;
+};
+
+&mt6359_vpu_buck_reg {
+ regulator-name = "dvdd_adsp";
+ regulator-always-on;
+};
+
+&mt6359_vrf12_ldo_reg {
+ regulator-name = "va12_abb2_pmu";
+ regulator-always-on;
+};
+
+&mt6359_vsram_md_ldo_reg {
+ regulator-always-on;
+};
+
+&mt6359_vsram_others_ldo_reg {
+ /* The name "vsram_gpu" is required by mtk-regulator-coupler */
+ regulator-name = "vsram_gpu";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <800000>;
+ regulator-coupled-with = <&mt6359_vproc2_buck_reg>;
+ regulator-coupled-max-spread = <225000>;
+};
+
+&mt6359_vsim1_ldo_reg {
+ regulator-name = "vsim1_pmu";
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <480>;
+};
+
+&mt6359_vufs_ldo_reg {
+ regulator-name = "vufs18_pmu";
+ regulator-always-on;
+};
+
+&ovl0_in {
+ remote-endpoint = <&vdosys0_ep_main>;
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_default_pins>;
+ status = "okay";
+};
+
+&pciephy {
+ status = "okay";
+};
+
+&pmic {
+ interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
+
+ keys {
+ compatible = "mediatek,mt6359-keys";
+ mediatek,long-press-mode = <1>;
+ power-off-time-sec = <0>;
+
+ power-key {
+ linux,keycodes = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+};
+
+&postmask0_in {
+ remote-endpoint = <&gamma0_out>;
+};
+
+&postmask0_out {
+ remote-endpoint = <&dither0_in>;
+};
+
+&scp_cluster {
+ status = "okay";
+};
+
+&scp_c0 {
+ memory-region = <&scp_mem>;
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-0 = <&spi0_pins>;
+ pinctrl-names = "default";
+ mediatek,pad-select = <0>;
+ status = "okay";
+};
+
+&spi1 {
+ pinctrl-0 = <&spi1_pins>;
+ pinctrl-names = "default";
+ mediatek,pad-select = <0>;
+ status = "okay";
+};
+
+&spmi {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ mt6315_6: pmic@6 {
+ compatible = "mediatek,mt6315-regulator";
+ reg = <0x6 SPMI_USID>;
+
+ regulators {
+ mt6315_6_vbuck1: vbuck1 {
+ regulator-name = "vbuck1";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-enable-ramp-delay = <256>;
+ regulator-allowed-modes = <0 1 2>;
+ regulator-always-on;
+ };
+
+ mt6315_6_vbuck3: vbuck3 {
+ regulator-name = "vbuck3";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-enable-ramp-delay = <256>;
+ regulator-allowed-modes = <0 1 2>;
+ regulator-always-on;
+ };
+
+ mt6315_6_vbuck4: vbuck4 {
+ regulator-name = "vbuck4";
+ regulator-min-microvolt = <1193750>;
+ regulator-max-microvolt = <1193750>;
+ regulator-enable-ramp-delay = <256>;
+ regulator-allowed-modes = <0 1 2>;
+ regulator-always-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1193750>;
+ };
+ };
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-0 = <&uart1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&ssusb0 {
+ dr_mode = "otg";
+ maximum-speed = "high-speed";
+ usb-role-switch;
+ wakeup-source;
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ pinctrl-0 = <&usbotg_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ hs_ep: endpoint {
+ remote-endpoint = <&usb_hs_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ss_ep: endpoint {
+ remote-endpoint = <&hd3ss3220_in_ep>;
+ };
+ };
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ usb_hs_ep: endpoint {
+ remote-endpoint = <&hs_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ usb_role_switch: endpoint {
+ remote-endpoint = <&hd3ss3220_out_ep>;
+ };
+ };
+ };
+};
+
+&u2port0 {
+ status = "okay";
+};
+
+&u3phy0 {
+ status = "okay";
+};
+
+&xhci0 {
+ vbus-supply = <&usb_p0_vbus>;
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ status = "okay";
+};
+
+&ssusb1 {
+ dr_mode = "host";
+ wakeup-source;
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ pinctrl-0 = <&usb1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&u2port1 {
+ status = "okay";
+};
+
+&u3port1 {
+ status = "okay";
+};
+
+&u3phy1 {
+ status = "okay";
+};
+
+&xhci1 {
+ vbus-supply = <&usb_p1_vbus>;
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ status = "okay";
+};
+
+&ssusb2 {
+ dr_mode = "host";
+ maximum-speed = "high-speed";
+ wakeup-source;
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ status = "okay";
+};
+
+&u2port2 {
+ status = "okay";
+};
+
+&u3phy2 {
+ status = "okay";
+};
+
+&xhci2 {
+ vbus-supply = <&usb_p2_vbus>;
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ ethernet@1 {
+ compatible = "usb424,7850";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@1 {
+ reg = <1>;
+ microchip,led-modes = <
+ LAN78XX_LINK_1000_ACTIVITY
+ LAN78XX_LINK_10_ACTIVITY
+ LAN78XX_LINK_10_100_ACTIVITY
+ LAN78XX_LINK_ACTIVITY
+ >;
+ };
+ };
+ };
+};
+
+&vdosys0 {
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdosys0_ep_main: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&ovl0_in>;
+ };
+ };
+};
+
+&watchdog {
+ pinctrl-names = "default";
+ pinctrl-0 = <&watchdog_pins>;
+};
+
+&pio {
+ audio_pins: audio-pins {
+ pins-aud-pmic {
+ pinmux = <PINMUX_GPIO101__FUNC_O_AUD_CLK_MOSI
+ PINMUX_GPIO102__FUNC_O_AUD_SYNC_MOSI
+ PINMUX_GPIO103__FUNC_O_AUD_DAT_MOSI0
+ PINMUX_GPIO104__FUNC_O_AUD_DAT_MOSI1
+ PINMUX_GPIO105__FUNC_I0_AUD_DAT_MISO0
+ PINMUX_GPIO106__FUNC_I0_AUD_DAT_MISO1>;
+ };
+
+ pins-pcm-wifi {
+ pinmux = <PINMUX_GPIO121__FUNC_B0_PCM_CLK
+ PINMUX_GPIO122__FUNC_B0_PCM_SYNC
+ PINMUX_GPIO123__FUNC_O_PCM_DO
+ PINMUX_GPIO124__FUNC_I0_PCM_DI>;
+ };
+
+ pins-i2s {
+ pinmux = <PINMUX_GPIO119__FUNC_O_I2SO1_MCK
+ PINMUX_GPIO112__FUNC_O_I2SO1_WS
+ PINMUX_GPIO120__FUNC_O_I2SO1_BCK
+ PINMUX_GPIO113__FUNC_O_I2SO1_D0
+ PINMUX_GPIO110__FUNC_I0_I2SIN_D0>;
+ };
+ };
+
+ disp_pwm0_pins: disp-pwm0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO29__FUNC_O_DISP_PWM0>;
+ bias-pull-down;
+ };
+ };
+
+ dsi0_sn65dsi84_pins: dsi0-sn65dsi84-pins {
+ pins-irq {
+ pinmux = <PINMUX_GPIO128__FUNC_B_GPIO128>;
+ bias-pull-down;
+ input-enable;
+ };
+
+ pins-enable {
+ pinmux = <PINMUX_GPIO25__FUNC_B_GPIO25>;
+ bias-pull-down;
+ };
+ };
+
+ eth_default_pins: eth-default-pins {
+ pins-txd {
+ pinmux = <PINMUX_GPIO131__FUNC_O_GBE_TXD3>,
+ <PINMUX_GPIO132__FUNC_O_GBE_TXD2>,
+ <PINMUX_GPIO133__FUNC_O_GBE_TXD1>,
+ <PINMUX_GPIO134__FUNC_O_GBE_TXD0>;
+ drive-strength = <8>;
+ };
+ pins-cc {
+ pinmux = <PINMUX_GPIO139__FUNC_B0_GBE_TXC>,
+ <PINMUX_GPIO142__FUNC_O_GBE_TXEN>,
+ <PINMUX_GPIO141__FUNC_I0_GBE_RXDV>;
+ drive-strength = <8>;
+ };
+ pins-rxd {
+ pinmux = <PINMUX_GPIO135__FUNC_I0_GBE_RXD3>,
+ <PINMUX_GPIO136__FUNC_I0_GBE_RXD2>,
+ <PINMUX_GPIO137__FUNC_I0_GBE_RXD1>,
+ <PINMUX_GPIO138__FUNC_I0_GBE_RXD0>,
+ <PINMUX_GPIO140__FUNC_I0_GBE_RXC>;
+ drive-strength = <8>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
+ };
+ pins-mdio {
+ pinmux = <PINMUX_GPIO143__FUNC_O_GBE_MDC>,
+ <PINMUX_GPIO144__FUNC_B1_GBE_MDIO>;
+ drive-strength = <8>;
+ input-enable;
+ };
+ pins-power {
+ pinmux = <PINMUX_GPIO27__FUNC_B_GPIO27>; /* GP_EQOS_RESET */
+ output-high;
+ };
+ pins-intr {
+ pinmux = <PINMUX_GPIO148__FUNC_B_GPIO148>; /* GPIRQ_EQOS_PHY */
+ bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
+ input-enable;
+ };
+ };
+
+ eth_sleep_pins: eth-sleep-pins {
+ pins-txd {
+ pinmux = <PINMUX_GPIO131__FUNC_B_GPIO131>,
+ <PINMUX_GPIO132__FUNC_B_GPIO132>,
+ <PINMUX_GPIO133__FUNC_B_GPIO133>,
+ <PINMUX_GPIO134__FUNC_B_GPIO134>;
+ };
+ pins-cc {
+ pinmux = <PINMUX_GPIO139__FUNC_B_GPIO139>,
+ <PINMUX_GPIO142__FUNC_B_GPIO142>,
+ <PINMUX_GPIO141__FUNC_B_GPIO141>,
+ <PINMUX_GPIO140__FUNC_B_GPIO140>;
+ };
+ pins-rxd {
+ pinmux = <PINMUX_GPIO135__FUNC_B_GPIO135>,
+ <PINMUX_GPIO136__FUNC_B_GPIO136>,
+ <PINMUX_GPIO137__FUNC_B_GPIO137>,
+ <PINMUX_GPIO138__FUNC_B_GPIO138>;
+ };
+ pins-mdio {
+ pinmux = <PINMUX_GPIO143__FUNC_B_GPIO143>,
+ <PINMUX_GPIO144__FUNC_B_GPIO144>;
+ input-disable;
+ bias-disable;
+ };
+ };
+
+ gpio_keys_pins: gpio-keys-pins {
+ pins-keys {
+ pinmux = <PINMUX_GPIO129__FUNC_B_GPIO129>,
+ <PINMUX_GPIO65__FUNC_B_GPIO65>,
+ <PINMUX_GPIO66__FUNC_B_GPIO66>;
+ bias-pull-up;
+ };
+ };
+
+ hd3ss3220_pins: hd3ss3320-pins {
+ pins-irq {
+ pinmux = <PINMUX_GPIO45__FUNC_B_GPIO45>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ input-enable;
+ };
+ };
+
+ hdmi_vreg_pins: hdmi-vreg-pins {
+ pins-pwr {
+ pinmux = <PINMUX_GPIO50__FUNC_O_HDMITX20_PWR5V>;
+ bias-disable;
+ };
+ };
+
+ hdmi_pins: hdmi-pins {
+ pins-hotplug {
+ pinmux = <PINMUX_GPIO51__FUNC_I0_HDMITX20_HTPLG>;
+ bias-pull-down;
+ };
+
+ pins-cec {
+ pinmux = <PINMUX_GPIO52__FUNC_B1_HDMITX20_CEC>;
+ bias-disable;
+ };
+
+ pins-ddc {
+ pinmux = <PINMUX_GPIO53__FUNC_B1_HDMITX20_SCL>,
+ <PINMUX_GPIO54__FUNC_B1_HDMITX20_SDA>;
+ drive-strength = <10>;
+ };
+ };
+
+ i2c0_pins: i2c0-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>,
+ <PINMUX_GPIO55__FUNC_B1_SCL0>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ i2c0_mux_pins: i2c0-mux-pins {
+ pins-reset {
+ pinmux = <PINMUX_GPIO6__FUNC_B_GPIO6>;
+ bias-pull-up;
+ };
+ };
+
+ i2c1_pins: i2c1-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO58__FUNC_B1_SDA1>,
+ <PINMUX_GPIO57__FUNC_B1_SCL1>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ i2c2_pins: i2c2-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO60__FUNC_B1_SDA2>,
+ <PINMUX_GPIO59__FUNC_B1_SCL2>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ i2c3_pins: i2c3-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO62__FUNC_B1_SDA3>,
+ <PINMUX_GPIO61__FUNC_B1_SCL3>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ i2c4_pins: i2c4-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO64__FUNC_B1_SDA4>,
+ <PINMUX_GPIO63__FUNC_B1_SCL4>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ i2c_mux_smarc_lcd_pins: i2c-mux-smarc-lcd-pins {
+ pins-reset {
+ pinmux = <PINMUX_GPIO5__FUNC_B_GPIO5>;
+ bias-pull-down;
+ };
+ };
+
+ mmc0_default_pins: mmc0-default-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>,
+ <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>,
+ <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>,
+ <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>,
+ <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>,
+ <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>,
+ <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>,
+ <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>,
+ <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-clk {
+ pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>;
+ drive-strength = <6>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-rst {
+ pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc0_uhs_pins: mmc0-uhs-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>,
+ <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>,
+ <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>,
+ <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>,
+ <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>,
+ <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>,
+ <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>,
+ <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>,
+ <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <8>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-clk {
+ pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>;
+ drive-strength = <8>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-ds {
+ pinmux = <PINMUX_GPIO162__FUNC_B0_MSDC0_DSL>;
+ drive-strength = <8>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-rst {
+ pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>;
+ drive-strength = <8>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc1_default_pins: mmc1-default-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO163__FUNC_B1_MSDC1_CMD>,
+ <PINMUX_GPIO165__FUNC_B1_MSDC1_DAT0>,
+ <PINMUX_GPIO166__FUNC_B1_MSDC1_DAT1>,
+ <PINMUX_GPIO167__FUNC_B1_MSDC1_DAT2>,
+ <PINMUX_GPIO168__FUNC_B1_MSDC1_DAT3>;
+ input-enable;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-pwr {
+ pinmux = <PINMUX_GPIO111__FUNC_B_GPIO111>;
+ bias-pull-down;
+ };
+
+ pins-pullup {
+ pinmux = <PINMUX_GPIO11__FUNC_B_GPIO11>;
+ bias-pull-up;
+ };
+
+ pins-clk {
+ pinmux = <PINMUX_GPIO164__FUNC_B1_MSDC1_CLK>;
+ drive-strength = <6>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-insert {
+ pinmux = <PINMUX_GPIO2__FUNC_B_GPIO2>;
+ bias-pull-up;
+ };
+ };
+
+ mmc1_uhs_pins: mmc1-uhs-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO163__FUNC_B1_MSDC1_CMD>,
+ <PINMUX_GPIO165__FUNC_B1_MSDC1_DAT0>,
+ <PINMUX_GPIO166__FUNC_B1_MSDC1_DAT1>,
+ <PINMUX_GPIO167__FUNC_B1_MSDC1_DAT2>,
+ <PINMUX_GPIO168__FUNC_B1_MSDC1_DAT3>;
+ input-enable;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-clk {
+ pinmux = <PINMUX_GPIO164__FUNC_B1_MSDC1_CLK>;
+ drive-strength = <6>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+ };
+
+ mmc2_default_pins: mmc2-default-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO170__FUNC_B1_MSDC2_CLK>;
+ drive-strength = <4>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO169__FUNC_B1_MSDC2_CMD>,
+ <PINMUX_GPIO171__FUNC_B1_MSDC2_DAT0>,
+ <PINMUX_GPIO172__FUNC_B1_MSDC2_DAT1>,
+ <PINMUX_GPIO173__FUNC_B1_MSDC2_DAT2>,
+ <PINMUX_GPIO174__FUNC_B1_MSDC2_DAT3>;
+ input-enable;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc2_uhs_pins: mmc2-uhs-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO170__FUNC_B1_MSDC2_CLK>;
+ drive-strength = <4>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO169__FUNC_B1_MSDC2_CMD>,
+ <PINMUX_GPIO171__FUNC_B1_MSDC2_DAT0>,
+ <PINMUX_GPIO172__FUNC_B1_MSDC2_DAT1>,
+ <PINMUX_GPIO173__FUNC_B1_MSDC2_DAT2>,
+ <PINMUX_GPIO174__FUNC_B1_MSDC2_DAT3>;
+ input-enable;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc2_eint_pins: mmc2-eint-pins {
+ pins-dat1 {
+ pinmux = <PINMUX_GPIO172__FUNC_B_GPIO172>;
+ input-enable;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ rv3028_pins: rv3028-pins {
+ pins-irq {
+ pinmux = <PINMUX_GPIO42__FUNC_B_GPIO42>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ input-enable;
+ };
+ };
+
+ spi0_pins: spi0-pins {
+ pins-spi {
+ pinmux = <PINMUX_GPIO69__FUNC_O_SPIM0_CSB>,
+ <PINMUX_GPIO70__FUNC_O_SPIM0_CLK>,
+ <PINMUX_GPIO71__FUNC_B0_SPIM0_MOSI>,
+ <PINMUX_GPIO72__FUNC_B0_SPIM0_MISO>;
+ bias-disable;
+ };
+ };
+
+ spi1_pins: spi1-pins {
+ pins-spi {
+ pinmux = <PINMUX_GPIO75__FUNC_O_SPIM1_CSB>,
+ <PINMUX_GPIO76__FUNC_O_SPIM1_CLK>,
+ <PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI>,
+ <PINMUX_GPIO78__FUNC_B0_SPIM1_MISO>;
+ bias-disable;
+ };
+ };
+
+ pcie_default_pins: pcie-default-pins {
+ pins {
+ pinmux = <PINMUX_GPIO47__FUNC_I1_WAKEN>,
+ <PINMUX_GPIO48__FUNC_O_PERSTN>,
+ <PINMUX_GPIO49__FUNC_B1_CLKREQN>;
+ bias-pull-up;
+ };
+ };
+
+ ts_dsi0_goodix_pins: ts-dsi0-goodix-pins {
+ pins-irq {
+ pinmux = <PINMUX_GPIO146__FUNC_B_GPIO146>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ input-enable;
+ };
+
+ pins-reset {
+ pinmux = <PINMUX_GPIO7__FUNC_B_GPIO7>;
+ bias-pull-down;
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO31__FUNC_O_UTXD0>,
+ <PINMUX_GPIO32__FUNC_I1_URXD0>;
+ bias-pull-up;
+ };
+ };
+
+ uart1_pins: uart1-pins {
+ pins {
+ pinmux = <PINMUX_GPIO33__FUNC_O_UTXD1>,
+ <PINMUX_GPIO34__FUNC_I1_URXD1>;
+ bias-pull-up;
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ pins {
+ pinmux = <PINMUX_GPIO35__FUNC_O_UTXD2>,
+ <PINMUX_GPIO36__FUNC_I1_URXD2>;
+ bias-pull-up;
+ };
+ };
+
+ usbotg_pins: usbotg-pins {
+ pins-iddig {
+ pinmux = <PINMUX_GPIO83__FUNC_B_GPIO83>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins-valid {
+ pinmux = <PINMUX_GPIO85__FUNC_I0_VBUSVALID>;
+ input-enable;
+ };
+
+ pins-vbus {
+ pinmux = <PINMUX_GPIO84__FUNC_O_USB_DRVVBUS>;
+ output-high;
+ };
+ };
+
+ usb1_hub_pins: usb1-hub-pins {
+ pins {
+ pinmux = <PINMUX_GPIO147__FUNC_B_GPIO147>;
+ output-low;
+ };
+ };
+
+ usb1_pins: usb1-pins {
+ pins {
+ pinmux = <PINMUX_GPIO88__FUNC_I0_VBUSVALID_1P>;
+ input-enable;
+ };
+ };
+
+ usb2_eth_pins: usb2-eth-pins {
+ pins {
+ pinmux = <PINMUX_GPIO80__FUNC_B_GPIO80>;
+ output-low;
+ };
+ };
+
+ wifi_pwrseq_pins: wifi-pwrseq-pins {
+ pins {
+ pinmux = <PINMUX_GPIO89__FUNC_B_GPIO89>;
+ output-low;
+ };
+ };
+
+ watchdog_pins: watchdog-pins {
+ pins {
+ pinmux = <PINMUX_GPIO100__FUNC_O_WATCHDOG>;
+ bias-pull-up;
+ };
+ };
+};
stdout-path = "serial0:921600n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+ ddc-i2c-bus = <&hdmitx_ddc>;
+ hdmi-pwr-supply = <&hdmi_phy>;
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi0_out>;
+ };
+ };
+ };
+
firmware {
optee {
compatible = "linaro,optee-tz";
wakeup-delay-ms = <200>;
};
+&dpi1 {
+ status = "okay";
+};
+
+&dpi1_in {
+ remote-endpoint = <&merge5_out>;
+};
+
+&dpi1_out {
+ remote-endpoint = <&hdmi0_in>;
+};
+
&dsi0 {
#address-cells = <1>;
#size-cells = <0>;
};
};
+ðdr0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ ethdr0_in: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vdosys1_ep_ext>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ ethdr0_out: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&merge5_in>;
+ };
+ };
+ };
+};
+
&gamma0_out {
remote-endpoint = <&dither0_in>;
};
status = "okay";
};
+&hdmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pins>;
+ status = "okay";
+};
+
+&hdmi0_in {
+ remote-endpoint = <&dpi1_out>;
+};
+
+&hdmi0_out {
+ remote-endpoint = <&hdmi_connector_in>;
+};
+
+&hdmi_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_vreg_pins>;
+
+ status = "okay";
+};
+
&i2c1 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c1_pins>;
};
};
+&merge5 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ merge5_in: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <ðdr0_out>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ merge5_out: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dpi1_in>;
+ };
+ };
+ };
+};
+
&mfg0 {
domain-supply = <&mt6315_7_vbuck1>;
};
};
};
+ hdmi_vreg_pins: hdmi-vreg-pins {
+ pins-pwr {
+ pinmux = <PINMUX_GPIO31__FUNC_HDMITX20_PWR5V>;
+ bias-disable;
+ };
+ };
+
+ hdmi_pins: hdmi-pins {
+ pins-hotplug {
+ pinmux = <PINMUX_GPIO32__FUNC_HDMITX20_HTPLG>;
+ bias-pull-down;
+ };
+
+ pins-ddc {
+ pinmux = <PINMUX_GPIO34__FUNC_HDMITX20_SCL>,
+ <PINMUX_GPIO35__FUNC_HDMITX20_SDA>;
+ drive-strength = <10>;
+ };
+
+ pins-cec {
+ pinmux = <PINMUX_GPIO33__FUNC_HDMITX20_CEC>;
+ bias-disable;
+ };
+ };
+
i2c0_pins: i2c0-pins {
pins {
pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
sound-dai = <&pmic 0>;
};
};
+
+ hdmi-dai-link {
+ link-name = "ETDM3_OUT_BE";
+
+ codec {
+ sound-dai = <&hdmi 0>;
+ };
+ };
};
&spi1 {
};
};
+&vdosys1 {
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdosys1_ep_ext: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <ðdr0_in>;
+ };
+ };
+};
+
&xhci0 {
status = "okay";
};
stdout-path = "serial0:921600n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+ ddc-i2c-bus = <&hdmitx_ddc>;
+ hdmi-pwr-supply = <&hdmi_phy>;
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi0_out>;
+ };
+ };
+ };
+
firmware {
optee {
compatible = "linaro,optee-tz";
};
};
+&dpi1 {
+ status = "okay";
+};
+
+&dpi1_in {
+ remote-endpoint = <&merge5_out>;
+};
+
+&dpi1_out {
+ remote-endpoint = <&hdmi0_in>;
+};
+
ð {
phy-mode = "rgmii-rxid";
phy-handle = <&rgmii_phy>;
};
};
+ðdr0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ ethdr0_in: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vdosys1_ep_ext>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ ethdr0_out: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&merge5_in>;
+ };
+ };
+ };
+};
+
&gpu {
mali-supply = <&mt6315_7_vbuck1>;
status = "okay";
};
+&hdmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pins>;
+ status = "okay";
+};
+
+&hdmi0_in {
+ remote-endpoint = <&dpi1_out>;
+};
+
+&hdmi0_out {
+ remote-endpoint = <&hdmi_connector_in>;
+};
+
+&hdmi_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_vreg_pins>;
+
+ status = "okay";
+};
+
&i2c2 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c2_pins>;
};
};
+&merge5 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ merge5_in: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <ðdr0_out>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ merge5_out: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dpi1_in>;
+ };
+ };
+ };
+};
+
&mfg0 {
domain-supply = <&mt6315_7_vbuck1>;
};
};
};
+ hdmi_vreg_pins: hdmi-vreg-pins {
+ pins-pwr {
+ pinmux = <PINMUX_GPIO31__FUNC_HDMITX20_PWR5V>;
+ bias-disable;
+ };
+ };
+
+ hdmi_pins: hdmi-pins {
+ pins-hotplug {
+ pinmux = <PINMUX_GPIO32__FUNC_HDMITX20_HTPLG>;
+ bias-pull-down;
+ };
+
+ pins-ddc {
+ pinmux = <PINMUX_GPIO34__FUNC_HDMITX20_SCL>,
+ <PINMUX_GPIO35__FUNC_HDMITX20_SDA>;
+ drive-strength = <10>;
+ };
+
+ pins-cec {
+ pinmux = <PINMUX_GPIO33__FUNC_HDMITX20_CEC>;
+ bias-disable;
+ };
+ };
+
i2c2_pins: i2c2-pins {
pins-bus {
pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
sound-dai = <&pmic 0>;
};
};
+
+ hdmi-dai-link {
+ link-name = "ETDM3_OUT_BE";
+
+ codec {
+ sound-dai = <&hdmi 0>;
+ };
+ };
};
&spi1 {
status = "okay";
};
+&vdosys1 {
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdosys1_ep_ext: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <ðdr0_in>;
+ };
+ };
+};
+
&xhci0 {
vbus-supply = <&otg_vbus_regulator>;
status = "okay";
};
memory@0 {
+ device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
};
psci {
- compatible = "arm,psci-1.0";
- method = "smc";
+ compatible = "arm,psci-1.0";
+ method = "smc";
};
timer {
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dma-channel-mask = <0xfffffffe>;
- status = "okay";
};
aconnect@2900000 {
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- status = "okay";
};
uarta: serial@3100000 {
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
nvidia,axi2apb = <&axi2apb>;
nvidia,apbmisc = <&apbmisc>;
- status = "okay";
};
axi2apb: axi2apb@2390000 {
<0x0 0x23c0000 0x0 0x1000>,
<0x0 0x23d0000 0x0 0x1000>,
<0x0 0x23e0000 0x0 0x1000>;
- status = "okay";
};
pinmux: pinmux@2430000 {
compatible = "nvidia,tegra194-pinmux";
reg = <0x0 0x2430000 0x0 0x17000>;
- status = "okay";
pex_clkreq_c5_bi_dir_state: pinmux-pex-clkreq-c5-bi-dir {
clkreq {
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dma-channel-mask = <0xfffffffe>;
- status = "okay";
};
aconnect@2900000 {
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- status = "okay";
};
uarta: serial@3100000 {
nvidia,int-threshold = <1>;
nvidia,slices = <11>;
#timestamp-cells = <1>;
- status = "okay";
};
hsp_top0: hsp@3c00000 {
<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
nvidia,axi2apb = <&axi2apb>;
nvidia,apbmisc = <&apbmisc>;
- status = "okay";
};
rce-noc@be00000 {
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
nvidia,axi2apb = <&axi2apb>;
nvidia,apbmisc = <&apbmisc>;
- status = "okay";
};
hsp_aon: hsp@c150000 {
nvidia,int-threshold = <1>;
nvidia,slices = <3>;
#timestamp-cells = <1>;
- status = "okay";
};
gen2_i2c: i2c@c240000 {
pinmux_aon: pinmux@c300000 {
compatible = "nvidia,tegra194-pinmux-aon";
reg = <0x0 0xc300000 0x0 0x4000>;
-
- status = "okay";
};
pwm4: pwm@c340000 {
interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
nvidia,apbmisc = <&apbmisc>;
- status = "okay";
};
bpmp-noc@d600000 {
<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
nvidia,axi2apb = <&axi2apb>;
nvidia,apbmisc = <&apbmisc>;
- status = "okay";
};
iommu@10000000 {
#iommu-cells = <1>;
nvidia,memory-controller = <&mc>;
- status = "okay";
};
host1x@13e00000 {
psci {
compatible = "arm,psci-1.0";
- status = "okay";
method = "smc";
};
};
host1x@50000000 {
+ dpaux1: dpaux@54040000 {
+ vdd-supply = <&pp3300>;
+ status = "okay";
+ };
+
dsia: dsi@54300000 {
avdd-dsi-csi-supply = <&vdd_dsi_csi>;
status = "okay";
};
};
+ sor1: sor@54580000 {
+ avdd-io-hdmi-dp-supply = <&pp1800>;
+ vdd-hdmi-dp-pll-supply = <&avddio_1v05>;
+ nvidia,dpaux = <&dpaux1>;
+ status = "okay";
+ };
+
dpaux: dpaux@545c0000 {
status = "okay";
};
status = "okay";
vbus-supply = <&usbc_vbus>;
mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "host";
};
usb3-0 {
status = "okay";
};
+ usb@700d0000 {
+ phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
+ <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>;
+ phy-names = "usb2-0", "usb3-0";
+
+ avddio-usb-supply = <&avddio_1v05>;
+ hvdd-usb-supply = <&pp3300>;
+
+ status = "okay";
+ };
+
clock@70110000 {
status = "okay";
nvidia,cf = <6>;
compatible = "nvidia,tegra234-misc";
reg = <0x0 0x00100000 0x0 0xf000>,
<0x0 0x0010f000 0x0 0x1000>;
- status = "okay";
};
timer@2080000 {
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
- status = "okay";
};
gpio: gpio@2200000 {
"ch11", "ch12", "ch13", "ch14", "ch15";
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
#interconnect-cells = <1>;
- status = "okay";
#address-cells = <2>;
#size-cells = <2>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA234_CLK_EMC>;
clock-names = "emc";
- status = "okay";
#interconnect-cells = <0>;
#iommu-cells = <1>;
nvidia,memory-controller = <&mc>;
- status = "okay";
};
sce-fabric@b600000 {
compatible = "nvidia,tegra234-rce-fabric";
reg = <0x0 0xbe00000 0x0 0x40000>;
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
- status = "okay";
};
hsp_aon: hsp@c150000 {
compatible = "nvidia,tegra234-aon-fabric";
reg = <0x0 0xc600000 0x0 0x40000>;
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
- status = "okay";
};
bpmp-fabric@d600000 {
compatible = "nvidia,tegra234-bpmp-fabric";
reg = <0x0 0xd600000 0x0 0x40000>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- status = "okay";
};
dce-fabric@de00000 {
compatible = "nvidia,tegra234-dce-fabric";
reg = <0x0 0xde00000 0x0 0x40000>;
interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
- status = "okay";
};
ccplex@e000000 {
compatible = "nvidia,tegra234-ccplex-cluster";
reg = <0x0 0x0e000000 0x0 0x5ffff>;
nvidia,bpmp = <&bpmp>;
- status = "okay";
};
gic: interrupt-controller@f400000 {
#iommu-cells = <1>;
nvidia,memory-controller = <&mc>;
- status = "okay";
};
smmu_niso0: iommu@12000000 {
#iommu-cells = <1>;
nvidia,memory-controller = <&mc>;
- status = "okay";
};
cbb-fabric@13a00000 {
compatible = "nvidia,tegra234-cbb-fabric";
reg = <0x0 0x13a00000 0x0 0x400000>;
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
- status = "okay";
};
host1x@13e00000 {
pmu {
compatible = "arm,cortex-a78-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
- status = "okay";
};
psci {
compatible = "arm,psci-1.0";
- status = "okay";
method = "smc";
};
status = "okay";
};
+ cmdqv@5200000 {
+ status = "okay";
+ };
+
iommu@6000000 {
status = "okay";
};
+
+ cmdqv@6200000 {
+ status = "okay";
+ };
};
};
<0x02 0x00000000 0xd0 0x00000000 0x08 0x80000000>; /* ECAM, prefetchable memory, I/O */
smmu1: iommu@5000000 {
- compatible = "arm,smmu-v3";
+ compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
reg = <0x00 0x5000000 0x0 0x200000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 13 IRQ_TYPE_EDGE_RISING>;
#iommu-cells = <1>;
dma-coherent;
+ nvidia,cmdqv = <&cmdqv1>;
+ };
+
+ cmdqv1: cmdqv@5200000 {
+ compatible = "nvidia,tegra264-cmdqv";
+ reg = <0x00 0x5200000 0x0 0x830000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
smmu2: iommu@6000000 {
- compatible = "arm,smmu-v3";
+ compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
reg = <0x00 0x6000000 0x0 0x200000>;
interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
#iommu-cells = <1>;
dma-coherent;
+ nvidia,cmdqv = <&cmdqv2>;
+ };
+
+ cmdqv2: cmdqv@6200000 {
+ compatible = "nvidia,tegra264-cmdqv";
+ reg = <0x00 0x6200000 0x0 0x830000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
mc: memory-controller@8020000 {
reg = <0x00 0x8800000 0x0 0x20000>,
<0x00 0x8890000 0x0 0x20000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&bpmp TEGRA264_CLK_EMC>;
- clock-names = "emc";
+ clocks = <&bpmp TEGRA264_CLK_EMC>,
+ <&bpmp TEGRA264_CLK_DBB_UPHY0>;
+ clock-names = "emc", "dbb";
#interconnect-cells = <0>;
nvidia,bpmp = <&bpmp>;
};
smmu0: iommu@a000000 {
- compatible = "arm,smmu-v3";
+ compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
reg = <0x00 0xa000000 0x0 0x200000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
#iommu-cells = <1>;
dma-coherent;
+ nvidia,cmdqv = <&cmdqv0>;
+ };
+
+ cmdqv0: cmdqv@a200000 {
+ compatible = "nvidia,tegra264-cmdqv";
+ reg = <0x00 0xa200000 0x0 0x830000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
smmu4: iommu@b000000 {
- compatible = "arm,smmu-v3";
+ compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
reg = <0x00 0xb000000 0x0 0x200000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
#iommu-cells = <1>;
dma-coherent;
+ nvidia,cmdqv = <&cmdqv4>;
+ };
+
+ cmdqv4: cmdqv@b200000 {
+ compatible = "nvidia,tegra264-cmdqv";
+ reg = <0x00 0xb200000 0x0 0x830000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
i2c14: i2c@c410000 {
ranges = <0x00 0x00000000 0x88 0x00000000 0x01 0x00000000>;
smmu3: iommu@6000000 {
- compatible = "arm,smmu-v3";
+ compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
reg = <0x00 0x6000000 0x0 0x200000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 226 IRQ_TYPE_EDGE_RISING>;
#iommu-cells = <1>;
dma-coherent;
+ nvidia,cmdqv = <&cmdqv3>;
+ };
+
+ cmdqv3: cmdqv@6200000 {
+ compatible = "nvidia,tegra264-cmdqv";
+ reg = <0x00 0x6200000 0x0 0x830000>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
hda@90b0000 {
#size-cells = <0>;
cpu0: cpu@0 {
- compatible = "arm,armv8";
+ compatible = "arm,neoverse-v3ae";
device_type = "cpu";
reg = <0x00000>;
- status = "okay";
enable-method = "psci";
};
cpu1: cpu@1 {
- compatible = "arm,armv8";
+ compatible = "arm,neoverse-v3ae";
device_type = "cpu";
reg = <0x10000>;
- status = "okay";
enable-method = "psci";
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
- status = "okay";
};
psci {
compatible = "arm,psci-1.0";
- status = "okay";
method = "smc";
};
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
- status = "okay";
};
};
bias-disable;
};
+ qup_uart2_default: qup-uart2-default-state {
+ pins = "gpio6", "gpio7", "gpio71", "gpio80";
+ function = "qup2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
qup_uart3_default: qup-uart3-default-state {
pins = "gpio8", "gpio9", "gpio10", "gpio11";
function = "qup3";
bias-disable;
};
+ mclk0_default: mclk0-default-state {
+ pins = "gpio20";
+ function = "cam_mclk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ mclk1_default: mclk1-default-state {
+ pins = "gpio21";
+ function = "cam_mclk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ mclk2_default: mclk2-default-state {
+ pins = "gpio27";
+ function = "cam_mclk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ mclk3_default: mclk3-default-state {
+ pins = "gpio28";
+ function = "cam_mclk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
sdc1_state_on: sdc1-on-state {
clk-pins {
pins = "sdc1_clk";
status = "disabled";
};
+ uart2: serial@4a88000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a88000 0x0 0x4000>;
+ interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_uart2_default>;
+ pinctrl-names = "default";
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
+ &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+ status = "disabled";
+ };
+
i2c3: i2c@4a8c000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x04a8c000 0x0 0x4000>;
gpu: gpu@5900000 {
compatible = "qcom,adreno-07000200", "qcom,adreno";
- reg = <0x0 0x05900000 0x0 0x40000>;
- reg-names = "kgsl_3d0_reg_memory";
+ reg = <0x0 0x05900000 0x0 0x40000>,
+ <0x0 0x0599e000 0x0 0x1000>,
+ <0x0 0x05961000 0x0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem",
+ "cx_dbgc";
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
interconnect-names = "gfx-mem";
- iommus = <&adreno_smmu 0 1>,
- <&adreno_smmu 2 0>;
+ iommus = <&adreno_smmu 0 1>;
operating-points-v2 = <&gpu_opp_table>;
power-domains = <&rpmpd QCM2290_VDDCX>;
qcom,gmu = <&gmu_wrapper>;
power-domains = <&dispcc MDSS_GDSC>;
- iommus = <&apps_smmu 0x420 0x2>,
- <&apps_smmu 0x421 0x0>;
+ iommus = <&apps_smmu 0x420 0x2>;
interconnects = <&mmrt_virt MASTER_MDP0 RPM_ALWAYS_TAG
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
};
};
};
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "adsp";
+
+ qcom,non-secure-domain;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu 0x1c3 0x0>;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+ iommus = <&apps_smmu 0x1c4 0x0>;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&apps_smmu 0x1c5 0x0>;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+ iommus = <&apps_smmu 0x1c6 0x0>;
+ };
+
+ compute-cb@7 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <7>;
+ iommus = <&apps_smmu 0x1c7 0x0>;
+ };
+ };
};
};
memory-region = <&pil_video_mem>;
iommus = <&apps_smmu 0x860 0x0>,
- <&apps_smmu 0x880 0x0>,
- <&apps_smmu 0x861 0x04>,
- <&apps_smmu 0x863 0x0>,
- <&apps_smmu 0x804 0xe0>;
+ <&apps_smmu 0x880 0x0>;
interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __DTS_GLYMUR_MAILBOX_IPCC_H
+#define __DTS_GLYMUR_MAILBOX_IPCC_H
+
+/* Glymur physical client IDs */
+#define IPCC_MPROC_AOP 0
+#define IPCC_MPROC_TZ 1
+#define IPCC_MPROC_MPSS 2
+#define IPCC_MPROC_LPASS 3
+#define IPCC_MPROC_SLPI 4
+#define IPCC_MPROC_SDC 5
+#define IPCC_MPROC_CDSP 6
+#define IPCC_MPROC_NPU 7
+#define IPCC_MPROC_APSS 8
+#define IPCC_MPROC_GPU 9
+#define IPCC_MPROC_ICP 11
+#define IPCC_MPROC_VPU 12
+#define IPCC_MPROC_PCIE0 13
+#define IPCC_MPROC_PCIE1 14
+#define IPCC_MPROC_PCIE2 15
+#define IPCC_MPROC_SPSS 16
+#define IPCC_MPROC_PCIE3 19
+#define IPCC_MPROC_PCIE4 20
+#define IPCC_MPROC_PCIE5 21
+#define IPCC_MPROC_PCIE6 22
+#define IPCC_MPROC_TME 23
+#define IPCC_MPROC_WPSS 24
+#define IPCC_MPROC_PCIE7 44
+#define IPCC_MPROC_SOCCP 46
+
+#define IPCC_COMPUTE_L0_LPASS 0
+#define IPCC_COMPUTE_L0_CDSP 1
+#define IPCC_COMPUTE_L0_APSS 2
+#define IPCC_COMPUTE_L0_GPU 3
+#define IPCC_COMPUTE_L0_CVP 6
+#define IPCC_COMPUTE_L0_ICP 7
+#define IPCC_COMPUTE_L0_VPU 8
+#define IPCC_COMPUTE_L0_DPU 9
+#define IPCC_COMPUTE_L0_SOCCP 11
+
+#define IPCC_COMPUTE_L1_LPASS 0
+#define IPCC_COMPUTE_L1_CDSP 1
+#define IPCC_COMPUTE_L1_APSS 2
+#define IPCC_COMPUTE_L1_GPU 3
+#define IPCC_COMPUTE_L1_CVP 6
+#define IPCC_COMPUTE_L1_ICP 7
+#define IPCC_COMPUTE_L1_VPU 8
+#define IPCC_COMPUTE_L1_DPU 9
+#define IPCC_COMPUTE_L1_SOCCP 11
+
+#define IPCC_PERIPH_LPASS 0
+#define IPCC_PERIPH_APSS 1
+#define IPCC_PERIPH_PCIE0 2
+#define IPCC_PERIPH_PCIE1 3
+#define IPCC_PERIPH_PCIE2 6
+#define IPCC_PERIPH_PCIE3 7
+#define IPCC_PERIPH_PCIE4 8
+#define IPCC_PERIPH_PCIE5 9
+#define IPCC_PERIPH_PCIE6 10
+#define IPCC_PERIPH_PCIE7 11
+#define IPCC_PERIPH_SOCCP 13
+#define IPCC_PERIPH_WPSS 16
+
+#endif
/dts-v1/;
+#include <dt-bindings/leds/common.h>
#include "hamoa-iot-som.dtsi"
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
model = "Qualcomm Technologies, Inc. Hamoa IoT EVK";
serial1 = &uart14;
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pmk8550_pwm 0 5000000>;
+ enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
+ power-supply = <&vreg_edp_bl>;
+
+ pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>;
+ pinctrl-names = "default";
+ };
+
wcd938x: audio-codec {
compatible = "qcom,wcd9385-codec";
stdout-path = "serial0:115200n8";
};
+ connector3 {
+ compatible = "usb-a-connector";
+ label = "USB-3-Type-A";
+ power-role = "source";
+
+ vbus-supply = <®ulator_usb3_vbus>;
+
+ port {
+ connector_3_in: endpoint {
+ };
+ };
+ };
+
+ connector6 {
+ compatible = "usb-a-connector";
+ label = "USB-6-Type-A";
+ power-role = "source";
+
+ vbus-supply = <®ulator_usb6_vbus>;
+
+ port {
+ connector_4_in: endpoint {
+ };
+ };
+ };
+
pmic-glink {
compatible = "qcom,x1e80100-pmic-glink",
"qcom,sm8550-pmic-glink",
regulator-boot-on;
};
+ vreg_edp_bl: regulator-edp-bl {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VBL9";
+ regulator-min-microvolt = <3600000>;
+ regulator-max-microvolt = <3600000>;
+
+ gpio = <&pmc8380_3_gpios 10 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&edp_bl_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-boot-on;
+ };
+
vreg_nvme: regulator-nvme {
compatible = "regulator-fixed";
regulator-boot-on;
};
+ vreg_pcie_12v: regulator-pcie-12v {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_PCIE_12V";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+
+ gpio = <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&pcie_x8_12v>;
+ pinctrl-names = "default";
+ };
+
+ vreg_pcie_3v3: regulator-pcie-3v3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_PCIE_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&pmc8380_3_gpios 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&pm_sde7_main_3p3_en>;
+ pinctrl-names = "default";
+ };
+
+ vreg_pcie_3v3_aux: regulator-pcie-3v3-aux {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_PCIE_3P3_AUX";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&pmc8380_3_gpios 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&pm_sde7_aux_3p3_en>;
+ pinctrl-names = "default";
+ };
+
/* Left unused as the retimer is not used on this board. */
vreg_rtmr0_1p15: regulator-rtmr0-1p15 {
compatible = "regulator-fixed";
regulator-boot-on;
};
+ regulator_usb3_vbus: regulator-usb3-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "USB3_VBUS";
+ gpio = <&pm8550ve_9_gpios 4 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&usb3_en>;
+ pinctrl-names = "default";
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ regulator_usb6_vbus: regulator-usb6-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "USB6_VBUS";
+ gpio = <&pm8550ve_9_gpios 5 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&usb6_en>;
+ pinctrl-names = "default";
+ enable-active-high;
+ regulator-always-on;
+ };
+
vph_pwr: regulator-vph-pwr {
compatible = "regulator-fixed";
bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>;
wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&wcn_bt_en>;
+ pinctrl-0 = <&wcn_bt_en>, <&wcn_wlan_en>;
pinctrl-names = "default";
regulators {
aux-bus {
panel {
compatible = "edp-panel";
+
+ backlight = <&backlight>;
power-supply = <&vreg_edp_3p3>;
port {
status = "okay";
};
+&pcie3_port0 {
+ vpcie12v-supply = <&vreg_pcie_12v>;
+ vpcie3v3-supply = <&vreg_pcie_3v3>;
+ vpcie3v3aux-supply = <&vreg_pcie_3v3_aux>;
+
+ reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+};
+
+&pcie4_port0 {
+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
+ wifi@0 {
+ compatible = "pci17cb,1107";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+ vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+ vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+ };
+};
+
+&pcie5 {
+ vddpe-3v3-supply = <&vreg_wwan>;
+};
+
+&pcie5_port0 {
+ reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+};
+
&pcie6a {
vddpe-3v3-supply = <&vreg_nvme>;
};
+&pcie6a_port0 {
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
&pm8550_gpios {
rtmr0_default: rtmr0-reset-n-active-state {
pins = "gpio10";
};
};
+&pm8550ve_8_gpios {
+ pcie_x8_12v: pcie-12v-default-state {
+ pins = "gpio8";
+ function = "normal";
+ output-enable;
+ output-high;
+ bias-pull-down;
+ power-source = <0>;
+ };
+};
+
&pm8550ve_9_gpios {
usb0_1p8_reg_en: usb0-1p8-reg-en-state {
pins = "gpio8";
input-disable;
output-enable;
};
+
+ usb3_en: usb3-en-state {
+ pins = "gpio4";
+ function = "normal";
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+ output-enable;
+ power-source = <0>;
+ };
+
+ usb6_en: usb6-en-state {
+ pins = "gpio5";
+ function = "normal";
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+ output-enable;
+ power-source = <0>;
+ };
+};
+
+&pm8550_pwm {
+ status = "okay";
+
+ multi-led {
+ color = <LED_COLOR_ID_MULTI>;
+ function = LED_FUNCTION_STATUS;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+ };
+};
+
+&pmc8380_3_gpios {
+ edp_bl_en: edp-bl-en-state {
+ pins = "gpio4";
+ function = "normal";
+ power-source = <1>;
+ input-disable;
+ output-enable;
+ };
+
+ edp_bl_reg_en: edp-bl-reg-en-state {
+ pins = "gpio10";
+ function = "normal";
+ };
+};
+
+&pmc8380_3_gpios {
+ pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state {
+ pins = "gpio8";
+ function = "normal";
+ output-enable;
+ bias-pull-down;
+ power-source = <0>;
+ };
+
+ pm_sde7_main_3p3_en: pcie-main-3p3-default-state {
+ pins = "gpio6";
+ function = "normal";
+ output-enable;
+ bias-pull-down;
+ power-source = <0>;
+ };
};
&pmc8380_5_gpios {
};
};
+&pmk8550_gpios {
+ edp_bl_pwm: edp-bl-pwm-state {
+ pins = "gpio5";
+ function = "func3";
+ };
+};
+
+&pmk8550_pwm {
+ status = "okay";
+};
+
&smb2360_0 {
status = "okay";
};
vdd3-supply = <&vreg_l8b_3p0>;
};
+&spi11 {
+ status = "okay";
+
+ tpm@0 {
+ compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ };
+};
+
&swr0 {
status = "okay";
bias-disable;
};
+ wcn_wlan_en: wcn-wlan-en-state {
+ pins = "gpio117";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
wwan_sw_en: wwan-sw-en-state {
pins = "gpio221";
function = "gpio";
firmware-name = "qcom/x1e80100/gen70500_zap.mbn";
};
-&pcie4 {
- perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+&pcie3 {
+ pinctrl-0 = <&pcie3_default>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie3_phy {
+ vdda-phy-supply = <&vreg_l3c_0p8>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+ status = "okay";
+};
+
+&pcie4 {
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
status = "okay";
};
-&pcie6a {
- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+&pcie5 {
+ pinctrl-0 = <&pcie5_default>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie5_phy {
+ vdda-phy-supply = <&vreg_l3i_0p8>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+ status = "okay";
+};
+
+&pcie6a {
pinctrl-0 = <&pcie6a_default>;
pinctrl-names = "default";
&tlmm {
gpio-reserved-ranges = <34 2>; /* TPM LP & INT */
+ pcie3_default: pcie3-default-state {
+ clkreq-n-pins {
+ pins = "gpio144";
+ function = "pcie3_clk";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio143";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake-n-pins {
+ pins = "gpio145";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
pcie4_default: pcie4-default-state {
clkreq-n-pins {
pins = "gpio147";
};
};
+ pcie5_default: pcie5-default-state {
+ clkreq-n-pins {
+ pins = "gpio150";
+ function = "pcie5_clk";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio149";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake-n-pins {
+ pins = "gpio151";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
pcie6a_default: pcie6a-default-state {
clkreq-n-pins {
pins = "gpio153";
idle-state-name = "ret";
arm,psci-suspend-param = <0x00000004>;
entry-latency-us = <180>;
- exit-latency-us = <500>;
+ exit-latency-us = <320>;
min-residency-us = <600>;
};
};
#address-cells = <2>;
#size-cells = <2>;
- dma-ranges = <0 0 0 0 0x10 0>;
- ranges = <0 0 0 0 0x10 0>;
+ dma-ranges = <0 0 0 0 0x100 0>;
+ ranges = <0 0 0 0 0x100 0>;
gcc: clock-controller@100000 {
compatible = "qcom,x1e80100-gcc";
<0>,
<0>,
<0>,
+ <0>,
+ <0>,
+ <0>,
<0>;
power-domains = <&rpmhpd RPMHPD_CX>;
reg = <0 0x00fda000 0 0x4000>;
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
+ <&tcsr TCSR_USB4_1_CLKREF_EN>,
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
<&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
clock-names = "aux",
reg = <0 0x00fdf000 0 0x4000>;
clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
+ <&tcsr TCSR_USB4_2_CLKREF_EN>,
<&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>,
<&gcc GCC_USB3_TERT_PHY_PIPE_CLK>;
clock-names = "aux",
};
};
+ rng: rng@10c3000 {
+ compatible = "qcom,x1e80100-trng", "qcom,trng";
+ reg = <0x0 0x010c3000 0x0 0x1000>;
+ };
+
cnoc_main: interconnect@1500000 {
compatible = "qcom,x1e80100-cnoc-main";
reg = <0 0x01500000 0 0x14400>;
mmss_noc: interconnect@1780000 {
compatible = "qcom,x1e80100-mmss-noc";
- reg = <0 0x01780000 0 0x5B800>;
+ reg = <0 0x01780000 0 0x5b800>;
qcom,bcm-voters = <&apps_bcm_voter>;
power-domains = <&gcc GCC_PCIE_3_GDSC>;
- phys = <&pcie3_phy>;
- phy-names = "pciephy";
-
eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555
0x5555 0x5555 0x5555 0x5555>;
eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>;
};
};
- pcie3_port: pcie@0 {
+ pcie3_port0: pcie@0 {
device_type = "pci";
compatible = "pciclass,0604";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie3_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
power-domains = <&gcc GCC_PCIE_6A_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
- phys = <&pcie6a_phy>;
- phy-names = "pciephy";
-
eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
status = "disabled";
+
+ pcie6a_port0: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ phys = <&pcie6a_phy>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie6a_phy: phy@1bfc000 {
power-domains = <&gcc GCC_PCIE_5_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
- phys = <&pcie5_phy>;
- phy-names = "pciephy";
-
eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
status = "disabled";
+
+ pcie5_port0: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ phys = <&pcie5_phy>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie5_phy: phy@1c06000 {
power-domains = <&gcc GCC_PCIE_4_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
- phys = <&pcie4_phy>;
- phy-names = "pciephy";
-
eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
status = "disabled";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie4_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
status = "disabled";
};
+ cryptobam: dma-controller@1dc4000 {
+ compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+ reg = <0x0 0x01dc4000 0x0 0x28000>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ iommus = <&apps_smmu 0x480 0x0>,
+ <&apps_smmu 0x481 0x0>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely;
+ num-channels = <20>;
+ qcom,num-ees = <4>;
+ };
+
+ crypto: crypto@1dfa000 {
+ compatible = "qcom,x1e80100-qce", "qcom,sm8150-qce", "qcom,qce";
+ reg = <0x0 0x01dfa000 0x0 0x6000>;
+ dmas = <&cryptobam 4>, <&cryptobam 5>;
+ dma-names = "rx",
+ "tx";
+ iommus = <&apps_smmu 0x480 0x0>,
+ <&apps_smmu 0x481 0x0>;
+ interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "memory";
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0 0x01f40000 0 0x20000>;
nsp_noc: interconnect@320c0000 {
compatible = "qcom,x1e80100-nsp-noc";
- reg = <0 0x320C0000 0 0xe080>;
+ reg = <0 0x320c0000 0 0xe080>;
qcom,bcm-voters = <&apps_bcm_voter>;
lpass_lpicx_noc: interconnect@7430000 {
compatible = "qcom,x1e80100-lpass-lpicx-noc";
- reg = <0 0x07430000 0 0x3A200>;
+ reg = <0 0x07430000 0 0x3a200>;
qcom,bcm-voters = <&apps_bcm_voter>;
phy-names = "dp";
#sound-dai-cells = <0>;
+ sound-name-prefix = "DisplayPort0";
status = "disabled";
phy-names = "dp";
#sound-dai-cells = <0>;
+ sound-name-prefix = "DisplayPort1";
status = "disabled";
phy-names = "dp";
#sound-dai-cells = <0>;
+ sound-name-prefix = "DisplayPort2";
status = "disabled";
phy-names = "dp";
#sound-dai-cells = <0>;
+ sound-name-prefix = "DisplayPort3";
status = "disabled";
<0 0x0aec2000 0 0x1c8>;
clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
- <&dispcc DISP_CC_MDSS_AHB_CLK>;
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&tcsr TCSR_EDP_CLKREF_EN>;
clock-names = "aux",
- "cfg_ahb";
+ "cfg_ahb",
+ "ref";
power-domains = <&rpmhpd RPMHPD_MX>;
<0 0x0aec5000 0 0x1c8>;
clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
- <&dispcc DISP_CC_MDSS_AHB_CLK>;
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&tcsr TCSR_EDP_CLKREF_EN>;
clock-names = "aux",
- "cfg_ahb";
+ "cfg_ahb",
+ "ref";
power-domains = <&rpmhpd RPMHPD_MX>;
};
};
+ apss_watchdog: watchdog@17410000 {
+ compatible = "qcom,apss-wdt-x1e80100", "qcom,kpss-wdt";
+ reg = <0x0 0x17410000 0x0 0x1000>;
+ clocks = <&sleep_clk>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
+ status = "reserved"; /* Reserved by Gunyah */
+ };
+
cpucp_mbox: mailbox@17430000 {
compatible = "qcom,x1e80100-cpucp-mbox";
reg = <0 0x17430000 0 0x10000>, <0 0x18830000 0 0x10000>;
};
tsens: thermal-sensor@4a9000 {
- compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1";
+ compatible = "qcom,ipq5018-tsens";
reg = <0x004a9000 0x1000>,
<0x004a8000 0x1000>;
compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
reg = <0x08af8800 0x400>;
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq";
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq";
clocks = <&gcc GCC_USB0_MASTER_CLK>,
<&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
assigned-clock-rates = <200000000>,
<24000000>;
- interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "pwr_event";
+ interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "dm_hs_phy_irq",
+ "dp_hs_phy_irq";
resets = <&gcc GCC_USB_BCR>;
status = "disabled";
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __DTS_KAANAPALI_MAILBOX_IPCC_H
+#define __DTS_KAANAPALI_MAILBOX_IPCC_H
+
+/* Physical client IDs */
+#define IPCC_MPROC_AOP 0
+#define IPCC_MPROC_TZ 1
+#define IPCC_MPROC_MPSS 2
+#define IPCC_MPROC_LPASS 3
+#define IPCC_MPROC_SDC 4
+#define IPCC_MPROC_CDSP 5
+#define IPCC_MPROC_APSS 6
+#define IPCC_MPROC_SOCCP 13
+#define IPCC_MPROC_DCP 14
+#define IPCC_MPROC_SPSS 15
+#define IPCC_MPROC_TME 16
+#define IPCC_MPROC_WPSS 17
+
+#define IPCC_COMPUTE_L0_CDSP 2
+#define IPCC_COMPUTE_L0_APSS 3
+#define IPCC_COMPUTE_L0_GPU 4
+#define IPCC_COMPUTE_L0_CVP 8
+#define IPCC_COMPUTE_L0_CAM 9
+#define IPCC_COMPUTE_L0_CAM1 10
+#define IPCC_COMPUTE_L0_DCP 11
+#define IPCC_COMPUTE_L0_VPU 12
+#define IPCC_COMPUTE_L0_SOCCP 16
+
+#define IPCC_COMPUTE_L1_CDSP 2
+#define IPCC_COMPUTE_L1_APSS 3
+#define IPCC_COMPUTE_L1_GPU 4
+#define IPCC_COMPUTE_L1_CVP 8
+#define IPCC_COMPUTE_L1_CAM 9
+#define IPCC_COMPUTE_L1_CAM1 10
+#define IPCC_COMPUTE_L1_DCP 11
+#define IPCC_COMPUTE_L1_VPU 12
+#define IPCC_COMPUTE_L1_SOCCP 16
+
+#define IPCC_PERIPH_CDSP 2
+#define IPCC_PERIPH_APSS 3
+#define IPCC_PERIPH_PCIE0 4
+#define IPCC_PERIPH_PCIE1 5
+
+#define IPCC_FENCE_CDSP 2
+#define IPCC_FENCE_APSS 3
+#define IPCC_FENCE_GPU 4
+#define IPCC_FENCE_CVP 8
+#define IPCC_FENCE_CAM 8
+#define IPCC_FENCE_CAM1 10
+#define IPCC_FENCE_DCP 11
+#define IPCC_FENCE_VPU 20
+#define IPCC_FENCE_SOCCP 24
+
+#endif
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "kaanapali.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Kaanapali MTP";
+ compatible = "qcom,kaanapali-mtp", "qcom,kaanapali";
+ chassis-type = "handset";
+
+ aliases {
+ serial0 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ clock-frequency = <76800000>;
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32764>;
+ #clock-cells = <0>;
+ };
+
+ bi_tcxo_div2: bi-tcxo-div2-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK_A>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pmh0101-rpmh-regulators";
+ qcom,pmic-id = "B_E0";
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <4000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <3552000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3048000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l4b_1p8: ldo4 {
+ regulator-name = "vreg_l4b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3148000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10b_1p8: ldo10 {
+ regulator-name = "vreg_l10b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l11b_1p0: ldo11 {
+ regulator-name = "vreg_l11b_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1292000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18b_1p2: ldo18 {
+ regulator-name = "vreg_l18b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pmh0110-rpmh-regulators";
+ qcom,pmic-id = "D_E0";
+
+ vreg_s10d_1p0: smps10 {
+ regulator-name = "vreg_s10d_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1d_1p2: ldo1 {
+ regulator-name = "vreg_l1d_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1256000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l2d_0p9: ldo2 {
+ regulator-name = "vreg_l2d_0p9";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <958000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l3d_0p8: ldo3 {
+ regulator-name = "vreg_l3d_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l4d_1p2: ldo4 {
+ regulator-name = "vreg_l4d_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pmh0110-rpmh-regulators";
+ qcom,pmic-id = "F_E0";
+
+ vreg_s6f_0p5: smps6 {
+ regulator-name = "vreg_s6f_0p5";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <570000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s7f_1p2: smps7 {
+ regulator-name = "vreg_s7f_1p2";
+ regulator-min-microvolt = <1224000>;
+ regulator-max-microvolt = <1372000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s8f_1p8: smps8 {
+ regulator-name = "vreg_s8f_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1f_1p2: ldo1 {
+ regulator-name = "vreg_l1f_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l2f_1p2: ldo2 {
+ regulator-name = "vreg_l2f_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l3f_0p8: ldo3 {
+ regulator-name = "vreg_l3f_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <936000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l4f_0p8: ldo4 {
+ regulator-name = "vreg_l4f_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pmh0110-rpmh-regulators";
+ qcom,pmic-id = "G_E0";
+
+ vreg_s7g_0p9: smps7 {
+ regulator-name = "vreg_s7g_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s9g_1p0: smps9 {
+ regulator-name = "vreg_s9g_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1g_1p2: ldo1 {
+ regulator-name = "vreg_l1g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l2g_1p8: ldo2 {
+ regulator-name = "vreg_l2g_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l3g_1p2: ldo3 {
+ regulator-name = "vreg_l3g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l4g_0p9: ldo4 {
+ regulator-name = "vreg_l4g_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pmh0110-rpmh-regulators";
+ qcom,pmic-id = "I_E0";
+
+ vreg_s7i_0p9: smps7 {
+ regulator-name = "vreg_s7i_0p9";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <972000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2i_1p2: ldo2 {
+ regulator-name = "vreg_l2i_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l3i_0p8: ldo3 {
+ regulator-name = "vreg_l3i_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pmh0104-rpmh-regulators";
+ qcom,pmic-id = "J_E1";
+
+ vreg_s1j_0p8: smps1 {
+ regulator-name = "vreg_s1j_0p8";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2j_0p8: smps2 {
+ regulator-name = "vreg_s2j_0p8";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3j_1p2: smps3 {
+ regulator-name = "vreg_s3j_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4j_0p7: smps4 {
+ regulator-name = "vreg_s4j_0p7";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-6 {
+ compatible = "qcom,pmr735d-rpmh-regulators";
+ qcom,pmic-id = "K_E1";
+
+ vreg_l1k_0p8: ldo1 {
+ regulator-name = "vreg_l1k_0p8";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2k_0p7: ldo2 {
+ regulator-name = "vreg_l2k_0p7";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3k_1p2: ldo3 {
+ regulator-name = "vreg_l3k_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4k_1p0: ldo4 {
+ regulator-name = "vreg_l4k_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5k_0p7: ldo5 {
+ regulator-name = "vreg_l5k_0p7";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6k_1p7: ldo6 {
+ regulator-name = "vreg_l6k_1p7";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7k_0p7: ldo7 {
+ regulator-name = "vreg_l7k_0p7";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <848000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "M_E1";
+
+ vreg_l1m_1p0: ldo1 {
+ regulator-name = "vreg_l1m_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2m_1p0: ldo2 {
+ regulator-name = "vreg_l2m_1p0";
+ regulator-min-microvolt = <1096000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3m_2p8: ldo3 {
+ regulator-name = "vreg_l3m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4m_2p2: ldo4 {
+ regulator-name = "vreg_l4m_2p2";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6m_2p8: ldo6 {
+ regulator-name = "vreg_l6m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7m_2p8: ldo7 {
+ regulator-name = "vreg_l7m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-8 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "N_E1";
+
+ vreg_l1n_1p1: ldo1 {
+ regulator-name = "vreg_l1n_1p1";
+ regulator-min-microvolt = <1096000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2n_1p2: ldo2 {
+ regulator-name = "vreg_l2n_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3n_1p8: ldo3 {
+ regulator-name = "vreg_l3n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4n_1p8: ldo4 {
+ regulator-name = "vreg_l4n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5n_2p8: ldo5 {
+ regulator-name = "vreg_l5n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6n_2p8: ldo6 {
+ regulator-name = "vreg_l6n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7n_3p3: ldo7 {
+ regulator-name = "vreg_l7n_3p3";
+ regulator-min-microvolt = <3304000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&pcie0 {
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l3i_0p8>;
+ vdda-pll-supply = <&vreg_l1d_1p2>;
+
+ status = "okay";
+};
+
+&pcie_port0 {
+ wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
+};
+
+&sdhc_2 {
+ cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&vreg_l9b_2p9>;
+ vqmmc-supply = <&vreg_l8b_1p8>;
+
+ bus-width = <4>;
+ no-sdio;
+ no-mmc;
+
+ pinctrl-0 = <&sdc2_default>;
+ pinctrl-1 = <&sdc2_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <36 4>, /* NFC eSE SPI */
+ <74 1>, /* eSE */
+ <119 2>, /* SoCCP */
+ <144 4>; /* CXM UART */
+
+ pcie0_default_state: pcie0-default-state {
+ perst-n-pins {
+ pins = "gpio102";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ clkreq-n-pins {
+ pins = "gpio103";
+ function = "pcie0_clk_req_n";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake-n-pins {
+ pins = "gpio104";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 217 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1200000>;
+ vccq-supply = <&vreg_l4d_1p2>;
+ vccq-max-microamp = <1200000>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l4g_0p9>;
+ vdda-pll-supply = <&vreg_l1d_1p2>;
+
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "kaanapali.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Kaanapali QRD";
+ compatible = "qcom,kaanapali-qrd", "qcom,kaanapali";
+ chassis-type = "handset";
+
+ aliases {
+ serial0 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ clock-frequency = <76800000>;
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32764>;
+ #clock-cells = <0>;
+ };
+
+ bi_tcxo_div2: bi-tcxo-div2-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK_A>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pmh0101-rpmh-regulators";
+ qcom,pmic-id = "B_E0";
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <4000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <3552000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3048000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l4b_1p8: ldo4 {
+ regulator-name = "vreg_l4b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3148000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10b_1p8: ldo10 {
+ regulator-name = "vreg_l10b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l11b_1p0: ldo11 {
+ regulator-name = "vreg_l11b_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1292000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18b_1p2: ldo18 {
+ regulator-name = "vreg_l18b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pmh0110-rpmh-regulators";
+ qcom,pmic-id = "D_E0";
+
+ vreg_s10d_1p0: smps10 {
+ regulator-name = "vreg_s10d_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1d_1p2: ldo1 {
+ regulator-name = "vreg_l1d_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1256000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l2d_0p9: ldo2 {
+ regulator-name = "vreg_l2d_0p9";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <958000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l3d_0p8: ldo3 {
+ regulator-name = "vreg_l3d_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l4d_1p2: ldo4 {
+ regulator-name = "vreg_l4d_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pmh0110-rpmh-regulators";
+ qcom,pmic-id = "F_E0";
+
+ vreg_s6f_0p5: smps6 {
+ regulator-name = "vreg_s6f_0p5";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <570000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s7f_1p2: smps7 {
+ regulator-name = "vreg_s7f_1p2";
+ regulator-min-microvolt = <1224000>;
+ regulator-max-microvolt = <1372000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s8f_1p8: smps8 {
+ regulator-name = "vreg_s8f_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1f_1p2: ldo1 {
+ regulator-name = "vreg_l1f_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l2f_1p2: ldo2 {
+ regulator-name = "vreg_l2f_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l3f_0p8: ldo3 {
+ regulator-name = "vreg_l3f_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <936000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l4f_0p8: ldo4 {
+ regulator-name = "vreg_l4f_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pmh0110-rpmh-regulators";
+ qcom,pmic-id = "G_E0";
+
+ vreg_s7g_0p9: smps7 {
+ regulator-name = "vreg_s7g_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s9g_1p0: smps9 {
+ regulator-name = "vreg_s9g_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1g_1p2: ldo1 {
+ regulator-name = "vreg_l1g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l2g_1p8: ldo2 {
+ regulator-name = "vreg_l2g_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l3g_1p2: ldo3 {
+ regulator-name = "vreg_l3g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l4g_0p9: ldo4 {
+ regulator-name = "vreg_l4g_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pmh0110-rpmh-regulators";
+ qcom,pmic-id = "I_E0";
+
+ vreg_s7i_0p9: smps7 {
+ regulator-name = "vreg_s7i_0p9";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <972000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2i_1p2: ldo2 {
+ regulator-name = "vreg_l2i_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l3i_0p8: ldo3 {
+ regulator-name = "vreg_l3i_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pmh0104-rpmh-regulators";
+ qcom,pmic-id = "J_E1";
+
+ vreg_s1j_0p8: smps1 {
+ regulator-name = "vreg_s1j_0p8";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2j_0p8: smps2 {
+ regulator-name = "vreg_s2j_0p8";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3j_1p2: smps3 {
+ regulator-name = "vreg_s3j_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4j_0p7: smps4 {
+ regulator-name = "vreg_s4j_0p7";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-6 {
+ compatible = "qcom,pmr735d-rpmh-regulators";
+ qcom,pmic-id = "K_E1";
+
+ vreg_l1k_0p8: ldo1 {
+ regulator-name = "vreg_l1k_0p8";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2k_0p7: ldo2 {
+ regulator-name = "vreg_l2k_0p7";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3k_1p2: ldo3 {
+ regulator-name = "vreg_l3k_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4k_1p0: ldo4 {
+ regulator-name = "vreg_l4k_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5k_0p7: ldo5 {
+ regulator-name = "vreg_l5k_0p7";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6k_1p7: ldo6 {
+ regulator-name = "vreg_l6k_1p7";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7k_0p7: ldo7 {
+ regulator-name = "vreg_l7k_0p7";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <848000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "M_E1";
+
+ vreg_l1m_1p0: ldo1 {
+ regulator-name = "vreg_l1m_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2m_1p0: ldo2 {
+ regulator-name = "vreg_l2m_1p0";
+ regulator-min-microvolt = <1096000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3m_2p8: ldo3 {
+ regulator-name = "vreg_l3m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4m_2p2: ldo4 {
+ regulator-name = "vreg_l4m_2p2";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6m_2p8: ldo6 {
+ regulator-name = "vreg_l6m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7m_2p8: ldo7 {
+ regulator-name = "vreg_l7m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-8 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "N_E1";
+
+ vreg_l1n_1p1: ldo1 {
+ regulator-name = "vreg_l1n_1p1";
+ regulator-min-microvolt = <1096000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2n_1p2: ldo2 {
+ regulator-name = "vreg_l2n_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3n_1p8: ldo3 {
+ regulator-name = "vreg_l3n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4n_1p8: ldo4 {
+ regulator-name = "vreg_l4n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5n_2p8: ldo5 {
+ regulator-name = "vreg_l5n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6n_2p8: ldo6 {
+ regulator-name = "vreg_l6n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7n_3p3: ldo7 {
+ regulator-name = "vreg_l7n_3p3";
+ regulator-min-microvolt = <3304000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&sdhc_2 {
+ cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&vreg_l9b_2p9>;
+ vqmmc-supply = <&vreg_l8b_1p8>;
+
+ bus-width = <4>;
+ no-sdio;
+ no-mmc;
+
+ pinctrl-0 = <&sdc2_default>;
+ pinctrl-1 = <&sdc2_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <36 4>, /* NFC eSE SPI */
+ <74 1>, /* eSE */
+ <119 2>, /* SoCCP */
+ <144 4>; /* CXM UART */
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 217 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1200000>;
+ vccq-supply = <&vreg_l4d_1p2>;
+ vccq-max-microamp = <1200000>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l4g_0p9>;
+ vdda-pll-supply = <&vreg_l1d_1p2>;
+
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/clock/qcom,kaanapali-gcc.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
+#include <dt-bindings/firmware/qcom,scm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+#include "kaanapali-ipcc.h"
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ power-domains = <&cpu_pd0>;
+ power-domain-names = "psci";
+ clocks = <&pdp_scmi_perf 0>;
+
+ l2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ power-domains = <&cpu_pd1>;
+ power-domain-names = "psci";
+ clocks = <&pdp_scmi_perf 0>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ power-domains = <&cpu_pd2>;
+ power-domain-names = "psci";
+ clocks = <&pdp_scmi_perf 0>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ power-domains = <&cpu_pd3>;
+ power-domain-names = "psci";
+ clocks = <&pdp_scmi_perf 0>;
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ power-domains = <&cpu_pd4>;
+ power-domain-names = "psci";
+ clocks = <&pdp_scmi_perf 0>;
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ power-domains = <&cpu_pd5>;
+ power-domain-names = "psci";
+ clocks = <&pdp_scmi_perf 0>;
+ };
+
+ cpu6: cpu@10000 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x10000>;
+ enable-method = "psci";
+ next-level-cache = <&l2_1>;
+ power-domains = <&cpu_pd6>;
+ power-domain-names = "psci";
+ clocks = <&pdp_scmi_perf 1>;
+
+ l2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
+ cpu7: cpu@10100 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x10100>;
+ enable-method = "psci";
+ next-level-cache = <&l2_1>;
+ power-domains = <&cpu_pd7>;
+ power-domain-names = "psci";
+ clocks = <&pdp_scmi_perf 1>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+
+ core4 {
+ cpu = <&cpu4>;
+ };
+
+ core5 {
+ cpu = <&cpu5>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu6>;
+ };
+
+ core1 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ cluster0_c4: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "retention";
+ arm,psci-suspend-param = <0x00000004>;
+ entry-latency-us = <93>;
+ exit-latency-us = <129>;
+ min-residency-us = <560>;
+ };
+
+ cluster1_c4: cpu-sleep-1 {
+ compatible = "arm,idle-state";
+ idle-state-name = "retention";
+ arm,psci-suspend-param = <0x00000004>;
+ entry-latency-us = <172>;
+ exit-latency-us = <130>;
+ min-residency-us = <686>;
+ };
+ };
+
+ domain-idle-states {
+ cluster_cl5: cluster-sleep-0 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x01000054>;
+ entry-latency-us = <2150>;
+ exit-latency-us = <1983>;
+ min-residency-us = <9144>;
+ };
+
+ domain_ss3: domain-sleep-0 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x0200c354>;
+ entry-latency-us = <2800>;
+ exit-latency-us = <4400>;
+ min-residency-us = <10150>;
+ };
+ };
+ };
+
+ firmware {
+ scm: scm {
+ compatible = "qcom,scm-kaanapali", "qcom,scm";
+ qcom,dload-mode = <&tcsr 0x19000>;
+ interconnects = <&aggre_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ };
+
+ scmi: scmi {
+ compatible = "arm,scmi";
+ mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>;
+ mbox-names = "tx", "rx";
+ shmem = <&pdp_tx>, <&pdp_rx>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pdp_scmi_perf: protocol@13 {
+ reg = <0x13>;
+ #clock-cells = <1>;
+ };
+ };
+ };
+
+ clk_virt: interconnect-0 {
+ compatible = "qcom,kaanapali-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mc_virt: interconnect-1 {
+ compatible = "qcom,kaanapali-mc-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ memory@a0000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0x0 0xa0000000 0x0 0x0>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+
+ cpu_pd0: power-domain-cpu0 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster0_c4>;
+ };
+
+ cpu_pd1: power-domain-cpu1 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster0_c4>;
+ };
+
+ cpu_pd2: power-domain-cpu2 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster0_c4>;
+ };
+
+ cpu_pd3: power-domain-cpu3 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster0_c4>;
+ };
+
+ cpu_pd4: power-domain-cpu4 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster0_c4>;
+ };
+
+ cpu_pd5: power-domain-cpu5 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster0_c4>;
+ };
+
+ cpu_pd6: power-domain-cpu6 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster1_c4>;
+ };
+
+ cpu_pd7: power-domain-cpu7 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cluster1_c4>;
+ };
+
+ cluster_pd: power-domain-cluster {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cluster_cl5>;
+ power-domains = <&system_pd>;
+ };
+
+ system_pd: power-domain-system {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&domain_ss3>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ pdp_mem: pdp@81300000 {
+ reg = <0x0 0x81300000 0x0 0x100000>;
+ no-map;
+ };
+
+ aop_cmd_db_mem: aop-cmd-db@81c60000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x0 0x81c60000 0x0 0x20000>;
+ no-map;
+ };
+
+ smem_mem: smem@81d00000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0x81d00000 0x0 0x200000>;
+ hwlocks = <&tcsr_mutex 3>;
+ no-map;
+ };
+
+ pdp_ns_shared_mem: pdp-ns-shared@81f00000 {
+ reg = <0x0 0x81f00000 0x0 0x100000>;
+ no-map;
+ };
+
+ dsm_partition_1_mem: dsm-partition-1@84a00000 {
+ reg = <0x0 0x84a00000 0x0 0x5500000>;
+ no-map;
+ };
+
+ dsm_partition_2_mem: dsm-partition-2@89f00000 {
+ reg = <0x0 0x89f00000 0x0 0xa80000>;
+ no-map;
+ };
+
+ mpss_mem: mpss@8aa00000 {
+ reg = <0x0 0x8aa00000 0x0 0xeb00000>;
+ no-map;
+ };
+
+ q6_mpss_dtb_mem: q6-mpss-dtb@99500000 {
+ reg = <0x0 0x99500000 0x0 0x80000>;
+ no-map;
+ };
+
+ ipa_fw_mem: ipa-fw@99580000 {
+ reg = <0x0 0x99580000 0x0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: ipa-gsi@99590000 {
+ reg = <0x0 0x99590000 0x0 0xa000>;
+ no-map;
+ };
+
+ gpu_microcode_mem: gpu-microcode@9959a000 {
+ reg = <0x0 0x9959a000 0x0 0x2000>;
+ no-map;
+ };
+
+ camera_mem: camera@99600000 {
+ reg = <0x0 0x99600000 0x0 0x800000>;
+ no-map;
+ };
+
+ camera_2_mem: camera-2@99e00000 {
+ reg = <0x0 0x99e00000 0x0 0x800000>;
+ no-map;
+ };
+
+ video_mem: video@9a600000 {
+ reg = <0x0 0x9a600000 0x0 0x800000>;
+ no-map;
+ };
+
+ cvp_mem: cvp@9ae00000 {
+ reg = <0x0 0x9ae00000 0x0 0x700000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp@9b500000 {
+ reg = <0x0 0x9b500000 0x0 0x1900000>;
+ no-map;
+ };
+
+ q6_cdsp_dtb_mem: q6-cdsp-dtb@9ce00000 {
+ reg = <0x0 0x9ce00000 0x0 0x80000>;
+ no-map;
+ };
+
+ soccp_mem: soccp@a03d0000 {
+ reg = <0x0 0xa03d0000 0x0 0x500000>;
+ no-map;
+ };
+
+ soccp_dtb_mem: soccp-dtb@a08d0000 {
+ reg = <0x0 0xa08d0000 0x0 0x40000>;
+ no-map;
+ };
+
+ q6_adsp_dtb_mem: q6-adsp-dtb@a1380000 {
+ reg = <0x0 0xa1380000 0x0 0x80000>;
+ no-map;
+ };
+
+ adspslpi_mem: adspslpi@a1400000 {
+ reg = <0x0 0xa1400000 0x0 0x4c00000>;
+ no-map;
+ };
+
+ rmtfs_mem: rmtfs@d7c00000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0x0 0xd7c00000 0x0 0x400000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
+ };
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
+ ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
+
+ gcc: clock-controller@100000 {
+ compatible = "qcom,kaanapali-gcc";
+ reg = <0x0 0x00100000 0x0 0x1f4200>;
+
+ clocks = <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&sleep_clk>,
+ <&pcie0_phy>,
+ <&ufs_mem_phy 0>,
+ <&ufs_mem_phy 1>,
+ <&ufs_mem_phy 2>,
+ <0>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ qupv3_1: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x00ac0000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AXI_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+
+ iommus = <&apps_smmu 0xa3 0x0>;
+
+ dma-coherent;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ uart7: serial@a9c000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0x0 0x00a9c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart7_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+ };
+
+ ipcc: mailbox@1106000 {
+ compatible = "qcom,kaanapali-ipcc", "qcom,ipcc";
+ reg = <0x0 0x01106000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ #mbox-cells = <2>;
+ };
+
+ cnoc_main: interconnect@1500000 {
+ compatible = "qcom,kaanapali-cnoc-main";
+ reg = <0x0 0x01500000 0x0 0x1a080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ config_noc: interconnect@1600000 {
+ compatible = "qcom,kaanapali-cnoc-cfg";
+ reg = <0x0 0x01600000 0x0 0x6200>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ system_noc: interconnect@1680000 {
+ compatible = "qcom,kaanapali-system-noc";
+ reg = <0x0 0x01680000 0x0 0x1f080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ pcie_noc: interconnect@16c0000 {
+ compatible = "qcom,kaanapali-pcie-anoc";
+ reg = <0x0 0x016c0000 0x0 0x11400>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+ <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
+ };
+
+ aggre_noc: interconnect@16e0000 {
+ compatible = "qcom,kaanapali-aggre-noc";
+ reg = <0x0 0x016e0000 0x0 0x42400>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&rpmhcc RPMH_IPA_CLK>;
+ };
+
+ mmss_noc: interconnect@1780000 {
+ compatible = "qcom,kaanapali-mmss-noc";
+ reg = <0x0 0x01780000 0x0 0x5b800>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ pcie0: pcie@1c00000 {
+ device_type = "pci";
+ compatible = "qcom,kaanapali-pcie", "qcom,pcie-sm8550";
+ reg = <0x0 0x01c00000 0x0 0x3000>,
+ <0x0 0x40000000 0x0 0xf1d>,
+ <0x0 0x40000f20 0x0 0xa8>,
+ <0x0 0x40001000 0x0 0x1000>,
+ <0x0 0x40100000 0x0 0x100000>,
+ <0x0 0x01c03000 0x0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
+ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x23d00000>;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+ <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_sf_tbu",
+ "noc_aggr",
+ "cnoc_sf_axi";
+
+ resets = <&gcc GCC_PCIE_0_BCR>,
+ <&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
+ reset-names = "pci",
+ "link_down";
+
+ interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "pcie-mem",
+ "cpu-pcie";
+
+ power-domains = <&gcc GCC_PCIE_0_GDSC>;
+
+ eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
+
+ operating-points-v2 = <&pcie0_opp_table>;
+
+ iommu-map = <0 &apps_smmu 0x1400 0x1>,
+ <0x100 &apps_smmu 0x1401 0x1>;
+
+ interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ #interrupt-cells = <1>;
+
+ msi-map = <0x0 &gic_its 0x1400 0x1>,
+ <0x100 &gic_its 0x1401 0x1>;
+ msi-map-mask = <0xff00>;
+ max-link-speed = <3>;
+ linux,pci-domain = <0>;
+ num-lanes = <2>;
+ bus-range = <0x00 0xff>;
+
+ dma-coherent;
+
+ status = "disabled";
+
+ pcie0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* GEN 1 x1 */
+ opp-2500000 {
+ opp-hz = /bits/ 64 <2500000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <250000 1>;
+ };
+
+ /* GEN 1 x2 and GEN 2 x1 */
+ opp-5000000 {
+ opp-hz = /bits/ 64 <5000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <500000 1>;
+ };
+
+ /* GEN 2 x2 */
+ opp-10000000 {
+ opp-hz = /bits/ 64 <10000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1000000 1>;
+ };
+
+ /* GEN 3 x1 */
+ opp-8000000 {
+ opp-hz = /bits/ 64 <8000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <984500 1>;
+ };
+
+ /* GEN 3 x2 */
+ opp-16000000 {
+ opp-hz = /bits/ 64 <16000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <1969000 1>;
+ };
+ };
+
+ pcie_port0: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ phys = <&pcie0_phy>;
+ };
+ };
+
+ pcie0_phy: phy@1c06000 {
+ compatible = "qcom,kaanapali-qmp-gen3x2-pcie-phy";
+ reg = <0x0 0x01c06000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&tcsr TCSR_PCIE_0_CLKREF_EN>,
+ <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe";
+
+ assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ resets = <&gcc GCC_PCIE_0_PHY_BCR>,
+ <&gcc GCC_PCIE_0_NOCSR_COM_PHY_BCR>;
+ reset-names = "phy",
+ "phy_nocsr";
+
+ power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie0_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ ufs_mem_phy: phy@1d80000 {
+ compatible = "qcom,kaanapali-qmp-ufs-phy", "qcom,sm8750-qmp-ufs-phy";
+ reg = <0x0 0x01d80000 0x0 0x2000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&tcsr TCSR_UFS_CLKREF_EN>;
+
+ clock-names = "ref",
+ "ref_aux",
+ "qref";
+
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+
+ power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ ufs_mem_hc: ufs@1d84000 {
+ compatible = "qcom,kaanapali-ufshc",
+ "qcom,ufshc",
+ "jedec,ufs-2.0";
+ reg = <0x0 0x01d84000 0x0 0x3000>;
+
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&rpmhcc RPMH_LN_BB_CLK3>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ clock-names = "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+
+ operating-points-v2 = <&ufs_opp_table>;
+
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+
+ interconnects = <&aggre_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "ufs-ddr",
+ "cpu-ufs";
+
+ power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ iommus = <&apps_smmu 0x60 0x0>;
+ dma-coherent;
+
+ lanes-per-direction = <2>;
+ qcom,ice = <&ice>;
+
+ phys = <&ufs_mem_phy>;
+ phy-names = "ufsphy";
+
+ #reset-cells = <1>;
+
+ status = "disabled";
+
+ ufs_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <75000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <100000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-403000000 {
+ opp-hz = /bits/ 64 <403000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <403000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ ice: crypto@1d88000 {
+ compatible = "qcom,kaanapali-inline-crypto-engine",
+ "qcom,inline-crypto-engine";
+ reg = <0x0 0x01d88000 0x0 0x18000>;
+
+ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+ };
+
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x0 0x01f40000 0x0 0x20000>;
+ #hwlock-cells = <1>;
+ };
+
+ tcsr: clock-controller@1fc0000 {
+ compatible = "qcom,kaanapali-tcsr", "syscon";
+ reg = <0x0 0x01fc0000 0x0 0x30000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ lpass_lpiaon_noc: interconnect@7400000 {
+ compatible = "qcom,kaanapali-lpass-lpiaon-noc";
+ reg = <0x0 0x07400000 0x0 0x19080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ lpass_lpicx_noc: interconnect@7420000 {
+ compatible = "qcom,kaanapali-lpass-lpicx-noc";
+ reg = <0x0 0x07420000 0x0 0x44080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ lpass_ag_noc: interconnect@7f40000 {
+ compatible = "qcom,kaanapali-lpass-ag-noc";
+ reg = <0x0 0x07f40000 0x0 0xe080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ sdhc_2: mmc@8804000 {
+ compatible = "qcom,kaanapali-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x08804000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "core", "xo";
+
+ interconnects = <&aggre_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "sdhc-ddr", "cpu-sdhc";
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+
+ qcom,dll-config = <0x0007442c>;
+ qcom,ddr-config = <0x80040868>;
+
+ iommus = <&apps_smmu 0x540 0x0>;
+ dma-coherent;
+
+ resets = <&gcc GCC_SDCC2_BCR>;
+ status = "disabled";
+
+ sdhc2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-peak-kBps = <160000 100000>;
+ opp-avg-kBps = <50000 0>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ opp-peak-kBps = <200000 120000>;
+ opp-avg-kBps = <104000 0>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,kaanapali-pdc", "qcom,pdc";
+ reg = <0x0 0x0b220000 0x0 0x10000>,
+ <0x0 0x179600f0 0x0 0xf4>;
+
+ qcom,pdc-ranges = <0 745 38>,
+ <40 785 11>,
+ <51 527 4>,
+ <58 534 2>,
+ <61 537 20>,
+ <84 559 14>,
+ <98 609 32>,
+ <130 717 12>,
+ <142 251 5>,
+ <147 796 16>,
+ <163 783 2>,
+ <165 531 2>,
+ <167 536 1>,
+ <168 557 2>,
+ <170 415 1>,
+ <171 438 1>,
+ <172 579 1>,
+ <173 703 1>,
+ <174 708 1>,
+ <175 714 1>,
+ <176 68 1>,
+ <177 86 1>,
+ <178 96 1>,
+ <179 249 1>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ aoss_qmp: power-management@c300000 {
+ compatible = "qcom,kaanapali-aoss-qmp", "qcom,aoss-qmp";
+ reg = <0x0 0x0c300000 0x0 0x400>;
+
+ interrupts-extended = <&ipcc IPCC_MPROC_AOP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_MPROC_AOP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ #clock-cells = <0>;
+ };
+
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,kaanapali-tlmm";
+ reg = <0x0 0x0f100000 0x0 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 218>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ wakeup-parent = <&pdc>;
+
+ qup_uart7_default: qup-uart7-state {
+ /* TX, RX */
+ pins = "gpio62", "gpio63";
+ function = "qup1_se7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ sdc2_default: sdc2-default-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ card-detect-pins {
+ pins = "gpio55";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_sleep: sdc2-sleep-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ card-detect-pins {
+ pins = "gpio55";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ sram@14680000 {
+ compatible = "qcom,kaanapali-imem", "mmio-sram";
+ reg = <0x0 0x14680000 0x0 0x1000>;
+ ranges = <0x0 0x0 0x14680000 0x1000>;
+
+ no-memory-wc;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pil-sram@94c {
+ compatible = "qcom,pil-reloc-info";
+ reg = <0x94c 0xc8>;
+ };
+ };
+
+ apps_smmu: iommu@15000000 {
+ compatible = "qcom,kaanapali-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x15000000 0x0 0x100000>;
+
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>;
+
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+
+ dma-coherent;
+ };
+
+ intc: interrupt-controller@17000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x17000000 0x0 0x10000>,
+ <0x0 0x17080000 0x0 0x200000>;
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ #interrupt-cells = <3>;
+ interrupt-controller;
+
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x40000>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic_its: msi-controller@17040000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x17040000 0x0 0x20000>;
+
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ watchdog@17600000 {
+ compatible = "qcom,apss-wdt-kaanapali", "qcom,kpss-wdt";
+ reg = <0x0 0x17600000 0x0 0x1000>;
+ clocks = <&sleep_clk>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pdp0_mbox: mailbox@17610000 {
+ compatible = "qcom,kaanapali-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
+ reg = <0x0 0x17610000 0x0 0x8000>, <0x0 0x19980000 0x0 0x8000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ };
+
+ timer@17810000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0 0x17810000 0x0 0x1000>;
+
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x0 0x20000000>;
+
+ frame@17811000 {
+ reg = <0x0 0x17811000 0x1000>,
+ <0x0 0x17812000 0x1000>;
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ frame@17813000 {
+ reg = <0x0 0x17813000 0x1000>;
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ frame@17815000 {
+ reg = <0x0 0x17815000 0x1000>;
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ frame@17817000 {
+ reg = <0x0 0x17817000 0x1000>;
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ frame@17819000 {
+ reg = <0x0 0x17819000 0x1000>;
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ frame@1781b000 {
+ reg = <0x0 0x1781b000 0x1000>;
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ frame@1781d000 {
+ reg = <0x0 0x1781d000 0x1000>;
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ apps_rsc: rsc@18900000 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x0 0x18900000 0x0 0x10000>,
+ <0x0 0x18910000 0x0 0x10000>,
+ <0x0 0x18920000 0x0 0x10000>;
+ reg-names = "drv-0",
+ "drv-1",
+ "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+
+ power-domains = <&system_pd>;
+ label = "apps_rsc";
+
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 3>,
+ <SLEEP_TCS 2>,
+ <WAKE_TCS 2>,
+ <CONTROL_TCS 0>;
+
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,kaanapali-rpmh-clk";
+ #clock-cells = <1>;
+ clocks = <&xo_board>;
+ clock-names = "xo";
+ };
+
+ rpmhpd: power-controller {
+ compatible = "qcom,kaanapali-rpmhpd";
+
+ operating-points-v2 = <&rpmhpd_opp_table>;
+
+ #power-domain-cells = <1>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp-16 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ rpmhpd_opp_low_svs_d3: opp-50 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
+ };
+
+ rpmhpd_opp_low_svs_d2_1: opp-51 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2_1>;
+ };
+
+ rpmhpd_opp_low_svs_d2: opp-52 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+ };
+
+ rpmhpd_opp_low_svs_d1_1: opp-54 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1_1>;
+ };
+
+ rpmhpd_opp_low_svs_d1: opp-56 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+ };
+
+ rpmhpd_opp_low_svs_d0: opp-60 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+ };
+
+ rpmhpd_opp_low_svs: opp-64 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ rpmhpd_opp_low_svs_l0: opp-76 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L0>;
+ };
+
+ rpmhpd_opp_low_svs_l1: opp-80 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+ };
+
+ rpmhpd_opp_low_svs_l2: opp-96 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>;
+ };
+
+ rpmhpd_opp_svs: opp-128 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ rpmhpd_opp_svs_l0: opp-144 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+ };
+
+ rpmhpd_opp_svs_l1: opp-192 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ rpmhpd_opp_svs_l2: opp-224 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ };
+
+ rpmhpd_opp_nom: opp-256 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ rpmhpd_opp_nom_l1: opp-320 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ rpmhpd_opp_nom_l2: opp-336 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+ };
+
+ rpmhpd_opp_turbo: opp-384 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ rpmhpd_opp_turbo_l0: opp-400 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L0>;
+ };
+
+ rpmhpd_opp_turbo_l1: opp-416 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+
+ rpmhpd_opp_turbo_l2: opp-432 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
+ };
+
+ rpmhpd_opp_turbo_l3: opp-448 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
+ };
+
+ rpmhpd_opp_turbo_l4: opp-452 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
+ };
+
+ rpmhpd_opp_turbo_l5: opp-456 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>;
+ };
+
+ rpmhpd_opp_super_turbo_no_cpr: opp-480 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR>;
+ };
+ };
+ };
+ };
+
+ nsp_noc: interconnect@260c0000 {
+ compatible = "qcom,kaanapali-nsp-noc";
+ reg = <0x0 0x260c0000 0x0 0x21280>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ /* Cluster 0 */
+ pmu@310b3400 {
+ compatible = "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon";
+ reg = <0x0 0x310b3400 0x0 0x600>;
+
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+ operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+ cpu_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <2188000>;
+ };
+
+ opp-1 {
+ opp-peak-kBps = <5412000>;
+ };
+
+ opp-2 {
+ opp-peak-kBps = <6220000>;
+ };
+
+ opp-3 {
+ opp-peak-kBps = <6832000>;
+ };
+
+ opp-4 {
+ opp-peak-kBps = <8368000>;
+ };
+
+ opp-5 {
+ opp-peak-kBps = <10944000>;
+ };
+
+ opp-6 {
+ opp-peak-kBps = <12748000>;
+ };
+
+ opp-7 {
+ opp-peak-kBps = <14744000>;
+ };
+
+ opp-8 {
+ opp-peak-kBps = <16896000>;
+ };
+
+ opp-9 {
+ opp-peak-kBps = <19120000>;
+ };
+
+ opp-10 {
+ opp-peak-kBps = <21332000>;
+ };
+ };
+ };
+
+ /* Cluster 1 */
+ pmu@310b7400 {
+ compatible = "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon";
+ reg = <0x0 0x310b7400 0x0 0x600>;
+
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+ operating-points-v2 = <&cpu_bwmon_opp_table>;
+ };
+
+ gem_noc: interconnect@31100000 {
+ compatible = "qcom,kaanapali-gem-noc";
+ reg = <0x0 0x31100000 0x0 0x153080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ system-cache-controller@31800000 {
+ compatible = "qcom,kaanapali-llcc";
+ reg = <0x0 0x31800000 0x0 0x200000>,
+ <0x0 0x32800000 0x0 0x200000>,
+ <0x0 0x31c00000 0x0 0x200000>,
+ <0x0 0x32c00000 0x0 0x200000>,
+ <0x0 0x34800000 0x0 0x200000>,
+ <0x0 0x34c00000 0x0 0x200000>;
+ reg-names = "llcc0_base",
+ "llcc1_base",
+ "llcc2_base",
+ "llcc3_base",
+ "llcc_broadcast_base",
+ "llcc_broadcast_and_base";
+
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sram: sram@81f08000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x81f08000 0x0 0x200>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x81f08000 0x200>;
+
+ pdp_rx: scp-sram-section@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x80>;
+ };
+
+ pdp_tx: scp-sram-section@100 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x100 0x80>;
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
qcom,client-id = <1>;
qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
};
+
+ adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@9cb80000 {
+ reg = <0x0 0x9cb80000 0x0 0x800000>;
+ no-map;
+ };
};
cpus {
status = "disabled";
- pcie@0 {
+ pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
compatible = "qcom,sc7280-lpass-lpi-pinctrl";
reg = <0 0x033c0000 0x0 0x20000>,
<0 0x03550000 0x0 0x10000>;
+
+ clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "core", "audio";
+
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpass_tlmm 0 0 15>;
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
qcom,non-secure-domain;
+ memory-region = <&adsp_rpc_remote_heap_mem>;
+ qcom,vmids = <QCOM_SCM_VMID_LPASS
+ QCOM_SCM_VMID_ADSP_HEAP>;
#address-cells = <1>;
#size-cells = <0>;
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/*
+ * Lemans specific modifications required to boot in EL2.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&iris {
+ status = "disabled";
+};
+
+&remoteproc_adsp {
+ iommus = <&apps_smmu 0x3000 0x0>;
+};
+
+&remoteproc_cdsp0 {
+ iommus = <&apps_smmu 0x21c0 0x0400>;
+};
+
+&remoteproc_cdsp1 {
+ iommus = <&apps_smmu 0x29c0 0x0400>;
+};
+
+&remoteproc_gpdsp0 {
+ iommus = <&apps_smmu 0x38a0 0x0>;
+};
+
+&remoteproc_gpdsp1 {
+ iommus = <&apps_smmu 0x38c0 0x0>;
+};
stdout-path = "serial0:115200n8";
};
+ connector-0 {
+ compatible = "usb-c-connector";
+ label = "USB0-Type-C";
+ data-role = "dual";
+ power-role = "dual";
+
+ vbus-supply = <&vbus_supply_regulator_0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb0_con_hs_ep: endpoint {
+ remote-endpoint = <&usb_0_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb0_con_ss_ep: endpoint {
+ remote-endpoint = <&hd3ss3220_in_ep>;
+ };
+ };
+ };
+ };
+
edp0-connector {
compatible = "dp-connector";
label = "EDP0";
};
};
+ vbus_supply_regulator_0: regulator-vbus-supply-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus_supply_0";
+ gpio = <&expander1 2 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ };
+
vmmc_sdc: regulator-vmmc-sdc {
compatible = "regulator-fixed";
status = "okay";
};
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/sa8775p/a663_zap.mbn";
+};
+
+&i2c11 {
+ status = "okay";
+
+ usb-typec@67 {
+ compatible = "ti,hd3ss3220";
+ reg = <0x67>;
+
+ interrupts-extended = <&pmm8654au_2_gpios 5 IRQ_TYPE_EDGE_FALLING>;
+
+ id-gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&usb_id>, <&usb0_intr_state>;
+ pinctrl-names = "default";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hd3ss3220_in_ep: endpoint {
+ remote-endpoint = <&usb0_con_ss_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ hd3ss3220_out_ep: endpoint {
+ remote-endpoint = <&usb_0_dwc3_ss>;
+ };
+ };
+ };
+ };
+};
+
&i2c18 {
status = "okay";
status = "okay";
};
+&pmm8654au_2_gpios {
+ usb0_intr_state: usb0-intr-state {
+ pins = "gpio5";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ power-source = <0>;
+ };
+};
+
&qup_i2c19_default {
drive-strength = <2>;
bias-pull-up;
clock-frequency = <32768>;
};
+&spi16 {
+ status = "okay";
+
+ tpm@0 {
+ compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ };
+};
+
&tlmm {
ethernet0_default: ethernet0-default-state {
ethernet0_mdc: ethernet0-mdc-pins {
};
};
+ qup_i2c11_default: qup-i2c11-state {
+ pins = "gpio48", "gpio49";
+ function = "qup1_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
sd_cd: sd-cd-state {
pins = "gpio36";
function = "gpio";
bias-pull-up;
};
+
+ usb_id: usb-id-state {
+ pins = "gpio50";
+ function = "gpio";
+ bias-pull-up;
+ };
};
&uart10 {
};
&usb_0 {
- dr_mode = "peripheral";
-
status = "okay";
};
+&usb_0_dwc3_hs {
+ remote-endpoint = <&usb0_con_hs_ep>;
+};
+
+&usb_0_dwc3_ss {
+ remote-endpoint = <&hd3ss3220_out_ep>;
+};
+
&usb_0_hsphy {
vdda-pll-supply = <&vreg_l7a>;
vdda18-supply = <&vreg_l6c>;
};
};
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/sa8775p/a663_zap.mbn";
+};
+
&i2c11 {
clock-frequency = <400000>;
status = "okay";
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
dynamic-power-coefficient = <100>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
dynamic-power-coefficient = <100>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&l2_2>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
dynamic-power-coefficient = <100>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&l2_3>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
dynamic-power-coefficient = <100>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
qcom,freq-domain = <&cpufreq_hw 1>;
next-level-cache = <&l2_4>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
dynamic-power-coefficient = <100>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
qcom,freq-domain = <&cpufreq_hw 1>;
next-level-cache = <&l2_5>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
dynamic-power-coefficient = <100>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
qcom,freq-domain = <&cpufreq_hw 1>;
next-level-cache = <&l2_6>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
dynamic-power-coefficient = <100>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
qcom,freq-domain = <&cpufreq_hw 1>;
next-level-cache = <&l2_7>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
dynamic-power-coefficient = <100>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
};
};
- aggre1_noc: interconnect-aggre1-noc {
- compatible = "qcom,sa8775p-aggre1-noc";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
- aggre2_noc: interconnect-aggre2-noc {
- compatible = "qcom,sa8775p-aggre2-noc";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
clk_virt: interconnect-clk-virt {
compatible = "qcom,sa8775p-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
- config_noc: interconnect-config-noc {
- compatible = "qcom,sa8775p-config-noc";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
- dc_noc: interconnect-dc-noc {
- compatible = "qcom,sa8775p-dc-noc";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
- gem_noc: interconnect-gem-noc {
- compatible = "qcom,sa8775p-gem-noc";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
- gpdsp_anoc: interconnect-gpdsp-anoc {
- compatible = "qcom,sa8775p-gpdsp-anoc";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
- lpass_ag_noc: interconnect-lpass-ag-noc {
- compatible = "qcom,sa8775p-lpass-ag-noc";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
mc_virt: interconnect-mc-virt {
compatible = "qcom,sa8775p-mc-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
- mmss_noc: interconnect-mmss-noc {
- compatible = "qcom,sa8775p-mmss-noc";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
- nspa_noc: interconnect-nspa-noc {
- compatible = "qcom,sa8775p-nspa-noc";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
- nspb_noc: interconnect-nspb-noc {
- compatible = "qcom,sa8775p-nspb-noc";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
- pcie_anoc: interconnect-pcie-anoc {
- compatible = "qcom,sa8775p-pcie-anoc";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
- system_noc: interconnect-system-noc {
- compatible = "qcom,sa8775p-system-noc";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
/* Will be updated by the bootloader. */
memory@80000000 {
device_type = "memory";
#mbox-cells = <2>;
};
+ qfprom: efuse@784000 {
+ compatible = "qcom,sa8775p-qfprom", "qcom,qfprom";
+ reg = <0x0 0x00784000 0x0 0x3000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gpu_speed_bin: gpu_speed_bin@240c {
+ reg = <0x240c 0x1>;
+ bits = <0 8>;
+ };
+ };
+
gpi_dma2: dma-controller@800000 {
compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0x0 0x00800000 0x0 0x60000>;
reg = <0 0x010d2000 0 0x1000>;
};
+ config_noc: interconnect@14c0000 {
+ compatible = "qcom,sa8775p-config-noc";
+ reg = <0x0 0x014c0000 0x0 0x13080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ system_noc: interconnect@1680000 {
+ compatible = "qcom,sa8775p-system-noc";
+ reg = <0x0 0x01680000 0x0 0x15080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre1_noc: interconnect@16c0000 {
+ compatible = "qcom,sa8775p-aggre1-noc";
+ reg = <0x0 0x016c0000 0x0 0x18080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>;
+ };
+
+ aggre2_noc: interconnect@1700000 {
+ compatible = "qcom,sa8775p-aggre2-noc";
+ reg = <0x0 0x01700000 0x0 0x1b080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ clocks = <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
+ <&rpmhcc RPMH_IPA_CLK>;
+ };
+
+ pcie_anoc: interconnect@1760000 {
+ compatible = "qcom,sa8775p-pcie-anoc";
+ reg = <0x0 0x01760000 0x0 0xc080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ gpdsp_anoc: interconnect@1780000 {
+ compatible = "qcom,sa8775p-gpdsp-anoc";
+ reg = <0x0 0x01780000 0x0 0xe080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mmss_noc: interconnect@17a0000 {
+ compatible = "qcom,sa8775p-mmss-noc";
+ reg = <0x0 0x017a0000 0x0 0x40000>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x0 0x01d84000 0x0 0x3000>;
<&apps_smmu 0x481 0x00>;
};
+ crypto: crypto@1dfa000 {
+ compatible = "qcom,sa8775p-qce", "qcom,sm8150-qce", "qcom,qce";
+ reg = <0x0 0x01dfa000 0x0 0x6000>;
+ dmas = <&cryptobam 4>, <&cryptobam 5>;
+ dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x480 0x0>,
+ <&apps_smmu 0x481 0x0>;
+ interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "memory";
+ };
+
+ lpass_ag_noc: interconnect@3c40000 {
+ compatible = "qcom,sa8775p-lpass-ag-noc";
+ reg = <0x0 0x03c40000 0x0 0x17200>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
ctcu@4001000 {
compatible = "qcom,sa8775p-ctcu";
reg = <0x0 0x04001000 0x0 0x1000>;
<&apss_funnel1_out>;
};
};
+
+ port@5 {
+ reg = <5>;
+
+ funnel1_in5: endpoint {
+ remote-endpoint = <&dlct0_funnel_out>;
+ };
+ };
};
};
};
};
+ tpda@4ad3000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x4ad3000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@10 {
+ reg = <16>;
+ dlct0_tpda_in16: endpoint {
+ remote-endpoint = <&turing0_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ dlct0_tpda_out: endpoint {
+ remote-endpoint =
+ <&dlct0_funnel_in0>;
+ };
+ };
+ };
+
+ };
+
+ funnel@4ad4000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x4ad4000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ dlct0_funnel_in0: endpoint {
+ remote-endpoint = <&dlct0_tpda_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ dlct0_funnel_out: endpoint {
+ remote-endpoint = <&funnel1_in5>;
+ };
+ };
+ };
+ };
+
funnel@4b04000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x4b04000 0x0 0x1000>;
clock-names = "apb_pclk";
};
+ funnel@4b83000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x4b83000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ turing0_funnel_in1: endpoint {
+ remote-endpoint = <&turing_llm_tpdm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ turing0_funnel_out: endpoint {
+ remote-endpoint = <&dlct0_tpda_in16>;
+ };
+ };
+ };
+ };
+
etm@6040000 {
compatible = "arm,primecell";
reg = <0x0 0x6040000 0x0 0x1000>;
reg = <0x0 0x0891c000 0x0 0x84>;
};
+ dc_noc: interconnect@90e0000 {
+ compatible = "qcom,sa8775p-dc-noc";
+ reg = <0x0 0x090e0000 0x0 0x5080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ gem_noc: interconnect@9100000 {
+ compatible = "qcom,sa8775p-gem-noc";
+ reg = <0x0 0x09100000 0x0 0xf6080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
usb_0: usb@a600000 {
compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3";
reg = <0 0x0a600000 0 0xfc100>;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
+ usb-role-switch;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_0_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_0_dwc3_ss: endpoint {
+ };
+ };
+ };
};
usb_1: usb@a800000 {
reg = <0x0 0x1fc0000 0x0 0x30000>;
};
+ gpu: gpu@3d00000 {
+ compatible = "qcom,adreno-663.0", "qcom,adreno";
+ reg = <0x0 0x03d00000 0x0 0x40000>,
+ <0x0 0x03d9e000 0x0 0x1000>,
+ <0x0 0x03d61000 0x0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem",
+ "cx_dbgc";
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&adreno_smmu 0 0xc00>,
+ <&adreno_smmu 1 0xc00>;
+ operating-points-v2 = <&gpu_opp_table>;
+ qcom,gmu = <&gmu>;
+ interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "gfx-mem";
+ #cooling-cells = <2>;
+
+ nvmem-cells = <&gpu_speed_bin>;
+ nvmem-cell-names = "speed_bin";
+
+ status = "disabled";
+
+ gpu_zap_shader: zap-shader {
+ memory-region = <&pil_gpu_mem>;
+ };
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-405000000 {
+ opp-hz = /bits/ 64 <405000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <5285156>;
+ opp-supported-hw = <0x3>;
+ };
+
+ opp-530000000 {
+ opp-hz = /bits/ 64 <530000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <12484375>;
+ opp-supported-hw = <0x2>;
+ };
+
+ opp-676000000 {
+ opp-hz = /bits/ 64 <676000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ opp-peak-kBps = <8171875>;
+ opp-supported-hw = <0x1>;
+ };
+
+ opp-778000000 {
+ opp-hz = /bits/ 64 <778000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ opp-peak-kBps = <10687500>;
+ opp-supported-hw = <0x1>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ opp-peak-kBps = <12484375>;
+ opp-supported-hw = <0x1>;
+ };
+ };
+ };
+
+ gmu: gmu@3d6a000 {
+ compatible = "qcom,adreno-gmu-663.0", "qcom,adreno-gmu";
+ reg = <0x0 0x03d6a000 0x0 0x34000>,
+ <0x0 0x03de0000 0x0 0x10000>,
+ <0x0 0x0b290000 0x0 0x10000>;
+ reg-names = "gmu", "rscc", "gmu_pdc";
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+ clock-names = "gmu",
+ "cxo",
+ "axi",
+ "memnoc",
+ "ahb",
+ "hub",
+ "smmu_vote";
+ power-domains = <&gpucc GPU_CC_CX_GDSC>,
+ <&gpucc GPU_CC_GX_GDSC>;
+ power-domain-names = "cx",
+ "gx";
+ iommus = <&adreno_smmu 5 0xc00>;
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+ };
+ };
+
gpucc: clock-controller@3d90000 {
compatible = "qcom,sa8775p-gpucc";
reg = <0x0 0x03d90000 0x0 0xa000>;
port@1 {
reg = <1>;
- mdss0_dsi0_out: endpoint{ };
+ mdss0_dsi0_out: endpoint { };
};
};
status = "disabled";
};
+ nspa_noc: interconnect@260c0000 {
+ compatible = "qcom,sa8775p-nspa-noc";
+ reg = <0x0 0x260c0000 0x0 0x16080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
remoteproc_cdsp0: remoteproc@26300000 {
compatible = "qcom,sa8775p-cdsp0-pas";
reg = <0x0 0x26300000 0x0 0x10000>;
};
};
+ nspb_noc: interconnect@2a0c0000 {
+ compatible = "qcom,sa8775p-nspb-noc";
+ reg = <0x0 0x2a0c0000 0x0 0x16080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
remoteproc_cdsp1: remoteproc@2a300000 {
compatible = "qcom,sa8775p-cdsp1-pas";
- reg = <0x0 0x2A300000 0x0 0x10000>;
+ reg = <0x0 0x2a300000 0x0 0x10000>;
interrupts-extended = <&intc GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING>,
thermal-sensors = <&tsens0 5>;
+ cooling-maps {
+ map0 {
+ trip = <&gpuss0_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpuss0_alert0: trip-point0 {
temperature = <105000>;
hysteresis = <5000>;
type = "passive";
thermal-sensors = <&tsens0 6>;
+ cooling-maps {
+ map0 {
+ trip = <&gpuss1_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpuss1_alert0: trip-point0 {
temperature = <105000>;
hysteresis = <5000>;
type = "passive";
thermal-sensors = <&tsens0 7>;
+ cooling-maps {
+ map0 {
+ trip = <&gpuss2_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpuss2_alert0: trip-point0 {
temperature = <105000>;
hysteresis = <5000>;
type = "passive";
thermal-sensors = <&tsens1 5>;
+ cooling-maps {
+ map0 {
+ trip = <&gpuss3_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpuss3_alert0: trip-point0 {
temperature = <105000>;
hysteresis = <5000>;
type = "passive";
thermal-sensors = <&tsens1 6>;
+ cooling-maps {
+ map0 {
+ trip = <&gpuss4_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpuss4_alert0: trip-point0 {
temperature = <105000>;
hysteresis = <5000>;
type = "passive";
thermal-sensors = <&tsens1 7>;
+ cooling-maps {
+ map0 {
+ trip = <&gpuss5_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpuss5_alert0: trip-point0 {
temperature = <105000>;
hysteresis = <5000>;
type = "passive";
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
+ turing-llm-tpdm {
+ compatible = "qcom,coresight-static-tpdm";
+
+ qcom,cmb-element-bits = <32>;
+
+ out-ports {
+ port {
+ turing_llm_tpdm_out: endpoint {
+ remote-endpoint = <&turing0_funnel_in1>;
+ };
+ };
+ };
+ };
+
pcie0: pcie@1c00000 {
compatible = "qcom,pcie-sa8775p";
reg = <0x0 0x01c00000 0x0 0x3000>,
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
+ */
+
+/dts-v1/;
+
+#define PMIV0104_SID 7
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "milos.dtsi"
+#include "pm7550.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmiv0104.dtsi" /* PMIV0108 */
+#include "pmk8550.dtsi" /* PMK7635 */
+#include "pmr735b.dtsi"
+
+/ {
+ model = "The Fairphone (Gen. 6)";
+ compatible = "fairphone,fp6", "qcom,milos";
+ chassis-type = "handset";
+
+ aliases {
+ serial0 = &uart5;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_default>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&pm7550_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+
+ switch {
+ label = "Switch";
+ gpios = <&tlmm 107 GPIO_ACTIVE_HIGH>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_MUTE_DEVICE>;
+ };
+ };
+
+ pmic-glink {
+ compatible = "qcom,milos-pmic-glink",
+ "qcom,sm8550-pmic-glink",
+ "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ orientation-gpios = <&tlmm 131 GPIO_ACTIVE_HIGH>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+ };
+ };
+ };
+
+ vreg_ff_afvdd_2p8: regulator-ff-afvdd-2p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "ff_afvdd_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ startup-delay-us = <100>;
+
+ gpio = <&tlmm 93 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vreg_bob>;
+ };
+
+ vreg_uw_afvdd_2p8: regulator-uw-afvdd-2p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "uw_afvdd_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ startup-delay-us = <100>;
+
+ gpio = <&tlmm 23 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vreg_bob>;
+ };
+
+ vreg_uw_dvdd: regulator-uw-dvdd {
+ compatible = "regulator-fixed";
+ regulator-name = "uw_dvdd";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ startup-delay-us = <100>;
+
+ gpio = <&tlmm 28 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vreg_s1b>;
+ };
+
+ vreg_ois_avdd0_1p8: regulator-ois-avdd0-1p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "ois_avdd0_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ startup-delay-us = <100>;
+
+ gpio = <&tlmm 27 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vreg_bob>;
+ };
+
+ vreg_ois_vdd: regulator-ois-vdd {
+ compatible = "regulator-fixed";
+ regulator-name = "ois_vdd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100>;
+
+ gpio = <&tlmm 24 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vph_pwr>;
+ };
+
+ vreg_oled_dvdd_1p2: regulator-oled-dvdd-1p2 {
+ compatible = "regulator-fixed";
+ regulator-name = "oled_dvdd_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ gpio = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vreg_s2b>;
+
+ regulator-boot-on;
+ };
+
+ vreg_s1j: regulator-pm3001a-s1j {
+ compatible = "regulator-fixed";
+ regulator-name = "pm3001a_s1j";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ startup-delay-us = <1000>;
+
+ gpio = <&pmr735b_gpios 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vph_pwr>;
+
+ pinctrl-0 = <&s1j_enable_default>;
+ pinctrl-names = "default";
+ };
+
+ vreg_vtof_ldo_3p3: regulator-vtof-ldo-3p3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vtof_ldo_3p3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100>;
+
+ gpio = <&tlmm 76 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vph_pwr>;
+ };
+
+ vph_pwr: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ thermal-zones {
+ pm8008-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&pm8008>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm7550-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s1b>;
+ vdd-l2-l3-supply = <&vreg_s3b>;
+ vdd-l4-l5-supply = <&vreg_s2b>;
+ vdd-l6-supply = <&vreg_s2b>;
+ vdd-l7-supply = <&vreg_s1b>;
+ vdd-l8-supply = <&vreg_s1b>;
+ vdd-l9-l10-supply = <&vreg_s1b>;
+ vdd-l11-supply = <&vreg_s1b>;
+ vdd-l12-l14-supply = <&vreg_bob>;
+ vdd-l13-l16-supply = <&vreg_bob>;
+ vdd-l15-l17-l18-l19-l20-l21-l22-l23-supply = <&vreg_bob>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "b";
+
+ vreg_s1b: smps1 {
+ regulator-name = "vreg_s1b";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2080000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2b: smps2 {
+ regulator-name = "vreg_s2b";
+ regulator-min-microvolt = <1256000>;
+ regulator-max-microvolt = <1408000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3b: smps3 {
+ regulator-name = "vreg_s3b";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <1040000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b: ldo2 {
+ regulator-name = "vreg_l2b";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3b: ldo3 {
+ regulator-name = "vreg_l3b";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4b: ldo4 {
+ regulator-name = "vreg_l4b";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b: ldo5 {
+ regulator-name = "vreg_l5b";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b: ldo7 {
+ regulator-name = "vreg_l7b";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b: ldo8 {
+ regulator-name = "vreg_l8b";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b: ldo9 {
+ regulator-name = "vreg_l9b";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10b: ldo10 {
+ regulator-name = "vreg_l10b";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b: ldo11 {
+ regulator-name = "vreg_l11b";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b: ldo12 {
+ regulator-name = "vreg_l12b";
+ /*
+ * Skip voltage voting for UFS VCC.
+ */
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b: ldo13 {
+ regulator-name = "vreg_l13b";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b: ldo14 {
+ regulator-name = "vreg_l14b";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b: ldo15 {
+ regulator-name = "vreg_l15b";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b: ldo16 {
+ regulator-name = "vreg_l16b";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b: ldo17 {
+ regulator-name = "vreg_l17b";
+ regulator-min-microvolt = <3104000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18b: ldo18 {
+ regulator-name = "vreg_l18b";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l19b: ldo19 {
+ regulator-name = "vreg_l19b";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l20b: ldo20 {
+ regulator-name = "vreg_l20b";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l21b: ldo21 {
+ regulator-name = "vreg_l21b";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l22b: ldo22 {
+ regulator-name = "vreg_l22b";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l23b: ldo23 {
+ regulator-name = "vreg_l23b";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob: bob {
+ regulator-name = "vreg_bob";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s3b>;
+ vdd-l3-supply = <&vreg_s3b>;
+
+ qcom,pmic-id = "c";
+
+ vreg_l2c: ldo2 {
+ regulator-name = "vreg_l2c";
+ regulator-min-microvolt = <320000>;
+ regulator-max-microvolt = <650000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pmr735b-rpmh-regulators";
+
+ vdd-l1-l2-supply= <&vreg_s3b>;
+ vdd-l3-supply= <&vreg_s3b>;
+ vdd-l4-supply= <&vreg_s1b>;
+ vdd-l5-supply= <&vreg_s2b>;
+ vdd-l6-supply= <&vreg_s2b>;
+ vdd-l7-l8-supply= <&vreg_s2b>;
+ vdd-l9-supply= <&vreg_s3b>;
+ vdd-l10-supply= <&vreg_s1b>;
+ vdd-l11-supply= <&vreg_s3b>;
+ vdd-l12-supply= <&vreg_s3b>;
+
+ qcom,pmic-id = "f";
+
+ vreg_l1f: ldo1 {
+ regulator-name = "vreg_l1f";
+ regulator-min-microvolt = <852000>;
+ regulator-max-microvolt = <950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f: ldo2 {
+ regulator-name = "vreg_l2f";
+ regulator-min-microvolt = <751000>;
+ regulator-max-microvolt = <824000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f: ldo3 {
+ regulator-name = "vreg_l3f";
+ regulator-min-microvolt = <650000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4f: ldo4 {
+ regulator-name = "vreg_l4f";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5f: ldo5 {
+ regulator-name = "vreg_l5f";
+ regulator-min-microvolt = <1140000>;
+ regulator-max-microvolt = <1260000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6f: ldo6 {
+ regulator-name = "vreg_l6f";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7f: ldo7 {
+ regulator-name = "vreg_l7f";
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8f: ldo8 {
+ regulator-name = "vreg_l8f";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9f: ldo9 {
+ regulator-name = "vreg_l9f";
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10f: ldo10 {
+ regulator-name = "vreg_l10f";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11f: ldo11 {
+ regulator-name = "vreg_l11f";
+ regulator-min-microvolt = <320000>;
+ regulator-max-microvolt = <864000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&gcc {
+ protected-clocks = <GCC_PCIE_1_AUX_CLK>, <GCC_PCIE_1_AUX_CLK_SRC>,
+ <GCC_PCIE_1_CFG_AHB_CLK>, <GCC_PCIE_1_MSTR_AXI_CLK>,
+ <GCC_PCIE_1_PHY_RCHNG_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>,
+ <GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>,
+ <GCC_PCIE_1_PIPE_DIV2_CLK>, <GCC_PCIE_1_PIPE_DIV2_CLK_SRC>,
+ <GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
+};
+
+&i2c1 {
+ /* Samsung NFC @ 0x27 */
+
+ status = "okay";
+};
+
+&i2c3 {
+ /* AW88261FCR amplifier (top) @ 0x34 */
+ /* AW88261FCR amplifier (bottom) @ 0x35 */
+
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+
+ pm8008: pmic@8 {
+ compatible = "qcom,pm8008";
+ reg = <0x8>;
+
+ interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_RISING>;
+ reset-gpios = <&pmr735b_gpios 3 GPIO_ACTIVE_LOW>;
+
+ vdd-l1-l2-supply = <&vreg_s2b>;
+ vdd-l3-l4-supply = <&vreg_bob>;
+ vdd-l5-supply = <&vreg_bob>;
+ vdd-l6-supply = <&vreg_s1b>;
+ vdd-l7-supply = <&vreg_bob>;
+
+ pinctrl-0 = <&pm8008_int_default>, <&pm8008_reset_n_default>;
+ pinctrl-names = "default";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pm8008 0 0 2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ #thermal-sensor-cells = <0>;
+
+ regulators {
+ vreg_l1p: ldo1 {
+ regulator-name = "vreg_l1p";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vreg_l2p: ldo2 {
+ regulator-name = "vreg_l2p";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1144000>;
+ };
+
+ vreg_l3p: ldo3 {
+ regulator-name = "vreg_l3p";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ vreg_l4p: ldo4 {
+ regulator-name = "vreg_l4p";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ vreg_l5p: ldo5 {
+ regulator-name = "vreg_l5p";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ vreg_l6p: ldo6 {
+ regulator-name = "vreg_l6p";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1896000>;
+ };
+
+ vreg_l7p: ldo7 {
+ regulator-name = "vreg_l7p";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3400000>;
+ };
+ };
+ };
+
+ /* VL53L3 ToF @ 0x29 */
+ /* AW86938FCR vibrator @ 0x5a */
+};
+
+&pm8550vs_c {
+ status = "okay";
+};
+
+&pmiv0104_eusb2_repeater {
+ vdd18-supply = <&vreg_l7b>;
+ vdd3-supply = <&vreg_l17b>;
+
+ qcom,tune-res-fsdif = /bits/ 8 <0x5>;
+ qcom,tune-usb2-amplitude = /bits/ 8 <0x8>;
+ qcom,tune-usb2-disc-thres = /bits/ 8 <0x7>;
+ qcom,tune-usb2-preem = /bits/ 8 <0x6>;
+};
+
+&pmr735b_gpios {
+ s1j_enable_default: s1j-enable-default-state {
+ pins = "gpio1";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ power-source = <0>;
+ bias-disable;
+ output-low;
+ };
+
+ pm8008_reset_n_default: pm8008-reset-n-default-state {
+ pins = "gpio3";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ bias-pull-down;
+ };
+};
+
+&pm7550_gpios {
+ volume_up_default: volume-up-default-state {
+ pins = "gpio6";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ power-source = <1>;
+ bias-pull-up;
+ };
+};
+
+&pm7550_flash {
+ status = "okay";
+
+ led-0 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ led-sources = <1>, <4>;
+ led-max-microamp = <350000>;
+ flash-max-microamp = <1500000>;
+ flash-max-timeout-us = <400000>;
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/milos/fairphone/fp6/adsp.mbn",
+ "qcom/milos/fairphone/fp6/adsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/milos/fairphone/fp6/cdsp.mbn",
+ "qcom/milos/fairphone/fp6/cdsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/milos/fairphone/fp6/modem.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_wpss {
+ firmware-name = "qcom/milos/fairphone/fp6/wpss.mbn";
+
+ status = "okay";
+};
+
+&sdhc_2 {
+ cd-gpios = <&tlmm 65 GPIO_ACTIVE_HIGH>;
+
+ vmmc-supply = <&vreg_l13b>;
+ vqmmc-supply = <&vreg_l23b>;
+ no-sdio;
+ no-mmc;
+
+ pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>;
+ pinctrl-names = "default", "sleep";
+
+ status = "okay";
+};
+
+&spi0 {
+ /* Eswin EPH8621 touchscreen @ 0 */
+};
+
+&tlmm {
+ gpio-reserved-ranges = <8 4>, /* Fingerprint SPI */
+ <13 1>, /* NC */
+ <63 2>; /* WLAN UART */
+
+ sdc2_card_det_n: sdc2-card-det-state {
+ pins = "gpio65";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ pm8008_int_default: pm8008-int-default-state {
+ pins = "gpio125";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usb_1 {
+ dr_mode = "otg";
+
+ /* USB 2.0 only, HW does not support USB 3.x */
+ qcom,select-utmi-as-pipe-clk;
+
+ status = "okay";
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l2b>;
+ vdda12-supply = <&vreg_l4b>;
+
+ phys = <&pmiv0104_eusb2_repeater>;
+
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
+ */
+
+#include <dt-bindings/clock/qcom,milos-camcc.h>
+#include <dt-bindings/clock/qcom,milos-dispcc.h>
+#include <dt-bindings/clock/qcom,milos-gcc.h>
+#include <dt-bindings/clock/qcom,milos-gpucc.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm8650-tcsr.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/firmware/qcom,scm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,milos-rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/power/qcom,rpmhpd.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <76800000>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32764>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a520";
+ reg = <0x0 0x0>;
+
+ clocks = <&cpufreq_hw 0>;
+
+ power-domains = <&cpu_pd0>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+
+ qcom,freq-domain = <&cpufreq_hw 0>;
+
+ #cooling-cells = <2>;
+
+ l2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_0>;
+
+ l3_0: l3-cache {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-unified;
+ };
+ };
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a520";
+ reg = <0x0 0x100>;
+
+ clocks = <&cpufreq_hw 0>;
+
+ power-domains = <&cpu_pd1>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+
+ qcom,freq-domain = <&cpufreq_hw 0>;
+
+ #cooling-cells = <2>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a520";
+ reg = <0x0 0x200>;
+
+ clocks = <&cpufreq_hw 0>;
+
+ power-domains = <&cpu_pd2>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&l2_2>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+
+ qcom,freq-domain = <&cpufreq_hw 0>;
+
+ #cooling-cells = <2>;
+
+ l2_2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_0>;
+ };
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a520";
+ reg = <0x0 0x300>;
+
+ clocks = <&cpufreq_hw 0>;
+
+ power-domains = <&cpu_pd3>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&l2_2>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+
+ qcom,freq-domain = <&cpufreq_hw 0>;
+
+ #cooling-cells = <2>;
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x400>;
+
+ clocks = <&cpufreq_hw 1>;
+
+ power-domains = <&cpu_pd4>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&l2_4>;
+ capacity-dmips-mhz = <1670>;
+ dynamic-power-coefficient = <264>;
+
+ qcom,freq-domain = <&cpufreq_hw 1>;
+
+ #cooling-cells = <2>;
+
+ l2_4: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_0>;
+ };
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x500>;
+
+ clocks = <&cpufreq_hw 1>;
+
+ power-domains = <&cpu_pd5>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&l2_5>;
+ capacity-dmips-mhz = <1670>;
+ dynamic-power-coefficient = <264>;
+
+ qcom,freq-domain = <&cpufreq_hw 1>;
+
+ #cooling-cells = <2>;
+
+ l2_5: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_0>;
+ };
+ };
+
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x600>;
+
+ clocks = <&cpufreq_hw 1>;
+
+ power-domains = <&cpu_pd6>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&l2_6>;
+ capacity-dmips-mhz = <1670>;
+ dynamic-power-coefficient = <264>;
+
+ qcom,freq-domain = <&cpufreq_hw 1>;
+
+ #cooling-cells = <2>;
+
+ l2_6: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_0>;
+ };
+ };
+
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x700>;
+
+ clocks = <&cpufreq_hw 2>;
+
+ power-domains = <&cpu_pd7>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&l2_7>;
+ capacity-dmips-mhz = <1670>;
+ dynamic-power-coefficient = <287>;
+
+ qcom,freq-domain = <&cpufreq_hw 2>;
+
+ #cooling-cells = <2>;
+
+ l2_7: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_0>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+
+ core1 {
+ cpu = <&cpu5>;
+ };
+
+ core2 {
+ cpu = <&cpu6>;
+ };
+ };
+
+ cluster2 {
+ core0 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ silver_cpu_sleep_0: cpu-sleep-0-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "pc";
+ arm,psci-suspend-param = <0x40000003>;
+ entry-latency-us = <250>;
+ exit-latency-us = <700>;
+ min-residency-us = <5200>;
+ local-timer-stop;
+ };
+
+ silver_cpu_sleep_1: cpu-sleep-0-1 {
+ compatible = "arm,idle-state";
+ idle-state-name = "silver-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <550>;
+ exit-latency-us = <750>;
+ min-residency-us = <6700>;
+ local-timer-stop;
+ };
+
+ gold_cpu_sleep_0: cpu-sleep-1-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "silver-power-collapse";
+ arm,psci-suspend-param = <0x40000003>;
+ entry-latency-us = <400>;
+ exit-latency-us = <900>;
+ min-residency-us = <5511>;
+ local-timer-stop;
+ };
+
+ gold_cpu_sleep_1: cpu-sleep-1-1 {
+ compatible = "arm,idle-state";
+ idle-state-name = "gold-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <600>;
+ exit-latency-us = <1300>;
+ min-residency-us = <8136>;
+ local-timer-stop;
+ };
+
+ gold_plus_cpu_sleep_0: cpu-sleep-2-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "gold-plus-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <600>;
+ exit-latency-us = <1500>;
+ min-residency-us = <8551>;
+ local-timer-stop;
+ };
+ };
+
+ domain-idle-states {
+ cluster_sleep_0: cluster-sleep-0 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x41000044>;
+ entry-latency-us = <750>;
+ exit-latency-us = <2350>;
+ min-residency-us = <9144>;
+ };
+
+ cluster_sleep_1: cluster-sleep-1 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x41003344>;
+ entry-latency-us = <2800>;
+ exit-latency-us = <4400>;
+ min-residency-us = <10150>;
+ };
+ };
+ };
+
+ firmware {
+ scm: scm {
+ compatible = "qcom,scm-milos", "qcom,scm";
+ qcom,dload-mode = <&tcsr 0x19000>;
+ };
+ };
+
+ clk_virt: interconnect-0 {
+ compatible = "qcom,milos-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mc_virt: interconnect-1 {
+ compatible = "qcom,milos-mc-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0 0 0 0>;
+ };
+
+ pmu-a520 {
+ compatible = "arm,cortex-a520-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
+ };
+
+ pmu-a720 {
+ compatible = "arm,cortex-a720-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+
+ cpu_pd0: power-domain-cpu0 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>;
+ };
+
+ cpu_pd1: power-domain-cpu1 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>;
+ };
+
+ cpu_pd2: power-domain-cpu2 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>;
+ };
+
+ cpu_pd3: power-domain-cpu3 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>;
+ };
+
+ cpu_pd4: power-domain-cpu4 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>;
+ };
+
+ cpu_pd5: power-domain-cpu5 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>;
+ };
+
+ cpu_pd6: power-domain-cpu6 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>;
+ };
+
+ cpu_pd7: power-domain-cpu7 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&gold_plus_cpu_sleep_0>;
+ };
+
+ cluster_pd: power-domain-cluster {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gunyah_hyp_mem: gunyah-hyp-region@80000000 {
+ reg = <0x0 0x80000000 0x0 0xe00000>;
+ no-map;
+ };
+
+ xbl_sc_mem: xbl-sc-region@81800000 {
+ reg = <0x0 0x81800000 0x0 0x40000>;
+ no-map;
+ };
+
+ cpucp_fw_mem: cpucp-fw-region@81840000 {
+ reg = <0x0 0x81840000 0x0 0x1c0000>;
+ no-map;
+ };
+
+ xbl_dtlog_mem: xbl-dtlog-region@81a00000 {
+ reg = <0x0 0x81a00000 0x0 0x40000>;
+ no-map;
+ };
+
+ xbl_ramdump_mem: xbl-ramdump-region@81a40000 {
+ reg = <0x0 0x81a40000 0x0 0x1c0000>;
+ no-map;
+ };
+
+ aop_image_mem: aop-image-region@81c00000 {
+ reg = <0x0 0x81c00000 0x0 0x60000>;
+ no-map;
+ };
+
+ aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x0 0x81c60000 0x0 0x20000>;
+ no-map;
+ };
+
+ aop_config_mem: aop-config-region@81c80000 {
+ reg = <0x0 0x81c80000 0x0 0x20000>;
+ no-map;
+ };
+
+ tme_crash_dump_mem: tme-crash-dump-region@81ca0000 {
+ reg = <0x0 0x81ca0000 0x0 0x40000>;
+ no-map;
+ };
+
+ tme_log_mem: tme-log-region@81ce0000 {
+ reg = <0x0 0x81ce0000 0x0 0x4000>;
+ no-map;
+ };
+
+ uefi_log_mem: uefi-log-region@81ce4000 {
+ reg = <0x0 0x81ce4000 0x0 0x10000>;
+ no-map;
+ };
+
+ chipinfo_mem: chipinfo-region@81cf4000 {
+ reg = <0x0 0x81cf4000 0x0 0x1000>;
+ no-map;
+ };
+
+ secdata_apss_mem: secdata-apss-region@81cff000 {
+ reg = <0x0 0x81cff000 0x0 0x1000>;
+ no-map;
+ };
+
+ smem_mem: smem-region@81d00000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0x81d00000 0x0 0x200000>;
+ hwlocks = <&tcsr_mutex 3>;
+ no-map;
+ };
+
+ adsp_mhi_mem: adsp-mhi-region@81f00000 {
+ reg = <0x0 0x81f00000 0x0 0x20000>;
+ no-map;
+ };
+
+ pvm_fw_mem: pvm-fw-region@824a0000 {
+ reg = <0x0 0x824a0000 0x0 0x100000>;
+ no-map;
+ };
+
+ hyp_mem_database_mem: hyp-mem-database-region@825a0000 {
+ reg = <0x0 0x825a0000 0x0 0x60000>;
+ no-map;
+ };
+
+ global_sync_mem: global-sync-region@82600000 {
+ reg = <0x0 0x82600000 0x0 0x100000>;
+ no-map;
+ };
+
+ tz_stat_mem: tz-stat-region@82700000 {
+ reg = <0x0 0x82700000 0x0 0x100000>;
+ no-map;
+ };
+
+ qdss_apps_mem: qdss-apps-region@82800000 {
+ reg = <0x0 0x82800000 0x0 0x2000000>;
+ reusable;
+ };
+
+ mpss_mem: mpss-region@8ac00000 {
+ reg = <0x0 0x8ac00000 0x0 0xe600000>;
+ no-map;
+ };
+
+ q6_mpss_dtb_mem: q6-mpss-dtb-region@99200000 {
+ reg = <0x0 0x99200000 0x0 0x80000>;
+ no-map;
+ };
+
+ q6_adsp_dtb_mem: q6-adsp-dtb-region@99280000 {
+ reg = <0x0 0x99280000 0x0 0x80000>;
+ no-map;
+ };
+
+ adspslpi_mem: adspslpi-region@99300000 {
+ reg = <0x0 0x99300000 0x0 0x2800000>;
+ no-map;
+ };
+
+ wpss_mem: wpss-region@9bb00000 {
+ reg = <0x0 0x9bb00000 0x0 0x1900000>;
+ no-map;
+ };
+
+ video_mem: video-region@9d400000 {
+ reg = <0x0 0x9d400000 0x0 0x700000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp-region@9db00000 {
+ reg = <0x0 0x9db00000 0x0 0xf00000>;
+ no-map;
+ };
+
+ q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9ea00000 {
+ reg = <0x0 0x9ea00000 0x0 0x80000>;
+ no-map;
+ };
+
+ ipa_fw_mem: ipa-fw-region@9ea80000 {
+ reg = <0x0 0x9ea80000 0x0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: ipa-gsi-region@9ea90000 {
+ reg = <0x0 0x9ea90000 0x0 0xa000>;
+ no-map;
+ };
+
+ gpu_microcode_mem: gpu-microcode-region@9ea9a000 {
+ reg = <0x0 0x9ea9a000 0x0 0x2000>;
+ no-map;
+ };
+
+ camera_mem: camera-region@9eb00000 {
+ reg = <0x0 0x9eb00000 0x0 0x800000>;
+ no-map;
+ };
+
+ wlan_msa_mem: wlan-msa-region@a6400000 {
+ reg = <0x0 0xa6400000 0x0 0xc00000>;
+ no-map;
+ };
+
+ cpusys_vm_mem: cpusys-vm-region@e0600000 {
+ reg = <0x0 0xe0600000 0x0 0x400000>;
+ no-map;
+ };
+
+ rmtfs_mem: rmtfs@e1f00000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0x0 0xe1f00000 0x0 0x600000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
+ };
+
+ qtee_mem: qtee-region@e8900000 {
+ reg = <0x0 0xe8900000 0x0 0x500000>;
+ no-map;
+ };
+
+ tags_mem: tags-region@e8e00000 {
+ reg = <0x0 0xe8e00000 0x0 0x700000>;
+ no-map;
+ };
+
+ trusted_apps_mem: trusted-apps-region@e9500000 {
+ reg = <0x0 0xe9500000 0x0 0x1200000>;
+ no-map;
+ };
+ };
+
+ smp2p-adsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <443>, <429>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ smp2p_adsp_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_adsp_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-cdsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <94>, <432>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ smp2p_cdsp_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_cdsp_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-modem {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ smp2p_modem_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_modem_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_ipa_out: ipa-ap-to-modem {
+ qcom,entry-name = "ipa";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_ipa_in: ipa-modem-to-ap {
+ qcom,entry-name = "ipa";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-wpss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <617>, <616>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_WPSS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <13>;
+
+ smp2p_wpss_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_wpss_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_wlan_out: wlan-ap-to-wpss {
+ qcom,entry-name = "wlan";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_wlan_in: wlan-wpss-to-ap {
+ qcom,entry-name = "wlan";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0 0 0 0 0x10 0>;
+ ranges = <0 0 0 0 0x10 0>;
+
+ gcc: clock-controller@100000 {
+ compatible = "qcom,milos-gcc";
+ reg = <0x0 0x00100000 0x0 0x1f4200>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <0>, /* pcie_0_pipe_clk */
+ <0>, /* pcie_1_pipe_clk */
+ <0>, /* ufs_phy_rx_symbol_0_clk */
+ <0>, /* ufs_phy_rx_symbol_1_clk */
+ <0>, /* ufs_phy_tx_symbol_0_clk */
+ <0>; /* usb3_phy_wrapper_gcc_usb30_pipe_clk */
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ ipcc: mailbox@405000 {
+ compatible = "qcom,milos-ipcc", "qcom,ipcc";
+ reg = <0x0 0x00405000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ #mbox-cells = <2>;
+ };
+
+ gpi_dma1: dma-controller@800000 {
+ compatible = "qcom,milos-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x00800000 0x0 0x60000>;
+
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ dma-channels = <12>;
+ dma-channel-mask = <0x3f>;
+ #dma-cells = <3>;
+
+ iommus = <&apps_smmu 0x36 0x0>;
+ dma-coherent;
+ };
+
+ qupv3_id_1: geniqup@8c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x008c0000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core";
+
+ iommus = <&apps_smmu 0x23 0>;
+
+ dma-coherent;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ i2c7: i2c@880000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00880000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_cfg SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c7_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart11: serial@890000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00890000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_cfg SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart11_default>, <&qup_uart11_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+ };
+
+ gpi_dma0: dma-controller@a00000 {
+ compatible = "qcom,milos-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x00a00000 0x0 0x60000>;
+
+ interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ dma-channels = <12>;
+ dma-channel-mask = <0x3e>;
+ #dma-cells = <3>;
+
+ iommus = <&apps_smmu 0x576 0x0>;
+ dma-coherent;
+ };
+
+ qupv3_id_0: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x00ac0000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core";
+
+ iommus = <&apps_smmu 0x563 0>;
+
+ dma-coherent;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ spi0: spi@a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a80000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c1: i2c@a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a84000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c1_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c3: i2c@a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a8c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c3_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart5: serial@a94000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0x0 0x00a94000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart5_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+ };
+
+ rng: rng@10c3000 {
+ compatible = "qcom,milos-trng", "qcom,trng";
+ reg = <0x0 0x010c3000 0x0 0x1000>;
+ };
+
+ mmss_noc: interconnect@1400000 {
+ compatible = "qcom,milos-mmss-noc";
+ reg = <0x0 0x01400000 0x0 0xdb800>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ cnoc_main: interconnect@1500000 {
+ compatible = "qcom,milos-cnoc-main";
+ reg = <0x0 0x01500000 0x0 0x14400>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ cnoc_cfg: interconnect@1600000 {
+ compatible = "qcom,milos-cnoc-cfg";
+ reg = <0x0 0x01600000 0x0 0x6e00>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ system_noc: interconnect@1680000 {
+ compatible = "qcom,milos-system-noc";
+ reg = <0x0 0x01680000 0x0 0x40000>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ pcie_anoc: interconnect@16c0000 {
+ compatible = "qcom,milos-pcie-anoc";
+ reg = <0x0 0x016c0000 0x0 0x12400>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+ <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre1_noc: interconnect@16e0000 {
+ compatible = "qcom,milos-aggre1-noc";
+ reg = <0x0 0x016e0000 0x0 0x16400>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre2_noc: interconnect@1700000 {
+ compatible = "qcom,milos-aggre2-noc";
+ reg = <0x0 0x01700000 0x0 0x1f400>;
+ #interconnect-cells = <2>;
+ clocks = <&rpmhcc RPMH_IPA_CLK>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x0 0x01f40000 0x0 0x20000>;
+
+ #hwlock-cells = <1>;
+ };
+
+ tcsr: clock-controller@1fc0000 {
+ compatible = "qcom,milos-tcsr", "syscon";
+ reg = <0x0 0x01fc0000 0x0 0xa0000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ remoteproc_adsp: remoteproc@3000000 {
+ compatible = "qcom,milos-adsp-pas";
+ reg = <0x0 0x03000000 0x0 0x10000>;
+
+ interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd RPMHPD_LCX>,
+ <&rpmhpd RPMHPD_LMX>;
+ power-domain-names = "lcx",
+ "lmx";
+
+ interconnects = <&lpass_ag_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_adsp_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "lpass";
+ qcom,remote-pid = <2>;
+ };
+ };
+
+ lpass_ag_noc: interconnect@3c40000 {
+ compatible = "qcom,milos-lpass-ag-noc";
+ reg = <0x0 0x03c40000 0x0 0x17200>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ gpucc: clock-controller@3d90000 {
+ compatible = "qcom,milos-gpucc";
+ reg = <0x0 0x03d90000 0x0 0x9800>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ adreno_smmu: iommu@3da0000 {
+ compatible = "qcom,milos-smmu-500", "qcom,adreno-smmu",
+ "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x03da0000 0x0 0x40000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>;
+ clock-names = "hlos",
+ "bus",
+ "iface",
+ "ahb";
+ power-domains = <&gpucc GPU_CC_CX_GDSC>;
+ dma-coherent;
+ };
+
+ remoteproc_mpss: remoteproc@4080000 {
+ compatible = "qcom,milos-mpss-pas";
+ reg = <0x0 0x04080000 0x0 0x10000>;
+
+ interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>,
+ <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MSS>;
+ power-domain-names = "cx",
+ "mss";
+
+ interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ memory-region = <&mpss_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_modem_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "mpss";
+ qcom,remote-pid = <1>;
+ };
+ };
+
+ sdhc_2: mmc@8804000 {
+ compatible = "qcom,milos-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x08804000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "hc_irq",
+ "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface",
+ "core",
+ "xo";
+
+ interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_cfg SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+
+ iommus = <&apps_smmu 0x540 0>;
+
+ bus-width = <4>;
+
+ qcom,dll-config = <0x0007442c>;
+ qcom,ddr-config = <0x80040868>;
+
+ dma-coherent;
+
+ status = "disabled";
+
+ sdhc2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ usb_1_hsphy: phy@88e3000 {
+ compatible = "qcom,milos-snps-eusb2-phy",
+ "qcom,sm8550-snps-eusb2-phy";
+ reg = <0x0 0x088e3000 0x0 0x154>;
+ #phy-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+ status = "disabled";
+ };
+
+ remoteproc_wpss: remoteproc@8a00000 {
+ compatible = "qcom,milos-wpss-pas";
+ reg = <0x0 0x08a00000 0x0 0x10000>;
+
+ interrupts-extended = <&intc GIC_SPI 579 IRQ_TYPE_EDGE_RISING 0>,
+ <&smp2p_wpss_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_wpss_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_wpss_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_wpss_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_wpss_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MX>;
+ power-domain-names = "cx",
+ "mx";
+
+ memory-region = <&wpss_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_wpss_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_WPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "wpss";
+ qcom,remote-pid = <13>;
+ };
+ };
+
+ usb_1: usb@a600000 {
+ compatible = "qcom,milos-dwc3", "qcom,snps-dwc3";
+ reg = <0x0 0x0a600000 0x0 0xfc000>;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "xo";
+
+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&intc GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 25 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dwc_usb3",
+ "pwr_event",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
+
+ iommus = <&apps_smmu 0x40 0x0>;
+ power-domains = <&gcc USB30_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+ interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_cfg SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "usb-ddr", "apps-usb";
+
+ phys = <&usb_1_hsphy>;
+ phy-names = "usb2-phy";
+
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,dis_enblslpm_quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,has-lpm-erratum;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,is-utmi-l1-suspend;
+ snps,parkmode-disable-ss-quirk;
+ tx-fifo-resize;
+ dma-coherent;
+ usb-role-switch;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs: endpoint {
+ };
+ };
+ };
+ };
+
+ videocc: clock-controller@aaf0000 {
+ compatible = "qcom,milos-videocc";
+ reg = <0x0 0x0aaf0000 0x0 0x10000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>,
+ <&gcc GCC_VIDEO_AHB_CLK>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ camcc: clock-controller@adb0000 {
+ compatible = "qcom,milos-camcc";
+ reg = <0x0 0x0adb0000 0x0 0x40000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <&gcc GCC_CAMERA_AHB_CLK>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,milos-dispcc";
+ reg = <0x0 0x0af00000 0x0 0x20000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
+ <0>, /* dsi0_phy_pll_out_byteclk */
+ <0>, /* dsi0_phy_pll_out_dsiclk */
+ <0>, /* dp0_phy_pll_link_clk */
+ <0>; /* dp0_phy_pll_vco_div_clk */
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,milos-pdc", "qcom,pdc";
+ reg = <0x0 0x0b220000 0x0 0x30000>,
+ <0x0 0x174000f0 0x0 0x64>;
+ interrupt-parent = <&intc>;
+
+ qcom,pdc-ranges = <0 480 40>, <40 140 11>, <51 527 47>,
+ <98 609 31>, <129 63 1>, <130 716 12>,
+ <142 251 5>;
+
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ };
+
+ tsens0: thermal-sensor@c228000 {
+ compatible = "qcom,milos-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c228000 0x0 0x1000>,
+ <0x0 0x0c222000 0x0 0x1000>;
+
+ interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <15>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens1: thermal-sensor@c229000 {
+ compatible = "qcom,milos-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c229000 0x0 0x1000>,
+ <0x0 0x0c223000 0x0 0x1000>;
+
+ interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <14>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ aoss_qmp: power-management@c300000 {
+ compatible = "qcom,milos-aoss-qmp", "qcom,aoss-qmp";
+ reg = <0x0 0x0c300000 0x0 0x400>;
+
+ interrupt-parent = <&ipcc>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ #clock-cells = <0>;
+ };
+
+ sram@c3f0000 {
+ compatible = "qcom,rpmh-stats";
+ reg = <0x0 0x0c3f0000 0x0 0x400>;
+ };
+
+ spmi_bus: spmi@c400000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x0 0x0c400000 0x0 0x3000>,
+ <0x0 0x0c500000 0x0 0x400000>,
+ <0x0 0x0c440000 0x0 0x80000>,
+ <0x0 0x0c4c0000 0x0 0x10000>,
+ <0x0 0x0c42d000 0x0 0x4000>;
+ reg-names = "core",
+ "chnls",
+ "obsrvr",
+ "intr",
+ "cnfg";
+
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "periph_irq";
+
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ qcom,bus-id = <0>;
+
+ interrupt-controller;
+ #interrupt-cells = <4>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,milos-tlmm";
+ reg = <0x0 0x0f100000 0x0 0x300000>;
+
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ gpio-ranges = <&tlmm 0 0 168>;
+
+ wakeup-parent = <&pdc>;
+
+ qup_i2c1_data_clk: qup-i2c1-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio4", "gpio5";
+ function = "qup0_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c3_data_clk: qup-i2c3-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio15", "gpio16";
+ function = "qup0_se3";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c7_data_clk: qup-i2c7-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio32", "gpio33";
+ function = "qup1_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi0_cs: qup-spi0-cs-state {
+ pins = "gpio3";
+ function = "qup0_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi0_data_clk: qup-spi0-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio0", "gpio1", "gpio2";
+ function = "qup0_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart5_default: qup-uart5-default-state {
+ /* TX, RX */
+ pins = "gpio25", "gpio26";
+ function = "qup0_se5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart11_default: qup-uart11-default-state {
+ /* TX, RX */
+ pins = "gpio50", "gpio51";
+ function = "qup1_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart11_cts_rts: qup-uart11-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio48", "gpio49";
+ function = "qup1_se4";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ sdc2_default: sdc2-default-state {
+ clk-pins {
+ pins = "gpio62";
+ function = "sdc2_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "gpio61";
+ function = "sdc2_cmd";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "gpio58", "gpio57", "gpio35", "gpio34";
+ function = "sdc2_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_sleep: sdc2-sleep-state {
+ clk-pins {
+ pins = "gpio62";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "gpio61";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "gpio58", "gpio57", "gpio35", "gpio34";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ apps_smmu: iommu@15000000 {
+ compatible = "qcom,milos-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x15000000 0x0 0x100000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH 0>;
+ dma-coherent;
+ };
+
+ intc: interrupt-controller@17100000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x17100000 0x0 0x10000>,
+ <0x0 0x17180000 0x0 0x200000>;
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ #interrupt-cells = <4>;
+ interrupt-controller;
+
+ #redistributor-regions = <1>;
+ redistributor-stride = <0 0x40000>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ };
+
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
+ };
+ };
+
+ gic_its: msi-controller@17140000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x17140000 0x0 0x20000>;
+
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ timer@17420000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0 0x17420000 0x0 0x1000>;
+
+ ranges = <0 0 0 0x20000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ frame@17421000 {
+ reg = <0x17421000 0x1000>,
+ <0x17422000 0x1000>;
+
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ frame-number = <0>;
+ };
+
+ frame@17423000 {
+ reg = <0x17423000 0x1000>;
+
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ frame-number = <1>;
+
+ status = "disabled";
+ };
+
+ frame@17425000 {
+ reg = <0x17425000 0x1000>;
+
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ frame-number = <2>;
+
+ status = "disabled";
+ };
+
+ frame@17427000 {
+ reg = <0x17427000 0x1000>;
+
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ frame-number = <3>;
+
+ status = "disabled";
+ };
+
+ frame@17429000 {
+ reg = <0x17429000 0x1000>;
+
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ frame-number = <4>;
+
+ status = "disabled";
+ };
+
+ frame@1742b000 {
+ reg = <0x1742b000 0x1000>;
+
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ frame-number = <5>;
+
+ status = "disabled";
+ };
+
+ frame@1742d000 {
+ reg = <0x1742d000 0x1000>;
+
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ frame-number = <6>;
+
+ status = "disabled";
+ };
+ };
+
+ apps_rsc: rsc@17a00000 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x0 0x17a00000 0x0 0x10000>,
+ <0x0 0x17a10000 0x0 0x10000>,
+ <0x0 0x17a20000 0x0 0x10000>;
+ reg-names = "drv-0",
+ "drv-1",
+ "drv-2";
+
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ power-domains = <&cluster_pd>;
+
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
+ <WAKE_TCS 2>, <CONTROL_TCS 0>;
+
+ label = "apps_rsc";
+
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,milos-rpmh-clk";
+
+ clocks = <&xo_board>;
+ clock-names = "xo";
+
+ #clock-cells = <1>;
+ };
+
+ rpmhpd: power-controller {
+ compatible = "qcom,milos-rpmhpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmhpd_opp_table>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp-16 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ rpmhpd_opp_low_svs_d1: opp-56 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+ };
+
+ rpmhpd_opp_low_svs: opp-64 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ rpmhpd_opp_svs: opp-128 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ rpmhpd_opp_svs_l1: opp-192 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ rpmhpd_opp_nom: opp-256 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ rpmhpd_opp_nom_l1: opp-320 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ rpmhpd_opp_turbo: opp-384 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ rpmhpd_opp_turbo_l1: opp-416 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+ };
+ };
+ };
+
+ cpufreq_hw: cpufreq@17d91000 {
+ compatible = "qcom,milos-cpufreq-epss", "qcom,cpufreq-epss";
+ reg = <0x0 0x17d91000 0x0 0x1000>,
+ <0x0 0x17d92000 0x0 0x1000>,
+ <0x0 0x17d93000 0x0 0x1000>;
+ reg-names = "freq-domain0",
+ "freq-domain1",
+ "freq-domain2";
+
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "dcvsh-irq-0",
+ "dcvsh-irq-1",
+ "dcvsh-irq-2";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPLL0>;
+ clock-names = "xo",
+ "alternate";
+
+ #freq-domain-cells = <1>;
+ #clock-cells = <1>;
+ };
+
+ gem_noc: interconnect@24100000 {
+ compatible = "qcom,milos-gem-noc";
+ reg = <0x0 0x24100000 0x0 0xff080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ nsp_noc: interconnect@320c0000 {
+ compatible = "qcom,milos-nsp-noc";
+ reg = <0x0 0x320c0000 0x0 0xe080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ remoteproc_cdsp: remoteproc@32300000 {
+ compatible = "qcom,milos-cdsp-pas";
+ reg = <0x0 0x32300000 0x0 0x10000>;
+
+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>,
+ <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MX>;
+ power-domain-names = "cx",
+ "mx";
+
+ interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_cdsp_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "cdsp";
+ qcom,remote-pid = <5>;
+ };
+ };
+ };
+
+ thermal-zones {
+ aoss0-thermal {
+ thermal-sensors = <&tsens0 0>;
+
+ trips {
+ aoss0-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ aoss0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss0-thermal {
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ cpuss0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss1-thermal {
+ thermal-sensors = <&tsens0 2>;
+
+ trips {
+ cpuss1-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu4-left-thermal {
+ thermal-sensors = <&tsens0 3>;
+
+ trips {
+ cpu4-left-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu4-right-thermal {
+ thermal-sensors = <&tsens0 4>;
+
+ trips {
+ cpu4-right-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu5-left-thermal {
+ thermal-sensors = <&tsens0 5>;
+
+ trips {
+ cpu5-left-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu5-right-thermal {
+ thermal-sensors = <&tsens0 6>;
+
+ trips {
+ cpu5-right-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu6-left-thermal {
+ thermal-sensors = <&tsens0 7>;
+
+ trips {
+ cpu6-left-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu6-right-thermal {
+ thermal-sensors = <&tsens0 8>;
+
+ trips {
+ cpu6-right-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu7-left-thermal {
+ thermal-sensors = <&tsens0 9>;
+
+ trips {
+ cpu7-left-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu7-right-thermal {
+ thermal-sensors = <&tsens0 10>;
+
+ trips {
+ cpu7-right-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu0-thermal {
+ thermal-sensors = <&tsens0 11>;
+
+ trips {
+ cpu0-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu1-thermal {
+ thermal-sensors = <&tsens0 12>;
+
+ trips {
+ cpu1-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu2-thermal {
+ thermal-sensors = <&tsens0 13>;
+
+ trips {
+ cpu2-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu3-thermal {
+ thermal-sensors = <&tsens0 14>;
+
+ trips {
+ cpu3-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss1-thermal {
+ thermal-sensors = <&tsens1 0>;
+
+ trips {
+ aoss1-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ aoss1-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphvx0-thermal {
+ polling-delay-passive = <10>;
+
+ thermal-sensors = <&tsens1 1>;
+
+ trips {
+ nsphvx0-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ nsphvx0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphmx1-thermal {
+ polling-delay-passive = <10>;
+
+ thermal-sensors = <&tsens1 2>;
+
+ trips {
+ nsphmx1-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ nsphmx1-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphmx0-thermal {
+ polling-delay-passive = <10>;
+
+ thermal-sensors = <&tsens1 3>;
+
+ trips {
+ nsphmx0-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ nsphmx0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss0-thermal {
+ polling-delay-passive = <10>;
+
+ thermal-sensors = <&tsens1 4>;
+
+ trips {
+ gpu0_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <90000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ gpuss0-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss1-thermal {
+ polling-delay-passive = <10>;
+
+ thermal-sensors = <&tsens1 5>;
+
+ trips {
+ gpu1_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <90000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ gpuss1-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ video-thermal {
+ thermal-sensors = <&tsens1 7>;
+
+ trips {
+ video-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ video-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ ddr-thermal {
+ polling-delay-passive = <10>;
+
+ thermal-sensors = <&tsens1 8>;
+
+ trips {
+ ddr-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ ddr-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ camera0-thermal {
+ thermal-sensors = <&tsens1 9>;
+
+ trips {
+ camera0-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ camera0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ modem0-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&tsens1 10>;
+
+ trips {
+ modem0-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ modem0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ modem1-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&tsens1 11>;
+
+ trips {
+ modem1-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ modem1-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ modem2-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&tsens1 12>;
+
+ trips {
+ modem2-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ modem2-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ modem3-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&tsens1 13>;
+
+ trips {
+ modem3-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ modem3-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>;
+ };
+};
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
status = "okay";
+ fan_controller: fan@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ #pwm-cells = <2>;
+
+ fan {
+ pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>;
+ };
+ };
+
eeprom0: eeprom@50 {
compatible = "atmel,24c256";
reg = <0x50>;
status = "okay";
};
+&pcie0 {
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l6a>;
+ vdda-pll-supply = <&vreg_l5a>;
+
+ status = "okay";
+};
+
+&pcie1 {
+ pinctrl-0 = <&pcie1_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l6a>;
+ vdda-pll-supply = <&vreg_l5a>;
+
+ status = "okay";
+};
+
+&pcieport0 {
+ reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+};
+
+&pcieport1 {
+ reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+};
+
&qupv3_id_0 {
firmware-name = "qcom/qcs8300/qupv3fw.elf";
status = "okay";
status = "okay";
};
+&spi10 {
+ status = "okay";
+
+ tpm@0 {
+ compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ };
+};
+
&tlmm {
+
+ pcie0_default_state: pcie0-default-state {
+ wake-pins {
+ pins = "gpio0";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ clkreq-pins {
+ pins = "gpio1";
+ function = "pcie0_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-pins {
+ pins = "gpio2";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
ethernet0_default: ethernet0-default-state {
ethernet0_mdc: ethernet0-mdc-pins {
pins = "gpio5";
bias-pull-up;
};
+ pcie1_default_state: pcie1-default-state {
+ wake-pins {
+ pins = "gpio21";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ clkreq-pins {
+ pins = "gpio22";
+ function = "pcie1_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-pins {
+ pins = "gpio23";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
qup_i2c15_default: qup-i2c15-state {
pins = "gpio91", "gpio92";
function = "qup1_se7";
power-domain-names = "psci";
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <472>;
+ #cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
capacity-dmips-mhz = <1946>;
+ #cooling-cells = <2>;
dynamic-power-coefficient = <472>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
capacity-dmips-mhz = <1946>;
+ #cooling-cells = <2>;
dynamic-power-coefficient = <507>;
qcom,freq-domain = <&cpufreq_hw 2>;
operating-points-v2 = <&cpu2_opp_table>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
capacity-dmips-mhz = <1946>;
+ #cooling-cells = <2>;
dynamic-power-coefficient = <507>;
qcom,freq-domain = <&cpufreq_hw 2>;
operating-points-v2 = <&cpu2_opp_table>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
hwlocks = <&tcsr_mutex 3>;
};
+ gunyah_md_mem: gunyah-md-region@91a80000 {
+ reg = <0x0 0x91a80000 0x0 0x80000>;
+ no-map;
+ };
+
lpass_machine_learning_mem: lpass-machine-learning-region@93b00000 {
reg = <0x0 0x93b00000 0x0 0xf00000>;
no-map;
#power-domain-cells = <1>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
- <0>,
- <0>,
+ <&pcie0_phy>,
+ <&pcie1_phy>,
<0>,
<0>,
<0>,
#address-cells = <1>;
#size-cells = <1>;
- gpu_speed_bin: gpu_speed_bin@240c {
+ gpu_speed_bin: gpu-speed-bin@240c {
reg = <0x240c 0x1>;
bits = <0 8>;
};
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ pcie0: pci@1c00000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p";
+ reg = <0x0 0x01c00000 0x0 0x3000>,
+ <0x0 0x40000000 0x0 0xf20>,
+ <0x0 0x40000f20 0x0 0xa8>,
+ <0x0 0x40001000 0x0 0x4000>,
+ <0x0 0x40100000 0x0 0x100000>,
+ <0x0 0x01c03000 0x0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
+ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
+ bus-range = <0x00 0xff>;
+
+ dma-coherent;
+
+ linux,pci-domain = <0>;
+ num-lanes = <2>;
+
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a";
+
+ assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "pcie-mem",
+ "cpu-pcie";
+
+ iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
+ <0x100 &pcie_smmu 0x0001 0x1>;
+
+ resets = <&gcc GCC_PCIE_0_BCR>,
+ <&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
+ reset-names = "pci",
+ "link_down";
+
+ power-domains = <&gcc GCC_PCIE_0_GDSC>;
+
+ eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
+ eq-presets-16gts = /bits/ 8 <0x55 0x55>;
+
+ operating-points-v2 = <&pcie0_opp_table>;
+
+ status = "disabled";
+
+ pcie0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* GEN 1 x1 */
+ opp-2500000 {
+ opp-hz = /bits/ 64 <2500000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ opp-peak-kBps = <250000 1>;
+ };
+
+ /* GEN 1 x2 and GEN 2 x1 */
+ opp-5000000 {
+ opp-hz = /bits/ 64 <5000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ opp-peak-kBps = <500000 1>;
+ };
+
+ /* GEN 2 x2 */
+ opp-10000000 {
+ opp-hz = /bits/ 64 <10000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ opp-peak-kBps = <1000000 1>;
+ };
+
+ /* GEN 3 x1 */
+ opp-8000000 {
+ opp-hz = /bits/ 64 <8000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ opp-peak-kBps = <984500 1>;
+ };
+
+ /* GEN 3 x2 and GEN 4 x1 */
+ opp-16000000 {
+ opp-hz = /bits/ 64 <16000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <1969000 1>;
+ };
+
+ /* GEN 4 x2 */
+ opp-32000000 {
+ opp-hz = /bits/ 64 <32000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <3938000 1>;
+ };
+ };
+
+ pcieport0: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ phys = <&pcie0_phy>;
+ };
+ };
+
+ pcie0_phy: phy@1c04000 {
+ compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy";
+ reg = <0x0 0x01c04000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_CLKREF_EN>,
+ <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK>,
+ <&gcc GCC_PCIE_0_PIPEDIV2_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe",
+ "pipediv2";
+
+ resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+ reset-names = "phy";
+
+ assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_0_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ pcie1: pci@1c10000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p";
+ reg = <0x0 0x01c10000 0x0 0x3000>,
+ <0x0 0x60000000 0x0 0xf20>,
+ <0x0 0x60000f20 0x0 0xa8>,
+ <0x0 0x60001000 0x0 0x4000>,
+ <0x0 0x60100000 0x0 0x100000>,
+ <0x0 0x01c13000 0x0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>;
+ bus-range = <0x00 0xff>;
+
+ dma-coherent;
+
+ linux,pci-domain = <1>;
+ num-lanes = <4>;
+
+ interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a";
+
+ assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&pcie_anoc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
+ <0x100 &pcie_smmu 0x0081 0x1>;
+
+ resets = <&gcc GCC_PCIE_1_BCR>,
+ <&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
+ reset-names = "pci",
+ "link_down";
+
+ power-domains = <&gcc GCC_PCIE_1_GDSC>;
+
+ eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
+ eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
+
+ operating-points-v2 = <&pcie1_opp_table>;
+
+ status = "disabled";
+
+ pcie1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* GEN 1 x1 */
+ opp-2500000 {
+ opp-hz = /bits/ 64 <2500000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ opp-peak-kBps = <250000 1>;
+ };
+
+ /* GEN 1 x2 and GEN 2 x1 */
+ opp-5000000 {
+ opp-hz = /bits/ 64 <5000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ opp-peak-kBps = <500000 1>;
+ };
+
+ /* GEN 1 x4 and GEN 2 x2 */
+ opp-10000000 {
+ opp-hz = /bits/ 64 <10000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ opp-peak-kBps = <1000000 1>;
+ };
+
+ /* GEN 2 x4 */
+ opp-20000000 {
+ opp-hz = /bits/ 64 <20000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <2000000 1>;
+ };
+
+ /* GEN 3 x1 */
+ opp-8000000 {
+ opp-hz = /bits/ 64 <8000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ opp-peak-kBps = <984500 1>;
+ };
+
+ /* GEN 3 x2 and GEN 4 x1 */
+ opp-16000000 {
+ opp-hz = /bits/ 64 <16000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <1969000 1>;
+ };
+
+ /* GEN 3 x4 and GEN 4 x2 */
+ opp-32000000 {
+ opp-hz = /bits/ 64 <32000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <3938000 1>;
+ };
+
+ /* GEN 4 x4 */
+ opp-64000000 {
+ opp-hz = /bits/ 64 <64000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <7876000 1>;
+ };
+ };
+
+ pcieport1: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ phys = <&pcie1_phy>;
+ };
+ };
+
+ pcie1_phy: phy@1c14000 {
+ compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
+ reg = <0x0 0x01c14000 0x0 0x4000>;
+
+ clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_CLKREF_EN>,
+ <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_1_PIPE_CLK>,
+ <&gcc GCC_PCIE_1_PIPEDIV2_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe",
+ "pipediv2";
+
+ assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ resets = <&gcc GCC_PCIE_1_PHY_BCR>;
+ reset-names = "phy";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_1_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
ufs_mem_hc: ufs@1d84000 {
compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x0 0x01d84000 0x0 0x3000>;
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
};
+ crypto: crypto@1dfa000 {
+ compatible = "qcom,qcs8300-qce", "qcom,sm8150-qce", "qcom,qce";
+ reg = <0x0 0x01dfa000 0x0 0x6000>;
+ dmas = <&cryptobam 4>, <&cryptobam 5>;
+ dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x480 0x0>,
+ <&apps_smmu 0x481 0x0>;
+ interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "memory";
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x20000>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ ctcu@4001000 {
+ compatible = "qcom,qcs8300-ctcu", "qcom,sa8775p-ctcu";
+ reg = <0x0 0x04001000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ctcu_in0: endpoint {
+ remote-endpoint = <&etr0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ctcu_in1: endpoint {
+ remote-endpoint = <&etr1_out>;
+ };
+ };
+ };
+ };
+
stm@4002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x0 0x04002000 0x0 0x1000>,
#address-cells = <1>;
#size-cells = <0>;
+ port@0 {
+ reg = <0>;
+
+ swao_rep_out0: endpoint {
+ remote-endpoint = <&qdss_rep_in>;
+ };
+ };
+
port@1 {
reg = <1>;
};
};
+ replicator@4046000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x04046000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ qdss_rep_in: endpoint {
+ remote-endpoint = <&swao_rep_out0>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ qdss_rep_out0: endpoint {
+ remote-endpoint = <&etr_rep_in>;
+ };
+ };
+ };
+ };
+
+ tmc@4048000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x04048000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ iommus = <&apps_smmu 0x04c0 0x00>;
+
+ arm,scatter-gather;
+
+ in-ports {
+ port {
+ etr0_in: endpoint {
+ remote-endpoint = <&etr_rep_out0>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etr0_out: endpoint {
+ remote-endpoint = <&ctcu_in0>;
+ };
+ };
+ };
+ };
+
+ replicator@404e000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x0404e000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ etr_rep_in: endpoint {
+ remote-endpoint = <&qdss_rep_out0>;
+ };
+ };
+ };
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ etr_rep_out0: endpoint {
+ remote-endpoint = <&etr0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ etr_rep_out1: endpoint {
+ remote-endpoint = <&etr1_in>;
+ };
+ };
+ };
+ };
+
+ tmc@404f000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x0404f000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ iommus = <&apps_smmu 0x04a0 0x40>;
+
+ arm,scatter-gather;
+ arm,buffer-size = <0x400000>;
+
+ in-ports {
+ port {
+ etr1_in: endpoint {
+ remote-endpoint = <&etr_rep_out1>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etr1_out: endpoint {
+ remote-endpoint = <&ctcu_in1>;
+ };
+ };
+ };
+ };
+
tpdm@4841000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x04841000 0x0 0x1000>;
#power-domain-cells = <1>;
};
- camcc: clock-controller@ade0000 {
- compatible = "qcom,qcs8300-camcc";
- reg = <0x0 0x0ade0000 0x0 0x20000>;
- clocks = <&gcc GCC_CAMERA_AHB_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
- <&rpmhcc RPMH_CXO_CLK_A>,
- <&sleep_clk>;
- power-domains = <&rpmhpd RPMHPD_MMCX>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- };
+ camss: isp@ac78000 {
+ compatible = "qcom,qcs8300-camss";
+
+ reg = <0x0 0xac78000 0x0 0x1000>,
+ <0x0 0xac7a000 0x0 0xf00>,
+ <0x0 0xac7c000 0x0 0xf00>,
+ <0x0 0xac84000 0x0 0xf00>,
+ <0x0 0xac88000 0x0 0xf00>,
+ <0x0 0xac8c000 0x0 0xf00>,
+ <0x0 0xac90000 0x0 0xf00>,
+ <0x0 0xac94000 0x0 0xf00>,
+ <0x0 0xac9c000 0x0 0x2000>,
+ <0x0 0xac9e000 0x0 0x2000>,
+ <0x0 0xaca0000 0x0 0x2000>,
+ <0x0 0xacac000 0x0 0x400>,
+ <0x0 0xacad000 0x0 0x400>,
+ <0x0 0xacae000 0x0 0x400>,
+ <0x0 0xac4d000 0x0 0xf000>,
+ <0x0 0xac60000 0x0 0xf000>,
+ <0x0 0xac85000 0x0 0xd00>,
+ <0x0 0xac89000 0x0 0xd00>,
+ <0x0 0xac8d000 0x0 0xd00>,
+ <0x0 0xac91000 0x0 0xd00>,
+ <0x0 0xac95000 0x0 0xd00>;
+ reg-names = "csid_wrapper",
+ "csid0",
+ "csid1",
+ "csid_lite0",
+ "csid_lite1",
+ "csid_lite2",
+ "csid_lite3",
+ "csid_lite4",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "tpg0",
+ "tpg1",
+ "tpg2",
+ "vfe0",
+ "vfe1",
+ "vfe_lite0",
+ "vfe_lite1",
+ "vfe_lite2",
+ "vfe_lite3",
+ "vfe_lite4";
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_0_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_1_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>,
+ <&camcc CAM_CC_ICP_AHB_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+ clock-names = "camnoc_axi",
+ "core_ahb",
+ "cpas_ahb",
+ "cpas_fast_ahb_clk",
+ "cpas_vfe_lite",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "csid",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy_rx",
+ "gcc_axi_hf",
+ "gcc_axi_sf",
+ "icp_ahb",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid";
+
+ interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid_lite0",
+ "csid_lite1",
+ "csid_lite2",
+ "csid_lite3",
+ "csid_lite4",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "tpg0",
+ "tpg1",
+ "tpg2",
+ "vfe0",
+ "vfe1",
+ "vfe_lite0",
+ "vfe_lite1",
+ "vfe_lite2",
+ "vfe_lite3",
+ "vfe_lite4";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_0";
+
+ iommus = <&apps_smmu 0x2400 0x20>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "top";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ };
+ };
+ };
+
+ camcc: clock-controller@ade0000 {
+ compatible = "qcom,qcs8300-camcc";
+ reg = <0x0 0x0ade0000 0x0 0x20000>;
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ mdss: display-subsystem@ae00000 {
+ compatible = "qcom,qcs8300-mdss";
+ reg = <0x0 0x0ae00000 0x0 0x1000>;
+ reg-names = "mdss";
+
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>;
+
+ resets = <&dispcc MDSS_DISP_CC_MDSS_CORE_BCR>;
+
+ interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+ "mdp1-mem",
+ "cpu-cfg";
+
+ power-domains = <&dispcc MDSS_DISP_CC_MDSS_CORE_GDSC>;
+
+ iommus = <&apps_smmu 0x1000 0x402>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss_mdp: display-controller@ae01000 {
+ compatible = "qcom,qcs8300-dpu", "qcom,sa8775p-dpu";
+ reg = <0x0 0x0ae01000 0x0 0x8f000>,
+ <0x0 0x0aeb0000 0x0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ interrupts-extended = <&mdss 0>;
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dpu_intf0_out: endpoint {
+ remote-endpoint = <&mdss_dp0_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-575000000 {
+ opp-hz = /bits/ 64 <575000000>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ required-opps = <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+ };
+
+ mdss_dp0_phy: phy@aec2a00 {
+ compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy";
+
+ reg = <0x0 0x0aec2a00 0x0 0x19c>,
+ <0x0 0x0aec2200 0x0 0xec>,
+ <0x0 0x0aec2600 0x0 0xec>,
+ <0x0 0x0aec2000 0x0 0x1c8>;
+
+ clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "aux",
+ "cfg_ahb";
+
+ power-domains = <&rpmhpd RPMHPD_MX>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ mdss_dp0: displayport-controller@af54000 {
+ compatible = "qcom,qcs8300-dp", "qcom,sa8775p-dp";
+
+ reg = <0x0 0x0af54000 0x0 0x200>,
+ <0x0 0x0af54200 0x0 0x200>,
+ <0x0 0x0af55000 0x0 0xc00>,
+ <0x0 0x0af56000 0x0 0x09c>,
+ <0x0 0x0af57000 0x0 0x09c>,
+ <0x0 0x0af58000 0x0 0x09c>,
+ <0x0 0x0af59000 0x0 0x09c>,
+ <0x0 0x0af5a000 0x0 0x23c>,
+ <0x0 0x0af5b000 0x0 0x23c>;
+
+ interrupts-extended = <&mdss 12>;
+
+ clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel",
+ "stream_1_pixel",
+ "stream_2_pixel",
+ "stream_3_pixel";
+ assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+ <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
+ <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
+ <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dp0_phy 0>,
+ <&mdss_dp0_phy 1>,
+ <&mdss_dp0_phy 1>,
+ <&mdss_dp0_phy 1>,
+ <&mdss_dp0_phy 1>;
+ phys = <&mdss_dp0_phy>;
+ phy-names = "dp";
+
+ operating-points-v2 = <&dp_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dp0_in: endpoint {
+ remote-endpoint = <&dpu_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dp0_out: endpoint { };
+ };
+ };
+
+ dp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+ };
dispcc: clock-controller@af00000 {
compatible = "qcom,sa8775p-dispcc0";
<&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
- <0>, <0>, <0>, <0>,
+ <&mdss_dp0_phy 0>,
+ <&mdss_dp0_phy 1>,
+ <0>, <0>,
<0>, <0>, <0>, <0>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
#clock-cells = <1>;
<235 723 5>;
};
+ tsens2: thermal-sensor@c251000 {
+ compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c251000 0x0 0x1000>,
+ <0x0 0x0c224000 0x0 0x1000>;
+ interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow", "critical";
+ #qcom,sensors = <10>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens3: thermal-sensor@c252000 {
+ compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c252000 0x0 0x1000>,
+ <0x0 0x0c225000 0x0 0x1000>;
+ interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow", "critical";
+ #qcom,sensors = <10>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens0: thermal-sensor@c263000 {
+ compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c263000 0x0 0x1000>,
+ <0x0 0x0c222000 0x0 0x1000>;
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow", "critical";
+ #qcom,sensors = <10>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens1: thermal-sensor@c265000 {
+ compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c265000 0x0 0x1000>,
+ <0x0 0x0c223000 0x0 0x1000>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow", "critical";
+ #qcom,sensors = <10>;
+ #thermal-sensor-cells = <1>;
+ };
+
aoss_qmp: power-management@c300000 {
compatible = "qcom,qcs8300-aoss-qmp", "qcom,aoss-qmp";
reg = <0x0 0x0c300000 0x0 0x400>;
};
qup_uart10_rts: qup-uart10-rts-state {
- pins = "gpio84";
+ pins = "gpio85";
function = "qup1_se2";
};
qup_uart10_tx: qup-uart10-tx-state {
- pins = "gpio85";
+ pins = "gpio86";
function = "qup1_se2";
};
};
};
+ thermal_zones: thermal-zones {
+ aoss-0-thermal {
+ thermal-sensors = <&tsens0 0>;
+
+ trips {
+ aoss0-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-0-0-thermal {
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ cpu-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-1-0-thermal {
+ thermal-sensors = <&tsens0 2>;
+
+ trips {
+ cpu-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-2-0-thermal {
+ thermal-sensors = <&tsens0 3>;
+
+ trips {
+ cpu-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-3-0-thermal {
+ thermal-sensors = <&tsens0 4>;
+
+ trips {
+ cpu-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-0-thermal {
+ thermal-sensors = <&tsens0 5>;
+
+ trips {
+ gpuss0_alert0: trip-point0 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ gpuss0-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&gpuss0_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ audio-thermal {
+ thermal-sensors = <&tsens0 6>;
+
+ trips {
+ audio-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ camss-0-thermal {
+ thermal-sensors = <&tsens0 7>;
+
+ trips {
+ camss-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ pcie-0-thermal {
+ thermal-sensors = <&tsens0 8>;
+
+ trips {
+ pcie-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss-0-0-thermal {
+ thermal-sensors = <&tsens0 9>;
+
+ trips {
+ cpuss0-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss-1-thermal {
+ thermal-sensors = <&tsens1 0>;
+
+ trips {
+ aoss1-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-0-1-thermal {
+ thermal-sensors = <&tsens1 1>;
+
+ trips {
+ cpu-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-1-1-thermal {
+ thermal-sensors = <&tsens1 2>;
+
+ trips {
+ cpu-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-2-1-thermal {
+ thermal-sensors = <&tsens1 3>;
+
+ trips {
+ cpu-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-3-1-thermal {
+ thermal-sensors = <&tsens1 4>;
+
+ trips {
+ cpu-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-1-thermal {
+ thermal-sensors = <&tsens1 5>;
+
+ trips {
+ gpuss1_alert0: trip-point0 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ gpuss1-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&gpuss1_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ video-thermal {
+ thermal-sensors = <&tsens1 6>;
+
+ trips {
+ video-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ camss-1-thermal {
+ thermal-sensors = <&tsens1 7>;
+
+ trips {
+ camss1-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ pcie-1-thermal {
+ thermal-sensors = <&tsens1 8>;
+
+ trips {
+ pcie-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss-0-1-thermal {
+ thermal-sensors = <&tsens1 9>;
+
+ trips {
+ cpuss0-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss-2-thermal {
+ thermal-sensors = <&tsens2 0>;
+
+ trips {
+ aoss2-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-0-0-thermal {
+ thermal-sensors = <&tsens2 1>;
+
+ trips {
+ cpu-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-1-0-thermal {
+ thermal-sensors = <&tsens2 2>;
+
+ trips {
+ cpu-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-2-0-thermal {
+ thermal-sensors = <&tsens2 3>;
+
+ trips {
+ cpu-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-3-0-thermal {
+ thermal-sensors = <&tsens2 4>;
+
+ trips {
+ cpu-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsp-0-0-0-thermal {
+ thermal-sensors = <&tsens2 5>;
+
+ trips {
+ nsp-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsp-0-1-0-thermal {
+ thermal-sensors = <&tsens2 6>;
+
+ trips {
+ nsp-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsp-0-2-0-thermal {
+ thermal-sensors = <&tsens2 7>;
+
+ trips {
+ nsp-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ ddrss-0-thermal {
+ thermal-sensors = <&tsens2 8>;
+
+ trips {
+ ddrss-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss-1-0-thermal {
+ thermal-sensors = <&tsens2 9>;
+
+ trips {
+ cpuss1-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss-3-thermal {
+ thermal-sensors = <&tsens3 0>;
+
+ trips {
+ aoss3-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-0-1-thermal {
+ thermal-sensors = <&tsens3 1>;
+
+ trips {
+ cpu-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-1-1-thermal {
+ thermal-sensors = <&tsens3 2>;
+
+ trips {
+ cpu-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-2-1-thermal {
+ thermal-sensors = <&tsens3 3>;
+
+ trips {
+ cpu-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-3-1-thermal {
+ thermal-sensors = <&tsens3 4>;
+
+ trips {
+ cpu-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsp-0-0-1-thermal {
+ thermal-sensors = <&tsens3 5>;
+
+ trips {
+ nsp-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsp-0-1-1-thermal {
+ thermal-sensors = <&tsens3 6>;
+
+ trips {
+ nsp-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsp-0-2-1-thermal {
+ thermal-sensors = <&tsens3 7>;
+
+ trips {
+ nsp-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ ddrss-1-thermal {
+ thermal-sensors = <&tsens3 8>;
+
+ trips {
+ ddrss-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss-1-1-thermal {
+ thermal-sensors = <&tsens3 9>;
+
+ trips {
+ cpuss1-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
- power-domains = <&rpmpd MSM8916_VDDCX>,
- <&rpmpd MSM8916_VDDMX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>,
+ <&rpmpd RPMPD_VDDMX>;
power-domain-names = "cx", "mx";
clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
<&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
- power-domains = <&rpmpd MSM8916_VDDCX>,
- <&rpmpd MSM8916_VDDMX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>,
+ <&rpmpd RPMPD_VDDMX>;
power-domain-names = "cx", "mx";
qcom,smem-states = <&wcnss_smp2p_out 0>;
clock-names = "iface",
"bus",
"vsync";
-
+ resets = <&gcc GCC_MDSS_BCR>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
phys = <&mdss_dsi0_phy>;
operating-points-v2 = <&mdss_dsi0_opp_table>;
- power-domains = <&rpmpd MSM8917_VDDCX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&sdc1_default>;
pinctrl-1 = <&sdc1_sleep>;
pinctrl-names = "default", "sleep";
- power-domains = <&rpmpd MSM8917_VDDCX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-ddr-1_8v;
pinctrl-0 = <&sdc2_default>;
pinctrl-1 = <&sdc2_sleep>;
pinctrl-names = "default", "sleep";
- power-domains = <&rpmpd MSM8917_VDDCX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
bus-width = <4>;
status = "disabled";
};
<&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
- power-domains = <&rpmpd MSM8917_VDDCX>,
- <&rpmpd MSM8917_VDDMX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>,
+ <&rpmpd RPMPD_VDDMX>;
power-domain-names = "cx", "mx";
qcom,smem-states = <&wcnss_smp2p_out 0>;
clock-names = "iface",
"bus",
"vsync";
+ resets = <&gcc GCC_MDSS_BCR>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
phys = <&mdss_dsi0_phy>;
operating-points-v2 = <&mdss_dsi0_opp_table>;
- power-domains = <&rpmpd MSM8937_VDDCX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
#address-cells = <1>;
#size-cells = <0>;
phys = <&mdss_dsi1_phy>;
operating-points-v2 = <&mdss_dsi1_opp_table>;
- power-domains = <&rpmpd MSM8937_VDDCX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-1 = <&sdc1_sleep>;
pinctrl-names = "default",
"sleep";
- power-domains = <&rpmpd MSM8937_VDDCX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-ddr-1_8v;
pinctrl-1 = <&sdc2_sleep>;
pinctrl-names = "default",
"sleep";
- power-domains = <&rpmpd MSM8937_VDDCX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
bus-width = <4>;
status = "disabled";
};
"handover",
"stop-ack";
- power-domains = <&rpmpd MSM8937_VDDCX>,
- <&rpmpd MSM8937_VDDMX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>,
+ <&rpmpd RPMPD_VDDMX>;
power-domain-names = "cx",
"mx";
serial0 = &blsp_uart2;
};
+ battery: battery {
+ compatible = "simple-battery";
+ device-chemistry = "lithium-ion-polymer";
+ voltage-min-design-microvolt = <3400000>;
+ voltage-max-design-microvolt = <4400000>;
+ energy-full-design-microwatt-hours = <11500000>;
+ charge-full-design-microamp-hours = <3000000>;
+
+ ocv-capacity-celsius = <(-20) 0 25 40 60>;
+ ocv-capacity-table-0 = <4378000 100>, <4220000 95>, <4125000 90>,
+ <4071000 85>, <3977000 80>, <3916000 75>, <3866000 70>,
+ <3838000 65>, <3822000 60>, <3809000 55>, <3797000 50>,
+ <3784000 45>, <3771000 40>, <3757000 35>, <3743000 30>,
+ <3726000 25>, <3707000 20>, <3688000 16>, <3670000 13>,
+ <3655000 11>, <3648000 10>, <3636000 9>, <3624000 8>,
+ <3612000 7>, <3592000 6>, <3569000 5>, <3540000 4>,
+ <3494000 3>, <3418000 2>, <3289000 1>, <3000000 0>;
+
+ ocv-capacity-table-1 = <4378000 100>, <4292000 95>, <4226000 90>,
+ <4166000 85>, <4109000 80>, <4064000 75>, <3992000 70>,
+ <3942000 65>, <3898000 60>, <3859000 55>, <3826000 50>,
+ <3802000 45>, <3788000 40>, <3779000 35>, <3768000 30>,
+ <3752000 25>, <3732000 20>, <3712000 16>, <3696000 13>,
+ <3688000 11>, <3684000 10>, <3680000 9>, <3675000 8>,
+ <3669000 7>, <3658000 6>, <3636000 5>, <3599000 4>,
+ <3544000 3>, <3466000 2>, <3341000 1>, <3000000 0>;
+
+ ocv-capacity-table-2 = <4372000 100>, <4306000 95>, <4247000 90>,
+ <4190000 85>, <4134000 80>, <4081000 75>, <4030000 70>,
+ <3984000 65>, <3930000 60>, <3884000 55>, <3850000 50>,
+ <3826000 45>, <3804000 40>, <3786000 35>, <3770000 30>,
+ <3753000 25>, <3734000 20>, <3712000 16>, <3693000 13>,
+ <3686000 11>, <3684000 10>, <3682000 9>, <3680000 8>,
+ <3676000 7>, <3668000 6>, <3643000 5>, <3600000 4>,
+ <3542000 3>, <3462000 2>, <3340000 1>, <3000000 0>;
+
+ ocv-capacity-table-3 = <4365000 100>, <4304000 95>, <4246000 90>,
+ <4189000 85>, <4133000 80>, <4080000 75>, <4030000 70>,
+ <3985000 65>, <3933000 60>, <3886000 55>, <3852000 50>,
+ <3827000 45>, <3806000 40>, <3789000 35>, <3769000 30>,
+ <3746000 25>, <3726000 20>, <3706000 16>, <3688000 13>,
+ <3681000 11>, <3678000 10>, <3676000 9>, <3676000 8>,
+ <3672000 7>, <3660000 6>, <3634000 5>, <3588000 4>,
+ <3528000 3>, <3448000 2>, <3322000 1>, <3000000 0>;
+
+ ocv-capacity-table-4 = <4358000 100>, <4298000 95>, <4240000 90>,
+ <4183000 85>, <4128000 80>, <4076000 75>, <4027000 70>,
+ <3983000 65>, <3935000 60>, <3887000 55>, <3852000 50>,
+ <3827000 45>, <3806000 40>, <3789000 35>, <3764000 30>,
+ <3738000 25>, <3715000 20>, <3695000 16>, <3677000 13>,
+ <3672000 11>, <3669000 10>, <3667000 9>, <3666000 8>,
+ <3662000 7>, <3652000 6>, <3622000 5>, <3577000 4>,
+ <3518000 3>, <3440000 2>, <3321000 1>, <3000000 0>;
+ };
+
chosen {
stdout-path = "serial0";
};
gpio-keys {
compatible = "gpio-keys";
- pinctrl-0 = <&gpio_keys_default>;
+ pinctrl-0 = <&gpio_hall_sensor_default>, <&gpio_keys_default>;
pinctrl-names = "default";
button-volume-up {
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <15>;
};
+
+ event-hall-sensor {
+ label = "Hall Effect Sensor";
+ gpios = <&tlmm 108 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ linux,can-disable;
+ debounce-interval = <150>;
+ };
};
reg_sd_vmmc: regulator-sdcard-vmmc {
reg = <0x0 0x86800000 0x0 0x5500000>;
};
+&pm8916_bms {
+ monitored-battery = <&battery>;
+
+ status = "okay";
+};
+
&pm8916_codec {
qcom,micbias-lvl = <2800>;
qcom,mbhc-vthreshold-low = <75 150 237 450 500>;
bias-pull-up;
};
+ gpio_hall_sensor_default: gpio-hall-sensor-default-state {
+ pins = "gpio108";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
usb_id_default: usb-id-default-state {
pins = "gpio110";
function = "gpio";
#include "msm8939.dtsi"
#include "pm8916.dtsi"
+&camss {
+ vdda-supply = <&pm8916_l2>;
+};
+
&mdss_dsi0 {
vdda-supply = <&pm8916_l2>;
vddio-supply = <&pm8916_l6>;
};
};
+ camss: isp@1b0ac00 {
+ compatible = "qcom,msm8939-camss";
+ reg = <0x01b0ac00 0x200>,
+ <0x01b00030 0x4>,
+ <0x01b0b000 0x200>,
+ <0x01b00038 0x4>,
+ <0x01b08000 0x100>,
+ <0x01b08400 0x100>,
+ <0x01b0a000 0x500>,
+ <0x01b00020 0x10>,
+ <0x01b10000 0x1000>,
+ <0x01b08800 0x100>,
+ <0x01b40000 0x200>;
+ reg-names = "csiphy0",
+ "csiphy0_clk_mux",
+ "csiphy1",
+ "csiphy1_clk_mux",
+ "csid0",
+ "csid1",
+ "ispif",
+ "csi_clk_mux",
+ "vfe0",
+ "csid2",
+ "vfe0_vbif";
+
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
+ <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
+ <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI0_CLK>,
+ <&gcc GCC_CAMSS_CSI0PHY_CLK>,
+ <&gcc GCC_CAMSS_CSI0PIX_CLK>,
+ <&gcc GCC_CAMSS_CSI0RDI_CLK>,
+ <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI1_CLK>,
+ <&gcc GCC_CAMSS_CSI1PHY_CLK>,
+ <&gcc GCC_CAMSS_CSI1PIX_CLK>,
+ <&gcc GCC_CAMSS_CSI1RDI_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>,
+ <&gcc GCC_CAMSS_VFE0_CLK>,
+ <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
+ <&gcc GCC_CAMSS_VFE_AHB_CLK>,
+ <&gcc GCC_CAMSS_VFE_AXI_CLK>,
+ <&gcc GCC_CAMSS_CSI2_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI2_CLK>,
+ <&gcc GCC_CAMSS_CSI2PHY_CLK>,
+ <&gcc GCC_CAMSS_CSI2PIX_CLK>,
+ <&gcc GCC_CAMSS_CSI2RDI_CLK>;
+ clock-names = "top_ahb",
+ "ispif_ahb",
+ "csiphy0_timer",
+ "csiphy1_timer",
+ "csi0_ahb",
+ "csi0",
+ "csi0_phy",
+ "csi0_pix",
+ "csi0_rdi",
+ "csi1_ahb",
+ "csi1",
+ "csi1_phy",
+ "csi1_pix",
+ "csi1_rdi",
+ "ahb",
+ "vfe0",
+ "csi_vfe0",
+ "vfe_ahb",
+ "vfe_axi",
+ "csi2_ahb",
+ "csi2",
+ "csi2_phy",
+ "csi2_pix",
+ "csi2_rdi";
+
+ interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csiphy0",
+ "csiphy1",
+ "csid0",
+ "csid1",
+ "ispif",
+ "vfe0",
+ "csid2";
+
+ iommus = <&apps_iommu 3>;
+
+ power-domains = <&gcc VFE_GDSC>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ cci: cci@1b0c000 {
+ compatible = "qcom,msm8916-cci", "qcom,msm8226-cci";
+ reg = <0x01b0c000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_CCI_AHB_CLK>,
+ <&gcc GCC_CAMSS_CCI_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ clock-names = "camss_top_ahb",
+ "cci_ahb",
+ "cci",
+ "camss_ahb";
+ assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
+ <&gcc GCC_CAMSS_CCI_CLK>;
+ assigned-clock-rates = <80000000>,
+ <19200000>;
+ pinctrl-0 = <&cci0_default>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ cci_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
gpu: gpu@1c00000 {
compatible = "qcom,adreno-405.0", "qcom,adreno";
reg = <0x01c00000 0x10000>;
#iommu-cells = <1>;
qcom,iommu-secure-id = <17>;
+ /* vfe */
+ iommu-ctx@3000 {
+ compatible = "qcom,msm-iommu-v1-sec";
+ reg = <0x3000 0x1000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
/* mdp_0: */
iommu-ctx@4000 {
compatible = "qcom,msm-iommu-v1-ns";
interrupt-controller;
#interrupt-cells = <2>;
- uart_console_active: uart-console-active-state {
- pins = "gpio4", "gpio5";
- function = "blsp_uart2";
- drive-strength = <2>;
- bias-disable;
- };
-
- uart_console_sleep: uart-console-sleep-state {
- pins = "gpio4", "gpio5";
- function = "blsp_uart2";
- drive-strength = <2>;
- bias-pull-down;
- };
-
- sdc1_clk_on: sdc1-clk-on-state {
- pins = "sdc1_clk";
- bias-disable;
- drive-strength = <16>;
- };
-
- sdc1_clk_off: sdc1-clk-off-state {
- pins = "sdc1_clk";
- bias-disable;
- drive-strength = <2>;
- };
-
- sdc1_cmd_on: sdc1-cmd-on-state {
- pins = "sdc1_cmd";
- bias-disable;
- drive-strength = <10>;
- };
-
- sdc1_cmd_off: sdc1-cmd-off-state {
- pins = "sdc1_cmd";
- bias-disable;
- drive-strength = <2>;
- };
-
- sdc1_data_on: sdc1-data-on-state {
- pins = "sdc1_data";
- bias-pull-up;
- drive-strength = <10>;
- };
-
- sdc1_data_off: sdc1-data-off-state {
- pins = "sdc1_data";
- bias-pull-up;
- drive-strength = <2>;
- };
-
- sdc1_rclk_on: sdc1-rclk-on-state {
- pins = "sdc1_rclk";
- bias-pull-down;
- };
-
- sdc1_rclk_off: sdc1-rclk-off-state {
- pins = "sdc1_rclk";
- bias-pull-down;
- };
-
- sdc2_clk_on: sdc2-clk-on-state {
- pins = "sdc2_clk";
- drive-strength = <16>;
- bias-disable;
- };
-
- sdc2_clk_off: sdc2-clk-off-state {
- pins = "sdc2_clk";
- bias-disable;
- drive-strength = <2>;
- };
-
- sdc2_cmd_on: sdc2-cmd-on-state {
- pins = "sdc2_cmd";
- bias-pull-up;
- drive-strength = <10>;
- };
-
- sdc2_cmd_off: sdc2-cmd-off-state {
- pins = "sdc2_cmd";
- bias-pull-up;
- drive-strength = <2>;
- };
-
- sdc2_data_on: sdc2-data-on-state {
- pins = "sdc2_data";
- bias-pull-up;
- drive-strength = <10>;
- };
-
- sdc2_data_off: sdc2-data-off-state {
- pins = "sdc2_data";
- bias-pull-up;
- drive-strength = <2>;
- };
-
- sdc2_cd_on: cd-on-state {
- pins = "gpio133";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- sdc2_cd_off: cd-off-state {
- pins = "gpio133";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- };
-
- gpio_key_default: gpio-key-default-state {
- pins = "gpio85";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
-
i2c_1_default: i2c-1-default-state {
pins = "gpio2", "gpio3";
function = "blsp_i2c1";
bias-disable;
};
- i2c_2_default: i2c-2-default-state {
- pins = "gpio6", "gpio7";
- function = "blsp_i2c2";
- drive-strength = <2>;
- bias-disable;
- };
-
- i2c_2_sleep: i2c-2-sleep-state {
- pins = "gpio6", "gpio7";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- };
-
- i2c_3_default: i2c-3-default-state {
- pins = "gpio10", "gpio11";
- function = "blsp_i2c3";
- drive-strength = <2>;
- bias-disable;
- };
-
- i2c_3_sleep: i2c-3-sleep-state {
- pins = "gpio10", "gpio11";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- };
-
- i2c_4_default: i2c-4-default-state {
- pins = "gpio14", "gpio15";
- function = "blsp_i2c4";
- drive-strength = <2>;
- bias-disable;
- };
-
- i2c_4_sleep: i2c-4-sleep-state {
- pins = "gpio14", "gpio15";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- };
-
- i2c_5_default: i2c-5-default-state {
- pins = "gpio18", "gpio19";
- function = "blsp_i2c5";
- drive-strength = <2>;
- bias-disable;
- };
-
- i2c_5_sleep: i2c-5-sleep-state {
- pins = "gpio18", "gpio19";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- };
-
- i2c_6_default: i2c-6-default-state {
- pins = "gpio22", "gpio23";
- function = "blsp_i2c6";
- drive-strength = <2>;
- bias-disable;
- };
-
- i2c_6_sleep: i2c-6-sleep-state {
- pins = "gpio22", "gpio23";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- };
-
- i2c_7_default: i2c-7-default-state {
- pins = "gpio135", "gpio136";
- function = "blsp_i2c7";
+ uart_console_active: uart-console-active-state {
+ pins = "gpio4", "gpio5";
+ function = "blsp_uart2";
drive-strength = <2>;
bias-disable;
};
- i2c_7_sleep: i2c-7-sleep-state {
- pins = "gpio135", "gpio136";
- function = "gpio";
+ uart_console_sleep: uart-console-sleep-state {
+ pins = "gpio4", "gpio5";
+ function = "blsp_uart2";
drive-strength = <2>;
- bias-disable;
+ bias-pull-down;
};
- i2c_8_default: i2c-8-default-state {
- pins = "gpio98", "gpio99";
- function = "blsp_i2c8";
+ i2c_2_default: i2c-2-default-state {
+ pins = "gpio6", "gpio7";
+ function = "blsp_i2c2";
drive-strength = <2>;
bias-disable;
};
- i2c_8_sleep: i2c-8-sleep-state {
- pins = "gpio98", "gpio99";
+ i2c_2_sleep: i2c-2-sleep-state {
+ pins = "gpio6", "gpio7";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
+ i2c_3_default: i2c-3-default-state {
+ pins = "gpio10", "gpio11";
+ function = "blsp_i2c3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c_3_sleep: i2c-3-sleep-state {
+ pins = "gpio10", "gpio11";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c_4_default: i2c-4-default-state {
+ pins = "gpio14", "gpio15";
+ function = "blsp_i2c4";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c_4_sleep: i2c-4-sleep-state {
+ pins = "gpio14", "gpio15";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
spi_5_default: spi-5-default-state {
cs-pins {
pins = "gpio18";
};
};
+ uart_5_default: uart-5-default-state {
+ pins = "gpio16", "gpio17", "gpio18", "gpio19";
+ function = "blsp_uart5";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ uart_5_sleep: uart-5-sleep-state {
+ pins = "gpio16", "gpio17", "gpio18", "gpio19";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c_5_default: i2c-5-default-state {
+ pins = "gpio18", "gpio19";
+ function = "blsp_i2c5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c_5_sleep: i2c-5-sleep-state {
+ pins = "gpio18", "gpio19";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
spi_6_default: spi-6-default-state {
cs-pins {
pins = "gpio22";
};
};
+ i2c_6_default: i2c-6-default-state {
+ pins = "gpio22", "gpio23";
+ function = "blsp_i2c6";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c_6_sleep: i2c-6-sleep-state {
+ pins = "gpio22", "gpio23";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cci0_default: cci0-default-state {
+ pins = "gpio29", "gpio30";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cci1_default: cci1-default-state {
+ pins = "gpio31", "gpio32";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wcnss_pin_a: wcnss-active-state {
+ wcss-wlan2-pins {
+ pins = "gpio76";
+ function = "wcss_wlan2";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ wcss-wlan1-pins {
+ pins = "gpio77";
+ function = "wcss_wlan1";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ wcss-wlan0-pins {
+ pins = "gpio78";
+ function = "wcss_wlan0";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ wcss-wlan-pins {
+ pins = "gpio79", "gpio80";
+ function = "wcss_wlan";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+ };
+
+ gpio_key_default: gpio-key-default-state {
+ pins = "gpio85";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ i2c_8_default: i2c-8-default-state {
+ pins = "gpio98", "gpio99";
+ function = "blsp_i2c8";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c_8_sleep: i2c-8-sleep-state {
+ pins = "gpio98", "gpio99";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ sdc2_cd_on: cd-on-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ sdc2_cd_off: cd-off-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c_7_default: i2c-7-default-state {
+ pins = "gpio135", "gpio136";
+ function = "blsp_i2c7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c_7_sleep: i2c-7-sleep-state {
+ pins = "gpio135", "gpio136";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
spi_7_default: spi-7-default-state {
cs-pins {
pins = "gpio136";
};
};
- uart_5_default: uart-5-default-state {
- pins = "gpio16", "gpio17", "gpio18", "gpio19";
- function = "blsp_uart5";
+ sdc1_clk_on: sdc1-clk-on-state {
+ pins = "sdc1_clk";
+ bias-disable;
drive-strength = <16>;
+ };
+
+ sdc1_clk_off: sdc1-clk-off-state {
+ pins = "sdc1_clk";
bias-disable;
+ drive-strength = <2>;
};
- uart_5_sleep: uart-5-sleep-state {
- pins = "gpio16", "gpio17", "gpio18", "gpio19";
- function = "gpio";
+ sdc1_cmd_on: sdc1-cmd-on-state {
+ pins = "sdc1_cmd";
+ bias-disable;
+ drive-strength = <10>;
+ };
+
+ sdc1_cmd_off: sdc1-cmd-off-state {
+ pins = "sdc1_cmd";
+ bias-disable;
drive-strength = <2>;
+ };
+
+ sdc1_data_on: sdc1-data-on-state {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ sdc1_data_off: sdc1-data-off-state {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ sdc1_rclk_on: sdc1-rclk-on-state {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+
+ sdc1_rclk_off: sdc1-rclk-off-state {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+
+ sdc2_clk_on: sdc2-clk-on-state {
+ pins = "sdc2_clk";
+ drive-strength = <16>;
bias-disable;
};
- wcnss_pin_a: wcnss-active-state {
+ sdc2_clk_off: sdc2-clk-off-state {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
- wcss-wlan2-pins {
- pins = "gpio76";
- function = "wcss_wlan2";
- drive-strength = <6>;
- bias-pull-up;
- };
+ sdc2_cmd_on: sdc2-cmd-on-state {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
- wcss-wlan1-pins {
- pins = "gpio77";
- function = "wcss_wlan1";
- drive-strength = <6>;
- bias-pull-up;
- };
+ sdc2_cmd_off: sdc2-cmd-off-state {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
- wcss-wlan0-pins {
- pins = "gpio78";
- function = "wcss_wlan0";
- drive-strength = <6>;
- bias-pull-up;
- };
+ sdc2_data_on: sdc2-data-on-state {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
- wcss-wlan-pins {
- pins = "gpio79", "gpio80";
- function = "wcss_wlan";
- drive-strength = <6>;
- bias-pull-up;
- };
+ sdc2_data_off: sdc2-data-off-state {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <2>;
};
};
};
};
+ cci: cci@1b0c000 {
+ compatible = "qcom,msm8953-cci";
+ reg = <0x1b0c000 0x4000>;
+
+ interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
+
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_CCI_AHB_CLK>,
+ <&gcc GCC_CAMSS_CCI_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ clock-names = "camss_top_ahb",
+ "cci_ahb",
+ "cci",
+ "camss_ahb";
+
+ assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
+ <&gcc GCC_CAMSS_CCI_CLK>;
+ assigned-clock-rates = <80000000>,
+ <19200000>;
+
+ pinctrl-0 = <&cci0_default &cci1_default>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
gpu: gpu@1c00000 {
compatible = "qcom,adreno-506.0", "qcom,adreno";
reg = <0x01c00000 0x40000>;
"handover",
"stop-ack";
- power-domains = <&rpmpd MSM8976_VDDCX>,
- <&rpmpd MSM8976_VDDMX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>,
+ <&rpmpd RPMPD_VDDMX>;
power-domain-names = "cx", "mx";
qcom,smem-states = <&wcnss_smp2p_out 0>;
chassis-type = "handset";
qcom,msm-id = <251 0>, <252 0>;
- qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
+ qcom,pmic-id = <0x10009 0x1000a 0x0 0x0>;
/* Bullhead firmware doesn't support PSCI */
/delete-node/ psci;
chassis-type = "handset";
/* required for bootloader to select correct board */
qcom,msm-id = <207 0x20000>;
- qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
+ qcom,pmic-id = <0x10009 0x1000a 0x0 0x0>;
qcom,board-id = <8026 0>;
aliases {
status = "okay";
sideinteraction: touch@2c {
- compatible = "ad,ad7147_captouch";
+ compatible = "adi,ad7147_captouch";
reg = <0x2c>;
pinctrl-names = "default", "sleep";
qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
- power-domains = <&rpmpd MSM8998_VDDCX>,
- <&rpmpd MSM8998_VDDMX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>,
+ <&rpmpd RPMPD_VDDMX>;
power-domain-names = "cx", "mx";
status = "disabled";
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&adreno_smmu 0>;
operating-points-v2 = <&gpu_opp_table>;
- power-domains = <&rpmpd MSM8998_VDDMX>;
+ power-domains = <&rpmpd RPMPD_VDDMX>;
status = "disabled";
gpu_opp_table: opp-table {
qcom,smem-states = <&slpi_smp2p_out 0>;
qcom,smem-state-names = "stop";
- power-domains = <&rpmpd MSM8998_SSCCX>;
+ power-domains = <&rpmpd RPMPD_SSCCX>;
power-domain-names = "ssc_cx";
status = "disabled";
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
- power-domains = <&rpmpd MSM8998_VDDMX>;
+ power-domains = <&rpmpd RPMPD_VDDMX>;
mdp_opp_table: opp-table {
compatible = "operating-points-v2";
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
operating-points-v2 = <&dsi_opp_table>;
- power-domains = <&rpmpd MSM8998_VDDCX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
phys = <&mdss_dsi0_phy>;
phy-names = "dsi";
<&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>;
operating-points-v2 = <&dsi_opp_table>;
- power-domains = <&rpmpd MSM8998_VDDCX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
phys = <&mdss_dsi1_phy>;
phy-names = "dsi";
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
- power-domains = <&rpmpd MSM8998_VDDCX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
power-domain-names = "cx";
status = "disabled";
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+ thermal-zones {
+ pm7550_thermal: pm7550-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pm7550_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ /*
+ * Current Linux driver currently only supports up to
+ * 125°C, should be updated to 145°C once available.
+ */
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
+&spmi_bus {
+ pm7550: pmic@1 {
+ compatible = "qcom,pm7550", "qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm7550_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm7550_gpios: gpio@8800 {
+ compatible = "qcom,pm7550-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pm7550_gpios 0 0 12>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pm7550_flash: led-controller@ee00 {
+ compatible = "qcom,pm7550-flash-led", "qcom,spmi-flash-led";
+ reg = <0xee00>;
+ status = "disabled";
+ };
+ };
+};
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
+
pm8550vs_c_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
+
pm8550vs_d_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
+
pm8550vs_e_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
+
pm8550vs_g_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+ thermal-zones {
+ pmiv0104-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pmiv0104_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+
+ trip2 {
+ /*
+ * Current Linux driver currently only supports up to
+ * 125°C, should be updated to 145°C once available.
+ */
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
+&spmi_bus {
+ pmic@PMIV0104_SID {
+ compatible = "qcom,pmiv0104", "qcom,spmi-pmic";
+ reg = <PMIV0104_SID SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmiv0104_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <PMIV0104_SID 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmiv0104_gpios: gpio@8800 {
+ compatible = "qcom,pmiv0104-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmiv0104_gpios 0 0 10>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pmiv0104_eusb2_repeater: phy@fd00 {
+ compatible = "qcom,pmiv0104-eusb2-repeater";
+ reg = <0xfd00>;
+ #phy-cells = <0>;
+ };
+ };
+};
pinctrl-0 = <&wcd_default>;
pinctrl-names = "default";
- reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>;
vdd-buck-supply = <&vreg_l17b_1p7>;
vdd-rxtx-supply = <&vreg_l18b_1p8>;
};
};
+ dp0-connector {
+ compatible = "dp-connector";
+ label = "DP0";
+ type = "mini";
+
+ hpd-gpios = <&io_expander 8 GPIO_ACTIVE_HIGH>;
+
+ port {
+ dp0_connector_in: endpoint {
+ remote-endpoint = <&mdss_dp0_out>;
+ };
+ };
+ };
+
dp-dsi0-connector {
compatible = "dp-connector";
label = "DSI0";
status = "okay";
};
+&mdss_dp0 {
+ status = "okay";
+};
+
+&mdss_dp0_out {
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000>;
+ remote-endpoint = <&dp0_connector_in>;
+};
+
&mdss_dsi0 {
vdda-supply = <&vreg_l11a>;
status = "okay";
status = "okay";
};
+&usb_qmpphy_2 {
+ vdda-phy-supply = <&vreg_l5a>;
+ vdda-pll-supply = <&vreg_l12a>;
+
+ status = "okay";
+};
+
&usb_1 {
status = "okay";
};
};
};
+ vdd_ntn_0p9: regulator-vdd-ntn-0p9 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_NTN_0P9";
+ gpio = <&pm8350c_gpios 2 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <899400>;
+ regulator-max-microvolt = <899400>;
+ enable-active-high;
+ pinctrl-0 = <&ntn_0p9_en>;
+ pinctrl-names = "default";
+ regulator-enable-ramp-delay = <4300>;
+ };
+
+ vdd_ntn_1p8: regulator-vdd-ntn-1p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_NTN_1P8";
+ gpio = <&pm8350c_gpios 3 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ enable-active-high;
+ pinctrl-0 = <&ntn_1p8_en>;
+ pinctrl-names = "default";
+ regulator-enable-ramp-delay = <10000>;
+ };
+
wcn6750-pmu {
compatible = "qcom,wcn6750-pmu";
pinctrl-0 = <&bt_en>;
status = "okay";
};
+&pcie1_port0 {
+ pcie@0,0 {
+ compatible = "pci1179,0623";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x2 0xff>;
+
+ vddc-supply = <&vdd_ntn_0p9>;
+ vdd18-supply = <&vdd_ntn_1p8>;
+ vdd09-supply = <&vdd_ntn_0p9>;
+ vddio1-supply = <&vdd_ntn_1p8>;
+ vddio2-supply = <&vdd_ntn_1p8>;
+ vddio18-supply = <&vdd_ntn_1p8>;
+
+ i2c-parent = <&i2c0 0x77>;
+
+ resx-gpios = <&pm8350c_gpios 1 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&tc9563_resx_n>;
+ pinctrl-names = "default";
+
+ pcie@1,0 {
+ reg = <0x20800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x3 0xff>;
+ };
+
+ pcie@2,0 {
+ reg = <0x21000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x4 0xff>;
+ };
+
+ pcie@3,0 {
+ reg = <0x21800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ bus-range = <0x5 0xff>;
+
+ pci@0,0 {
+ reg = <0x50000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+
+ pci@0,1 {
+ reg = <0x50100 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+ };
+ };
+};
+
&pm7325_gpios {
kypd_vol_up_n: kypd-vol-up-n-state {
pins = "gpio6";
};
};
+&pm8350c_gpios {
+ ntn_0p9_en: ntn-0p9-en-state {
+ pins = "gpio2";
+ function = "normal";
+
+ bias-disable;
+ input-disable;
+ output-enable;
+ power-source = <0>;
+ };
+
+ ntn_1p8_en: ntn-1p8-en-state {
+ pins = "gpio3";
+ function = "normal";
+
+ bias-disable;
+ input-disable;
+ output-enable;
+ power-source = <0>;
+ };
+
+ tc9563_resx_n: tc9563-resx-state {
+ pins = "gpio1";
+ function = "normal";
+
+ bias-disable;
+ input-disable;
+ output-enable;
+ power-source = <0>;
+ };
+};
+
&tlmm {
gpio-reserved-ranges = <32 2>, /* ADSP */
<48 4>; /* NFC */
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Thundercomm All rights reserved.
+ */
+
+/dts-v1/;
+
+/* PM7250B is configured to use SID8/9 */
+#define PM7250B_SID 8
+#define PM7250B_SID1 9
+
+#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "kodiak.dtsi"
+#include "pm7250b.dtsi"
+#include "pm7325.dtsi"
+#include "pm8350c.dtsi" /* PM7350C */
+#include "pmk8350.dtsi" /* PMK7325 */
+
+/delete-node/ &adsp_mem;
+/delete-node/ &cdsp_mem;
+/delete-node/ &ipa_fw_mem;
+/delete-node/ &mpss_mem;
+/delete-node/ &remoteproc_mpss;
+/delete-node/ &remoteproc_wpss;
+/delete-node/ &rmtfs_mem;
+/delete-node/ &video_mem;
+/delete-node/ &wifi;
+/delete-node/ &wlan_ce_mem;
+/delete-node/ &wlan_fw_mem;
+/delete-node/ &wpss_mem;
+/delete-node/ &xbl_mem;
+
+/ {
+ model = "Thundercomm RUBIK Pi 3";
+ compatible = "thundercomm,rubikpi3", "qcom,qcm6490";
+ chassis-type = "embedded";
+
+ aliases {
+ serial0 = &uart5;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&kypd_vol_up_n>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ linux,can-disable;
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <<9611_out>;
+ };
+ };
+ };
+
+ pmic-glink {
+ compatible = "qcom,qcm6490-pmic-glink", "qcom,pmic-glink";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ orientation-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_sbu_in: endpoint {
+ remote-endpoint = <&usb1_sbu_mux>;
+ };
+ };
+ };
+ };
+ };
+
+ fan0: pwm-fan {
+ compatible = "pwm-fan";
+
+ /* cooling level (0, 1, 2, 3) : (0% duty, 25% duty, 50% duty, 100% duty) */
+ cooling-levels = <0 64 128 255>;
+ #cooling-cells = <2>;
+ pwms = <&pm8350c_pwm 3 1000000>;
+
+ pinctrl-0 = <&fan_pwm_out_default>;
+ pinctrl-names = "default";
+ };
+
+ vreg_eth_1v8: regulator-eth-1v8 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vreg_eth_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <50000>;
+
+ gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&usb_eth_power>;
+ pinctrl-names = "default";
+
+ vin-supply = <&vreg_usbhub_pwr_1v8>;
+ };
+
+ vreg_lt9611_3v3: regulator-lt9611-3v3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vreg_lt9611_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 83 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <<9611_vcc_pin>;
+ pinctrl-names = "default";
+ };
+
+ vreg_m2_1v8: regulator-m2-1v8 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vreg_m2_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <50000>;
+
+ gpio = <&tlmm 56 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&m2_vcc_pin>;
+ pinctrl-names = "default";
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vreg_usbhub_pwr_1v8: regulator-usbhub-pwr-1v8 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vreg_usbhub_pwr_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <50000>;
+
+ gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&usbhub_power>;
+ pinctrl-names = "default";
+
+ regulator-always-on;
+ };
+
+ vreg_usbhub_rest_1v8: regulator-usbhub-rest-1v8 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vreg_usbhub_rest_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <50000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&tlmm 136 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&usbhub_rest>;
+ pinctrl-names = "default";
+
+ vin-supply = <&vreg_eth_1v8>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vph_pwr: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+ vreg_wifi_1v8: regulator-wifi-1v8 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vreg_wifi_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <50000>;
+
+ gpio = <&tlmm 125 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&wifi_reset_active>,
+ <&wifi_host_wake>,
+ <&wifi_power_on>;
+ pinctrl-names = "default";
+
+ regulator-always-on;
+ };
+
+ reserved-memory {
+ xbl_mem: xbl@80700000 {
+ reg = <0x0 0x80700000 0x0 0x100000>;
+ no-map;
+ };
+
+ cdsp_secure_heap_mem: cdsp-secure-heap@81800000 {
+ reg = <0x0 0x81800000 0x0 0x1e00000>;
+ no-map;
+ };
+
+ camera_mem: camera@84300000 {
+ reg = <0x0 0x84300000 0x0 0x500000>;
+ no-map;
+ };
+
+ adsp_mem: adsp@86100000 {
+ reg = <0x0 0x86100000 0x0 0x2800000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp@88900000 {
+ reg = <0x0 0x88900000 0x0 0x1e00000>;
+ no-map;
+ };
+
+ video_mem: video@8a700000 {
+ reg = <0x0 0x8a700000 0x0 0x700000>;
+ no-map;
+ };
+
+ cvp_mem: cvp@8ae00000 {
+ reg = <0x0 0x8ae00000 0x0 0x500000>;
+ no-map;
+ };
+
+ gpu_microcode_mem: gpu-microcode@8b31a000 {
+ reg = <0x0 0x8b31a000 0x0 0x2000>;
+ no-map;
+ };
+
+ tz_stat_mem: tz-stat@c0000000 {
+ reg = <0x0 0xc0000000 0x0 0x100000>;
+ no-map;
+ };
+
+ tags_mem: tags@c0100000 {
+ reg = <0x0 0xc0100000 0x0 0x1200000>;
+ no-map;
+ };
+
+ qtee_mem: qtee@c1300000 {
+ reg = <0x0 0xc1300000 0x0 0x500000>;
+ no-map;
+ };
+
+ trusted_apps_mem: trusted-apps@c1800000 {
+ reg = <0x0 0xc1800000 0x0 0x1c00000>;
+ no-map;
+ };
+
+ debug_vm_mem: debug-vm@d0600000 {
+ reg = <0x0 0xd0600000 0x0 0x100000>;
+ no-map;
+ };
+ };
+
+ thermal-zones {
+ quiet-thermal {
+ thermal-sensors = <&pmk8350_adc_tm 1>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ sdm-skin-thermal {
+ thermal-sensors = <&pmk8350_adc_tm 3>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ xo-thermal {
+ thermal-sensors = <&pmk8350_adc_tm 0>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+ };
+
+ usb1-sbu-mux {
+ compatible = "pericom,pi3usb102", "gpio-sbu-mux";
+
+ enable-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
+ select-gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&usb1_sbu_default>;
+ pinctrl-names = "default";
+
+ mode-switch;
+ orientation-switch;
+
+ port {
+ usb1_sbu_mux: endpoint {
+ remote-endpoint = <&pmic_glink_sbu_in>;
+ };
+ };
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm7325-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p972>;
+ vdd-l2-l7-supply = <&vreg_bob_3p296>;
+ vdd-l3-supply = <&vreg_s2b_0p876>;
+ vdd-l5-supply = <&vreg_s2b_0p876>;
+ vdd-l6-l9-l10-supply = <&vreg_s8b_1p272>;
+ vdd-l8-supply = <&vreg_s7b_0p972>;
+ vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p872>;
+ vdd-l13-supply = <&vreg_s7b_0p972>;
+ vdd-l14-l16-supply = <&vreg_s8b_1p272>;
+
+ vreg_s1b_1p872: smps1 {
+ regulator-name = "vreg_s1b_1p872";
+ regulator-min-microvolt = <1840000>;
+ regulator-max-microvolt = <2040000>;
+ };
+
+ vreg_s2b_0p876: smps2 {
+ regulator-name = "vreg_s2b_0p876";
+ regulator-min-microvolt = <570070>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ vreg_s7b_0p972: smps7 {
+ regulator-name = "vreg_s7b_0p972";
+ regulator-min-microvolt = <535000>;
+ regulator-max-microvolt = <1120000>;
+ };
+
+ vreg_s8b_1p272: smps8 {
+ regulator-name = "vreg_s8b_1p272";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>;
+ };
+
+ vreg_l1b_0p912: ldo1 {
+ regulator-name = "vreg_l1b_0p912";
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <925000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p072: ldo2 {
+ regulator-name = "vreg_l2b_3p072";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3b_0p504: ldo3 {
+ regulator-name = "vreg_l3b_0p504";
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <910000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4b_0p752: ldo4 {
+ regulator-name = "vreg_l4b_0p752";
+ regulator-min-microvolt = <752000>;
+ regulator-max-microvolt = <820000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ reg_l5b_0p752: ldo5 {
+ regulator-name = "reg_l5b_0p752";
+ regulator-min-microvolt = <552000>;
+ regulator-max-microvolt = <832000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p2: ldo6 {
+ regulator-name = "vreg_l6b_1p2";
+ regulator-min-microvolt = <1140000>;
+ regulator-max-microvolt = <1260000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_2p952: ldo7 {
+ regulator-name = "vreg_l7b_2p952";
+ regulator-min-microvolt = <2952000>;
+ regulator-max-microvolt = <2952000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_0p904: ldo8 {
+ regulator-name = "vreg_l8b_0p904";
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_1p2: ldo9 {
+ regulator-name = "vreg_l9b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p504: ldo11 {
+ regulator-name = "vreg_l11b_1p504";
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_0p751: ldo12 {
+ regulator-name = "vreg_l12b_0p751";
+ regulator-min-microvolt = <751000>;
+ regulator-max-microvolt = <824000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_0p53: ldo13 {
+ regulator-name = "vreg_l13b_0p53";
+ regulator-min-microvolt = <530000>;
+ regulator-max-microvolt = <824000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_1p08: ldo14 {
+ regulator-name = "vreg_l14b_1p08";
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_0p765: ldo15 {
+ regulator-name = "vreg_l15b_0p765";
+ regulator-min-microvolt = <765000>;
+ regulator-max-microvolt = <1020000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_1p1: ldo16 {
+ regulator-name = "vreg_l16b_1p1";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_1p7: ldo17 {
+ regulator-name = "vreg_l17b_1p7";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18b_1p8: ldo18 {
+ regulator-name = "vreg_l18b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l19b_1p8: ldo19 {
+ regulator-name = "vreg_l19b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8350c-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+ vdd-l1-l12-supply = <&vreg_s1b_1p872>;
+ vdd-l2-l8-supply = <&vreg_s1b_1p872>;
+ vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob_3p296>;
+ vdd-l6-l9-l11-supply = <&vreg_bob_3p296>;
+ vdd-l10-supply = <&vreg_s7b_0p972>;
+ vdd-bob-supply = <&vph_pwr>;
+
+ vreg_s1c_2p19: smps1 {
+ regulator-name = "vreg_s1c_2p19";
+ regulator-min-microvolt = <2190000>;
+ regulator-max-microvolt = <2210000>;
+ };
+
+ vreg_s2c_0p752: smps2 {
+ regulator-name = "vreg_s2c_0p752";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <800000>;
+ };
+
+ vreg_s5c_0p752: smps5 {
+ regulator-name = "vreg_s5c_0p752";
+ regulator-min-microvolt = <465000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ vreg_s7c_0p752: smps7 {
+ regulator-name = "vreg_s7c_0p752";
+ regulator-min-microvolt = <465000>;
+ regulator-max-microvolt = <800000>;
+ };
+
+ vreg_s9c_1p084: smps9 {
+ regulator-name = "vreg_s9c_1p084";
+ regulator-min-microvolt = <1010000>;
+ regulator-max-microvolt = <1170000>;
+ };
+
+ vreg_l1c_1p8: ldo1 {
+ regulator-name = "vreg_l1c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2c_1p62: ldo2 {
+ regulator-name = "vreg_l2c_1p62";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <1980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c_2p8: ldo3 {
+ regulator-name = "vreg_l3c_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3540000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4c_1p62: ldo4 {
+ regulator-name = "vreg_l4c_1p62";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5c_1p62: ldo5 {
+ regulator-name = "vreg_l5c_1p62";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6c_2p96: ldo6 {
+ regulator-name = "vreg_l6c_2p96";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7c_3p0: ldo7 {
+ regulator-name = "vreg_l7c_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c_1p62: ldo8 {
+ regulator-name = "vreg_l8c_1p62";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9c_2p96: ldo9 {
+ regulator-name = "vreg_l9c_2p96";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10c_0p88: ldo10 {
+ regulator-name = "vreg_l10c_0p88";
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11c_2p8: ldo11 {
+ regulator-name = "vreg_l11c_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12c_1p65: ldo12 {
+ regulator-name = "vreg_l12c_1p65";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13c_2p7: ldo13 {
+ regulator-name = "vreg_l13c_2p7";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob_3p296: bob {
+ regulator-name = "vreg_bob_3p296";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3960000>;
+ };
+ };
+};
+
+&gcc {
+ protected-clocks = <GCC_CFG_NOC_LPASS_CLK>,
+ <GCC_MSS_CFG_AHB_CLK>,
+ <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>,
+ <GCC_MSS_OFFLINE_AXI_CLK>,
+ <GCC_MSS_Q6SS_BOOT_CLK_SRC>,
+ <GCC_MSS_Q6_MEMNOC_AXI_CLK>,
+ <GCC_MSS_SNOC_AXI_CLK>,
+ <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+ <GCC_QSPI_CORE_CLK>,
+ <GCC_QSPI_CORE_CLK_SRC>,
+ <GCC_SEC_CTRL_CLK_SRC>,
+ <GCC_WPSS_AHB_BDG_MST_CLK>,
+ <GCC_WPSS_AHB_CLK>,
+ <GCC_WPSS_RSCP_CLK>;
+};
+
+&gpi_dma0 {
+ status = "okay";
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/qcs6490/a660_zap.mbn";
+};
+
+/* Pin 3, 5 in 40-pin connector */
+&i2c1 {
+ status = "okay";
+};
+
+&i2c9 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ lt9611_codec: hdmi-bridge@39 {
+ compatible = "lontium,lt9611";
+ reg = <0x39>;
+
+ interrupts-extended = <&tlmm 20 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <&vreg_lt9611_3v3>;
+ vcc-supply = <&vreg_lt9611_3v3>;
+
+ pinctrl-0 = <<9611_irq_pin>,
+ <<9611_rst_pin>;
+ pinctrl-names = "default";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lt9611_a: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ lt9611_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
+&lpass_audiocc {
+ compatible = "qcom,qcm6490-lpassaudiocc";
+ /delete-property/ power-domains;
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dp {
+ status = "okay";
+};
+
+&mdss_dp_out {
+ data-lanes = <0 1>;
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+
+ remote-endpoint = <&usb_dp_qmpphy_dp_in>;
+};
+
+&mdss_dsi {
+ vdda-supply = <&vreg_l6b_1p2>;
+
+ status = "okay";
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <<9611_a>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi_phy {
+ vdds-supply = <&vreg_l10c_0p88>;
+
+ status = "okay";
+};
+
+&pcie0 {
+ perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&pcie0_clkreq_n>,
+ <&pcie0_reset_n>,
+ <&pcie0_wake_n>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l10c_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+
+ status = "okay";
+};
+
+&pcie1 {
+ perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie1_clkreq_n>,
+ <&pcie1_reset_n>,
+ <&pcie1_wake_n>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l10c_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+
+ status = "okay";
+};
+
+&pm7325_gpios {
+ kypd_vol_up_n: kypd-vol-up-n-state {
+ pins = "gpio6";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&pm7325_temp_alarm {
+ io-channels = <&pmk8350_vadc PM7325_ADC7_DIE_TEMP>;
+ io-channel-names = "thermal";
+};
+
+&pmk8350_adc_tm {
+ status = "okay";
+
+ xo-therm@0 {
+ reg = <0>;
+ io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ quiet-therm@1 {
+ reg = <1>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ sdm-skin-therm@3 {
+ reg = <3>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+};
+
+&pm8350c_pwm {
+ status = "okay";
+
+ multi-led {
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_INDICATOR;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@3 {
+ reg = <3>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+};
+
+&pmk8350_rtc {
+ allow-set-time;
+
+ status = "okay";
+};
+
+&pmk8350_vadc {
+ channel@3 {
+ reg = <PMK8350_ADC7_DIE_TEMP>;
+ label = "pmk8350_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@44 {
+ reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ label = "xo_therm";
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,ratiometric;
+ };
+
+ channel@103 {
+ reg = <PM7325_ADC7_DIE_TEMP>;
+ label = "pm7325_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@144 {
+ reg = <PM7325_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_quiet_therm";
+ };
+
+ channel@146 {
+ reg = <PM7325_ADC7_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_sdm_skin_therm";
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ firmware-name = "qcom/qcm6490/qupv3fw.elf";
+
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ firmware-name = "qcom/qcm6490/qupv3fw.elf";
+
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/qcs6490/Thundercomm/RubikPi3/adsp.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/qcs6490/cdsp.mbn";
+
+ status = "okay";
+};
+
+/* WIFI part of the AP6256 connected with SDIO */
+&sdhc_2 {
+ vmmc-supply = <&vreg_l9c_2p96>;
+ vqmmc-supply = <&vreg_l6c_2p96>;
+
+ non-removable;
+ keep-power-in-suspend;
+ /delete-property/ cd-gpios;
+
+ status = "okay";
+};
+
+/* Pin 19, 21, 23, 24 in 40-pin connector */
+&spi12 {
+ status = "okay";
+};
+
+&thermal_zones {
+ cpu0-thermal {
+ trips {
+ cpu_tepid: cpu-tepid {
+ temperature = <65000>;
+ hysteresis = <5000>;
+ type = "active";
+ };
+
+ cpu_warm: cpu-warm {
+ temperature = <80000>;
+ hysteresis = <5000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map-cpu-tepid {
+ cooling-device = <&fan0 1 1>;
+ trip = <&cpu_tepid>;
+ };
+
+ map-cpu-warm {
+ cooling-device = <&fan0 2 2>;
+ trip = <&cpu_warm>;
+ };
+
+ map-cpu-hot {
+ cooling-device = <&fan0 3 3>;
+ trip = <&cpu0_alert0>;
+ };
+ };
+ };
+};
+
+/* Pin 8, 10 in 40-pin connector */
+&uart2 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+/* BT part of the AP6256 connected with UART */
+&uart7 {
+ /delete-property/ interrupts;
+ interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
+ <&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-1 = <&qup_uart7_sleep_cts>,
+ <&qup_uart7_sleep_rts>,
+ <&qup_uart7_sleep_tx>,
+ <&qup_uart7_sleep_rx>;
+ pinctrl-names = "default",
+ "sleep";
+
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4345c5";
+ clocks = <&sleep_clk>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&tlmm 137 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&tlmm 17 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&bt_device_wake>,
+ <&bt_host_wake>,
+ <&bt_reset>;
+ pinctrl-names = "default";
+ vbat-supply = <&vreg_wifi_1v8>;
+ vddio-supply = <&vreg_wifi_1v8>;
+ max-speed = <3000000>;
+ };
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_hsphy {
+ vdda-pll-supply = <&vreg_l10c_0p88>;
+ vdda33-supply = <&vreg_l2b_3p072>;
+ vdda18-supply = <&vreg_l1c_1p8>;
+
+ status = "okay";
+};
+
+&usb_1_qmpphy {
+ vdda-phy-supply = <&vreg_l6b_1p2>;
+ vdda-pll-supply = <&vreg_l1b_0p912>;
+
+ status = "okay";
+};
+
+&usb_2 {
+ dr_mode = "host";
+
+ status = "okay";
+};
+
+&usb_2_hsphy {
+ vdda-pll-supply = <&vreg_l10c_0p88>;
+ vdda18-supply = <&vreg_l1c_1p8>;
+ vdda33-supply = <&vreg_l2b_3p072>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss_in>;
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l7b_2p952>;
+ vcc-max-microamp = <800000>;
+ vccq-supply = <&vreg_l9b_1p2>;
+ vccq-max-microamp = <900000>;
+ vccq2-supply = <&vreg_l9b_1p2>;
+ vccq2-max-microamp = <900000>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l10c_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+
+ status = "okay";
+};
+
+&venus {
+ status = "okay";
+};
+
+/* PINCTRL - additions to nodes defined in kodiak.dtsi */
+&pcie0_clkreq_n {
+ bias-pull-up;
+ drive-strength = <8>;
+};
+
+&pcie1_clkreq_n {
+ bias-pull-up;
+ drive-strength = <8>;
+};
+
+&pm8350c_gpios {
+ fan_pwm_out_default: fan-pwm-out-default-state {
+ pins = "gpio8";
+ function = "func1";
+ power-source = <1>;
+ drive-push-pull;
+ output-high;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+ };
+};
+
+&qup_uart7_cts {
+ /*
+ * Configure a bias-bus-hold on CTS to lower power
+ * usage when Bluetooth is turned off. Bus hold will
+ * maintain a low power state regardless of whether
+ * the Bluetooth module drives the pin in either
+ * direction or leaves the pin fully unpowered.
+ */
+ bias-bus-hold;
+};
+
+&qup_uart7_rts {
+ /* We'll drive RTS, so no pull */
+ bias-disable;
+ drive-strength = <2>;
+};
+
+&qup_uart7_rx {
+ /*
+ * Configure a pull-up on RX. This is needed to avoid
+ * garbage data when the TX pin of the Bluetooth module is
+ * in tri-state (module powered off or not driving the
+ * signal yet).
+ */
+ bias-pull-up;
+};
+
+&qup_uart7_tx {
+ /* We'll drive TX, so no pull */
+ bias-disable;
+ drive-strength = <2>;
+};
+
+&sdc2_clk {
+ bias-disable;
+ drive-strength = <16>;
+};
+
+&sdc2_cmd {
+ bias-pull-up;
+ drive-strength = <10>;
+};
+
+&sdc2_data {
+ bias-pull-up;
+ drive-strength = <10>;
+};
+
+&tlmm {
+ pcie1_reset_n: pcie1-reset-n-state {
+ pins = "gpio2";
+ function = "gpio";
+ drive-strength = <8>;
+ output-low;
+ bias-disable;
+ };
+
+ pcie1_wake_n: pcie1-wake-n-state {
+ pins = "gpio3";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ usb_eth_power: usb-eth-power-state {
+ pins = "gpio7";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ wifi_reset_active: wifi-reset-active-state {
+ pins = "gpio16";
+ function = "gpio";
+ drive-strength = <8>;
+ output-high;
+ bias-disable;
+ };
+
+ bt_reset: bt-reset-state {
+ pins = "gpio17";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ lt9611_irq_pin: lt9611-irq-state {
+ pins = "gpio20";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ lt9611_rst_pin: lt9611-rst-state {
+ pins = "gpio21";
+ function = "gpio";
+ drive-strength = <8>;
+ output-high;
+ input-disable;
+ };
+
+ qup_uart7_sleep_cts: qup-uart7-sleep-cts-state {
+ pins = "gpio28";
+ function = "gpio";
+ /*
+ * Configure a bias-bus-hold on CTS to lower power
+ * usage when Bluetooth is turned off. Bus hold will
+ * maintain a low power state regardless of whether
+ * the Bluetooth module drives the pin in either
+ * direction or leaves the pin fully unpowered.
+ */
+ bias-bus-hold;
+ };
+
+ qup_uart7_sleep_rts: qup-uart7-sleep-rts-state {
+ pins = "gpio29";
+ function = "gpio";
+ /*
+ * Configure pull-down on RTS. As RTS is active low
+ * signal, pull it low to indicate the BT SoC that it
+ * can wakeup the system anytime from suspend state by
+ * pulling RX low (by sending wakeup bytes).
+ */
+ bias-pull-down;
+ };
+
+ qup_uart7_sleep_tx: qup-uart7-sleep-tx-state {
+ pins = "gpio30";
+ function = "gpio";
+ /*
+ * Configure pull-up on TX when it isn't actively driven
+ * to prevent BT SoC from receiving garbage during sleep.
+ */
+ bias-pull-up;
+ };
+
+ qup_uart7_sleep_rx: qup-uart7-sleep-rx-state {
+ pins = "gpio31";
+ function = "gpio";
+ /*
+ * Configure a pull-up on RX. This is needed to avoid
+ * garbage data when the TX pin of the Bluetooth module
+ * is floating which may cause spurious wakeups.
+ */
+ bias-pull-up;
+ };
+
+ wifi_host_wake: wifi-host-wake-state {
+ pins = "gpio38";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ bt_device_wake: bt-device-wake-state {
+ pins = "gpio39";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ usb1_sbu_default: usb1-sbu-state {
+ sel-pins {
+ pins = "gpio52";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ oe-n-pins {
+ pins = "gpio53";
+ function = "gpio";
+ drive-strength = <8>;
+ output-high;
+ bias-disable;
+ };
+ };
+
+ m2_vcc_pin: m2-vcc-state {
+ pins = "gpio56";
+ function = "gpio";
+ drive-strength = <8>;
+ output-high;
+ input-disable;
+ };
+
+ lt9611_vcc_pin: lt9611-vcc-pin-state {
+ pins = "gpio83";
+ function = "gpio";
+ drive-strength = <8>;
+ output-high;
+ input-disable;
+ };
+
+ usbhub_power: usbhub-power-state {
+ pins = "gpio86";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ pcie0_reset_n: pcie0-reset-n-state {
+ pins = "gpio87";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ pcie0_wake_n: pcie0-wake-n-state {
+ pins = "gpio89";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ wifi_power_on: wifi-power-on-state {
+ pins = "gpio125";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ usbhub_rest: usbhub-reset-state {
+ pins = "gpio136";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ bt_host_wake: bt-host-wake-state {
+ pins = "gpio137";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+};
stdout-path = "serial0:115200n8";
};
+ dp0-connector {
+ compatible = "dp-connector";
+ label = "DP0";
+ type = "full-size";
+
+ port {
+ dp0_connector_in: endpoint {
+ remote-endpoint = <&mdss_dp0_out>;
+ };
+ };
+ };
+
regulator-usb2-vbus {
compatible = "regulator-fixed";
regulator-name = "USB2_VBUS";
status = "okay";
};
+&mdss {
+ status = "okay";
+};
+
+&mdss_dp0 {
+ pinctrl-0 = <&dp_hot_plug_det>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&mdss_dp0_out {
+ data-lanes = <0 1 2 3>;
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+ remote-endpoint = <&dp0_connector_in>;
+};
+
+&mdss_dp0_phy {
+ vdda-phy-supply = <&vreg_l5a>;
+ vdda-pll-supply = <&vreg_l4a>;
+
+ status = "okay";
+};
+
+&pcie0 {
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcieport0 {
+ reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l6a>;
+ vdda-pll-supply = <&vreg_l5a>;
+
+ status = "okay";
+};
+
+&pcie1 {
+ pinctrl-0 = <&pcie1_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcieport1 {
+ reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l6a>;
+ vdda-pll-supply = <&vreg_l5a>;
+
+ status = "okay";
+};
+
&qupv3_id_0 {
status = "okay";
};
};
&tlmm {
+ pcie0_default_state: pcie0-default-state {
+ wake-pins {
+ pins = "gpio0";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ clkreq-pins {
+ pins = "gpio1";
+ function = "pcie0_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-pins {
+ pins = "gpio2";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
ethernet0_default: ethernet0-default-state {
ethernet0_mdc: ethernet0-mdc-pins {
pins = "gpio5";
bias-pull-up;
};
};
+
+ pcie1_default_state: pcie1-default-state {
+ wake-pins {
+ pins = "gpio21";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ clkreq-pins {
+ pins = "gpio22";
+ function = "pcie1_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-pins {
+ pins = "gpio23";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ dp_hot_plug_det: dp-hot-plug-det-state {
+ pins = "gpio94";
+ function = "edp0_hot";
+ bias-disable;
+ };
};
&uart7 {
vdd3-supply = <&vreg_l5b_3p1>;
};
+&pm8550vs_c {
+ status = "okay";
+};
+
+&pm8550vs_d {
+ status = "okay";
+};
+
+&pm8550vs_e {
+ status = "okay";
+};
+
+&pm8550vs_g {
+ status = "okay";
+};
+
&sleep_clk {
clock-frequency = <32764>;
};
gem_noc: interconnect@19100000 {
compatible = "qcom,qdu1000-gem-noc";
- reg = <0x0 0x19100000 0x0 0xB8080>;
+ reg = <0x0 0x19100000 0x0 0xb8080>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2025, Arduino SRL
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include "agatti.dtsi"
+#include "pm4125.dtsi"
+
+/delete-node/ &cont_splash_memory;
+
+/ {
+ model = "Arduino UnoQ";
+ compatible = "arduino,imola", "qcom,qrb2210", "qcom,qcm2290";
+ chassis-type = "embedded";
+
+ aliases {
+ serial0 = &uart4;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ sdhc1 = &sdhc_1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+ pinctrl-0 = <&key_volp_n>, <&key_vold_n>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ gpios = <&tlmm 36 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+
+ led-bt {
+ label = "unoq:bt-blue2";
+ function = LED_FUNCTION_BLUETOOTH;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "bluetooth-power";
+ default-state = "off";
+ };
+
+ led-panic {
+ label = "unoq:panic-red2";
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "none";
+ default-state = "off";
+ panic-indicator;
+ };
+
+ led-wlan {
+ label = "unoq:wlan-green2";
+ function = LED_FUNCTION_WLAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+
+ ledb: led-user-blue {
+ label = "unoq:user-blue1";
+ gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+
+ ledg: led-user-green {
+ label = "unoq:user-green1";
+ gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ ledr: led-user-red {
+ label = "unoq:user-red1";
+ gpios = <&tlmm 41 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ };
+ };
+
+ multi-led {
+ compatible = "leds-group-multicolor";
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_INDICATOR;
+ leds = <&ledr>, <&ledg>, <&ledb>;
+ };
+
+ /* PM4125 charger out, supplied by VBAT */
+ vph_pwr: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&gpi_dma0 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/qcm2290/a702_zap.mbn";
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+
+ status = "okay";
+};
+
+&pm4125_vbus {
+ regulator-min-microamp = <500000>;
+ regulator-max-microamp = <500000>;
+
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/qcm2290/adsp.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/qcm2290/modem.mbn";
+
+ status = "okay";
+};
+
+&rpm_requests {
+ regulators {
+ compatible = "qcom,rpm-pm2250-regulators";
+ vdd_s3-supply = <&vph_pwr>;
+ vdd_s4-supply = <&vph_pwr>;
+ vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12-supply = <&pm4125_s3>;
+ vdd_l4_l17_l18_l19_l20_l21_l22-supply = <&vph_pwr>;
+ vdd_l13_l14_l15_l16-supply = <&pm4125_s4>;
+
+ pm4125_s3: s3 {
+ /* 0.4V-1.6625V -> 1.3V (Power tree requirements) */
+ regulator-min-microvolt = <1352000>;
+ regulator-max-microvolt = <1352000>;
+ regulator-boot-on;
+ };
+
+ pm4125_s4: s4 {
+ /* 1.2V-2.35V -> 2.05V (Power tree requirements) */
+ regulator-min-microvolt = <2072000>;
+ regulator-max-microvolt = <2072000>;
+ regulator-boot-on;
+ };
+
+ pm4125_l2: l2 {
+ /* LPDDR4X VDD2 */
+ regulator-min-microvolt = <1136000>;
+ regulator-max-microvolt = <1136000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm4125_l3: l3 {
+ /* LPDDR4X VDDQ */
+ regulator-min-microvolt = <616000>;
+ regulator-max-microvolt = <616000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm4125_l4: l4 {
+ /* max = 3.05V -> max = 2.7 to disable 3V signaling (SDHCI2) */
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2700000>;
+ regulator-allow-set-load;
+ };
+
+ pm4125_l5: l5 {
+ /* CSI/DSI */
+ regulator-min-microvolt = <1232000>;
+ regulator-max-microvolt = <1232000>;
+ regulator-allow-set-load;
+ regulator-boot-on;
+ };
+
+ pm4125_l6: l6 {
+ /* DRAM PLL */
+ regulator-min-microvolt = <928000>;
+ regulator-max-microvolt = <928000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm4125_l7: l7 {
+ /* Wi-Fi CX */
+ regulator-min-microvolt = <664000>;
+ regulator-max-microvolt = <664000>;
+ };
+
+ pm4125_l10: l10 {
+ /* Wi-Fi RFA */
+ regulator-min-microvolt = <1304000>;
+ regulator-max-microvolt = <1304000>;
+ };
+
+ pm4125_l11: l11 {
+ /* ANX7625 DVDD1P0V/AVDD1P0V */
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ pm4125_l12: l12 {
+ /* USB PHYs */
+ regulator-min-microvolt = <928000>;
+ regulator-max-microvolt = <928000>;
+ regulator-allow-set-load;
+ regulator-boot-on;
+ };
+
+ pm4125_l13: l13 {
+ /* USB/QFPROM/PLLs */
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allow-set-load;
+ regulator-boot-on;
+ };
+
+ pm4125_l14: l14 {
+ /* SDHCI1 EMMC VCCQ */
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allow-set-load;
+ /* Broken hardware, never turn it off! */
+ regulator-always-on;
+ };
+
+ pm4125_l15: l15 {
+ /* VDDIO */
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allow-set-load;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm4125_l20: l20 {
+ /* SDHCI1 EMMC */
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-allow-set-load;
+ };
+
+ pm4125_l21: l21 {
+ /* USB HS */
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-allow-set-load;
+ regulator-boot-on;
+ };
+
+ pm4125_l22: l22 {
+ /* Wi-Fi VDD */
+ regulator-min-microvolt = <3312000>;
+ regulator-max-microvolt = <3312000>;
+ };
+ };
+};
+
+&sdhc_1 {
+ vmmc-supply = <&pm4125_l20>;
+ vqmmc-supply = <&pm4125_l14>;
+ pinctrl-0 = <&sdc1_state_on>;
+ pinctrl-1 = <&sdc1_state_off>;
+ pinctrl-names = "default", "sleep";
+ mmc-hs400-1_8v;
+ mmc-hs200-1_8v;
+ non-removable;
+ supports-cqe;
+ no-sdio;
+ no-sd;
+
+ status = "okay";
+};
+
+&spi5 {
+ status = "okay";
+
+ spidev@0 {
+ reg = <0>;
+ compatible = "arduino,unoq-mcu";
+ pinctrl-0 = <&spidev_cs>;
+ pinctrl-names = "default";
+ };
+};
+
+&tlmm {
+ spidev_cs: spidev-cs-state {
+ pins = "gpio17";
+ function = "gpio";
+ drive-strength = <16>;
+ };
+
+ jmisc_gpio18: jmisc-gpio18-state {
+ pins = "gpio18";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ jmisc_gpio28: jmisc-gpio28-state {
+ pins = "gpio28";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ key_vold_n: key-vold-n-state {
+ pins = "gpio36";
+ function = "gpio";
+ bias-pull-up;
+ output-disable;
+ };
+
+ key_volp_n: key-volp-n-state {
+ pins = "gpio96";
+ function = "gpio";
+ bias-pull-up;
+ output-disable;
+ };
+
+ jmisc_gpio98: jmisc-gpio98-state {
+ pins = "gpio98";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ jmisc_gpio99: jmisc-gpio99-state {
+ pins = "gpio99";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ jmisc_gpio100: jmisc-gpio100-state {
+ pins = "gpio100";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ jmisc_gpio101: jmisc-gpio101-state {
+ pins = "gpio101";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+/* UART connected to Bluetooth */
+&uart3 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,wcn3988-bt";
+
+ vddio-supply = <&pm4125_l15>;
+ vddxo-supply = <&pm4125_l13>;
+ vddrf-supply = <&pm4125_l10>;
+ vddch0-supply = <&pm4125_l22>;
+ enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
+ max-speed = <3000000>;
+ };
+};
+
+/* UART exposed in JCTL */
+&uart4 {
+ compatible = "qcom,geni-debug-uart";
+
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb_hsphy {
+ vdd-supply = <&pm4125_l12>;
+ vdda-pll-supply = <&pm4125_l13>;
+ vdda-phy-dpdm-supply = <&pm4125_l21>;
+
+ status = "okay";
+};
+
+&usb_qmpphy {
+ vdda-phy-supply = <&pm4125_l12>;
+ vdda-pll-supply = <&pm4125_l13>;
+
+ status = "okay";
+};
+
+&wifi {
+ vdd-0.8-cx-mx-supply = <&pm4125_l7>;
+ vdd-1.8-xo-supply = <&pm4125_l13>;
+ vdd-1.3-rfa-supply = <&pm4125_l10>;
+ vdd-3.3-ch0-supply = <&pm4125_l22>;
+ qcom,ath10k-calibration-variant = "ArduinoImola";
+ firmware-name = "qcm2290";
+
+ status = "okay";
+};
+
+&xo_board {
+ clock-frequency = <38400000>;
+};
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
+#include <dt-bindings/gpio/gpio.h>
+
+&pm8008 {
+ status = "okay";
+};
+
+&camss {
+ status = "okay";
+
+ vdd-csiphy-1p2-supply = <&pm4125_l5>;
+ vdd-csiphy-1p8-supply = <&pm4125_l13>;
+
+ ports {
+ port@0 {
+ csiphy0_ep: endpoint {
+ data-lanes = <0 1>;
+ remote-endpoint = <&ov9282_ep>;
+ };
+ };
+ };
+};
+
+&cci {
+ status = "okay";
+};
+
+&cci_i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Vision Mezzanine DIP3-1 must be ON (Selects camera CAM0A&B) */
+ camera@60 {
+ compatible = "ovti,ov9282";
+ reg = <0x60>;
+
+ /* Reset is active-low, but driver applies inverted reset logic */
+ reset-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&mclk3_default>;
+ pinctrl-names = "default";
+
+ clocks = <&gcc GCC_CAMSS_MCLK3_CLK>;
+ assigned-clocks = <&gcc GCC_CAMSS_MCLK3_CLK>;
+ assigned-clock-rates = <24000000>;
+
+ avdd-supply = <&vreg_l3p>;
+ dvdd-supply = <&vreg_l1p>;
+ dovdd-supply = <&vreg_l7p>;
+
+ port {
+ ov9282_ep: endpoint {
+ link-frequencies = /bits/ 64 <400000000>;
+ data-lanes = <1 2>;
+ remote-endpoint = <&csiphy0_ep>;
+ };
+ };
+ };
+};
firmware-name = "qcom/qcm2290/a702_zap.mbn";
};
+&i2c1 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ pm8008: pmic@8 {
+ compatible = "qcom,pm8008";
+ reg = <0x8>;
+
+ interrupts-extended = <&tlmm 25 IRQ_TYPE_EDGE_RISING>;
+ reset-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
+
+ vdd-l1-l2-supply = <&pm4125_s3>;
+ vdd-l3-l4-supply = <&vph_pwr>;
+ vdd-l5-supply = <&vph_pwr>;
+ vdd-l6-supply = <&vph_pwr>;
+ vdd-l7-supply = <&vph_pwr>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pm8008 0 0 2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ #thermal-sensor-cells = <0>;
+
+ status = "disabled";
+
+ regulators {
+ vreg_l1p: ldo1 {
+ regulator-name = "vreg_l1p";
+ regulator-min-microvolt = <528000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vreg_l2p: ldo2 {
+ regulator-name = "vreg_l2p";
+ regulator-min-microvolt = <528000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vreg_l3p: ldo3 {
+ regulator-name = "vreg_l3p";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ vreg_l4p: ldo4 {
+ regulator-name = "vreg_l4p";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <3404000>;
+ };
+
+ vreg_l5p: ldo5 {
+ regulator-name = "vreg_l5p";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ vreg_l6p: ldo6 {
+ regulator-name = "vreg_l6p";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ vreg_l7p: ldo7 {
+ regulator-name = "vreg_l7p";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+ };
+ };
+};
+
&i2c2_gpio {
clock-frequency = <400000>;
status = "okay";
&uart3 {
interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <&tlmm 11 IRQ_TYPE_LEVEL_HIGH>;
+ <&tlmm 11 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&uart3_default>;
pinctrl-1 = <&uart3_sleep>;
pinctrl-names = "default", "sleep";
status = "okay";
};
+&lpass_tlmm {
+ /delete-property/ clocks;
+ /delete-property/ clock-names;
+};
+
&lpasscc {
status = "okay";
};
qcom,dout-ports = <5>;
qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
- qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
- qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
+ qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
+ qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
pwr_cluster_sleep_0: cluster-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "pwr-cluster-dynamic-retention";
- arm,psci-suspend-param = <0x400000F2>;
+ arm,psci-suspend-param = <0x400000f2>;
entry-latency-us = <284>;
exit-latency-us = <384>;
min-residency-us = <9987>;
pwr_cluster_sleep_1: cluster-sleep-0-1 {
compatible = "arm,idle-state";
idle-state-name = "pwr-cluster-retention";
- arm,psci-suspend-param = <0x400000F3>;
+ arm,psci-suspend-param = <0x400000f3>;
entry-latency-us = <338>;
exit-latency-us = <423>;
min-residency-us = <9987>;
pwr_cluster_sleep_2: cluster-sleep-0-2 {
compatible = "arm,idle-state";
idle-state-name = "pwr-cluster-retention";
- arm,psci-suspend-param = <0x400000F4>;
+ arm,psci-suspend-param = <0x400000f4>;
entry-latency-us = <515>;
exit-latency-us = <1821>;
min-residency-us = <9987>;
perf_cluster_sleep_0: cluster-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "perf-cluster-dynamic-retention";
- arm,psci-suspend-param = <0x400000F2>;
+ arm,psci-suspend-param = <0x400000f2>;
entry-latency-us = <272>;
exit-latency-us = <329>;
min-residency-us = <9987>;
perf_cluster_sleep_1: cluster-sleep-1-1 {
compatible = "arm,idle-state";
idle-state-name = "perf-cluster-retention";
- arm,psci-suspend-param = <0x400000F3>;
+ arm,psci-suspend-param = <0x400000f3>;
entry-latency-us = <332>;
exit-latency-us = <368>;
min-residency-us = <9987>;
perf_cluster_sleep_2: cluster-sleep-1-2 {
compatible = "arm,idle-state";
idle-state-name = "perf-cluster-retention";
- arm,psci-suspend-param = <0x400000F4>;
+ arm,psci-suspend-param = <0x400000f4>;
entry-latency-us = <545>;
exit-latency-us = <1609>;
min-residency-us = <9987>;
};
};
- soc@0 {
+ soc: soc@0 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
};
gpu_speed_bin: gpu-speed-bin@41a0 {
- reg = <0x41a2 0x1>;
- bits = <5 7>;
+ reg = <0x41a2 0x2>;
+ bits = <5 8>;
};
};
qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
- power-domains = <&rpmpd SDM660_VDDCX>,
- <&rpmpd SDM660_VDDMX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>,
+ <&rpmpd RPMPD_VDDMX>;
power-domain-names = "cx", "mx";
memory-region = <&mba_region>, <&mpss_region>, <&mdata_mem>;
"rbcpr",
"core";
- power-domains = <&rpmpd SDM660_VDDMX>;
+ power-domains = <&rpmpd RPMPD_VDDMX>;
iommus = <&kgsl_smmu 0>;
nvmem-cells = <&gpu_speed_bin>;
reg = <0x05100000 0x40000>;
#iommu-cells = <1>;
+ clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
+ clock-names = "bus";
+
+ power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
+
#global-interrupts = <2>;
interrupts =
<GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_state_on>;
pinctrl-1 = <&sdc2_state_off>;
- power-domains = <&rpmpd SDM660_VDDCX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
status = "disabled";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_state_on>;
pinctrl-1 = <&sdc1_state_off>;
- power-domains = <&rpmpd SDM660_VDDCX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
bus-width = <8>;
non-removable;
reg-names = "mdss_phys", "vbif_phys";
power-domains = <&mmcc MDSS_GDSC>;
+ resets = <&mmcc MDSS_BCR>;
clocks = <&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>,
"rotator-mem";
iommus = <&mmss_smmu 0>;
operating-points-v2 = <&mdp_opp_table>;
- power-domains = <&rpmpd SDM660_VDDCX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
ports {
#address-cells = <1>;
reg-names = "dsi_ctrl";
operating-points-v2 = <&dsi_opp_table>;
- power-domains = <&rpmpd SDM660_VDDCX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
interrupt-parent = <&mdss>;
interrupts = <4>;
status = "disabled";
};
+ lpi_tlmm: pinctrl@15070000 {
+ compatible = "qcom,sdm660-lpass-lpi-pinctrl";
+ reg = <0x15070000 0x20000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpi_tlmm 0 0 32>;
+
+ cdc_pdm_default: cdc-pdm-default-state {
+ clk-pins {
+ pins = "gpio18";
+ function = "pdm_clk";
+ drive-strength = <8>;
+ output-high;
+ };
+
+ sync-pins {
+ pins = "gpio19";
+ function = "pdm_sync";
+ drive-strength = <4>;
+ output-high;
+ };
+
+ tx-pins {
+ pins = "gpio20";
+ function = "pdm_tx";
+ drive-strength = <8>;
+ };
+
+ rx-pins {
+ pins = "gpio21", "gpio23", "gpio25";
+ function = "pdm_rx";
+ drive-strength = <4>;
+ output-high;
+ };
+ };
+
+ cdc_comp_default: cdc-comp-default-state {
+ pins = "gpio22", "gpio24";
+ function = "comp_rx";
+ drive-strength = <8>;
+ };
+
+ cdc_dmic_default: cdc-dmic-default-state {
+ dmic1-clk-pins {
+ pins = "gpio26";
+ function = "dmic1_clk";
+ drive-strength = <8>;
+ output-high;
+ };
+
+ dmic1-data-pins {
+ pins = "gpio27";
+ function = "dmic1_data";
+ drive-strength = <8>;
+ output-high;
+ };
+
+ dmic2-clk-pins {
+ pins = "gpio28";
+ function = "dmic2_clk";
+ drive-strength = <8>;
+ input-enable;
+ };
+
+ dmic2-data-pins {
+ pins = "gpio29";
+ function = "dmic2_data";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+ };
+
adsp_pil: remoteproc@15700000 {
compatible = "qcom,sdm660-adsp-pas";
reg = <0x15700000 0x4040>;
clock-names = "xo";
memory-region = <&adsp_region>;
- power-domains = <&rpmpd SDM660_VDDCX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
power-domain-names = "cx";
qcom,smem-states = <&adsp_smp2p_out 0>;
};
};
};
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "adsp";
+ qcom,non-secure-domain;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@1 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <1>;
+ iommus = <&lpass_smmu 3>;
+ };
+
+ compute-cb@2 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <2>;
+ iommus = <&lpass_smmu 7>;
+ };
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&lpass_smmu 8>;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+ iommus = <&lpass_smmu 9>;
+ };
+ };
};
};
};
};
+ vreg_cam_af_2p85: regulator-cam-af-2p85 {
+ compatible = "regulator-fixed";
+ regulator-name = "cam_af_2p85";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+
+ gpio = <&tlmm 128 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vph_pwr>;
+ };
+
+ vreg_cam_io_1p8: regulator-cam-io-1p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "cam_io_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&tlmm 130 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vph_pwr>;
+ };
+
+ vreg_cam2_dig_1p2: regulator-cam2-dig-1p2 {
+ compatible = "regulator-fixed";
+ regulator-name = "cam2_dig_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ gpio = <&tlmm 46 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vph_pwr>;
+ };
+
/* Dummy regulator until PMI632 has LCDB VSP/VSN support */
lcdb_dummy: regulator-lcdb-dummy {
compatible = "regulator-fixed";
};
};
+&cci {
+ status = "okay";
+};
+
+&cci_i2c0 {
+ /* Sony IMX363 (rear) @ 0x10 */
+
+ eeprom@50 {
+ compatible = "belling,bl24s64", "atmel,24c64";
+ reg = <0x50>;
+ vcc-supply = <&vreg_cam_io_1p8>;
+ read-only;
+ };
+
+ /* ON Semi LC898217 VCM @ 0x72 */
+};
+
+&cci_i2c1 {
+ /* Samsung S5K4H7YX (front) @ 0x10 */
+};
+
&gpu {
status = "okay";
};
#include "sdm660.dtsi"
-/*
- * According to the downstream DTS,
- * 636 is basically a 660 except for
- * different CPU frequencies, Adreno
- * 509 instead of 512 and lack of
- * turing IP. These differences will
- * be addressed when the aforementioned
- * peripherals will be enabled upstream.
- */
+/delete-node/ &remoteproc_cdsp;
+/delete-node/ &cdsp_smmu;
+/delete-node/ &cdsp_region;
+
+/ {
+ /delete-node/ smp2p-cdsp;
+
+ reserved-memory {
+ buffer_mem: tzbuffer@94a00000 {
+ reg = <0x0 0x94a00000 0x00 0x100000>;
+ no-map;
+ };
+ };
+};
&adreno_gpu {
compatible = "qcom,adreno-509.0", "qcom,adreno";
#include "sdm630.dtsi"
+/delete-node/ &buffer_mem;
+
+/ {
+ smp2p-cdsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <94>, <432>;
+ interrupts = <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apcs_glb 30>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ cdsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ cdsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ reserved-memory {
+ cdsp_region: cdsp@94a00000 {
+ reg = <0x0 0x94a00000 0x00 0x600000>;
+ no-map;
+ };
+ };
+};
+
&adreno_gpu {
compatible = "qcom,adreno-512.0", "qcom,adreno";
operating-points-v2 = <&gpu_sdm660_opp_table>;
/* DSI1 shares the OPP table with DSI0 */
operating-points-v2 = <&dsi_opp_table>;
- power-domains = <&rpmpd SDM660_VDDCX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
interrupt-parent = <&mdss>;
interrupts = <5>;
<0>;
};
+&soc {
+ cdsp_smmu: iommu@5180000 {
+ compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
+ reg = <0x5180000 0x40000>;
+ #iommu-cells = <1>;
+
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_HLOS1_VOTE_TURING_ADSP_SMMU_CLK>;
+ clock-names = "bus";
+
+ power-domains = <&gcc HLOS1_VOTE_TURING_ADSP_GDSC>;
+
+ };
+
+ remoteproc_cdsp: remoteproc@1a300000 {
+ compatible = "qcom,sdm660-cdsp-pas";
+ reg = <0x1a300000 0x00100>;
+ interrupts-extended = <&intc GIC_SPI 518 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "xo";
+
+ memory-region = <&cdsp_region>;
+ power-domains = <&rpmpd SDM660_VDDCX>;
+ power-domain-names = "cx";
+
+ qcom,smem-states = <&cdsp_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ glink-edge {
+ interrupts = <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>;
+
+ label = "cdsp";
+ mboxes = <&apcs_glb 29>;
+ qcom,remote-pid = <5>;
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "cdsp";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&cdsp_smmu 3>;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+ iommus = <&cdsp_smmu 4>;
+ };
+
+ compute-cb@7 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <7>;
+ iommus = <&cdsp_smmu 5>;
+ };
+
+ compute-cb@8 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <8>;
+ iommus = <&cdsp_smmu 6>;
+ };
+
+ compute-cb@9 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <9>;
+ iommus = <&cdsp_smmu 7>;
+ };
+
+ compute-cb@10 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <10>;
+ iommus = <&cdsp_smmu 8>;
+ };
+
+ compute-cb@11 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <11>;
+ iommus = <&cdsp_smmu 9>;
+ };
+
+ compute-cb@12 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <12>;
+ iommus = <&cdsp_smmu 10>;
+ };
+
+ compute-cb@13 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <13>;
+ iommus = <&cdsp_smmu 11>;
+ };
+ };
+ };
+ };
+};
+
&tlmm {
compatible = "qcom,sdm660-pinctrl";
};
#address-cells = <1>;
#size-cells = <1>;
- gpu_speed_bin: gpu_speed_bin@1a2 {
+ gpu_speed_bin: gpu-speed-bin@1a2 {
reg = <0x1a2 0x2>;
bits = <5 8>;
};
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
+ vreg_l23a_3p3: ldo23 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
vreg_l24a_3p075: ldo24 {
regulator-min-microvolt = <3088000>;
regulator-max-microvolt = <3088000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi0_default>;
- cs-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
can@0 {
compatible = "microchip,mcp2517fd";
vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
+ vdd-3.3-ch1-supply = <&vreg_l23a_3p3>;
qcom,snoc-host-cap-8bit-quirk;
qcom,calibration-variant = "Thundercomm_DB845C";
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+
+/dts-v1/;
+
+#include "sdm845-google-common.dtsi"
+
+/ {
+ model = "Google Pixel 3";
+ compatible = "google,blueline", "qcom,sdm845";
+};
+
+&battery {
+ charge-full-design-microamp-hours = <2970000>;
+ voltage-min-design-microvolt = <3600000>;
+ voltage-max-design-microvolt = <4400000>;
+};
+
+&framebuffer0 {
+ width = <1080>;
+ height = <2160>;
+ stride = <(1080 * 4)>;
+};
+
+&i2c2 {
+ clock-frequency = <1000000>;
+
+ status = "okay";
+
+ /* ST,FTS @ 49 */
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vdda_mipi_dsi0_1p2>;
+
+ status = "okay";
+
+ panel@0 {
+ compatible = "lg,sw43408-lh546wf1-ed01", "lg,sw43408";
+ reg = <0>;
+
+ vddi-supply = <&vreg_l14a_1p8>;
+ vpnl-supply = <&vreg_l28a_3p0>;
+
+ reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&panel_default>;
+ pinctrl-names = "default";
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi0_out {
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&panel_in>;
+ qcom,te-source = "mdp_vsync_e";
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vdda_mipi_dsi0_pll>;
+
+ status = "okay";
+};
+
+&tlmm {
+ panel_default: panel-default-state {
+ reset-pins {
+ pins = "gpio6";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ te-pins {
+ pins = "gpio12";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+};
+
+&wifi {
+ qcom,calibration-variant = "Google_blueline";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+
+/dts-v1/;
+
+#include <dt-bindings/arm/qcom,ids.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "sdm845.dtsi"
+#include "pm8998.dtsi"
+#include "pmi8998.dtsi"
+
+/delete-node/ &mpss_region;
+/delete-node/ &venus_mem;
+/delete-node/ &cdsp_mem;
+/delete-node/ &mba_region;
+/delete-node/ &slpi_mem;
+/delete-node/ &spss_mem;
+/delete-node/ &rmtfs_mem;
+
+/ {
+ chassis-type = "handset";
+ qcom,board-id = <0x00021505 0>;
+ qcom,msm-id = <QCOM_ID_SDM845 0x20001>;
+
+ aliases {
+ serial0 = &uart9;
+ serial1 = &uart6;
+ };
+
+ battery: battery {
+ compatible = "simple-battery";
+ };
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ stdout-path = "serial0:115200n8";
+
+ /* Use display framebuffer as setup by bootloader */
+ framebuffer0: framebuffer-0 {
+ compatible = "simple-framebuffer";
+ memory-region = <&cont_splash_mem>;
+
+ format = "a8r8g8b8";
+ };
+ };
+
+ reserved-memory {
+ cont_splash_mem: splash@9d400000 {
+ reg = <0 0x9d400000 0 0x02400000>;
+ no-map;
+ };
+
+ mpss_region: memory@8e000000 {
+ reg = <0 0x8e000000 0 0x9800000>;
+ no-map;
+ };
+
+ venus_mem: venus@97800000 {
+ reg = <0 0x97800000 0 0x500000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp-mem@97D00000 {
+ reg = <0 0x97D00000 0 0x800000>;
+ no-map;
+ };
+
+ mba_region: mba@98500000 {
+ reg = <0 0x98500000 0 0x200000>;
+ no-map;
+ };
+
+ slpi_mem: slpi@98700000 {
+ reg = <0 0x98700000 0 0x1400000>;
+ no-map;
+ };
+
+ spss_mem: spss@99B00000 {
+ reg = <0 0x99B00000 0 0x100000>;
+ no-map;
+ };
+
+ rmtfs_mem: rmtfs-region@f2700000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0 0xf2700000 0 0x202000>;
+ qcom,use-guard-pages;
+ no-map;
+
+ qcom,client-id = <1>;
+ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ label = "Volume keys";
+ autorepeat;
+
+ pinctrl-0 = <&volume_up_gpio>;
+ pinctrl-names = "default";
+
+ key-vol-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ };
+ };
+
+ vph_pwr: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+ vreg_s4a_1p8: regulator-vreg-s4a-1p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s4a_1p8";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ vin-supply = <&vph_pwr>;
+ };
+};
+
+&adsp_pas {
+ firmware-name = "qcom/sdm845/Google/blueline/adsp.mbn";
+
+ status = "okay";
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8998-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+ vdd-s11-supply = <&vph_pwr>;
+ vdd-s12-supply = <&vph_pwr>;
+ vdd-s13-supply = <&vph_pwr>;
+ vdd-l1-l27-supply = <&vreg_s7a_1p025>;
+ vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
+ vdd-l3-l11-supply = <&vreg_s7a_1p025>;
+ vdd-l4-l5-supply = <&vreg_s7a_1p025>;
+ vdd-l6-supply = <&vph_pwr>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
+ vdd-l9-supply = <&vreg_bob>;
+ vdd-l10-l23-l25-supply = <&vreg_bob>;
+ vdd-l13-l19-l21-supply = <&vreg_bob>;
+ vdd-l16-l28-supply = <&vreg_bob>;
+ vdd-l18-l22-supply = <&vreg_bob>;
+ vdd-l20-l24-supply = <&vreg_bob>;
+ vdd-l26-supply = <&vreg_s3a_1p35>;
+ vin-lvs-1-2-supply = <&vreg_s4a_1p8>;
+
+ vreg_s3a_1p35: smps3 {
+ regulator-min-microvolt = <1352000>;
+ regulator-max-microvolt = <1352000>;
+ };
+
+ vreg_s5a_2p04: smps5 {
+ regulator-min-microvolt = <1904000>;
+ regulator-max-microvolt = <2040000>;
+ };
+
+ vreg_s7a_1p025: smps7 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1028000>;
+ };
+
+ vdda_mipi_dsi0_pll:
+ vreg_l1a_0p875: ldo1 {
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-boot-on;
+ };
+
+ vreg_l5a_0p8: ldo5 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12a_1p8: ldo12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7a_1p8: ldo7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13a_2p95: ldo13 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14a_1p8: ldo14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-boot-on;
+ /*
+ * We can't properly bring the panel back if it gets turned off
+ * so keep it's regulators always on for now.
+ */
+ regulator-always-on;
+ };
+
+ vreg_l17a_1p3: ldo17 {
+ regulator-min-microvolt = <1304000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l19a_3p3: ldo19 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ /*
+ * The touchscreen needs this to be 3.3v, which is apparently
+ * quite close to the hardware limit for this LDO (3.312v)
+ * It must be kept in high power mode to prevent TS brownouts
+ */
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l20a_2p95: ldo20 {
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2968000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l21a_2p95: ldo21 {
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2968000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l24a_3p075: ldo24 {
+ regulator-min-microvolt = <3088000>;
+ regulator-max-microvolt = <3088000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l25a_3p3: ldo25 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdda_mipi_dsi0_1p2:
+ vreg_l26a_1p2: ldo26 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-boot-on;
+ };
+
+ vreg_l28a_3p0: ldo28 {
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ regulator-boot-on;
+ /*
+ * We can't properly bring the panel back if it gets turned off
+ * so keep it's regulators always on for now.
+ */
+ regulator-always-on;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pmi8998-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-bob-supply = <&vph_pwr>;
+
+ vreg_bob: bob {
+ regulator-min-microvolt = <3312000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-bypass;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8005-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+
+ vreg_s3c_0p6: smps3 {
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <600000>;
+ };
+ };
+};
+
+&cci {
+ status = "okay";
+};
+
+&cci_i2c1 {
+ /* actuator @0c */
+
+ /* front camera, imx355 @1a */
+
+ /* eeprom @50, at24 driver says 8K */
+};
+
+&cdsp_pas {
+ firmware-name = "qcom/sdm845/Google/blueline/cdsp.mbn";
+
+ status = "okay";
+};
+
+&gcc {
+ protected-clocks = <GCC_QSPI_CORE_CLK>,
+ <GCC_QSPI_CORE_CLK_SRC>,
+ <GCC_QSPI_CNOC_PERIPH_AHB_CLK>;
+};
+
+&gpi_dma0 {
+ status = "okay";
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/sdm845/Google/blueline/a630_zap.mbn";
+};
+
+&i2c12 {
+ /* Bottom spkr (right) CS35L36 @ 40 */
+
+ /* Top spkr (left) CS35L36 @ 41 */
+};
+
+&ipa {
+ firmware-name = "qcom/sdm845/Google/blueline/ipa_fws.mbn";
+ memory-region = <&ipa_fw_mem>;
+
+ status = "okay";
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mss_pil {
+ firmware-name = "qcom/sdm845/Google/blueline/mba.mbn",
+ "qcom/sdm845/Google/blueline/modem.mbn";
+
+ status = "okay";
+};
+
+&pm8998_gpios {
+ volume_up_gpio: vol-up-active-state {
+ pins = "gpio6";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ qcom,drive-strength = <0>;
+ };
+};
+
+&pm8998_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&pmi8998_charger {
+ monitored-battery = <&battery>;
+
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&qup_uart9_rx {
+ drive-strength = <2>;
+ bias-pull-up;
+};
+
+&qup_uart9_tx {
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&tlmm {
+ gpio-reserved-ranges = < 0 4>, /* SPI (Intel MNH Pixel Visual Core) */
+ <81 4>; /* SPI (most likely Fingerprint Cards FPC1075) */
+
+ touchscreen_reset: ts-reset-state {
+ pins = "gpio99";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ touchscreen_pins: ts-pins-gpio-state {
+ pins = "gpio125";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ touchscreen_i2c_pins: qup-i2c2-gpio-state {
+ pins = "gpio27", "gpio28";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&uart6 {
+ pinctrl-0 = <&qup_uart6_4pin>;
+
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,wcn3990-bt";
+
+ vddio-supply = <&vreg_s4a_1p8>;
+ vddxo-supply = <&vreg_l7a_1p8>;
+ vddrf-supply = <&vreg_l17a_1p3>;
+ vddch0-supply = <&vreg_l25a_3p3>;
+ max-speed = <3200000>;
+ };
+};
+
+&uart9 {
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l20a_2p95>;
+ vcc-max-microamp = <800000>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1a_0p875>;
+ vdda-pll-supply = <&vreg_l26a_1p2>;
+
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l1a_0p875>;
+ vdda-pll-supply = <&vreg_l12a_1p8>;
+ vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
+
+ qcom,imp-res-offset-value = <8>;
+ qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
+ qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
+ qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
+
+ status = "okay";
+};
+
+&usb_1_qmpphy {
+ vdda-phy-supply = <&vreg_l26a_1p2>;
+ vdda-pll-supply = <&vreg_l1a_0p875>;
+
+ status = "okay";
+};
+
+&venus {
+ firmware-name = "qcom/sdm845/Google/blueline/venus.mbn";
+
+ status = "okay";
+};
+
+&wifi {
+ vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
+ vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
+ vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
+ vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
+
+ qcom,snoc-host-cap-8bit-quirk;
+
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+
+/dts-v1/;
+
+#include "sdm845-google-common.dtsi"
+
+/ {
+ model = "Google Pixel 3 XL";
+ compatible = "google,crosshatch", "qcom,sdm845";
+};
+
+&battery {
+ charge-full-design-microamp-hours = <3480000>;
+ voltage-min-design-microvolt = <3600000>;
+ voltage-max-design-microvolt = <4400000>;
+};
+
+&dispcc {
+ /* Disable for now so simple-framebuffer continues working */
+ status = "disabled";
+};
+
+&framebuffer0 {
+ width = <1440>;
+ height = <2960>;
+ stride = <(1440 * 4)>;
+};
+
+&mdss {
+ /* Disable for now so simple-framebuffer continues working */
+ status = "disabled";
+};
+
+&wifi {
+ qcom,calibration-variant = "Google_crosshatch";
+};
};
chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
stdout-path = "serial0:115200n8";
+
+ framebuffer: framebuffer@9d400000 {
+ compatible = "simple-framebuffer";
+ memory-region = <&cont_splash_mem>;
+
+ format = "a8r8g8b8";
+ stride = <(1080 * 4)>;
+ width = <1080>;
+ };
};
gpio-hall-sensor {
};
reserved-memory {
+ cont_splash_mem: splash@9d400000 {
+ reg = <0 0x9d400000 0 0x02400000>;
+ no-map;
+ };
+
/*
* The rmtfs memory region in downstream is 'dynamically allocated'
* but given the same address every time. Hard code it as this address is
gpio = <&tlmm 88 0>;
enable-active-high;
- regulator-boot-on;
};
panel_vci_3v3: panel-vci-3v3-regulator {
};
&adsp_pas {
+ firmware-name = "qcom/sdm845/OnePlus/enchilada/adsp.mbn";
+
status = "okay";
- firmware-name = "qcom/sdm845/oneplus6/adsp.mbn";
};
&apps_rsc {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-always-on;
+ regulator-boot-on;
};
vreg_l17a_1p3: ldo17 {
};
&cdsp_pas {
+ firmware-name = "qcom/sdm845/OnePlus/enchilada/cdsp.mbn";
+
status = "okay";
- firmware-name = "qcom/sdm845/oneplus6/cdsp.mbn";
};
&gcc {
};
&gpu_zap_shader {
- firmware-name = "qcom/sdm845/oneplus6/a630_zap.mbn";
+ firmware-name = "qcom/sdm845/OnePlus/enchilada/a630_zap.mbn";
};
&i2c10 {
&ipa {
qcom,gsi-loader = "self";
memory-region = <&ipa_fw_mem>;
- firmware-name = "qcom/sdm845/oneplus6/ipa_fws.mbn";
+ firmware-name = "qcom/sdm845/OnePlus/enchilada/ipa_fws.mbn";
+
status = "okay";
};
/* Modem/wifi */
&mss_pil {
+ firmware-name = "qcom/sdm845/OnePlus/enchilada/mba.mbn",
+ "qcom/sdm845/OnePlus/enchilada/modem.mbn";
+
status = "okay";
- firmware-name = "qcom/sdm845/oneplus6/mba.mbn", "qcom/sdm845/oneplus6/modem.mbn";
};
&pm8998_gpios {
};
&slpi_pas {
- firmware-name = "qcom/sdm845/oneplus6/slpi.mbn";
+ firmware-name = "qcom/sdm845/OnePlus/enchilada/slpi.mbn";
+
status = "okay";
};
* This path is relative to the qca/
* subdir under lib/firmware.
*/
- firmware-name = "oneplus6/crnv21.bin";
+ firmware-name = "OnePlus/enchilada/crnv21.bin";
vddio-supply = <&vreg_s4a_1p8>;
vddxo-supply = <&vreg_l7a_1p8>;
};
&venus {
+ firmware-name = "qcom/sdm845/OnePlus/enchilada/venus.mbn";
+
status = "okay";
- firmware-name = "qcom/sdm845/oneplus6/venus.mbn";
};
&wcd9340 {
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
vdd-3.3-ch1-supply = <&vreg_l23a_3p3>;
+ qcom,calibration-variant = "oneplus_sdm845";
qcom,snoc-host-cap-8bit-quirk;
};
};
};
+&bq27441_fg {
+ monitored-battery = <&battery>;
+};
+
&display_panel {
compatible = "samsung,sofef00-ams628nw01", "samsung,sofef00";
status = "okay";
};
-&bq27441_fg {
- monitored-battery = <&battery>;
+&framebuffer {
+ height = <2280>;
};
&i2c4 {
+ clock-frequency = <100000>;
+
status = "okay";
max98927_codec: max98927@3a {
compatible = "samsung,s6e3fc2x01-ams641rw", "samsung,s6e3fc2x01";
};
+&framebuffer {
+ height = <2340>;
+};
+
&i2c4 {
/* nxp,tfa9894 @ 0x34 */
};
};
&gpu_zap_shader {
- firmware-name = "qcom/sdm845/starqltechn/a630_zap.mbn";
+ firmware-name = "qcom/sdm845/Samsung/starqltechn/a630_zap.mbn";
};
&mdss {
};
&adsp_pas {
- firmware-name = "qcom/sdm845/starqltechn/adsp.mbn";
+ firmware-name = "qcom/sdm845/Samsung/starqltechn/adsp.mbn";
+
status = "okay";
};
};
&mss_pil {
- firmware-name = "qcom/sdm845/starqltechn/mba.mbn",
- "qcom/sdm845/starqltechn/modem.mbn";
+ firmware-name = "qcom/sdm845/Samsung/starqltechn/mba.mbn",
+ "qcom/sdm845/Samsung/starqltechn/modem.mbn";
+
status = "okay";
};
&ipa {
qcom,gsi-loader = "self";
memory-region = <&ipa_fw_mem>;
- firmware-name = "qcom/sdm845/starqltechn/ipa_fws.mbn";
+ firmware-name = "qcom/sdm845/Samsung/starqltechn/ipa_fws.mbn";
+
status = "okay";
};
&slpi_pas {
- firmware-name = "qcom/sdm845/starqltechn/slpi.mbn";
+ firmware-name = "qcom/sdm845/Samsung/starqltechn/slpi.mbn";
cx-supply = <&slpi_regulator>;
status = "okay";
};
&adsp_pas {
+ firmware-name = "qcom/sdm845/SHIFT/axolotl/adsp.mbn";
+
status = "okay";
- firmware-name = "qcom/sdm845/axolotl/adsp.mbn";
};
&apps_rsc {
};
&cdsp_pas {
+ firmware-name = "qcom/sdm845/SHIFT/axolotl/cdsp.mbn";
+
status = "okay";
- firmware-name = "qcom/sdm845/axolotl/cdsp.mbn";
};
&gcc {
};
&gpu_zap_shader {
- firmware-name = "qcom/sdm845/axolotl/a630_zap.mbn";
+ firmware-name = "qcom/sdm845/SHIFT/axolotl/a630_zap.mbn";
};
&i2c5 {
&ipa {
qcom,gsi-loader = "self";
memory-region = <&ipa_fw_mem>;
- firmware-name = "qcom/sdm845/axolotl/ipa_fws.mbn";
+ firmware-name = "qcom/sdm845/SHIFT/axolotl/ipa_fws.mbn";
+
status = "okay";
};
};
&mss_pil {
+ firmware-name = "qcom/sdm845/SHIFT/axolotl/mba.mbn", "qcom/sdm845/SHIFT/axolotl/modem.mbn";
+
status = "okay";
- firmware-name = "qcom/sdm845/axolotl/mba.mbn", "qcom/sdm845/axolotl/modem.mbn";
};
&pm8998_gpios {
};
&slpi_pas {
- firmware-name = "qcom/sdm845/axolotl/slpi.mbn";
+ firmware-name = "qcom/sdm845/SHIFT/axolotl/slpi.mbn";
+
status = "okay";
};
* This path is relative to the qca/
* subdir under lib/firmware.
*/
- firmware-name = "axolotl/crnv21.bin";
+ firmware-name = "SHIFT/axolotl/crnv21.bin";
vddio-supply = <&vreg_s4a_1p8>;
vddxo-supply = <&vreg_l7a_1p8>;
};
&venus {
+ firmware-name = "qcom/sdm845/SHIFT/axolotl/venus.mbn";
+
status = "okay";
- firmware-name = "qcom/sdm845/axolotl/venus.mbn";
};
&wifi {
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
vdd-3.3-ch1-supply = <&vreg_l23a_3p3>;
+ qcom,calibration-variant = "shift_axolotl";
qcom,snoc-host-cap-8bit-quirk;
};
&adsp_pas {
status = "okay";
- firmware-name = "qcom/sdm845/beryllium/adsp.mbn";
+ firmware-name = "qcom/sdm845/Xiaomi/beryllium/adsp.mbn";
};
&apps_rsc {
};
};
+&cci_i2c0 {
+ status = "okay";
+
+ /* IMX363 @ 10 */
+};
+
&cdsp_pas {
status = "okay";
- firmware-name = "qcom/sdm845/beryllium/cdsp.mbn";
+ firmware-name = "qcom/sdm845/Xiaomi/beryllium/cdsp.mbn";
};
&gcc {
};
&gpu_zap_shader {
- firmware-name = "qcom/sdm845/beryllium/a630_zap.mbn";
+ firmware-name = "qcom/sdm845/Xiaomi/beryllium/a630_zap.mbn";
};
&ibb {
qcom,discharge-resistor-kohms = <300>;
};
+&ipa {
+ qcom,gsi-loader = "self";
+ memory-region = <&ipa_fw_mem>;
+ firmware-name = "qcom/sdm845/beryllium/ipa_fws.mbn";
+
+ status = "okay";
+};
+
+&i2c5 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ /* TAS2559 @ 4C */
+};
+
&lab {
regulator-min-microvolt = <4600000>;
regulator-max-microvolt = <6000000>;
&mss_pil {
status = "okay";
- firmware-name = "qcom/sdm845/beryllium/mba.mbn", "qcom/sdm845/beryllium/modem.mbn";
-};
-
-&ipa {
- qcom,gsi-loader = "self";
- memory-region = <&ipa_fw_mem>;
- firmware-name = "qcom/sdm845/beryllium/ipa_fws.mbn";
- status = "okay";
+ firmware-name = "qcom/sdm845/Xiaomi/beryllium/mba.mbn",
+ "qcom/sdm845/Xiaomi/beryllium/modem.mbn";
};
&pm8998_gpios {
cd-gpios = <&tlmm 126 GPIO_ACTIVE_HIGH>;
};
+&slpi_pas {
+ firmware-name = "qcom/sdm845/Xiaomi/beryllium/slpi.mbn";
+
+ status = "okay";
+};
+
&sound {
compatible = "qcom,db845c-sndcard", "qcom,sdm845-sndcard";
pinctrl-0 = <&quat_mi2s_active
&venus {
status = "okay";
- firmware-name = "qcom/sdm845/beryllium/venus.mbn";
+ firmware-name = "qcom/sdm845/Xiaomi/beryllium/venus.mbn";
};
&wcd9340 {
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
vdd-3.3-ch1-supply = <&vreg_l23a_3p3>;
+
+ qcom,calibration-variant = "xiaomi_beryllium";
};
+
};
&cdsp_pas {
- firmware-name = "qcom/sdm845/polaris/cdsp.mbn";
+ firmware-name = "qcom/sdm845/Xiaomi/polaris/cdsp.mbn";
+
status = "okay";
};
};
&gpu_zap_shader {
- firmware-name = "qcom/sdm845/polaris/a630_zap.mbn";
+ firmware-name = "qcom/sdm845/Xiaomi/polaris/a630_zap.mbn";
};
&ibb {
&ipa {
qcom,gsi-loader = "self";
memory-region = <&ipa_fw_mem>;
- firmware-name = "qcom/sdm845/polaris/ipa_fws.mbn";
+ firmware-name = "qcom/sdm845/Xiaomi/polaris/ipa_fws.mbn";
+
status = "okay";
};
};
&mss_pil {
- firmware-name = "qcom/sdm845/polaris/mba.mbn", "qcom/sdm845/polaris/modem.mbn";
+ firmware-name = "qcom/sdm845/Xiaomi/polaris/mba.mbn",
+ "qcom/sdm845/Xiaomi/polaris/modem.mbn";
+
status = "okay";
};
compatible = "qcom,wcn3990-bt";
/* This path is relative to the qca/ subdir under lib/firmware. */
- firmware-name = "polaris/crnv21.bin";
+ firmware-name = "Xiaomi/polaris/crnv21.bin";
vddio-supply = <&vreg_s4a_1p8>;
vddxo-supply = <&vreg_l7a_1p8>;
};
&venus {
- firmware-name = "qcom/sdm845/polaris/venus.mbn";
+ firmware-name = "qcom/sdm845/Xiaomi/polaris/venus.mbn";
+
status = "okay";
};
/delete-node/ &ipa_fw_mem;
/delete-node/ &ipa_gsi_mem;
/delete-node/ &gpu_mem;
-/delete-node/ &adsp_mem;
/delete-node/ &wlan_msa_mem;
-/delete-node/ &slpi_mem;
/ {
model = "Huawei MateBook E 2019";
no-map;
};
- adsp_mem: adsp@8c500000 {
- reg = <0 0x8c500000 0 0x1a00000>;
- no-map;
- };
-
ipa_fw_mem: ipa-fw@8df00000 {
- reg = <0 0x8df00000 0 0x100000>;
+ reg = <0 0x8df00000 0 0x5a000>;
no-map;
};
- slpi_mem: slpi@96700000 {
- reg = <0 0x96700000 0 0x1200000>;
- };
-
- gpu_mem: gpu@97900000 {
- reg = <0 0x97900000 0 0x5000>;
+ gpu_mem: gpu@8df5a000 {
+ reg = <0 0x8df5a000 0 0x5000>;
no-map;
};
<&apps_smmu 0x94 0x11>,
<&apps_smmu 0x96 0x11>,
<&apps_smmu 0x98 0x1>,
- <&apps_smmu 0x9F 0>;
+ <&apps_smmu 0x9f 0>;
};
crypto: crypto@1b3a000 {
<&apps_smmu 0x94 0x11>,
<&apps_smmu 0x96 0x11>,
<&apps_smmu 0x98 0x1>,
- <&apps_smmu 0x9F 0>;
+ <&apps_smmu 0x9f 0>;
};
usb_qmpphy: phy@1615000 {
gpu: gpu@5900000 {
compatible = "qcom,adreno-610.0", "qcom,adreno";
- reg = <0x0 0x05900000 0x0 0x40000>;
- reg-names = "kgsl_3d0_reg_memory";
+ reg = <0x0 0x05900000 0x0 0x40000>,
+ <0x0 0x0599e000 0x0 0x1000>,
+ <0x0 0x05961000 0x0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem",
+ "cx_dbgc";
/* There's no (real) GMU, so we have to handle quite a bunch of clocks! */
clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
chassis-type = "handset";
/* required for bootloader to select correct board */
- qcom,msm-id = <QCOM_ID_SM6125>;
+ qcom,msm-id = <QCOM_ID_SM6125 0x10000>;
qcom,board-id = <22 0>;
chosen {
clock-names = "iface", "core", "xo";
iommus = <&apps_smmu 0x160 0x0>;
- power-domains = <&rpmpd SM6125_VDDCX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
qcom,dll-config = <0x000f642c>;
qcom,ddr-config = <0x80040873>;
pinctrl-1 = <&sdc2_off_state>;
pinctrl-names = "default", "sleep";
- power-domains = <&rpmpd SM6125_VDDCX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040873>;
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
- power-domains = <&rpmpd SM6125_VDDCX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
ports {
#address-cells = <1>;
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
operating-points-v2 = <&dsi_opp_table>;
- power-domains = <&rpmpd SM6125_VDDCX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
phys = <&mdss_dsi0_phy>;
phy-names = "dsi";
"ref";
required-opps = <&rpmpd_opp_nom>;
- power-domains = <&rpmpd SM6125_VDDMX>;
+ power-domains = <&rpmpd RPMPD_VDDMX>;
status = "disabled";
};
"gcc_disp_gpll0_div_clk_src";
required-opps = <&rpmpd_opp_ret>;
- power-domains = <&rpmpd SM6125_VDDCX>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
#clock-cells = <1>;
#power-domain-cells = <1>;
compatible = "sony,pdx213", "qcom,sm6350";
chassis-type = "handset";
qcom,msm-id = <434 0x10000>, <459 0x10000>;
- qcom,board-id = <0x1000B 0>;
+ qcom,board-id = <0x1000b 0>;
chosen {
#address-cells = <2>;
reg = <0x0 0x016e0000 0x0 0x15080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
+ clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
};
aggre2_noc: interconnect@1700000 {
reg = <0x0 0x01700000 0x0 0x1f880>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
+ clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&rpmhcc RPMH_IPA_CLK>;
compute_noc: interconnect-compute-noc {
compatible = "qcom,sm6350-compute-noc";
};
};
};
+
+ vreg_32m_cam_dvdd_1p05: regulator-32m-cam-dvdd-1p05 {
+ compatible = "regulator-fixed";
+ regulator-name = "32M_CAM_DVDD_1P05";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ gpio = <&pm6150l_gpios 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vreg_s8e>;
+ };
+
+ vreg_48m_ois_avdd0_1p8: regulator-48m-ois-avdd0-1p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "48M_OIS_AVDD0_1P8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&pm6150l_gpios 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vreg_bob>;
+ };
+
+ vreg_48m_uw_avdd0_1p8: regulator-48m-uw-avdd0-1p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "48M_UW_AVDD0_1P8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&pm6150l_gpios 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vreg_bob>;
+ };
+
+ vreg_ois_2p8: regulator-ois-2p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "OIS_2P8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&tlmm 72 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vreg_bob>;
+ };
};
&adsp {
};
&cci0_i2c0 {
- /* IMX582 @ 0x1a */
+ /* Main cam (Sony IMX582) @ 0x1a */
+ /* VCM driver (Onsemi LC898219XI) @ 0x28 */
+ /* OIS driver (CML CM401) @ 0x30 */
+
+ eeprom@50 {
+ compatible = "giantec,gt24p128e", "atmel,24c128";
+ reg = <0x50>;
+ vcc-supply = <&vreg_l6p>;
+ read-only;
+ };
};
&cci0_i2c1 {
- /* IMX582 @ 0x1a */
+ /* VCM driver (Dongwoon DW9800W) @ 0xc */
+ /* Ultra-wide cam (Sony IMX582) @ 0x1a */
+
+ eeprom@50 {
+ compatible = "giantec,gt24p64a", "atmel,24c64";
+ reg = <0x50>;
+ vcc-supply = <&vreg_l6p>;
+ read-only;
+ };
};
&cci1 {
};
&cci1_i2c0 {
- /* IMX576 @ 0x10 */
+ /* Front cam (Sony IMX576) @ 0x10 */
+
+ eeprom@50 {
+ compatible = "giantec,gt24p64a", "atmel,24c64";
+ reg = <0x50>;
+ vcc-supply = <&vreg_l6p>;
+ read-only;
+ };
};
&cdsp {
regulator-name = "vreg_l6p";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1800000>;
+ /* Pull-up for CCI I2C busses */
+ regulator-always-on;
};
vreg_l7p: ldo7 {
status = "okay";
};
+&gpu_zap_shader {
+ firmware-name = "qcom/sm8150/a640_zap.mbn";
+};
+
&i2c4 {
clock-frequency = <100000>;
status = "okay";
};
+&gpu_zap_shader {
+ firmware-name = "qcom/sm8150/a640_zap.mbn";
+};
+
&pon {
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
status = "disabled";
};
+ uart13: serial@c8c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00c8c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
i2c14: i2c@c90000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00c90000 0 0x4000>;
reg = <0x0 0x03100000 0x0 0x300000>,
<0x0 0x03500000 0x0 0x300000>,
<0x0 0x03900000 0x0 0x300000>,
- <0x0 0x03D00000 0x0 0x300000>;
+ <0x0 0x03d00000 0x0 0x300000>;
reg-names = "west", "east", "north", "south";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&tlmm 0 0 176>;
status = "okay";
};
+&gpu_zap_shader {
+ firmware-name = "qcom/sm8250/a650_zap.mbn";
+};
+
&pon {
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pinctrl-0 = <&cam3_default>;
pinctrl-names = "default";
afvdd-supply = <&vreg_l7n_2p96>;
- avdd-supply = <&vreg_l4m_2p8>;
- dovdd-supply = <&vreg_l5n_1p8>;
- dvdd-supply = <&vreg_l2m_1p056>;
+ vdda-supply = <&vreg_l4m_2p8>;
+ vddd-supply = <&vreg_l2m_1p056>;
+ vddio-supply = <&vreg_l5n_1p8>;
port {
cam_tele: endpoint {
link-frequencies = /bits/ 64 <602500000>;
- data-lanes = <0 1 2 3>;
remote-endpoint = <&csiphy3_ep>;
};
};
vdd3-supply = <&vreg_l5b_3p1>;
};
+&pm8550vs_c {
+ status = "okay";
+};
+
+&pm8550vs_d {
+ status = "okay";
+};
+
+&pm8550vs_e {
+ status = "okay";
+};
+
+&pm8550vs_g {
+ status = "okay";
+};
+
&pon_pwrkey {
status = "okay";
};
vdd3-supply = <&vreg_l5b_3p1>;
};
+&pm8550vs_c {
+ status = "okay";
+};
+
+&pm8550vs_d {
+ status = "okay";
+};
+
+&pm8550vs_e {
+ status = "okay";
+};
+
+&pm8550vs_g {
+ status = "okay";
+};
+
&qupv3_id_0 {
status = "okay";
};
pinctrl-0 = <&cam3_default>;
pinctrl-names = "default";
afvdd-supply = <&vreg_l7n_2p96>;
- avdd-supply = <&vreg_l4m_2p8>;
- dovdd-supply = <&vreg_l5n_1p8>;
- dvdd-supply = <&vreg_l2m_1p056>;
+ vdda-supply = <&vreg_l4m_2p8>;
+ vddd-supply = <&vreg_l2m_1p056>;
+ vddio-supply = <&vreg_l5n_1p8>;
port {
cam_tele: endpoint {
link-frequencies = /bits/ 64 <602500000>;
- data-lanes = <0 1 2 3>;
remote-endpoint = <&csiphy3_ep>;
};
};
vdd3-supply = <&vreg_l5b_3p1>;
};
+&pm8550vs_c {
+ status = "okay";
+};
+
+&pm8550vs_d {
+ status = "okay";
+};
+
+&pm8550vs_e {
+ status = "okay";
+};
+
+&pm8550vs_g {
+ status = "okay";
+};
+
&pon_pwrkey {
status = "okay";
};
};
};
+&pm8550vs_c {
+ status = "okay";
+};
+
+&pm8550vs_d {
+ status = "okay";
+};
+
+&pm8550vs_e {
+ status = "okay";
+};
+
+&pm8550vs_g {
+ status = "okay";
+};
+
&pon_pwrkey {
status = "okay";
};
};
};
+&pm8550vs_c {
+ status = "okay";
+};
+
+&pm8550vs_d {
+ status = "okay";
+};
+
+&pm8550vs_e {
+ status = "okay";
+};
+
+&pm8550vs_g {
+ status = "okay";
+};
+
&pm8550vs_g_gpios {
cam_pwr_a_cs: cam-pwr-a-cs-state {
pins = "gpio4";
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * SM8650-HDK Rear Camera Card overlay
+ *
+ * Copyright (c) 2025, Linaro Limited
+ */
+
+#include <dt-bindings/clock/qcom,sm8650-camcc.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/dts-v1/;
+/plugin/;
+
+&camss {
+ vdd-csiphy35-0p9-supply = <&vreg_l2i_0p88>;
+ vdd-csiphy35-1p2-supply = <&vreg_l3i_1p2>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@3 {
+ reg = <3>;
+
+ csiphy3_ep: endpoint {
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&cam_tele>;
+ };
+ };
+ };
+};
+
+&cci1 {
+ status = "okay";
+};
+
+&cci1_i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sensor@56 {
+ compatible = "samsung,s5kjn1";
+ reg = <0x56>;
+ clocks = <&camcc CAM_CC_MCLK3_CLK>;
+ assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>;
+ assigned-clock-rates = <24000000>;
+ reset-gpios = <&tlmm 109 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&cam3_default>;
+ pinctrl-names = "default";
+ afvdd-supply = <&vreg_l7m_2p96>;
+ vdda-supply = <&vreg_l4m_2p8>;
+ vddd-supply = <&vreg_l2m_1p056>;
+ vddio-supply = <&vreg_l3n_1p8>;
+
+ port {
+ cam_tele: endpoint {
+ link-frequencies = /bits/ 64 <700000000>;
+ remote-endpoint = <&csiphy3_ep>;
+ };
+ };
+ };
+};
+
+&pm8550_flash {
+ status = "okay";
+
+ led-0 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_YELLOW>;
+ led-sources = <1>, <4>;
+ led-max-microamp = <500000>;
+ flash-max-microamp = <2000000>;
+ flash-max-timeout-us = <1280000>;
+ function-enumerator = <0>;
+ };
+
+ led-1 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ led-sources = <2>, <3>;
+ led-max-microamp = <500000>;
+ flash-max-microamp = <2000000>;
+ flash-max-timeout-us = <1280000>;
+ function-enumerator = <1>;
+ };
+};
vdd3-supply = <&vreg_l5b_3p1>;
};
+&pm8550vs_c {
+ status = "okay";
+};
+
+&pm8550vs_d {
+ status = "okay";
+};
+
+&pm8550vs_e {
+ status = "okay";
+};
+
+&pm8550vs_g {
+ status = "okay";
+};
+
&pon_pwrkey {
status = "okay";
};
vdd3-supply = <&vreg_l5b_3p1>;
};
+&pm8550vs_c {
+ status = "okay";
+};
+
+&pm8550vs_d {
+ status = "okay";
+};
+
+&pm8550vs_e {
+ status = "okay";
+};
+
+&pm8550vs_g {
+ status = "okay";
+};
+
&qupv3_id_1 {
status = "okay";
};
};
};
+&camss {
+ vdd-csiphy35-0p9-supply = <&vreg_l2i_0p88>;
+ vdd-csiphy35-1p2-supply = <&vreg_l3i_1p2>;
+ status = "okay";
+
+ ports {
+ port@3 {
+ csiphy3_ep: endpoint {
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&cam_tele>;
+ };
+ };
+ };
+};
+
+&cci1 {
+ status = "okay";
+};
+
+&cci1_i2c0 {
+ sensor@56 {
+ compatible = "samsung,s5kjn1";
+ reg = <0x56>;
+ clocks = <&camcc CAM_CC_MCLK3_CLK>;
+ assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>;
+ assigned-clock-rates = <24000000>;
+ reset-gpios = <&tlmm 109 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&cam3_default>;
+ pinctrl-names = "default";
+ afvdd-supply = <&vreg_l7m_2p96>;
+ vdda-supply = <&vreg_l4m_2p8>;
+ vddd-supply = <&vreg_l2m_1p056>;
+ vddio-supply = <&vreg_l3n_1p8>;
+
+ port {
+ cam_tele: endpoint {
+ link-frequencies = /bits/ 64 <700000000>;
+ remote-endpoint = <&csiphy3_ep>;
+ };
+ };
+ };
+};
+
&gpi_dma1 {
status = "okay";
};
vdd3-supply = <&vreg_l5b_3p1>;
};
+&pm8550vs_c {
+ status = "okay";
+};
+
+&pm8550vs_d {
+ status = "okay";
+};
+
+&pm8550vs_e {
+ status = "okay";
+};
+
+&pm8550vs_g {
+ status = "okay";
+};
+
&qup_i2c3_data_clk {
/* Use internal I2C pull-up */
bias-pull-up = <2200>;
};
};
+ camss: isp@acb6000 {
+ compatible = "qcom,sm8650-camss";
+
+ reg = <0 0x0acb6000 0 0x1000>,
+ <0 0x0acb8000 0 0x1000>,
+ <0 0x0acba000 0 0x1000>,
+ <0 0x0acbc000 0 0x1000>,
+ <0 0x0accb000 0 0x1000>,
+ <0 0x0acd0000 0 0x1000>,
+ <0 0x0ace4000 0 0x2000>,
+ <0 0x0ace6000 0 0x2000>,
+ <0 0x0ace8000 0 0x2000>,
+ <0 0x0acea000 0 0x2000>,
+ <0 0x0acec000 0 0x2000>,
+ <0 0x0acee000 0 0x2000>,
+ <0 0x0ac62000 0 0xf000>,
+ <0 0x0ac71000 0 0xf000>,
+ <0 0x0ac80000 0 0xf000>,
+ <0 0x0accc000 0 0x2000>,
+ <0 0x0acd1000 0 0x2000>;
+ reg-names = "csid_wrapper",
+ "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "csiphy5",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_0_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_1_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_2_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY4_CLK>,
+ <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY5_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_2_CLK>,
+ <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "cpas_fast_ahb",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "cpas_vfe2",
+ "cpas_vfe_lite",
+ "csid",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy3",
+ "csiphy3_timer",
+ "csiphy4",
+ "csiphy4_timer",
+ "csiphy5",
+ "csiphy5_timer",
+ "csiphy_rx",
+ "gcc_axi_hf",
+ "qdss_debug_xo",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe2",
+ "vfe2_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid";
+
+ interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 376 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 448 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 89 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 602 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 604 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 688 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 606 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 377 IRQ_TYPE_EDGE_RISING 0>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "csiphy5",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC 0
+ &config_noc SLAVE_CAMERA_CFG 0>,
+ <&mmss_noc MASTER_CAMNOC_HF 0
+ &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "ahb",
+ "hf_mnoc";
+
+ iommus = <&apps_smmu 0x800 0x20>,
+ <&apps_smmu 0x18a0 0x40>,
+ <&apps_smmu 0x1860 0x00>;
+
+ power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
+ <&camcc CAM_CC_IFE_1_GDSC>,
+ <&camcc CAM_CC_IFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "ife0", "ife1", "ife2", "top";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ };
+
+ port@3 {
+ reg = <3>;
+ };
+
+ port@4 {
+ reg = <4>;
+ };
+
+ port@5 {
+ reg = <5>;
+ };
+ };
+ };
+
camcc: clock-controller@ade0000 {
compatible = "qcom,sm8650-camcc";
reg = <0 0x0ade0000 0 0x20000>;
wakeup-parent = <&pdc>;
+ cam0_default: cam0-default-state {
+ pins = "gpio100";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam0_sleep: cam0-sleep-state {
+ pins = "gpio100";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cam1_default: cam1-default-state {
+ pins = "gpio101";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam1_sleep: cam1-sleep-state {
+ pins = "gpio101";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cam2_default: cam2-default-state {
+ pins = "gpio102";
+ function = "cam_aon_mclk2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam2_sleep: cam2-sleep-state {
+ pins = "gpio102";
+ function = "cam_aon_mclk2";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cam3_default: cam3-default-state {
+ pins = "gpio103";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam3_sleep: cam3-sleep-state {
+ pins = "gpio103";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cam4_default: cam4-default-state {
+ pins = "gpio104";
+ function = "cam_aon_mclk4";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam4_sleep: cam4-sleep-state {
+ pins = "gpio104";
+ function = "cam_aon_mclk4";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cam5_default: cam5-default-state {
+ pins = "gpio105";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam5_sleep: cam5-sleep-state {
+ pins = "gpio105";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cam6_default: cam6-default-state {
+ pins = "gpio108";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam6_sleep: cam6-sleep-state {
+ pins = "gpio108";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cam7_default: cam7-default-state {
+ pins = "gpio106";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam7_sleep: cam7-sleep-state {
+ pins = "gpio106";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
cci0_0_default: cci0-0-default-state {
sda-pins {
pins = "gpio113";
};
};
+&iris {
+ status = "okay";
+};
+
&lpass_vamacro {
pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
pinctrl-names = "default";
};
&pmih0108_eusb2_repeater {
- status = "okay";
+ qcom,tune-usb2-preem = /bits/ 8 <0x3>;
+ qcom,tune-usb2-amplitude = /bits/ 8 <0xa>;
+ qcom,squelch-detector-bp = <(-2000)>;
vdd18-supply = <&vreg_l15b_1p8>;
vdd3-supply = <&vreg_l5b_3p1>;
+
+ status = "okay";
};
&qupv3_1 {
status = "fail";
};
+&sdhc_2 {
+ cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&vreg_l9b_2p9>;
+ vqmmc-supply = <&vreg_l8b_1p8>;
+
+ no-sdio;
+ no-mmc;
+
+ pinctrl-0 = <&sdc2_default &sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>;
+ pinctrl-names = "default", "sleep";
+
+ status = "okay";
+};
+
&swr0 {
status = "okay";
};
};
+ sdc2_card_det_n: sd-card-det-n-state {
+ pins = "gpio55";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
wcd_default: wcd-reset-n-active-state {
pins = "gpio101";
function = "gpio";
};
};
+&iris {
+ status = "okay";
+};
+
&pm8550_flash {
status = "okay";
status = "okay";
};
+&sdhc_2 {
+ cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&vreg_l9b_2p9>;
+ vqmmc-supply = <&vreg_l8b_1p8>;
+
+ no-sdio;
+ no-mmc;
+
+ pinctrl-0 = <&sdc2_default &sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>;
+ pinctrl-names = "default", "sleep";
+
+ status = "okay";
+};
+
&swr0 {
status = "okay";
/* reserved for secure world */
gpio-reserved-ranges = <36 4>, <74 1>;
+ sdc2_card_det_n: sd-card-det-n-state {
+ pins = "gpio55";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
spkr_0_sd_n_active: spkr-0-sd-n-active-state {
pins = "gpio76";
function = "gpio";
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm8750-gcc.h>
#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
+#include <dt-bindings/clock/qcom,sm8750-videocc.h>
#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&l2_0>;
- power-domains = <&cpu_pd0>;
- power-domain-names = "psci";
+ power-domains = <&cpu_pd0>, <&scmi_dvfs 0>;
+ power-domain-names = "psci", "perf";
l2_0: l2-cache {
compatible = "cache";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&l2_0>;
- power-domains = <&cpu_pd1>;
- power-domain-names = "psci";
+ power-domains = <&cpu_pd1>, <&scmi_dvfs 0>;
+ power-domain-names = "psci", "perf";
};
cpu2: cpu@200 {
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&l2_0>;
- power-domains = <&cpu_pd2>;
- power-domain-names = "psci";
+ power-domains = <&cpu_pd2>, <&scmi_dvfs 0>;
+ power-domain-names = "psci", "perf";
};
cpu3: cpu@300 {
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&l2_0>;
- power-domains = <&cpu_pd3>;
- power-domain-names = "psci";
+ power-domains = <&cpu_pd3>, <&scmi_dvfs 0>;
+ power-domain-names = "psci", "perf";
};
cpu4: cpu@400 {
reg = <0x0 0x400>;
enable-method = "psci";
next-level-cache = <&l2_0>;
- power-domains = <&cpu_pd4>;
- power-domain-names = "psci";
+ power-domains = <&cpu_pd4>, <&scmi_dvfs 0>;
+ power-domain-names = "psci", "perf";
};
cpu5: cpu@500 {
reg = <0x0 0x500>;
enable-method = "psci";
next-level-cache = <&l2_0>;
- power-domains = <&cpu_pd5>;
- power-domain-names = "psci";
+ power-domains = <&cpu_pd5>, <&scmi_dvfs 0>;
+ power-domain-names = "psci", "perf";
};
cpu6: cpu@10000 {
reg = <0x0 0x10000>;
enable-method = "psci";
next-level-cache = <&l2_1>;
- power-domains = <&cpu_pd6>;
- power-domain-names = "psci";
+ power-domains = <&cpu_pd6>, <&scmi_dvfs 1>;
+ power-domain-names = "psci", "perf";
l2_1: l2-cache {
compatible = "cache";
reg = <0x0 0x10100>;
enable-method = "psci";
next-level-cache = <&l2_1>;
- power-domains = <&cpu_pd7>;
- power-domain-names = "psci";
+ power-domains = <&cpu_pd7>, <&scmi_dvfs 1>;
+ power-domain-names = "psci", "perf";
};
cpu-map {
interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
};
+
+ scmi {
+ compatible = "arm,scmi";
+ mboxes = <&cpucp_mbox 0>, <&cpucp_mbox 2>;
+ mbox-names = "tx", "rx";
+ shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+ };
};
clk_virt: interconnect-0 {
reg = <0x0 0xff800000 0x0 0x800000>;
no-map;
};
+
+ adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0xc00000>;
+ reusable;
+ };
};
smp2p-adsp {
<&apps_smmu 0x481 0>;
qcom,ee = <0>;
+ qcom,num-ees = <4>;
+ num-channels = <20>;
qcom,controlled-remotely;
};
qcom,remote-pid = <2>;
label = "lpass";
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "adsp";
+ memory-region = <&adsp_rpc_remote_heap_mem>;
+ qcom,vmids = <QCOM_SCM_VMID_LPASS
+ QCOM_SCM_VMID_ADSP_HEAP>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu 0x1003 0x80>,
+ <&apps_smmu 0x1043 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+ iommus = <&apps_smmu 0x1004 0x80>,
+ <&apps_smmu 0x1044 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&apps_smmu 0x1005 0x80>,
+ <&apps_smmu 0x1045 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+ iommus = <&apps_smmu 0x1006 0x80>,
+ <&apps_smmu 0x1046 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@7 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <7>;
+ iommus = <&apps_smmu 0x1007 0x40>,
+ <&apps_smmu 0x1067 0x0>,
+ <&apps_smmu 0x1087 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@8 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <8>;
+ iommus = <&apps_smmu 0x1008 0x80>,
+ <&apps_smmu 0x1048 0x20>;
+ dma-coherent;
+ };
+ };
+
gpr {
compatible = "qcom,gpr";
qcom,glink-channels = "adsp_apps";
};
};
+ sdhc_2: mmc@8804000 {
+ compatible = "qcom,sm8750-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x08804000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq",
+ "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface",
+ "core",
+ "xo";
+
+ interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+
+ qcom,dll-config = <0x0007442c>;
+ qcom,ddr-config = <0x80040868>;
+
+ iommus = <&apps_smmu 0x540 0x0>;
+ dma-coherent;
+
+ bus-width = <4>;
+ max-sd-hs-hz = <37500000>;
+
+ resets = <&gcc GCC_SDCC2_BCR>;
+
+ status = "disabled";
+
+ sdhc2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
usb_hsphy: phy@88e3000 {
compatible = "qcom,sm8750-m31-eusb2-phy";
reg = <0x0 0x88e3000 0x0 0x29c>;
};
};
+ iris: video-codec@aa00000 {
+ compatible = "qcom,sm8750-iris";
+ reg = <0x0 0x0aa00000 0x0 0xf0000>;
+
+ clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+ <&videocc VIDEO_CC_MVS0C_CLK>,
+ <&videocc VIDEO_CC_MVS0_CLK>,
+ <&gcc GCC_VIDEO_AXI1_CLK>,
+ <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>,
+ <&videocc VIDEO_CC_MVS0_FREERUN_CLK>;
+ clock-names = "iface",
+ "core",
+ "vcodec0_core",
+ "iface1",
+ "core_freerun",
+ "vcodec0_core_freerun";
+
+ dma-coherent;
+ iommus = <&apps_smmu 0x1940 0>,
+ <&apps_smmu 0x1947 0>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "cpu-cfg",
+ "video-mem";
+
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ memory-region = <&video_mem>;
+
+ operating-points-v2 = <&iris_opp_table>;
+
+ power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
+ <&videocc VIDEO_CC_MVS0_GDSC>,
+ <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_MMCX>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "mxc",
+ "mmcx";
+
+ resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
+ <&gcc GCC_VIDEO_AXI1_CLK_ARES>,
+ <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>,
+ <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>;
+ reset-names = "bus0",
+ "bus1",
+ "core",
+ "vcodec0_core";
+
+ /*
+ * IRIS firmware is signed by vendors, only
+ * enable in boards where the proper signed firmware
+ * is available.
+ */
+ status = "disabled";
+
+ iris_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-240000000 {
+ opp-hz = /bits/ 64 <240000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>,
+ <&rpmhpd_opp_low_svs_d1>;
+ };
+
+ opp-338000000 {
+ opp-hz = /bits/ 64 <338000000>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-420000000 {
+ opp-hz = /bits/ 64 <420000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs>;
+ };
+
+ opp-444000000 {
+ opp-hz = /bits/ 64 <444000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-533333334 {
+ opp-hz = /bits/ 64 <533333334>;
+ required-opps = <&rpmhpd_opp_nom>,
+ <&rpmhpd_opp_nom>;
+ };
+
+ opp-570000000 {
+ opp-hz = /bits/ 64 <570000000>;
+ required-opps = <&rpmhpd_opp_nom_l1>,
+ <&rpmhpd_opp_nom_l1>;
+ };
+
+ opp-630000000 {
+ opp-hz = /bits/ 64 <630000000>;
+ required-opps = <&rpmhpd_opp_turbo>,
+ <&rpmhpd_opp_turbo>;
+ };
+ };
+ };
+
+ videocc: clock-controller@aaf0000 {
+ compatible = "qcom,sm8750-videocc";
+ reg = <0x0 0x0aaf0000 0x0 0x10000>;
+ clocks = <&bi_tcxo_div2>,
+ <&gcc GCC_VIDEO_AHB_CLK>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8750-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>;
#reset-cells = <1>;
};
- apps_smmu: iommu@15000000 {
- compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500";
- reg = <0x0 0x15000000 0x0 0x100000>;
-
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>;
+ stm@10002000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0x0 0x10002000 0x0 0x1000>,
+ <0x0 0x37280000 0x0 0x180000>;
+ reg-names = "stm-base",
+ "stm-stimulus-base";
- #iommu-cells = <2>;
- #global-interrupts = <1>;
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
- dma-coherent;
+ out-ports {
+ port {
+ stm_out: endpoint {
+ remote-endpoint = <&funnel_in0_in7>;
+ };
+ };
+ };
};
- intc: interrupt-controller@16000000 {
- compatible = "arm,gic-v3";
- reg = <0x0 0x16000000 0x0 0x10000>,
- <0x0 0x16080000 0x0 0x200000>;
+ tpda@10004000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x10004000 0x0 0x1000>;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
- #interrupt-cells = <3>;
- interrupt-controller;
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
- #redistributor-regions = <1>;
- redistributor-stride = <0x0 0x40000>;
+ port@1 {
+ reg = <1>;
- #address-cells = <2>;
- #size-cells = <2>;
+ tpda_qdss_in1: endpoint {
+ remote-endpoint = <&tpdm_spdm_out>;
+ };
+ };
+
+ };
+
+ out-ports {
+ port {
+ tpda_qdss_out: endpoint {
+ remote-endpoint = <&funnel_in0_in6>;
+ };
+ };
+ };
+ };
+
+ tpdm@1000f000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1000f000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_spdm_out: endpoint {
+ remote-endpoint = <&tpda_qdss_in1>;
+ };
+ };
+ };
+ };
+
+ funnel@10041000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10041000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ funnel_in0_in0: endpoint {
+ remote-endpoint = <&tn_ag_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+
+ funnel_in0_in6: endpoint {
+ remote-endpoint = <&tpda_qdss_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+
+ funnel_in0_in7: endpoint {
+ remote-endpoint = <&stm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_in0_out: endpoint {
+ remote-endpoint = <&funnel_aoss_in7>;
+ };
+ };
+ };
+ };
+
+ tpdm@10800000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10800000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_modem0_out: endpoint {
+ remote-endpoint = <&tpda_modem_in0>;
+ };
+ };
+ };
+ };
+
+ tpda@10803000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x10803000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpda_modem_in0: endpoint {
+ remote-endpoint = <&tpdm_modem0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpda_modem_in1: endpoint {
+ remote-endpoint = <&tpdm_modem1_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tpda_modem_out: endpoint {
+ remote-endpoint = <&funnel_modem_dl_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@10804000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10804000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ funnel_modem_dl_in0: endpoint {
+ remote-endpoint = <&tpda_modem_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_modem_dl_out: endpoint {
+ remote-endpoint = <&tn_ag_in13>;
+ };
+ };
+ };
+ };
+
+ cti@1080b000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x1080b000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ };
+
+ tpdm@1082c000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1082c000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_gcc_out: endpoint {
+ remote-endpoint = <&tn_ag_in17>;
+ };
+ };
+ };
+ };
+
+ tpdm@10841000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10841000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_prng_out: endpoint {
+ remote-endpoint = <&tn_ag_in18>;
+ };
+ };
+ };
+ };
+
+ tpdm@1084e000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1084e000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_mm_bcv_out: endpoint {
+ remote-endpoint = <&tpda_mm_in0>;
+ };
+ };
+ };
+ };
+
+ tpdm@1084f000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1084f000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_mm_lmh_out: endpoint {
+ remote-endpoint = <&tpda_mm_in1>;
+ };
+ };
+ };
+ };
+
+ tpdm@10850000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10850000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_mm_dpm_out: endpoint {
+ remote-endpoint = <&tpda_mm_in2>;
+ };
+ };
+ };
+ };
+
+ tpda@10851000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x10851000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpda_mm_in0: endpoint {
+ remote-endpoint = <&tpdm_mm_bcv_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpda_mm_in1: endpoint {
+ remote-endpoint = <&tpdm_mm_lmh_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ tpda_mm_in2: endpoint {
+ remote-endpoint = <&tpdm_mm_dpm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tpda_mm_out: endpoint {
+ remote-endpoint = <&tn_ag_in4>;
+ };
+ };
+ };
+ };
+
+ tpdm@10980000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10980000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_cdsp_out: endpoint {
+ remote-endpoint = <&tpda_cdsp_in0>;
+ };
+ };
+ };
+ };
+
+ tpda@10986000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x10986000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpda_cdsp_in0: endpoint {
+ remote-endpoint = <&tpdm_cdsp_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpda_cdsp_in1: endpoint {
+ remote-endpoint = <&tpdm_cdsp_llm_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ tpda_cdsp_in2: endpoint {
+ remote-endpoint = <&tpdm_cdsp_llm2_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tpda_cdsp_out: endpoint {
+ remote-endpoint = <&funnel_cdsp_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@10987000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10987000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ funnel_cdsp_in0: endpoint {
+ remote-endpoint = <&tpda_cdsp_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_cdsp_out: endpoint {
+ remote-endpoint = <&tn_ag_in16>;
+ };
+ };
+ };
+ };
+
+ cti@1098b000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x1098b000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ };
+
+ tpdm@109a3000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x109a3000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-msrs-num = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_pmu_out: endpoint {
+ remote-endpoint = <&tn_ag_in29>;
+ };
+ };
+ };
+ };
+
+ tpdm@109a4000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x109a4000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_ipcc_cmb_out: endpoint {
+ remote-endpoint = <&tn_ag_in28>;
+ };
+ };
+ };
+ };
+
+ tpdm@109a5000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x109a5000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_dl_mm_out: endpoint {
+ remote-endpoint = <&tn_ag_in25>;
+ };
+ };
+ };
+ };
+
+ tpdm@109a6000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x109a6000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_north_dsb_out: endpoint {
+ remote-endpoint = <&tn_ag_in26>;
+ };
+ };
+ };
+ };
+
+ tpdm@109a7000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x109a7000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_south_dsb_out: endpoint {
+ remote-endpoint = <&tn_ag_in27>;
+ };
+ };
+ };
+ };
+
+ tpdm@109a8000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x109a8000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_rdpm_cmb0_out: endpoint {
+ remote-endpoint = <&tn_ag_in30>;
+ };
+ };
+ };
+ };
+
+ tpdm@109a9000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x109a9000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_rdpm_cmb1_out: endpoint {
+ remote-endpoint = <&tn_ag_in31>;
+ };
+ };
+ };
+ };
+
+ tpdm@109aa000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x109aa000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_rdpm_cmb2_out: endpoint {
+ remote-endpoint = <&tn_ag_in32>;
+ };
+ };
+ };
+ };
+
+ tn@109ab000 {
+ compatible = "qcom,coresight-tnoc", "arm,primecell";
+ reg = <0x0 0x109ab000 0x0 0x4200>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@4 {
+ reg = <4>;
+
+ tn_ag_in4: endpoint {
+ remote-endpoint = <&tpda_mm_out>;
+ };
+ };
+
+ port@d {
+ reg = <0xd>;
+
+ tn_ag_in13: endpoint {
+ remote-endpoint = <&funnel_modem_dl_out>;
+ };
+ };
+
+ port@10 {
+ reg = <0x10>;
+
+ tn_ag_in16: endpoint {
+ remote-endpoint = <&funnel_cdsp_out>;
+ };
+ };
+
+ port@11 {
+ reg = <0x11>;
+
+ tn_ag_in17: endpoint {
+ remote-endpoint = <&tpdm_gcc_out>;
+ };
+ };
+
+ port@12 {
+ reg = <0x12>;
+
+ tn_ag_in18: endpoint {
+ remote-endpoint = <&tpdm_prng_out>;
+ };
+ };
+
+ port@13 {
+ reg = <0x13>;
+
+ tn_ag_in19: endpoint {
+ remote-endpoint = <&tpdm_qm_out>;
+ };
+ };
+
+ port@19 {
+ reg = <0x19>;
+
+ tn_ag_in25: endpoint {
+ remote-endpoint = <&tpdm_dl_mm_out>;
+ };
+ };
+
+ port@1a {
+ reg = <0x1a>;
+
+ tn_ag_in26: endpoint {
+ remote-endpoint = <&tpdm_north_dsb_out>;
+ };
+ };
+
+ port@1b {
+ reg = <0x1b>;
+
+ tn_ag_in27: endpoint {
+ remote-endpoint = <&tpdm_south_dsb_out>;
+ };
+ };
+
+ port@1c {
+ reg = <0x1c>;
+
+ tn_ag_in28: endpoint {
+ remote-endpoint = <&tpdm_ipcc_cmb_out>;
+ };
+ };
+
+ port@1d {
+ reg = <0x1d>;
+
+ tn_ag_in29: endpoint {
+ remote-endpoint = <&tpdm_pmu_out>;
+ };
+ };
+
+ port@1e {
+ reg = <0x1e>;
+
+ tn_ag_in30: endpoint {
+ remote-endpoint = <&tpdm_rdpm_cmb0_out>;
+ };
+ };
+
+ port@1f {
+ reg = <0x1f>;
+
+ tn_ag_in31: endpoint {
+ remote-endpoint = <&tpdm_rdpm_cmb1_out>;
+ };
+ };
+
+ port@20 {
+ reg = <0x20>;
+
+ tn_ag_in32: endpoint {
+ remote-endpoint = <&tpdm_rdpm_cmb2_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tn_ag_out: endpoint {
+ remote-endpoint = <&funnel_in0_in0>;
+ };
+ };
+ };
+ };
+
+ tpdm@109d0000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x109d0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_qm_out: endpoint {
+ remote-endpoint = <&tn_ag_in19>;
+ };
+ };
+ };
+ };
+
+ funnel@10b04000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10b04000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@6 {
+ reg = <6>;
+
+ funnel_aoss_in6: endpoint {
+ remote-endpoint = <&tpda_aoss_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+
+ funnel_aoss_in7: endpoint {
+ remote-endpoint = <&funnel_in0_out>;
+ };
+ };
+
+ };
+
+ out-ports {
+ port {
+ funnel_aoss_out: endpoint {
+ remote-endpoint = <&tmc_etf_in>;
+ };
+ };
+ };
+ };
+
+ tmc@10b05000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x10b05000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ tmc_etf_in: endpoint {
+ remote-endpoint = <&funnel_aoss_out>;
+ };
+ };
+ };
+ };
+
+ tpda@10b08000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x10b08000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpda_aoss_in0: endpoint {
+ remote-endpoint = <&tpdm_swao_prio0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpda_aoss_in1: endpoint {
+ remote-endpoint = <&tpdm_swao_prio1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ tpda_aoss_in2: endpoint {
+ remote-endpoint = <&tpdm_swao_prio2_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ tpda_aoss_in3: endpoint {
+ remote-endpoint = <&tpdm_swao_prio3_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ tpda_aoss_in4: endpoint {
+ remote-endpoint =<&tpdm_swao_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tpda_aoss_out: endpoint {
+ remote-endpoint = <&funnel_aoss_in6>;
+ };
+ };
+ };
+ };
+
+ tpdm@10b09000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10b09000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_swao_prio0_out: endpoint {
+ remote-endpoint = <&tpda_aoss_in0>;
+ };
+ };
+ };
+ };
+
+ tpdm@10b0a000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10b0a000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_swao_prio1_out: endpoint {
+ remote-endpoint = <&tpda_aoss_in1>;
+ };
+ };
+ };
+ };
+
+ tpdm@10b0b000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10b0b000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_swao_prio2_out: endpoint {
+ remote-endpoint = <&tpda_aoss_in2>;
+ };
+ };
+ };
+ };
+
+ tpdm@10b0c000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10b0c000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_swao_prio3_out: endpoint {
+ remote-endpoint = <&tpda_aoss_in3>;
+ };
+ };
+ };
+ };
+
+ tpdm@10b0d000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10b0d000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_swao_out: endpoint {
+ remote-endpoint = <&tpda_aoss_in4>;
+ };
+ };
+ };
+ };
+
+ apps_smmu: iommu@15000000 {
+ compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x15000000 0x0 0x100000>;
+
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>;
+
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+
+ dma-coherent;
+ };
+
+ intc: interrupt-controller@16000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x16000000 0x0 0x10000>,
+ <0x0 0x16080000 0x0 0x200000>;
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ #interrupt-cells = <3>;
+ interrupt-controller;
+
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x40000>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
ranges;
gic_its: msi-controller@16040000 {
<0x0 0x40000f20 0x0 0xa8>,
<0x0 0x40001000 0x0 0x1000>,
<0x0 0x40100000 0x0 0x100000>,
- <0x0 0x01C03000 0x0 0x1000>;
+ <0x0 0x01c03000 0x0 0x1000>;
reg-names = "parf",
"dbi",
"elbi",
};
};
+ cpucp_mbox: mailbox@16430000 {
+ compatible = "qcom,sm8750-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
+ reg = <0x0 0x16430000 0x0 0x8000>, <0x0 0x17830000 0x0 0x8000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ };
+
apps_rsc: rsc@16500000 {
compatible = "qcom,rpmh-rsc";
reg = <0x0 0x16500000 0x0 0x10000>,
};
};
+ sram: sram@17b4e000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x17b4e000 0x0 0x400>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x17b4e000 0x400>;
+
+ cpu_scp_lpri0: scp-sram-section@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x200>;
+ };
+
+ cpu_scp_lpri1: scp-sram-section@200 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x200 0x200>;
+ };
+ };
+
/* cluster0 */
pmu@240b3400 {
compatible = "qcom,sm8750-cpu-bwmon", "qcom,sdm845-bwmon";
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
+
+ tpdm-cdsp-llm {
+ compatible = "qcom,coresight-static-tpdm";
+ qcom,cmb-element-bits = <32>;
+
+ out-ports {
+ port {
+ tpdm_cdsp_llm_out: endpoint {
+ remote-endpoint = <&tpda_cdsp_in1>;
+ };
+ };
+ };
+ };
+
+ tpdm-cdsp-llm2 {
+ compatible = "qcom,coresight-static-tpdm";
+ qcom,cmb-element-bits = <32>;
+
+ out-ports {
+ port {
+ tpdm_cdsp_llm2_out: endpoint {
+ remote-endpoint = <&tpda_cdsp_in2>;
+ };
+ };
+ };
+ };
+
+ tpdm-modem1 {
+ compatible = "qcom,coresight-static-tpdm";
+ qcom,dsb-element-bits = <32>;
+
+ out-ports {
+ port {
+ tpdm_modem1_out: endpoint {
+ remote-endpoint = <&tpda_modem_in1>;
+ };
+ };
+ };
+ };
};
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
qcom,bcm-voters = <&apps_bcm_voter>;
};
- ipa_virt: interconnect-1 {
- compatible = "qcom,qcs615-ipa-virt";
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
mc_virt: interconnect-2 {
compatible = "qcom,qcs615-mc-virt";
#interconnect-cells = <2>;
smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
- interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING 0>;
/* On this platform, bit 26 (normally SLPI) is repurposed for ADSP */
mboxes = <&apss_shared 26>;
smp2p-cdsp {
compatible = "qcom,smp2p";
qcom,smem = <94>, <432>;
- interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING 0>;
mboxes = <&apss_shared 6>;
qcom,local-pid = <0>;
qup_opp_table: opp-table-qup {
compatible = "operating-points-v2";
- opp-shared;
opp-75000000 {
opp-hz = /bits/ 64 <75000000>;
};
};
+ pmu-a55 {
+ compatible = "arm,cortex-a55-pmu";
+ interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
+ };
+
+ pmu-a76 {
+ compatible = "arm,cortex-a76-pmu";
+ interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
"cqhci",
"ice";
- interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "hc_irq",
"pwr_irq";
compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma";
reg = <0x0 0x800000 0x0 0x60000>;
#dma-cells = <3>;
- interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
dma-channels = <8>;
dma-channel-mask = <0xf>;
iommus = <&apps_smmu 0xd6 0x0>;
clock-names = "se";
pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>;
pinctrl-names = "default";
- interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH 0>;
interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
reg = <0x0 0x884000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_i2c1_data_clk>;
reg = <0x0 0x888000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_i2c2_data_clk>;
spi2: spi@888000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00888000 0x0 0x4000>;
- interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
uart2: serial@888000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x00888000 0x0 0x4000>;
- interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>,
reg = <0x0 0x88c000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_i2c3_data_clk>;
compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma";
reg = <0x0 0xa00000 0x0 0x60000>;
#dma-cells = <3>;
- interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>;
dma-channels = <8>;
dma-channel-mask = <0xf>;
iommus = <&apps_smmu 0x376 0x0>;
clock-names = "se";
pinctrl-0 = <&qup_i2c4_data_clk>;
pinctrl-names = "default";
- interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
clock-names = "se";
pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
pinctrl-names = "default";
- interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>,
<&qup_uart4_tx>, <&qup_uart4_rx>;
pinctrl-names = "default";
- interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
clock-names = "se";
pinctrl-0 = <&qup_i2c5_data_clk>;
pinctrl-names = "default";
- interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
clock-names = "se";
pinctrl-0 = <&qup_i2c6_data_clk>;
pinctrl-names = "default";
- interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
clock-names = "se";
pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
pinctrl-names = "default";
- interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>,
<&qup_uart6_tx>, <&qup_uart6_rx>;
pinctrl-names = "default";
- interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
clock-names = "se";
pinctrl-0 = <&qup_i2c7_data_clk>;
pinctrl-names = "default";
- interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
clock-names = "se";
pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
pinctrl-names = "default";
- interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>,
<&qup_uart7_tx>, <&qup_uart7_rx>;
pinctrl-names = "default";
- interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
linux,pci-domain = <0>;
num-lanes = <1>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "msi0",
"msi1",
"msi2",
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>,
+ <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>,
+ <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>,
+ <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
reg-names = "std",
"ice";
- interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
cryptobam: dma-controller@1dc4000 {
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
reg = <0x0 0x01dc4000 0x0 0x24000>;
- interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <1>;
qcom,ee = <0>;
qcom,controlled-remotely;
reg-names = "east",
"west",
"south";
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>;
gpio-ranges = <&tlmm 0 0 124>;
gpio-controller;
#gpio-cells = <2>;
compatible = "qcom,qcs615-cdsp-pas", "qcom,sm8150-cdsp-pas";
reg = <0x0 0x08300000 0x0 0x4040>;
- interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>,
<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
status = "disabled";
glink-edge {
- interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING 0>;
mboxes = <&apss_shared 4>;
label = "cdsp";
qcom,remote-pid = <5>;
pmu@90b6300 {
compatible = "qcom,qcs615-cpu-bwmon", "qcom,sdm845-bwmon";
reg = <0x0 0x090b6300 0x0 0x600>;
- interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
pmu@90cd000 {
compatible = "qcom,qcs615-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
reg = <0x0 0x090cd000 0x0 0x1000>;
- interrupts = <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH 0>;
interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
reg = <0x0 0x08804000 0x0 0x1000>;
reg-names = "hc";
- interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "hc_irq",
"pwr_irq";
venus: video-codec@aa00000 {
compatible = "qcom,qcs615-venus", "qcom,sc7180-venus";
reg = <0x0 0x0aa00000 0x0 0x100000>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
<&videocc VIDEO_CC_VENUS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0>;
dpu_intf0_out: endpoint {
+ remote-endpoint = <&mdss_dp0_in>;
};
};
};
};
+ mdss_dp0: displayport-controller@ae90000 {
+ compatible = "qcom,sm6150-dp", "qcom,sm8150-dp", "qcom,sm8350-dp";
+
+ reg = <0x0 0x0ae90000 0x0 0x200>,
+ <0x0 0x0ae90200 0x0 0x200>,
+ <0x0 0x0ae90400 0x0 0x600>,
+ <0x0 0x0ae90a00 0x0 0x600>,
+ <0x0 0x0ae91000 0x0 0x600>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <12>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel",
+ "stream_1_pixel";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>,
+ <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>;
+
+ phys = <&usb_qmpphy_2 QMP_USB43DP_DP_PHY>;
+ phy-names = "dp";
+
+ operating-points-v2 = <&dp_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dp0_in: endpoint {
+ remote-endpoint = <&dpu_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dp0_out: endpoint {
+ data-lanes = <3 2 0 1>;
+ };
+ };
+ };
+
+ dp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
mdss_dsi0: dsi@ae94000 {
compatible = "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0x0 0x0ae94000 0x0 0x400>;
<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
<0>,
- <0>,
- <0>;
+ <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
aoss_qmp: power-management@c300000 {
compatible = "qcom,qcs615-aoss-qmp", "qcom,aoss-qmp";
reg = <0x0 0x0c300000 0x0 0x400>;
- interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING 0>;
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
#global-interrupts = <1>;
dma-coherent;
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>;
};
spmi_bus: spmi@c440000 {
compatible = "arm,gic-v3";
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <0>;
- #interrupt-cells = <3>;
+ #interrupt-cells = <4>;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
+
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
+ };
+
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu6 &cpu7>;
+ };
+ };
};
apss_shared: mailbox@17c00000 {
watchdog: watchdog@17c10000 {
compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt";
reg = <0x0 0x17c10000 0x0 0x1000>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&sleep_clk>;
};
reg = <0x17c21000 0x1000>,
<0x17c22000 0x1000>;
frame-number = <0>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
};
frame@17c23000 {
reg = <0x17c23000 0x1000>;
frame-number = <1>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
status = "disabled";
};
frame@17c25000 {
reg = <0x17c25000 0x1000>;
frame-number = <2>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
status = "disabled";
};
frame@17c27000 {
reg = <0x17c27000 0x1000>;
frame-number = <3>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
status = "disabled";
};
frame@17c29000 {
reg = <0x17c29000 0x1000>;
frame-number = <4>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
status = "disabled";
};
frame@17c2b000 {
reg = <0x17c2b000 0x1000>;
frame-number = <5>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>;
status = "disabled";
};
frame@17c2d000 {
reg = <0x17c2d000 0x1000>;
frame-number = <6>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
status = "disabled";
};
};
"drv-1",
"drv-2";
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>;
qcom,drv-id = <2>;
qcom,tcs-offset = <0xd00>;
status = "disabled";
};
+ usb_qmpphy_2: phy@88e8000 {
+ compatible = "qcom,qcs615-qmp-usb3-dp-phy";
+ reg = <0x0 0x088e8000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_USB2_SEC_PHY_AUX_CLK>,
+ <&gcc GCC_USB3_SEC_CLKREF_CLK>,
+ <&gcc GCC_AHB2PHY_WEST_CLK>,
+ <&gcc GCC_USB2_SEC_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "cfg_ahb",
+ "pipe";
+
+ resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR >,
+ <&gcc GCC_USB3_DP_PHY_SEC_BCR>;
+ reset-names = "phy_phy",
+ "dp_phy";
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ qcom,tcsr-reg = <&tcsr 0xbff0 0xb24c>;
+
+ status = "disabled";
+ };
+
usb_1: usb@a6f8800 {
compatible = "qcom,qcs615-dwc3", "qcom,dwc3";
reg = <0x0 0x0a6f8800 0x0 0x400>;
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
- <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>,
<&pdc 9 IRQ_TYPE_EDGE_BOTH>,
<&pdc 8 IRQ_TYPE_EDGE_BOTH>,
<&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x0a600000 0x0 0xcd00>;
iommus = <&apps_smmu 0x140 0x0>;
- interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>;
phys = <&usb_1_hsphy>, <&usb_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
<&gcc GCC_USB20_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>,
- <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH 0>,
<&pdc 11 IRQ_TYPE_EDGE_BOTH>,
<&pdc 10 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "pwr_event",
reg = <0x0 0x0a800000 0x0 0xcd00>;
iommus = <&apps_smmu 0xe0 0x0>;
- interrupts = <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>;
phys = <&usb_hsphy_2>;
phy-names = "usb2-phy";
compatible = "qcom,qcs615-tsens", "qcom,tsens-v2";
reg = <0x0 0x0c263000 0x0 0x1000>,
<0x0 0x0c222000 0x0 0x1000>;
- interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "uplow", "critical";
#qcom,sensors = <16>;
#thermal-sensor-cells = <1>;
compatible = "qcom,qcs615-adsp-pas", "qcom,sm8150-adsp-pas";
reg = <0x0 0x62400000 0x0 0x4040>;
- interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
+ interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING 0>,
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
status = "disabled";
glink_edge: glink-edge {
- interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING 0>;
mboxes = <&apss_shared 24>;
label = "lpass";
qcom,remote-pid = <2>;
arch_timer: timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
+ <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
+ <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>;
};
thermal-zones {
};
&pcie4 {
- perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
status = "okay";
};
-&pcie6a {
- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+&pcie4_port0 {
+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+};
+&pcie6a {
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
status = "okay";
};
+&pcie6a_port0 {
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
&pm8550_gpios {
rtmr0_default: rtmr0-reset-n-active-state {
pins = "gpio10";
};
&pcie4 {
- perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
status = "okay";
};
+&pcie4_port0 {
+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+};
+
&pcie4_phy {
vdda-phy-supply = <&vreg_l3i_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
};
&pcie5 {
- perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_wwan>;
pinctrl-0 = <&pcie5_default>;
status = "okay";
};
-&pcie6a {
- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+&pcie5_port0 {
+ reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+};
+&pcie6a {
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-names = "default";
status = "okay";
};
+&pcie6a_port0 {
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
&pm8550_gpios {
kypd_vol_up_n: kypd-vol-up-n-state {
pins = "gpio6";
};
&pcie4 {
- perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
};
&pcie6a {
- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
status = "okay";
};
+&pcie6a_port0 {
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
&pcie6a_phy {
vdda-phy-supply = <&vreg_l1d_0p8>;
vdda-pll-supply = <&vreg_l2j_1p2>;
/dts-v1/;
/plugin/;
+&apss_watchdog {
+ status = "okay";
+};
+
/* We can't and don't need to use zap shader in EL2 as linux can zap the gpu on it's own. */
&gpu_zap_shader {
status = "disabled";
};
&pcie4 {
- perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
};
&pcie6a {
- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
status = "okay";
};
+&pcie6a_port0 {
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
&pcie6a_phy {
vdda-phy-supply = <&vreg_l1d_0p8>;
vdda-pll-supply = <&vreg_l2j_1p2>;
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2025 Dale Whinham <daleyo@gmail.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "hamoa-pmics.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart2;
+ serial1 = &uart14;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&hall_int_n_default>;
+ pinctrl-names = "default";
+
+ switch-lid {
+ gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ wakeup-source;
+ wakeup-event-action = <EV_ACT_DEASSERTED>;
+ };
+ };
+
+ pmic-glink {
+ compatible = "qcom,x1e80100-pmic-glink",
+ "qcom,sm8550-pmic-glink",
+ "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>,
+ <&tlmm 123 GPIO_ACTIVE_HIGH>;
+
+ /* Left-side bottom port */
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_ss0_hs_in: endpoint {
+ remote-endpoint = <&usb_1_ss0_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss0_ss_in: endpoint {
+ remote-endpoint = <&retimer_ss0_ss_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_ss0_con_sbu_in: endpoint {
+ remote-endpoint = <&retimer_ss0_con_sbu_out>;
+ };
+ };
+ };
+ };
+
+ /* Left-side top port */
+ connector@1 {
+ compatible = "usb-c-connector";
+ reg = <1>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_ss1_hs_in: endpoint {
+ remote-endpoint = <&usb_1_ss1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss1_ss_in: endpoint {
+ remote-endpoint = <&retimer_ss1_ss_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_ss1_con_sbu_in: endpoint {
+ remote-endpoint = <&retimer_ss1_con_sbu_out>;
+ };
+ };
+ };
+ };
+ };
+
+ reserved-memory {
+ linux,cma {
+ compatible = "shared-dma-pool";
+ size = <0x0 0x8000000>;
+ reusable;
+ linux,cma-default;
+ };
+ };
+
+ vreg_edp_3p3: regulator-edp-3p3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_EDP_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&edp_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-boot-on;
+ };
+
+ vreg_rtmr0_1p15: regulator-rtmr0-1p15 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_RTMR0_1P15";
+
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+
+ gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&rtmr0_1p15_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-boot-on;
+ };
+
+ vreg_rtmr0_1p8: regulator-rtmr0-1p8 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_RTMR0_1P8";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&rtmr0_1p8_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-boot-on;
+ };
+
+ vreg_rtmr0_3p3: regulator-rtmr0-3p3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_RTMR0_3P3";
+
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&rtmr0_3p3_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-boot-on;
+ };
+
+ vreg_rtmr1_1p15: regulator-rtmr1-1p15 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_RTMR1_1P15";
+
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+
+ gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&rtmr1_1p15_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-boot-on;
+ };
+
+ vreg_rtmr1_1p8: regulator-rtmr1-1p8 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_RTMR1_1P8";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&rtmr1_1p8_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-boot-on;
+ };
+
+ vreg_rtmr1_3p3: regulator-rtmr1-3p3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_RTMR1_3P3";
+
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&rtmr1_3p3_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-boot-on;
+ };
+
+ vreg_nvme: regulator-nvme {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_NVME_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&nvme_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-boot-on;
+ };
+
+ vph_pwr: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vreg_wcn_3p3: regulator-wcn-3p3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_WCN_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&wcn_sw_en>;
+ pinctrl-names = "default";
+
+ regulator-boot-on;
+ };
+
+ vreg_wcn_0p95: regulator-wcn-0p95 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_WCN_0P95";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <950000>;
+
+ vin-supply = <&vreg_wcn_3p3>;
+ };
+
+ vreg_wcn_1p9: regulator-wcn-1p9 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_WCN_1P9";
+ regulator-min-microvolt = <1900000>;
+ regulator-max-microvolt = <1900000>;
+
+ vin-supply = <&vreg_wcn_3p3>;
+ };
+
+ sound {
+ compatible = "qcom,x1e80100-sndcard";
+ model = "X1E80100-Microsoft-Surface-Pro-11";
+ audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA WSA_SPK2 OUT",
+ "VA DMIC0", "vdd-micb",
+ "VA DMIC1", "vdd-micb";
+
+ wsa-dai-link {
+ link-name = "WSA Playback";
+
+ codec {
+ sound-dai = <&left_spkr>, <&right_spkr>,
+ <&swr0 0>, <&lpass_wsamacro 0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ va-dai-link {
+ link-name = "VA Capture";
+
+ codec {
+ sound-dai = <&lpass_vamacro 0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+ };
+
+ wcn7850-pmu {
+ compatible = "qcom,wcn7850-pmu";
+
+ vdd-supply = <&vreg_wcn_0p95>;
+ vddio-supply = <&vreg_l15b_1p8>;
+ vddaon-supply = <&vreg_wcn_0p95>;
+ vdddig-supply = <&vreg_wcn_0p95>;
+ vddrfa1p2-supply = <&vreg_wcn_1p9>;
+ vddrfa1p8-supply = <&vreg_wcn_1p9>;
+
+ wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>;
+ bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&wcn_wlan_bt_en>;
+ pinctrl-names = "default";
+
+ regulators {
+ vreg_pmu_rfa_cmn: ldo0 {
+ regulator-name = "vreg_pmu_rfa_cmn";
+ };
+
+ vreg_pmu_aon_0p59: ldo1 {
+ regulator-name = "vreg_pmu_aon_0p59";
+ };
+
+ vreg_pmu_wlcx_0p8: ldo2 {
+ regulator-name = "vreg_pmu_wlcx_0p8";
+ };
+
+ vreg_pmu_wlmx_0p85: ldo3 {
+ regulator-name = "vreg_pmu_wlmx_0p85";
+ };
+
+ vreg_pmu_btcmx_0p85: ldo4 {
+ regulator-name = "vreg_pmu_btcmx_0p85";
+ };
+
+ vreg_pmu_rfa_0p8: ldo5 {
+ regulator-name = "vreg_pmu_rfa_0p8";
+ };
+
+ vreg_pmu_rfa_1p2: ldo6 {
+ regulator-name = "vreg_pmu_rfa_1p2";
+ };
+
+ vreg_pmu_rfa_1p8: ldo7 {
+ regulator-name = "vreg_pmu_rfa_1p8";
+ };
+
+ vreg_pmu_pcie_0p9: ldo8 {
+ regulator-name = "vreg_pmu_pcie_0p9";
+ };
+
+ vreg_pmu_pcie_1p8: ldo9 {
+ regulator-name = "vreg_pmu_pcie_1p8";
+ };
+ };
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob2>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l12-supply = <&vreg_s5j_1p2>;
+ vdd-l15-supply = <&vreg_s4c_1p8>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4b_1p8: ldo4 {
+ regulator-name = "vreg_l4b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_3p0: ldo8 {
+ regulator-name = "vreg_l8b_3p0";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10b_1p8: ldo10 {
+ regulator-name = "vreg_l10b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p2: ldo12 {
+ regulator-name = "vreg_l12b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p0: ldo14 {
+ regulator-name = "vreg_l14b_3p0";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-l1-supply = <&vreg_s5j_1p2>;
+ vdd-l2-supply = <&vreg_s1f_0p7>;
+ vdd-l3-supply = <&vreg_s1f_0p7>;
+ vdd-s4-supply = <&vph_pwr>;
+
+ vreg_s4c_1p8: smps4 {
+ regulator-name = "vreg_s4c_1p8";
+ regulator-min-microvolt = <1856000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1c_1p2: ldo1 {
+ regulator-name = "vreg_l1c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2c_0p8: ldo2 {
+ regulator-name = "vreg_l2c_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c_0p8: ldo3 {
+ regulator-name = "vreg_l3c_0p8";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pmc8380-rpmh-regulators";
+ qcom,pmic-id = "d";
+
+ vdd-l1-supply = <&vreg_s1f_0p7>;
+ vdd-l2-supply = <&vreg_s1f_0p7>;
+ vdd-l3-supply = <&vreg_s4c_1p8>;
+ vdd-s1-supply = <&vph_pwr>;
+
+ vreg_l1d_0p8: ldo1 {
+ regulator-name = "vreg_l1d_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2d_0p9: ldo2 {
+ regulator-name = "vreg_l2d_0p9";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3d_1p8: ldo3 {
+ regulator-name = "vreg_l3d_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pmc8380-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vdd-l2-supply = <&vreg_s1f_0p7>;
+ vdd-l3-supply = <&vreg_s5j_1p2>;
+
+ vreg_l2e_0p8: ldo2 {
+ regulator-name = "vreg_l2e_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3e_1p2: ldo3 {
+ regulator-name = "vreg_l3e_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pmc8380-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-l1-supply = <&vreg_s5j_1p2>;
+ vdd-l2-supply = <&vreg_s5j_1p2>;
+ vdd-l3-supply = <&vreg_s5j_1p2>;
+ vdd-s1-supply = <&vph_pwr>;
+
+ vreg_s1f_0p7: smps1 {
+ regulator-name = "vreg_s1f_0p7";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-6 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "i";
+
+ vdd-l1-supply = <&vreg_s4c_1p8>;
+ vdd-l2-supply = <&vreg_s5j_1p2>;
+ vdd-l3-supply = <&vreg_s1f_0p7>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+
+ vreg_s1i_0p9: smps1 {
+ regulator-name = "vreg_s1i_0p9";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2i_1p0: smps2 {
+ regulator-name = "vreg_s2i_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1i_1p8: ldo1 {
+ regulator-name = "vreg_l1i_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2i_1p2: ldo2 {
+ regulator-name = "vreg_l2i_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3i_0p8: ldo3 {
+ regulator-name = "vreg_l3i_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "j";
+
+ vdd-l1-supply = <&vreg_s1f_0p7>;
+ vdd-l2-supply = <&vreg_s5j_1p2>;
+ vdd-l3-supply = <&vreg_s1f_0p7>;
+ vdd-s5-supply = <&vph_pwr>;
+
+ vreg_s5j_1p2: smps5 {
+ regulator-name = "vreg_s5j_1p2";
+ regulator-min-microvolt = <1256000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1j_0p8: ldo1 {
+ regulator-name = "vreg_l1j_0p8";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2j_1p2: ldo2 {
+ regulator-name = "vreg_l2j_1p2";
+ regulator-min-microvolt = <1256000>;
+ regulator-max-microvolt = <1256000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3j_0p8: ldo3 {
+ regulator-name = "vreg_l3j_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&gpu {
+ status = "okay";
+
+ zap-shader {
+ memory-region = <&gpu_microcode_mem>;
+ firmware-name = "qcom/x1e80100/microsoft/qcdxkmsuc8380.mbn";
+ };
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+
+ status = "okay";
+
+ /* Something @39, @3e, @44 */
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ /* Left-side bottom port */
+ typec-mux@8 {
+ compatible = "parade,ps8830";
+ reg = <0x8>;
+
+ reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>;
+
+ clocks = <&rpmhcc RPMH_RF_CLK3>;
+
+ vdd-supply = <&vreg_rtmr0_1p15>;
+ vdd33-supply = <&vreg_rtmr0_3p3>;
+ vdd33-cap-supply = <&vreg_rtmr0_3p3>;
+ vddar-supply = <&vreg_rtmr0_1p15>;
+ vddat-supply = <&vreg_rtmr0_1p15>;
+ vddio-supply = <&vreg_rtmr0_1p8>;
+
+ pinctrl-0 = <&rtmr0_default>;
+ pinctrl-names = "default";
+
+ retimer-switch;
+ orientation-switch;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ retimer_ss0_ss_out: endpoint {
+ remote-endpoint = <&pmic_glink_ss0_ss_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ retimer_ss0_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss0_qmpphy_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ retimer_ss0_con_sbu_out: endpoint {
+ remote-endpoint = <&pmic_glink_ss0_con_sbu_in>;
+ };
+ };
+ };
+ };
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ /* Something @12, @14, @16, @18, @1a */
+};
+
+&i2c7 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ /* Left-side top port */
+ typec-mux@8 {
+ compatible = "parade,ps8830";
+ reg = <0x8>;
+
+ reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>;
+
+ clocks = <&rpmhcc RPMH_RF_CLK4>;
+
+ vdd-supply = <&vreg_rtmr1_1p15>;
+ vdd33-supply = <&vreg_rtmr1_3p3>;
+ vdd33-cap-supply = <&vreg_rtmr1_3p3>;
+ vddar-supply = <&vreg_rtmr1_1p15>;
+ vddat-supply = <&vreg_rtmr1_1p15>;
+ vddio-supply = <&vreg_rtmr1_1p8>;
+
+ retimer-switch;
+ orientation-switch;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ retimer_ss1_ss_out: endpoint {
+ remote-endpoint = <&pmic_glink_ss1_ss_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ retimer_ss1_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss1_qmpphy_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ retimer_ss1_con_sbu_out: endpoint {
+ remote-endpoint = <&pmic_glink_ss1_con_sbu_in>;
+ };
+ };
+ };
+ };
+};
+
+&lpass_tlmm {
+ spkr_01_sd_n_active: spkr-01-sd-n-active-state {
+ pins = "gpio12";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+};
+
+&lpass_vamacro {
+ pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
+ pinctrl-names = "default";
+
+ vdd-micb-supply = <&vreg_l1b_1p8>;
+ qcom,dmic-sample-rate = <4800000>;
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dp0 {
+ status = "okay";
+};
+
+&mdss_dp0_out {
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+};
+
+&mdss_dp1 {
+ status = "okay";
+};
+
+&mdss_dp1_out {
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+};
+
+&mdss_dp3 {
+ compatible = "qcom,x1e80100-dp";
+ /delete-property/ #sound-dai-cells;
+
+ status = "okay";
+
+ aux-bus {
+ panel: panel {
+ compatible = "edp-panel";
+ enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
+ power-supply = <&vreg_edp_3p3>;
+
+ pinctrl-0 = <&edp_bl_en>;
+ pinctrl-names = "default";
+
+ port {
+ edp_panel_in: endpoint {
+ remote-endpoint = <&mdss_dp3_out>;
+ };
+ };
+ };
+ };
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ mdss_dp3_out: endpoint {
+ data-lanes = <0 1 2 3>;
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+
+ remote-endpoint = <&edp_panel_in>;
+ };
+ };
+ };
+};
+
+&mdss_dp3_phy {
+ vdda-phy-supply = <&vreg_l3j_0p8>;
+ vdda-pll-supply = <&vreg_l2j_1p2>;
+
+ status = "okay";
+};
+
+&pcie4 {
+ status = "okay";
+};
+
+&pcie4_phy {
+ vdda-phy-supply = <&vreg_l3i_0p8>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&pcie4_port0 {
+ wifi@0 {
+ compatible = "pci17cb,1107";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+ vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+ vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+ };
+};
+
+&pcie6a {
+ vddpe-3v3-supply = <&vreg_nvme>;
+
+ pinctrl-0 = <&pcie6a_default>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie6a_phy {
+ vdda-phy-supply = <&vreg_l1d_0p8>;
+ vdda-pll-supply = <&vreg_l2j_1p2>;
+
+ status = "okay";
+};
+
+&pcie6a_port0 {
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
+&pm8550_gpios {
+ rtmr0_default: rtmr0-reset-n-active-state {
+ pins = "gpio10";
+ function = "normal";
+ power-source = <1>; /* 1.8V */
+ };
+
+ rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state {
+ pins = "gpio11";
+ function = "normal";
+ power-source = <1>; /* 1.8V */
+ };
+};
+
+&pm8550ve_9_gpios {
+ rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state {
+ pins = "gpio8";
+ function = "normal";
+ power-source = <1>; /* 1.8V */
+ };
+};
+
+&pmc8380_3_gpios {
+ edp_bl_en: edp-bl-en-state {
+ pins = "gpio4";
+ function = "normal";
+ power-source = <1>; /* 1.8V */
+ input-disable;
+ output-enable;
+ };
+};
+
+&pmc8380_5_gpios {
+ rtmr0_1p15_reg_en: rtmr0-1p15-reg-en-state {
+ pins = "gpio8";
+ function = "normal";
+ power-source = <1>; /* 1.8V */
+ };
+};
+
+&qupv3_0 {
+ status = "okay";
+};
+
+&qupv3_1 {
+ status = "okay";
+};
+
+&qupv3_2 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/x1e80100/microsoft/Denali/qcadsp8380.mbn",
+ "qcom/x1e80100/microsoft/Denali/adsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/x1e80100/microsoft/Denali/qccdsp8380.mbn",
+ "qcom/x1e80100/microsoft/Denali/cdsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&smb2360_0 {
+ status = "okay";
+};
+
+&smb2360_0_eusb2_repeater {
+ vdd18-supply = <&vreg_l3d_1p8>;
+ vdd3-supply = <&vreg_l2b_3p0>;
+};
+
+&smb2360_1 {
+ status = "okay";
+};
+
+&smb2360_1_eusb2_repeater {
+ vdd18-supply = <&vreg_l3d_1p8>;
+ vdd3-supply = <&vreg_l14b_3p0>;
+};
+
+&smb2360_2 {
+ status = "okay";
+};
+
+&smb2360_2_eusb2_repeater {
+ vdd18-supply = <&vreg_l3d_1p8>;
+ vdd3-supply = <&vreg_l8b_3p0>;
+};
+
+&swr0 {
+ status = "okay";
+
+ pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>;
+ pinctrl-names = "default";
+
+ /* WSA8845, Left Speaker */
+ left_spkr: speaker@0,0 {
+ compatible = "sdw20217020400";
+ reg = <0 0>;
+ reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrLeft";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l12b_1p2>;
+ qcom,port-mapping = <1 2 3 7 10 13>;
+ };
+
+ /* WSA8845, Right Speaker */
+ right_spkr: speaker@0,1 {
+ compatible = "sdw20217020400";
+ reg = <0 1>;
+ reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrRight";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l12b_1p2>;
+ qcom,port-mapping = <4 5 6 7 11 13>;
+ };
+};
+
+&tlmm {
+ gpio-reserved-ranges = <44 4>, /* SPI (TPM) */
+ <238 1>; /* UFS Reset */
+
+ hall_int_n_default: hall-int-n-state {
+ pins = "gpio2";
+ function = "gpio";
+ bias-disable;
+ };
+
+ nvme_reg_en: nvme-reg-en-state {
+ pins = "gpio18";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ edp_reg_en: edp-reg-en-state {
+ pins = "gpio70";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ ssam_state: ssam-state-state {
+ pins = "gpio91";
+ function = "gpio";
+ bias-disable;
+ };
+
+ wcn_wlan_bt_en: wcn-wlan-bt-en-state {
+ pins = "gpio116", "gpio117";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie4_default: pcie4-default-state {
+ clkreq-n-pins {
+ pins = "gpio147";
+ function = "pcie4_clk";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio146";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake-n-pins {
+ pins = "gpio148";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie6a_default: pcie6a-default-state {
+ perst-n-pins {
+ pins = "gpio152";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ clkreq-n-pins {
+ pins = "gpio153";
+ function = "pcie6a_clk";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake-n-pins {
+ pins = "gpio154";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ rtmr1_1p8_reg_en: rtmr1-1p8-reg-en-state {
+ pins = "gpio175";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rtmr1_3p3_reg_en: rtmr1-3p3-reg-en-state {
+ pins = "gpio186";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rtmr1_1p15_reg_en: rtmr1-1p15-reg-en-state {
+ pins = "gpio188";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wcn_sw_en: wcn-sw-en-state {
+ pins = "gpio214";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_indicator_en: cam-indicator-en-state {
+ pins = "gpio225";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&uart2 {
+ status = "okay";
+
+ embedded-controller {
+ compatible = "microsoft,surface-sam";
+
+ interrupts-extended = <&tlmm 91 IRQ_TYPE_EDGE_RISING>;
+
+ current-speed = <4000000>;
+
+ pinctrl-0 = <&ssam_state>;
+ pinctrl-names = "default";
+ };
+};
+
+&uart14 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,wcn7850-bt";
+ max-speed = <3200000>;
+
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+ };
+};
+
+&usb_1_ss0_hsphy {
+ vdd-supply = <&vreg_l3j_0p8>;
+ vdda12-supply = <&vreg_l2j_1p2>;
+
+ phys = <&smb2360_0_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_1_ss0_qmpphy {
+ vdda-phy-supply = <&vreg_l2j_1p2>;
+ vdda-pll-supply = <&vreg_l1j_0p8>;
+
+ status = "okay";
+};
+
+&usb_1_ss0 {
+ status = "okay";
+};
+
+&usb_1_ss0_dwc3 {
+ dr_mode = "host";
+};
+
+&usb_1_ss0_dwc3_hs {
+ remote-endpoint = <&pmic_glink_ss0_hs_in>;
+};
+
+&usb_1_ss0_qmpphy_out {
+ remote-endpoint = <&retimer_ss0_ss_in>;
+};
+
+&usb_1_ss1_hsphy {
+ vdd-supply = <&vreg_l3j_0p8>;
+ vdda12-supply = <&vreg_l2j_1p2>;
+
+ phys = <&smb2360_1_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_1_ss1_qmpphy {
+ vdda-phy-supply = <&vreg_l2j_1p2>;
+ vdda-pll-supply = <&vreg_l2d_0p9>;
+
+ status = "okay";
+};
+
+&usb_1_ss1 {
+ status = "okay";
+};
+
+&usb_1_ss1_dwc3 {
+ dr_mode = "host";
+};
+
+&usb_1_ss1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_ss1_hs_in>;
+};
+
+&usb_1_ss1_qmpphy_out {
+ remote-endpoint = <&retimer_ss1_ss_in>;
+};
};
&pcie4 {
- perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
status = "okay";
};
-&pcie5 {
- perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+&pcie4_port0 {
+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+};
+&pcie5 {
vddpe-3v3-supply = <&vreg_wwan>;
pinctrl-0 = <&pcie5_default>;
status = "okay";
};
-&pcie6a {
- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+&pcie5_port0 {
+ reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+};
+&pcie6a {
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-names = "default";
status = "okay";
};
+&pcie6a_port0 {
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
&pm8550_gpios {
rtmr0_default: rtmr0-reset-n-active-state {
pins = "gpio10";
};
};
+ hdmi-bridge {
+ compatible = "realtek,rtd2171";
+
+ pinctrl-0 = <&hdmi_hpd_default>;
+ pinctrl-names = "default";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi_bridge_dp_in: endpoint {
+ remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ hdmi_bridge_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <&hdmi_bridge_tmds_out>;
+ };
+ };
+ };
+
pmic-glink {
compatible = "qcom,x1e80100-pmic-glink",
"qcom,sm8550-pmic-glink",
"VA DMIC1", "VA MIC BIAS1",
"TX SWR_INPUT1", "ADC2_OUTPUT";
+ displayport-0-dai-link {
+ link-name = "DisplayPort0 Playback";
+
+ codec {
+ sound-dai = <&mdss_dp0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ displayport-1-dai-link {
+ link-name = "DisplayPort1 Playback";
+
+ codec {
+ sound-dai = <&mdss_dp1>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ displayport-2-dai-link {
+ link-name = "DisplayPort2 Playback";
+
+ codec {
+ sound-dai = <&mdss_dp2>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai DISPLAY_PORT_RX_2>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
wcd-playback-dai-link {
link-name = "WCD Playback";
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
};
+&mdss_dp2 {
+ status = "okay";
+};
+
+&mdss_dp2_out {
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+};
+
&mdss_dp3 {
/delete-property/ #sound-dai-cells;
};
&pcie4 {
- perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
status = "okay";
};
-&pcie5 {
- perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+&pcie4_port0 {
+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+};
+&pcie5 {
vddpe-3v3-supply = <&vreg_wwan>;
pinctrl-0 = <&pcie5_default>;
status = "okay";
};
-&pcie6a {
- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+&pcie5_port0 {
+ reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+};
+&pcie6a {
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
status = "okay";
};
+&pcie6a_port0 {
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
&pm8550_gpios {
rtmr0_default: rtmr0-reset-n-active-state {
pins = "gpio10";
output-low;
};
+ hdmi_hpd_default: hdmi-hpd-default-state {
+ pins = "gpio126";
+ function = "usb2_dp";
+ bias-disable;
+ };
+
tpad_default: tpad-default-state {
pins = "gpio3";
function = "gpio";
remote-endpoint = <&retimer_ss1_ss_in>;
};
+&usb_1_ss2_qmpphy {
+ vdda-phy-supply = <&vreg_l2j_1p2>;
+ vdda-pll-supply = <&vreg_l2d_0p9>;
+
+ /delete-property/ mode-switch;
+ /delete-property/ orientation-switch;
+
+ status = "okay";
+
+ ports {
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /delete-node/ endpoint;
+
+ usb_1_ss2_qmpphy_out_dp: endpoint@0 {
+ reg = <0>;
+
+ data-lanes = <3 2 1 0>;
+ remote-endpoint = <&hdmi_bridge_dp_in>;
+ };
+
+ /* No USB3 lanes connected */
+ };
+ };
+};
+
&usb_2 {
status = "okay";
};
};
};
+ hdmi-bridge {
+ compatible = "parade,ps185hdm";
+
+ pinctrl-0 = <&hdmi_hpd_default>;
+ pinctrl-names = "default";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi_bridge_dp_in: endpoint {
+ remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ hdmi_bridge_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <&hdmi_bridge_tmds_out>;
+ };
+ };
+ };
+
pmic-glink {
compatible = "qcom,x1e80100-pmic-glink",
"qcom,sm8550-pmic-glink",
reg = <1>;
pmic_glink_ss0_ss_in: endpoint {
- remote-endpoint = <&usb_1_ss0_qmpphy_out>;
+ remote-endpoint = <&retimer_ss0_ss_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_ss0_con_sbu_in: endpoint {
+ remote-endpoint = <&retimer_ss0_con_sbu_out>;
};
};
};
reg = <1>;
pmic_glink_ss1_ss_in: endpoint {
- remote-endpoint = <&usb_1_ss1_qmpphy_out>;
+ remote-endpoint = <&retimer_ss1_ss_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_ss1_con_sbu_in: endpoint {
+ remote-endpoint = <&retimer_ss1_con_sbu_out>;
};
};
};
regulator-boot-on;
};
+ vreg_rtmr0_1p15: regulator-rtmr0-1p15 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_RTMR0_1P15";
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+
+ gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&usb0_pwr_1p15_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-boot-on;
+ };
+
+ vreg_rtmr0_1p8: regulator-rtmr0-1p8 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_RTMR0_1P8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&usb0_1p8_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-boot-on;
+ };
+
+ vreg_rtmr0_3p3: regulator-rtmr0-3p3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_RTMR0_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&usb0_3p3_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-boot-on;
+ };
+
+ vreg_rtmr1_1p15: regulator-rtmr1-1p15 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_RTMR1_1P15";
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+
+ gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&usb1_pwr_1p15_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-boot-on;
+ };
+
+ vreg_rtmr1_1p8: regulator-rtmr1-1p8 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_RTMR1_1P8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&usb1_pwr_1p8_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-boot-on;
+ };
+
+ vreg_rtmr1_3p3: regulator-rtmr1-3p3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_RTMR1_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&usb1_pwr_3p3_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-boot-on;
+ };
+
vph_pwr: regulator-vph-pwr {
compatible = "regulator-fixed";
&i2c1 {
clock-frequency = <400000>;
status = "okay";
-
- /* PS8830 USB4 Retimer? @ 0x8 */
};
&i2c3 {
clock-frequency = <400000>;
status = "okay";
- /* PS8830 USB4 Retimer? @ 0x8 */
+ typec-mux@8 {
+ compatible = "parade,ps8830";
+ reg = <0x08>;
+
+ clocks = <&rpmhcc RPMH_RF_CLK3>;
+
+ vdd-supply = <&vreg_rtmr0_1p15>;
+ vdd33-supply = <&vreg_rtmr0_3p3>;
+ vdd33-cap-supply = <&vreg_rtmr0_3p3>;
+ vddar-supply = <&vreg_rtmr0_1p15>;
+ vddat-supply = <&vreg_rtmr0_1p15>;
+ vddio-supply = <&vreg_rtmr0_1p8>;
+
+ reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&rtmr0_default>;
+ pinctrl-names = "default";
+
+ orientation-switch;
+ retimer-switch;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ retimer_ss0_ss_out: endpoint {
+ remote-endpoint = <&pmic_glink_ss0_ss_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ retimer_ss0_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss0_qmpphy_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ retimer_ss0_con_sbu_out: endpoint {
+ remote-endpoint = <&pmic_glink_ss0_con_sbu_in>;
+ };
+ };
+ };
+ };
};
&i2c5 {
clock-frequency = <400000>;
status = "okay";
- /* PS8830 USB4 Retimer? @ 0x8 */
+ typec-mux@8 {
+ compatible = "parade,ps8830";
+ reg = <0x8>;
+
+ clocks = <&rpmhcc RPMH_RF_CLK4>;
+
+ vdd-supply = <&vreg_rtmr1_1p15>;
+ vdd33-supply = <&vreg_rtmr1_3p3>;
+ vdd33-cap-supply = <&vreg_rtmr1_3p3>;
+ vddar-supply = <&vreg_rtmr1_1p15>;
+ vddat-supply = <&vreg_rtmr1_1p15>;
+ vddio-supply = <&vreg_rtmr1_1p8>;
+
+ reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&rtmr1_default>;
+ pinctrl-names = "default";
+
+ retimer-switch;
+ orientation-switch;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ retimer_ss1_ss_out: endpoint {
+ remote-endpoint = <&pmic_glink_ss1_ss_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ retimer_ss1_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss1_qmpphy_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ retimer_ss1_con_sbu_out: endpoint {
+ remote-endpoint = <&pmic_glink_ss1_con_sbu_in>;
+ };
+ };
+ };
+ };
+};
+
+&iris {
+ firmware-name = "qcom/x1e80100/ASUSTeK/vivobook-s15/qcvss8380.mbn";
+ status = "okay";
};
&mdss {
status = "okay";
};
+&mdss_dp0 {
+ status = "okay";
+};
+
+&mdss_dp0_out {
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+};
+
+&mdss_dp1 {
+ status = "okay";
+};
+
+&mdss_dp1_out {
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+};
+
+&mdss_dp2 {
+ status = "okay";
+};
+
+&mdss_dp2_out {
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+};
+
&mdss_dp3 {
/delete-property/ #sound-dai-cells;
};
&pcie4 {
- perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
};
&pcie6a {
- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
status = "okay";
};
+&pcie6a_port0 {
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
+&pm8550_gpios {
+ rtmr0_default: rtmr0-reset-n-active-state {
+ pins = "gpio10";
+ function = "normal";
+ power-source = <1>; /* 1.8V */
+ bias-disable;
+ input-disable;
+ output-enable;
+ };
+
+ usb0_3p3_reg_en: usb0-3p3-reg-en-state {
+ pins = "gpio11";
+ function = "normal";
+ power-source = <1>; /* 1.8V */
+ bias-disable;
+ input-disable;
+ output-enable;
+ };
+};
+
+&pm8550ve_9_gpios {
+ usb0_1p8_reg_en: usb0-1p8-reg-en-state {
+ pins = "gpio8";
+ function = "normal";
+ power-source = <1>; /* 1.8V */
+ bias-disable;
+ input-disable;
+ output-enable;
+ };
+};
+
&pmc8380_3_gpios {
edp_bl_en: edp-bl-en-state {
pins = "gpio4";
};
};
+&pmc8380_5_gpios {
+ usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state {
+ pins = "gpio8";
+ function = "normal";
+ power-source = <1>; /* 1.8V */
+ bias-disable;
+ input-disable;
+ output-enable;
+ };
+};
+
&qupv3_0 {
status = "okay";
};
bias-disable;
};
+ hdmi_hpd_default: hdmi-hpd-default-state {
+ pins = "gpio126";
+ function = "usb2_dp";
+ bias-disable;
+ };
+
kybd_default: kybd-default-state {
pins = "gpio67";
function = "gpio";
};
};
+ rtmr1_default: rtmr1-reset-n-active-state {
+ pins = "gpio176";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
tpad_default: tpad-default-state {
pins = "gpio3";
function = "gpio";
bias-disable;
};
+ usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state {
+ pins = "gpio188";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state {
+ pins = "gpio175";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state {
+ pins = "gpio186";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
wcn_bt_en: wcn-bt-en-state {
pins = "gpio116";
function = "gpio";
};
&usb_1_ss0_qmpphy_out {
- remote-endpoint = <&pmic_glink_ss0_ss_in>;
+ remote-endpoint = <&retimer_ss0_ss_in>;
};
&usb_1_ss1_hsphy {
};
&usb_1_ss1_qmpphy_out {
- remote-endpoint = <&pmic_glink_ss1_ss_in>;
+ remote-endpoint = <&retimer_ss1_ss_in>;
+};
+
+&usb_1_ss2_qmpphy {
+ vdda-phy-supply = <&vreg_l2j_1p2>;
+ vdda-pll-supply = <&vreg_l2d_0p9>;
+
+ /delete-property/ mode-switch;
+ /delete-property/ orientation-switch;
+
+ status = "okay";
+
+ ports {
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /delete-node/ endpoint;
+
+ usb_1_ss2_qmpphy_out_dp: endpoint@0 {
+ reg = <0>;
+
+ data-lanes = <3 2 1 0>;
+ remote-endpoint = <&hdmi_bridge_dp_in>;
+ };
+
+ /* No USB3 lanes connected */
+ };
+ };
};
&usb_2 {
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
};
&pcie4 {
- perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
};
&pcie6a {
- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
status = "okay";
};
+&pcie6a_port0 {
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
&pm8550_gpios {
rtmr0_default: rtmr0-reset-n-active-state {
pins = "gpio10";
};
&pcie4 {
- perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
};
&pcie6a {
- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
status = "okay";
};
+&pcie6a_port0 {
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
&pm8550_gpios {
rtmr0_default: rtmr0-reset-n-active-state {
pins = "gpio10";
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2025 TUXEDO Computers GmbH
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "hamoa.dtsi"
+#include "hamoa-pmics.dtsi"
+
+/*
+ * This device tree also works for the TUXEDO Elite 14 Gen1 notebook
+ * prototype.
+ */
+
+/ {
+ model = "Medion SPRCHRGD 14 S1";
+ compatible = "medion,sprchrgd14s1", "qcom,x1e78100", "qcom,x1e80100";
+
+ aliases {
+ serial0 = &uart21;
+ serial1 = &uart14;
+ };
+
+ wcd938x: audio-codec {
+ compatible = "qcom,wcd9385-codec";
+
+ pinctrl-0 = <&wcd_default>;
+ pinctrl-names = "default";
+
+ qcom,micbias1-microvolt = <1800000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <1800000>;
+ qcom,micbias4-microvolt = <1800000>;
+ qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+ qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+ qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+ qcom,rx-device = <&wcd_rx>;
+ qcom,tx-device = <&wcd_tx>;
+
+ reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
+
+ vdd-buck-supply = <&vreg_l15b_1p8>;
+ vdd-rxtx-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l15b_1p8>;
+ vdd-mic-bias-supply = <&vreg_bob1>;
+
+ #sound-dai-cells = <1>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&hall_int_n_default>;
+ pinctrl-names = "default";
+
+ switch-lid {
+ gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ wakeup-source;
+ };
+ };
+
+ hdmi-bridge {
+ compatible = "asl-tek,cs5263";
+
+ pinctrl-0 = <&hdmi_hpd_default>;
+ pinctrl-names = "default";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi_bridge_dp_in: endpoint {
+ remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ hdmi_bridge_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <&hdmi_bridge_tmds_out>;
+ };
+ };
+ };
+
+ pmic-glink {
+ compatible = "qcom,x1e80100-pmic-glink",
+ "qcom,sm8550-pmic-glink",
+ "qcom,pmic-glink";
+ orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_ss0_hs_in: endpoint {
+ remote-endpoint = <&usb_1_ss0_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss0_ss_in: endpoint {
+ remote-endpoint = <&retimer_ss0_ss_out>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_ss0_con_sbu_in: endpoint {
+ remote-endpoint = <&retimer_ss0_con_sbu_out>;
+ };
+ };
+ };
+ };
+ };
+
+ vreg_edp_3p3: regulator-edp-3p3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_EDP_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&edp_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-boot-on;
+ };
+
+ vreg_nvme: regulator-nvme {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_NVME_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&nvme_reg_en>;
+ pinctrl-names = "default";
+ regulator-boot-on;
+ };
+
+ vreg_rtmr0_1p15: regulator-rtmr0-1p15 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_RTMR0_1P15";
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+
+ gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&usb0_pwr_1p15_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-boot-on;
+ };
+
+ vreg_rtmr0_1p8: regulator-rtmr0-1p8 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_RTMR0_1P8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&usb0_1p8_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-boot-on;
+ };
+
+ vreg_rtmr0_3p3: regulator-rtmr0-3p3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_RTMR0_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&usb0_3p3_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-boot-on;
+ };
+
+ vph_pwr: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /*
+ * TODO: These two regulators are actually part of the removable M.2
+ * card and not the mainboard. Need to describe this differently.
+ * Functionally it works correctly, because all we need to do is to
+ * turn on the actual 3.3V supply above.
+ */
+ vreg_wcn_0p95: regulator-wcn-0p95 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_WCN_0P95";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <950000>;
+
+ vin-supply = <&vreg_wcn_3p3>;
+ };
+
+ vreg_wcn_1p9: regulator-wcn-1p9 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_WCN_1P9";
+ regulator-min-microvolt = <1900000>;
+ regulator-max-microvolt = <1900000>;
+
+ vin-supply = <&vreg_wcn_3p3>;
+ };
+
+ vreg_wcn_3p3: regulator-wcn-3p3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_WCN_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&wcn_sw_en>;
+ pinctrl-names = "default";
+
+ regulator-boot-on;
+ };
+
+ reserved-memory {
+ linux,cma {
+ compatible = "shared-dma-pool";
+ size = <0x0 0x8000000>;
+ reusable;
+ linux,cma-default;
+ };
+ };
+
+ sound {
+ compatible = "qcom,x1e80100-sndcard";
+ model = "X1E80100-MEDION-SPRCHRGD-14-S1";
+ audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT",
+ "TweeterLeft IN", "WSA WSA_SPK2 OUT",
+ "WooferRight IN", "WSA2 WSA_SPK2 OUT",
+ "TweeterRight IN", "WSA2 WSA_SPK2 OUT",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "AMIC2", "MIC BIAS2",
+ "VA DMIC0", "MIC BIAS1",
+ "VA DMIC1", "MIC BIAS1",
+ "TX SWR_INPUT1", "ADC2_OUTPUT";
+
+ displayport-0-dai-link {
+ link-name = "DisplayPort0 Playback";
+
+ codec {
+ sound-dai = <&mdss_dp0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ displayport-2-dai-link {
+ link-name = "DisplayPort2 Playback";
+
+ codec {
+ sound-dai = <&mdss_dp2>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai DISPLAY_PORT_RX_2>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ va-dai-link {
+ link-name = "VA Capture";
+
+ codec {
+ sound-dai = <&lpass_vamacro 0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wcd-capture-dai-link {
+ link-name = "WCD Capture";
+
+ codec {
+ sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wcd-playback-dai-link {
+ link-name = "WCD Playback";
+
+ codec {
+ sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wsa-dai-link {
+ link-name = "WSA Playback";
+
+ codec {
+ sound-dai = <&left_woofer>, <&left_tweeter>,
+ <&swr0 0>, <&lpass_wsamacro 0>,
+ <&right_woofer>, <&right_tweeter>,
+ <&swr3 0>, <&lpass_wsa2macro 0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+ };
+
+ wcn7850-pmu {
+ compatible = "qcom,wcn7850-pmu";
+
+ vdd-supply = <&vreg_wcn_0p95>;
+ vddio-supply = <&vreg_l15b_1p8>;
+ vddaon-supply = <&vreg_wcn_0p95>;
+ vdddig-supply = <&vreg_wcn_0p95>;
+ vddrfa1p2-supply = <&vreg_wcn_1p9>;
+ vddrfa1p8-supply = <&vreg_wcn_1p9>;
+
+ wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>;
+ bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&wcn_wlan_bt_en>;
+ pinctrl-names = "default";
+
+ regulators {
+ vreg_pmu_rfa_cmn: ldo0 {
+ regulator-name = "vreg_pmu_rfa_cmn";
+ };
+
+ vreg_pmu_aon_0p59: ldo1 {
+ regulator-name = "vreg_pmu_aon_0p59";
+ };
+
+ vreg_pmu_wlcx_0p8: ldo2 {
+ regulator-name = "vreg_pmu_wlcx_0p8";
+ };
+
+ vreg_pmu_wlmx_0p85: ldo3 {
+ regulator-name = "vreg_pmu_wlmx_0p85";
+ };
+
+ vreg_pmu_btcmx_0p85: ldo4 {
+ regulator-name = "vreg_pmu_btcmx_0p85";
+ };
+
+ vreg_pmu_rfa_0p8: ldo5 {
+ regulator-name = "vreg_pmu_rfa_0p8";
+ };
+
+ vreg_pmu_rfa_1p2: ldo6 {
+ regulator-name = "vreg_pmu_rfa_1p2";
+ };
+
+ vreg_pmu_rfa_1p8: ldo7 {
+ regulator-name = "vreg_pmu_rfa_1p8";
+ };
+
+ vreg_pmu_pcie_0p9: ldo8 {
+ regulator-name = "vreg_pmu_pcie_0p9";
+ };
+
+ vreg_pmu_pcie_1p8: ldo9 {
+ regulator-name = "vreg_pmu_pcie_1p8";
+ };
+ };
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+ qcom,pmic-id = "b";
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob2>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l12-supply = <&vreg_s5j_1p2>;
+ vdd-l15-supply = <&vreg_s4c_1p8>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4b_1p8: ldo4 {
+ regulator-name = "vreg_l4b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_2p8: ldo7 {
+ regulator-name = "vreg_l7b_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_3p0: ldo8 {
+ regulator-name = "vreg_l8b_3p0";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10b_1p8: ldo10 {
+ regulator-name = "vreg_l10b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p2: ldo12 {
+ regulator-name = "vreg_l12b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p0: ldo14 {
+ regulator-name = "vreg_l14b_3p0";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_2p8: ldo16 {
+ regulator-name = "vreg_l16b_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-l1-supply = <&vreg_s5j_1p2>;
+ vdd-l2-supply = <&vreg_s1f_0p7>;
+ vdd-l3-supply = <&vreg_s1f_0p7>;
+ vdd-s4-supply = <&vph_pwr>;
+
+ vreg_l1c_1p2: ldo1 {
+ regulator-name = "vreg_l1c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2c_0p8: ldo2 {
+ regulator-name = "vreg_l2c_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c_0p9: ldo3 {
+ regulator-name = "vreg_l3c_0p9";
+ regulator-min-microvolt = <920000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4c_1p8: smps4 {
+ regulator-name = "vreg_s4c_1p8";
+ regulator-min-microvolt = <1856000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pmc8380-rpmh-regulators";
+ qcom,pmic-id = "d";
+
+ vdd-l1-supply = <&vreg_s1f_0p7>;
+ vdd-l2-supply = <&vreg_s1f_0p7>;
+ vdd-l3-supply = <&vreg_s4c_1p8>;
+ vdd-s1-supply = <&vph_pwr>;
+
+ vreg_l1d_0p8: ldo1 {
+ regulator-name = "vreg_l1d_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2d_0p9: ldo2 {
+ regulator-name = "vreg_l2d_0p9";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3d_1p8: ldo3 {
+ regulator-name = "vreg_l3d_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pmc8380-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vdd-l2-supply = <&vreg_s1f_0p7>;
+ vdd-l3-supply = <&vreg_s5j_1p2>;
+
+ vreg_l2e_0p8: ldo2 {
+ regulator-name = "vreg_l2e_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3e_1p2: ldo3 {
+ regulator-name = "vreg_l3e_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pmc8380-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-l1-supply = <&vreg_s5j_1p2>;
+ vdd-l2-supply = <&vreg_s5j_1p2>;
+ vdd-l3-supply = <&vreg_s5j_1p2>;
+ vdd-s1-supply = <&vph_pwr>;
+
+ vreg_s1f_0p7: smps1 {
+ regulator-name = "vreg_s1f_0p7";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-6 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "i";
+
+ vdd-l1-supply = <&vreg_s4c_1p8>;
+ vdd-l2-supply = <&vreg_s5j_1p2>;
+ vdd-l3-supply = <&vreg_s1f_0p7>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+
+ vreg_l1i_1p8: ldo1 {
+ regulator-name = "vreg_l1i_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2i_1p2: ldo2 {
+ regulator-name = "vreg_l2i_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3i_0p8: ldo3 {
+ regulator-name = "vreg_l3i_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s1i_0p9: smps1 {
+ regulator-name = "vreg_s1i_0p9";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2i_1p0: smps2 {
+ regulator-name = "vreg_s2i_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "j";
+
+ vdd-l1-supply = <&vreg_s1f_0p7>;
+ vdd-l2-supply = <&vreg_s5j_1p2>;
+ vdd-l3-supply = <&vreg_s1f_0p7>;
+ vdd-s5-supply = <&vph_pwr>;
+
+ vreg_l1j_0p9: ldo1 {
+ regulator-name = "vreg_l1j_0p9";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2j_1p2: ldo2 {
+ regulator-name = "vreg_l2j_1p2";
+ regulator-min-microvolt = <1256000>;
+ regulator-max-microvolt = <1256000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3j_0p8: ldo3 {
+ regulator-name = "vreg_l3j_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5j_1p2: smps5 {
+ regulator-name = "vreg_s5j_1p2";
+ regulator-min-microvolt = <1256000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&gpu {
+ status = "okay";
+
+ zap-shader {
+ firmware-name = "qcom/x1e80100/Medion/sprchrgd-14-s1/qcdxkmsuc8380.mbn";
+ };
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ touchpad@2c {
+ compatible = "hid-over-i2c";
+ reg = <0x2c>;
+
+ hid-descr-addr = <0x20>;
+ interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&tpad_default>;
+ pinctrl-names = "default";
+
+ wakeup-source;
+ };
+
+ keyboard@3a {
+ compatible = "hid-over-i2c";
+ reg = <0x3a>;
+
+ hid-descr-addr = <0x1>;
+ interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&kybd_default>;
+ pinctrl-names = "default";
+
+ wakeup-source;
+ };
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ typec-mux@8 {
+ compatible = "parade,ps8830";
+ reg = <0x8>;
+
+ clocks = <&rpmhcc RPMH_RF_CLK3>;
+
+ vdd33-supply = <&vreg_rtmr0_3p3>;
+ vdd33-cap-supply = <&vreg_rtmr0_3p3>;
+
+ vddio-supply = <&vreg_rtmr0_1p8>;
+
+ vdd-supply = <&vreg_rtmr0_1p15>;
+ vddar-supply = <&vreg_rtmr0_1p15>;
+ vddat-supply = <&vreg_rtmr0_1p15>;
+
+ reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&rtmr0_default>;
+ pinctrl-names = "default";
+
+ retimer-switch;
+ orientation-switch;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ retimer_ss0_ss_out: endpoint {
+ remote-endpoint = <&pmic_glink_ss0_ss_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ retimer_ss0_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss0_qmpphy_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ retimer_ss0_con_sbu_out: endpoint {
+ remote-endpoint = <&pmic_glink_ss0_con_sbu_in>;
+ };
+ };
+ };
+ };
+};
+
+&i2c5 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ eusb5_repeater: redriver@43 {
+ compatible = "nxp,ptn3222";
+ reg = <0x43>;
+ #phy-cells = <0>;
+
+ vdd1v8-supply = <&vreg_l4b_1p8>;
+ vdd3v3-supply = <&vreg_l13b_3p0>;
+
+ reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&eusb5_reset_n>;
+ pinctrl-names = "default";
+ };
+
+ eusb3_repeater: redriver@47 {
+ compatible = "nxp,ptn3222";
+ reg = <0x47>;
+ #phy-cells = <0>;
+
+ vdd1v8-supply = <&vreg_l4b_1p8>;
+ vdd3v3-supply = <&vreg_l13b_3p0>;
+
+ reset-gpios = <&tlmm 124 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&eusb3_reset_n>;
+ pinctrl-names = "default";
+ };
+
+ eusb6_repeater: redriver@4f {
+ compatible = "nxp,ptn3222";
+ reg = <0x4f>;
+ #phy-cells = <0>;
+
+ vdd1v8-supply = <&vreg_l4b_1p8>;
+ vdd3v3-supply = <&vreg_l13b_3p0>;
+
+ reset-gpios = <&tlmm 111 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&eusb6_reset_n>;
+ pinctrl-names = "default";
+ };
+};
+
+&iris {
+ firmware-name = "qcom/x1e80100/Medion/sprchrgd-14-s1/qcvss8380.mbn";
+
+ status = "okay";
+};
+
+&lpass_tlmm {
+ spkr_01_sd_n_active: spkr-01-sd-n-active-state {
+ pins = "gpio12";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ spkr_23_sd_n_active: spkr-23-sd-n-active-state {
+ pins = "gpio13";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+};
+
+&lpass_vamacro {
+ pinctrl-0 = <&dmic01_default>;
+ pinctrl-names = "default";
+
+ vdd-micb-supply = <&vreg_l1b_1p8>;
+ qcom,dmic-sample-rate = <4800000>;
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dp0 {
+ sound-name-prefix = "DisplayPort0";
+
+ status = "okay";
+};
+
+&mdss_dp0_out {
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+};
+
+&mdss_dp2 {
+ sound-name-prefix = "DisplayPort2";
+
+ status = "okay";
+};
+
+&mdss_dp2_out {
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+};
+
+&mdss_dp3 {
+ /delete-property/ #sound-dai-cells;
+
+ pinctrl-0 = <&edp0_hpd_default>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ aux-bus {
+ panel {
+ compatible = "edp-panel";
+ power-supply = <&vreg_edp_3p3>;
+
+ port {
+ edp_panel_in: endpoint {
+ remote-endpoint = <&mdss_dp3_out>;
+ };
+ };
+ };
+ };
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ mdss_dp3_out: endpoint {
+ data-lanes = <0 1 2 3>;
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+
+ remote-endpoint = <&edp_panel_in>;
+ };
+ };
+ };
+};
+
+&mdss_dp3_phy {
+ vdda-phy-supply = <&vreg_l3j_0p8>;
+ vdda-pll-supply = <&vreg_l2j_1p2>;
+
+ status = "okay";
+};
+
+&pcie4 {
+ pinctrl-0 = <&pcie4_default>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie4_phy {
+ vdda-phy-supply = <&vreg_l3j_0p8>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&pcie4_port0 {
+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
+ wifi@0 {
+ compatible = "pci17cb,1107";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+ vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+ vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+ };
+};
+
+&pcie6a {
+ vddpe-3v3-supply = <&vreg_nvme>;
+
+ pinctrl-0 = <&pcie6a_default>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie6a_phy {
+ vdda-phy-supply = <&vreg_l1d_0p8>;
+ vdda-pll-supply = <&vreg_l2j_1p2>;
+
+ status = "okay";
+};
+
+&pcie6a_port0 {
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
+&pm8550_gpios {
+ rtmr0_default: rtmr0-reset-n-active-state {
+ pins = "gpio10";
+ function = "normal";
+ power-source = <1>; /* 1.8V */
+ bias-disable;
+ input-disable;
+ output-enable;
+ };
+
+ usb0_3p3_reg_en: usb0-3p3-reg-en-state {
+ pins = "gpio11";
+ function = "normal";
+ power-source = <1>; /* 1.8V */
+ bias-disable;
+ input-disable;
+ output-enable;
+ };
+};
+
+&pm8550ve_9_gpios {
+ usb0_1p8_reg_en: usb0-1p8-reg-en-state {
+ pins = "gpio8";
+ function = "normal";
+ power-source = <1>; /* 1.8V */
+ bias-disable;
+ input-disable;
+ output-enable;
+ };
+};
+
+&pmc8380_5_gpios {
+ usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state {
+ pins = "gpio8";
+ function = "normal";
+ power-source = <1>; /* 1.8V */
+ bias-disable;
+ input-disable;
+ output-enable;
+ };
+};
+
+&qupv3_0 {
+ status = "okay";
+};
+
+&qupv3_1 {
+ status = "okay";
+};
+
+&qupv3_2 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/x1e80100/Medion/sprchrgd-14-s1/qcadsp8380.mbn",
+ "qcom/x1e80100/Medion/sprchrgd-14-s1/adsp_dtbs.elf";
+
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/x1e80100/Medion/sprchrgd-14-s1/qccdsp8380.mbn",
+ "qcom/x1e80100/Medion/sprchrgd-14-s1/cdsp_dtbs.elf";
+
+ status = "okay";
+};
+
+&smb2360_0 {
+ status = "okay";
+};
+
+&smb2360_0_eusb2_repeater {
+ vdd18-supply = <&vreg_l3d_1p8>;
+ vdd3-supply = <&vreg_l2b_3p0>;
+};
+
+&swr0 {
+ status = "okay";
+
+ pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>;
+ pinctrl-names = "default";
+
+ /* WSA8845, Left Woofer */
+ left_woofer: speaker@0,0 {
+ compatible = "sdw20217020400";
+ reg = <0 0>;
+ reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "WooferLeft";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l12b_1p2>;
+ qcom,port-mapping = <1 2 3 7 10 13>;
+ };
+
+ /* WSA8845, Left Tweeter */
+ left_tweeter: speaker@0,1 {
+ compatible = "sdw20217020400";
+ reg = <0 1>;
+ reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TweeterLeft";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l12b_1p2>;
+ qcom,port-mapping = <4 5 6 7 11 13>;
+ };
+};
+
+&swr1 {
+ status = "okay";
+
+ /* WCD9385 RX */
+ wcd_rx: codec@0,4 {
+ compatible = "sdw20217010d00";
+ reg = <0 4>;
+ qcom,rx-port-mapping = <1 2 3 4 5>;
+ };
+};
+
+&swr2 {
+ status = "okay";
+
+ /* WCD9385 TX */
+ wcd_tx: codec@0,3 {
+ compatible = "sdw20217010d00";
+ reg = <0 3>;
+ qcom,tx-port-mapping = <2 2 3 4>;
+ };
+};
+
+&swr3 {
+ status = "okay";
+
+ pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>;
+ pinctrl-names = "default";
+
+ /* WSA8845, Right Woofer */
+ right_woofer: speaker@0,0 {
+ compatible = "sdw20217020400";
+ reg = <0 0>;
+ reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "WooferRight";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l12b_1p2>;
+ qcom,port-mapping = <1 2 3 7 10 13>;
+ };
+
+ /* WSA8845, Right Tweeter */
+ right_tweeter: speaker@0,1 {
+ compatible = "sdw20217020400";
+ reg = <0 1>;
+ reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TweeterRight";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l12b_1p2>;
+ qcom,port-mapping = <4 5 6 7 11 13>;
+ };
+};
+
+&tlmm {
+ gpio-reserved-ranges = <28 4>, /* Unused */
+ <44 4>, /* SPI (TPM) */
+ <238 1>; /* UFS Reset */
+
+ edp_reg_en: edp-reg-en-state {
+ pins = "gpio54";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ eusb3_reset_n: eusb3-reset-n-state {
+ pins = "gpio124";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ eusb6_reset_n: eusb6-reset-n-state {
+ pins = "gpio111";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ eusb5_reset_n: eusb5-reset-n-state {
+ pins = "gpio184";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ hall_int_n_default: hall-int-n-state {
+ pins = "gpio92";
+ function = "gpio";
+ bias-disable;
+ };
+
+ hdmi_hpd_default: hdmi-hpd-default-state {
+ pins = "gpio126";
+ function = "usb2_dp";
+ bias-disable;
+ };
+
+ kybd_default: kybd-default-state {
+ pins = "gpio67";
+ function = "gpio";
+ bias-disable;
+ };
+
+ nvme_reg_en: nvme-reg-en-state {
+ pins = "gpio18";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie4_default: pcie4-default-state {
+ clkreq-n-pins {
+ pins = "gpio147";
+ function = "pcie4_clk";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio146";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake-n-pins {
+ pins = "gpio148";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie6a_default: pcie6a-default-state {
+ clkreq-n-pins {
+ pins = "gpio153";
+ function = "pcie6a_clk";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio152";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake-n-pins {
+ pins = "gpio154";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ tpad_default: tpad-default-state {
+ pins = "gpio3";
+ function = "gpio";
+ bias-disable;
+ };
+
+ wcd_default: wcd-reset-n-active-state {
+ pins = "gpio191";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ wcn_sw_en: wcn-sw-en-state {
+ pins = "gpio214";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wcn_wlan_bt_en: wcn-wlan-bt-en-state {
+ pins = "gpio116", "gpio117";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&uart14 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,wcn7850-bt";
+ max-speed = <3200000>;
+
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+ };
+};
+
+&usb_1_ss0_hsphy {
+ vdd-supply = <&vreg_l3j_0p8>;
+ vdda12-supply = <&vreg_l2j_1p2>;
+
+ phys = <&smb2360_0_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_1_ss0_qmpphy {
+ vdda-phy-supply = <&vreg_l2j_1p2>;
+ vdda-pll-supply = <&vreg_l1j_0p9>;
+
+ status = "okay";
+};
+
+&usb_1_ss0 {
+ status = "okay";
+};
+
+&usb_1_ss0_dwc3 {
+ dr_mode = "host";
+};
+
+&usb_1_ss0_dwc3_hs {
+ remote-endpoint = <&pmic_glink_ss0_hs_in>;
+};
+
+&usb_1_ss0_qmpphy_out {
+ remote-endpoint = <&retimer_ss0_ss_in>;
+};
+
+&usb_1_ss2_qmpphy {
+ vdda-phy-supply = <&vreg_l2j_1p2>;
+ vdda-pll-supply = <&vreg_l2d_0p9>;
+
+ /delete-property/ mode-switch;
+ /delete-property/ orientation-switch;
+
+ status = "okay";
+
+ ports {
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /delete-node/ endpoint;
+
+ usb_1_ss2_qmpphy_out_dp: endpoint@0 {
+ reg = <0>;
+
+ data-lanes = <3 2 1 0>;
+ remote-endpoint = <&hdmi_bridge_dp_in>;
+ };
+
+ /* No USB3 lanes connected */
+ };
+ };
+};
+
+/* Camera */
+&usb_2 {
+ status = "okay";
+};
+
+&usb_2_dwc3 {
+ dr_mode = "host";
+};
+
+&usb_2_hsphy {
+ vdd-supply = <&vreg_l2e_0p8>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ phys = <&eusb5_repeater>;
+
+ status = "okay";
+};
+
+&usb_mp {
+ status = "okay";
+};
+
+/* Right side USB-A (eUSB 3) */
+&usb_mp_hsphy0 {
+ vdd-supply = <&vreg_l2e_0p8>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ phys = <&eusb3_repeater>;
+
+ status = "okay";
+};
+
+/* Left side USB-A (eUSB 6) */
+&usb_mp_hsphy1 {
+ vdd-supply = <&vreg_l2e_0p8>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ phys = <&eusb6_repeater>;
+
+ status = "okay";
+};
+
+/* Right side USB-A (USB-SS 3) */
+&usb_mp_qmpphy0 {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l3c_0p9>;
+
+ status = "okay";
+};
+
+/* Left side USB-A (USB-SS 4) */
+&usb_mp_qmpphy1 {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l3c_0p9>;
+
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025 Dale Whinham <daleyo@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "hamoa.dtsi"
+#include "x1-microsoft-denali.dtsi"
+
+/ {
+ model = "Microsoft Surface Pro 11th Edition (OLED)";
+ compatible = "microsoft,denali-oled", "microsoft,denali",
+ "qcom,x1e80100";
+};
+
+&panel {
+ compatible = "samsung,atna30dw01", "samsung,atna33xc20";
+};
};
&pcie3 {
- perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>;
-
pinctrl-0 = <&pcie3_default>;
pinctrl-names = "default";
status = "okay";
};
+&pcie3_port0 {
+ reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+};
+
&pcie4 {
status = "okay";
};
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
};
&pcie6a {
- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
status = "okay";
};
+&pcie6a_port0 {
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
&pm8550_gpios {
rtmr0_default: rtmr0-reset-n-active-state {
pins = "gpio10";
&pcie3 {
pinctrl-names = "default";
pinctrl-0 = <&pcie3_default>;
- perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
status = "okay";
};
status = "okay";
};
-&pcie3_port {
+&pcie3_port0 {
vpcie12v-supply = <&vreg_pcie_12v>;
vpcie3v3-supply = <&vreg_pcie_3v3>;
vpcie3v3aux-supply = <&vreg_pcie_3v3_aux>;
+
+ reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
};
&pcie4 {
- perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
};
&pcie6a {
- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-names = "default";
status = "okay";
};
+&pcie6a_port0 {
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
&qupv3_0 {
status = "okay";
};
vdd-supply = <&vreg_cam_5p0>;
};
+ hdmi-bridge {
+ compatible = "realtek,rtd2171";
+
+ enable-gpios = <&tlmm 120 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&hdmi_hpd_default>;
+ pinctrl-names = "default";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi_bridge_dp_in: endpoint {
+ remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ hdmi_bridge_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <&hdmi_bridge_tmds_out>;
+ };
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
};
+&mdss_dp2 {
+ status = "okay";
+};
+
+&mdss_dp2_out {
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+};
+
&mdss_dp3 {
/delete-property/ #sound-dai-cells;
};
&pcie4 {
- perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
};
&pcie6a {
- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
status = "okay";
};
+&pcie6a_port0 {
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
&pm8550_pwm {
status = "okay";
};
bias-disable;
};
+ hdmi_bridge_en: hdmi-bridge-en-state {
+ pins = "gpio120";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-pull-down;
+ };
+
+ hdmi_hpd_default: hdmi-hpd-default-state {
+ pins = "gpio126";
+ function = "usb2_dp";
+ bias-disable;
+ };
+
kybd_default: kybd-default-state {
pins = "gpio67";
function = "gpio";
maximum-speed = "high-speed";
phys = <&usb_1_ss2_hsphy>;
phy-names = "usb2-phy";
+
+ /delete-property/ port@1;
};
&usb_1_ss2_hsphy {
status = "okay";
};
+&usb_1_ss2_qmpphy {
+ vdda-phy-supply = <&vreg_l2j_1p2>;
+ vdda-pll-supply = <&vreg_l2d_0p9>;
+
+ /delete-property/ mode-switch;
+ /delete-property/ orientation-switch;
+
+ status = "okay";
+
+ ports {
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /delete-node/ endpoint;
+
+ usb_1_ss2_qmpphy_out_dp: endpoint@0 {
+ reg = <0>;
+
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&hdmi_bridge_dp_in>;
+ };
+ };
+ };
+};
+
&usb_2 {
status = "okay";
};
--- /dev/null
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025 Dale Whinham <daleyo@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "hamoa.dtsi"
+#include "x1-microsoft-denali.dtsi"
+
+/ {
+ model = "Microsoft Surface Pro 11th Edition (LCD)";
+ compatible = "microsoft,denali-lcd", "microsoft,denali",
+ "qcom,x1p64100", "qcom,x1e80100";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Realtek Kent SoC family
+ *
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x0>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ dynamic-power-coefficient = <454>;
+ #cooling-cells = <2>;
+
+ l2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-size = <0x40000>;
+ cache-unified;
+ next-level-cache = <&l3>;
+ };
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x100>;
+ enable-method = "psci";
+ next-level-cache = <&l2_1>;
+ dynamic-power-coefficient = <454>;
+ #cooling-cells = <2>;
+
+ l2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-size = <0x40000>;
+ cache-unified;
+ next-level-cache = <&l3>;
+ };
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x200>;
+ enable-method = "psci";
+ next-level-cache = <&l2_2>;
+ dynamic-power-coefficient = <454>;
+ #cooling-cells = <2>;
+
+ l2_2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-size = <0x40000>;
+ cache-unified;
+ next-level-cache = <&l3>;
+ };
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x300>;
+ enable-method = "psci";
+ next-level-cache = <&l2_3>;
+ dynamic-power-coefficient = <454>;
+ #cooling-cells = <2>;
+
+ l2_3: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-size = <0x40000>;
+ cache-unified;
+ next-level-cache = <&l3>;
+ };
+ };
+
+ l3: l3-cache {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-size = <0x200000>;
+ cache-unified;
+ };
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc@0 {
+ compatible = "simple-bus";
+ ranges = <0x0 0x0 0x0 0x40000>, /* boot code */
+ <0x98000000 0x0 0x98000000 0xef0000>, /* rbus */
+ <0xa0000000 0x0 0xa0000000 0x10000000>, /* PCIE */
+ <0xff000000 0x0 0xff000000 0x200000>; /* GIC */
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ rbus: bus@98000000 {
+ compatible = "simple-bus";
+ ranges = <0x0 0x98000000 0xef0000>,
+ <0xa0000000 0xa0000000 0x10000000>; /* PCIE */
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: serial@7800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x7800 0x100>;
+ clock-frequency = <432000000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+ };
+
+ gic: interrupt-controller@ff100000 {
+ compatible = "arm,gic-v3";
+ reg = <0xff100000 0x10000>,
+ <0xff140000 0x80000>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #interrupt-cells = <3>;
+ #size-cells = <1>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Realtek RTD1501 SoC
+ *
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ */
+
+#include "kent.dtsi"
+
+&uart0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Realtek RTD1501S Phantom EVB
+ *
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ */
+
+/dts-v1/;
+
+#include "rtd1501s-phantom.dtsi"
+
+/ {
+ compatible = "realtek,phantom", "realtek,rtd1501s";
+ model = "Realtek Phantom EVB Chromium (8GB)";
+
+ memory@40000 {
+ device_type = "memory";
+ reg = <0x0 0x50000 0x0 0x7ffb0000>,
+ <0x0 0x8a100000 0x0 0xdef0000>,
+ <0x0 0x98700000 0x0 0x7900000>,
+ <0x0 0xa0600000 0x0 0x5ea00000>,
+ <0x1 0x0 0x0 0xa0000000>,
+ <0x1 0xa0600000 0x0 0x5fa00000>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Realtek RTD1501S Phantom EVB
+ *
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/thermal/thermal.h>
+#include "rtd1501.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial0:460800n8";
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alignment = <0x0 0x400000>;
+ alloc-ranges = <0x0 0x0 0x0 0x20000000>;
+ size = <0x0 0x2000000>;
+ reusable;
+ linux,cma-default;
+ };
+ };
+
+ cpu_opps: opp-table-cpu {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp800: opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <830000 830000 1100000>;
+ };
+
+ opp900: opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <850000 850000 1100000>;
+ };
+
+ opp1000: opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <870000 870000 1100000>;
+ };
+
+ opp1100: opp-1100000000 {
+ opp-hz = /bits/ 64 <1100000000>;
+ opp-microvolt = <890000 890000 1100000>;
+ };
+
+ opp1200: opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <910000 910000 1100000>;
+ };
+
+ opp1300: opp-1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ opp-microvolt = <930000 930000 1100000>;
+ };
+
+ opp1400: opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt = <950000 950000 1100000>;
+ };
+
+ opp1500: opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <970000 970000 1100000>;
+ };
+
+ opp1600: opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <990000 990000 1100000>;
+ opp-suspend;
+ };
+
+ opp1700: opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <1010000 1010000 1100000>;
+ };
+
+ opp1800: opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1030000 1030000 1100000>;
+ };
+
+ opp1900: opp-1900000000 {
+ opp-hz = /bits/ 64 <1900000000>;
+ opp-microvolt = <1050000 1050000 1100000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Realtek RTD1861 SoC
+ *
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ */
+
+#include "kent.dtsi"
+
+&uart0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Realtek RTD1861B Krypton EVB
+ *
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ */
+
+/dts-v1/;
+
+#include "rtd1861b-krypton.dtsi"
+
+/ {
+ compatible = "realtek,krypton", "realtek,rtd1861b";
+ model = "Realtek Krypton EVB (8GB)";
+
+ memory@40000 {
+ device_type = "memory";
+ reg = <0x0 0x50000 0x0 0x7ffb0000>,
+ <0x0 0x8a100000 0x0 0xdef0000>,
+ <0x0 0x98700000 0x0 0x7900000>,
+ <0x0 0xa0600000 0x0 0x5ea00000>,
+ <0x1 0x0 0x0 0xa0000000>,
+ <0x1 0xa0600000 0x0 0x5fa00000>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Realtek RTD1861B Krypton EVB
+ *
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ */
+
+/dts-v1/;
+
+#include "rtd1861.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial0:460800n8";
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alignment = <0x0 0x400000>;
+ alloc-ranges = <0x0 0x0 0x0 0x20000000>;
+ size = <0x0 0x2000000>;
+ reusable;
+ linux,cma-default;
+ };
+ };
+
+ cpu_opps: opp-table-cpu {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp1200: opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <900000>;
+ };
+
+ opp1600: opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <1000000>;
+ opp-suspend;
+ };
+
+ opp1800: opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1050000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Realtek RTD1920 SoC
+ *
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ */
+
+#include "kent.dtsi"
+
+&uart0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Realtek RTD1920S Smallville EVB
+ *
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ */
+
+/dts-v1/;
+
+#include "rtd1920s-smallville.dtsi"
+
+/ {
+ compatible = "realtek,smallville", "realtek,rtd1920s";
+ model = "Realtek Smallville EVB (4GB)";
+
+ memory@40000 {
+ device_type = "memory";
+ reg = <0x0 0x50000 0x0 0x7ffb0000>,
+ <0x0 0x8a100000 0x0 0xdef0000>,
+ <0x0 0x98700000 0x0 0x7900000>,
+ <0x0 0xa1000000 0x0 0x5e000000>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Realtek RTD1920S Smallville EVB
+ *
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/thermal/thermal.h>
+#include "rtd1920.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial0:460800n8";
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ protected_mem: protected-mem@50000 {
+ reg = <0x0 0x50000 0x0 0xbf0000>;
+ no-map;
+ };
+
+ metadata: metadata@c40000 {
+ reg = <0x0 0xc40000 0x0 0x3c4000>;
+ no-map;
+ };
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alignment = <0x0 0x400000>;
+ alloc-ranges = <0x0 0x0 0x0 0x20000000>;
+ size = <0x0 0x2000000>;
+ reusable;
+ linux,cma-default;
+ };
+ };
+
+ cpu_opps: opp-table-cpu {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp800: opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <830000 830000 1100000>;
+ };
+
+ opp900: opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <850000 850000 1100000>;
+ };
+
+ opp1000: opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <870000 870000 1100000>;
+ };
+
+ opp1100: opp-1100000000 {
+ opp-hz = /bits/ 64 <1100000000>;
+ opp-microvolt = <890000 890000 1100000>;
+ };
+
+ opp1200: opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <910000 910000 1100000>;
+ };
+
+ opp1300: opp-1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ opp-microvolt = <930000 930000 1100000>;
+ };
+
+ opp1400: opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt = <950000 950000 1100000>;
+ };
+
+ opp1500: opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <970000 970000 1100000>;
+ };
+
+ opp1600: opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <990000 990000 1100000>;
+ opp-suspend;
+ };
+
+ opp1700: opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <1010000 1010000 1100000>;
+ };
+
+ opp1800: opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1030000 1030000 1100000>;
+ };
+
+ opp1900: opp-1900000000 {
+ opp-hz = /bits/ 64 <1900000000>;
+ opp-microvolt = <1050000 1050000 1100000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
reg = <0x51>;
};
- versaclock5: versaclock_som@6a {
+ versaclock5: versaclock-som@6a {
compatible = "idt,5p49v6965";
reg = <0x6a>;
#clock-cells = <1>;
reg = <0x00040000 0x080000>;
read-only;
};
- cert_header_sa3@c0000 {
+ cert-header-sa3@c0000 {
reg = <0x000c0000 0x080000>;
read-only;
};
reg = <0x00140000 0x040000>;
read-only;
};
- cert_header_sa6@180000 {
+ cert-header-sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
&scif_clk {
clock-frequency = <14745600>;
};
+
+/* Firmware should reserve it but sadly doesn't */
+&swdt {
+ status = "reserved";
+};
reg = <0x00040000 0x140000>;
read-only;
};
- cert_header_sa6@180000 {
+ cert-header-sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
reg = <0x00040000 0x140000>;
read-only;
};
- cert_header_sa6@180000 {
+ cert-header-sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017 Ideas on Board <kieran.bingham@ideasonboard.com>
- * Copyright (C) 2021 Jacopo Mondi <jacopo+renesas@jmondi.org>
- *
- * Device Tree Source (overlay) that describes GMSL camera connected to
- * Fakra connectors for the Eagle V3M and Condor V3H (and compatible) boards.
- *
- * The following cameras are currently supported: RDACM20 and RDACM21.
- *
- * The board .dts file that include this has to select which cameras are in use
- * by specifying the camera model with:
- *
- * #define GMSL_CAMERA_RDACM20
- * or
- * #define GMSL_CAMERA_RDACM21
- *
- * And which cameras are connected to the board by defining:
- * for GMSL channel 0:
- * #define GMSL_CAMERA_0
- * #define GMSL_CAMERA_1
- * #define GMSL_CAMERA_2
- * #define GMSL_CAMERA_3
- *
- * for GMSL channel 1:
- * #define GMSL_CAMERA_4
- * #define GMSL_CAMERA_5
- * #define GMSL_CAMERA_6
- * #define GMSL_CAMERA_7
- */
-
-#include <dt-bindings/gpio/gpio.h>
-
-/* Validate the board file settings. */
-#if !defined(GMSL_CAMERA_RDACM20) && !defined(GMSL_CAMERA_RDACM21)
-#error "Camera model should be defined by the board file"
-#endif
-
-#if defined(GMSL_CAMERA_RDACM20) && defined(GMSL_CAMERA_RDACM21)
-#error "A single camera model should be selected"
-#endif
-
-#if !defined(GMSL_CAMERA_0) && !defined(GMSL_CAMERA_1) && \
- !defined(GMSL_CAMERA_2) && !defined(GMSL_CAMERA_3) && \
- !defined(GMSL_CAMERA_4) && !defined(GMSL_CAMERA_5) && \
- !defined(GMSL_CAMERA_6) && !defined(GMSL_CAMERA_7)
-#error "At least one camera should be selected"
-#endif
-
-/* Deduce from the enabled cameras which GMSL channels are active. */
-#if defined(GMSL_CAMERA_0) || defined(GMSL_CAMERA_1) || \
- defined(GMSL_CAMERA_2) || defined(GMSL_CAMERA_3)
-#define GMSL_0
-#endif
-
-#if defined(GMSL_CAMERA_4) || defined(GMSL_CAMERA_5) || \
- defined(GMSL_CAMERA_6) || defined(GMSL_CAMERA_7)
-#define GMSL_1
-#endif
-
-/* Deduce the camera model compatible string. */
-#if defined(GMSL_CAMERA_RDACM20)
-#define GMSL_CAMERA_MODEL "imi,rdacm20"
-#elif defined(GMSL_CAMERA_RDACM21)
-#define GMSL_CAMERA_MODEL "imi,rdacm21"
-#endif
-
-#ifdef GMSL_0
-&vin0 {
- status = "okay";
-};
-
-&vin1 {
- status = "okay";
-};
-
-&vin2 {
- status = "okay";
-};
-
-&vin3 {
- status = "okay";
-};
-
-&gmsl0 {
- status = "okay";
-
-#if defined(GMSL_CAMERA_RDACM21)
- maxim,reverse-channel-microvolt = <100000>;
-#endif
-
- ports {
-#ifdef GMSL_CAMERA_0
- port@0 {
- max9286_in0: endpoint {
- remote-endpoint = <&fakra_con0>;
- };
- };
-#endif
-
-#ifdef GMSL_CAMERA_1
- port@1 {
- max9286_in1: endpoint {
- remote-endpoint = <&fakra_con1>;
- };
-
- };
-#endif
-
-#ifdef GMSL_CAMERA_2
- port@2 {
- max9286_in2: endpoint {
- remote-endpoint = <&fakra_con2>;
- };
-
- };
-#endif
-
-#ifdef GMSL_CAMERA_3
- port@3 {
- max9286_in3: endpoint {
- remote-endpoint = <&fakra_con3>;
- };
-
- };
-#endif
- };
-
- i2c-mux {
-#ifdef GMSL_CAMERA_0
- i2c@0 {
- status = "okay";
-
- camera@51 {
- compatible = GMSL_CAMERA_MODEL;
- reg = <0x51>, <0x61>;
-
- port {
- fakra_con0: endpoint {
- remote-endpoint = <&max9286_in0>;
- };
- };
- };
- };
-#endif
-
-#ifdef GMSL_CAMERA_1
- i2c@1 {
- status = "okay";
-
- camera@52 {
- compatible = GMSL_CAMERA_MODEL;
- reg = <0x52>, <0x62>;
-
- port {
- fakra_con1: endpoint {
- remote-endpoint = <&max9286_in1>;
- };
- };
- };
- };
-#endif
-
-#ifdef GMSL_CAMERA_2
- i2c@2 {
- status = "okay";
-
- camera@53 {
- compatible = GMSL_CAMERA_MODEL;
- reg = <0x53>, <0x63>;
-
- port {
- fakra_con2: endpoint {
- remote-endpoint = <&max9286_in2>;
- };
- };
- };
- };
-#endif
-
-#ifdef GMSL_CAMERA_3
- i2c@3 {
- status = "okay";
-
- camera@54 {
- compatible = GMSL_CAMERA_MODEL;
- reg = <0x54>, <0x64>;
-
- port {
- fakra_con3: endpoint {
- remote-endpoint = <&max9286_in3>;
- };
- };
- };
- };
-#endif
- };
-};
-#endif /* ifdef GMSL_0 */
-
-#ifdef GMSL_1
-&vin4 {
- status = "okay";
-};
-
-&vin5 {
- status = "okay";
-};
-
-&vin6 {
- status = "okay";
-};
-
-&vin7 {
- status = "okay";
-};
-
-&gmsl1 {
- status = "okay";
-
-#if defined(GMSL_CAMERA_RDACM21)
- maxim,reverse-channel-microvolt = <100000>;
-#endif
-
- ports {
-#ifdef GMSL_CAMERA_4
- port@0 {
- max9286_in4: endpoint {
- remote-endpoint = <&fakra_con4>;
- };
- };
-#endif
-
-#ifdef GMSL_CAMERA_5
- port@1 {
- max9286_in5: endpoint {
- remote-endpoint = <&fakra_con5>;
- };
-
- };
-#endif
-
-#ifdef GMSL_CAMERA_6
- port@2 {
- max9286_in6: endpoint {
- remote-endpoint = <&fakra_con6>;
- };
-
- };
-#endif
-
-#ifdef GMSL_CAMERA_7
- port@3 {
- max9286_in7: endpoint {
- remote-endpoint = <&fakra_con7>;
- };
-
- };
-#endif
- };
-
- i2c-mux {
-#ifdef GMSL_CAMERA_4
- i2c@0 {
- status = "okay";
-
- camera@55 {
- compatible = GMSL_CAMERA_MODEL;
- reg = <0x55>, <0x65>;
-
- port {
- fakra_con4: endpoint {
- remote-endpoint = <&max9286_in4>;
- };
- };
- };
- };
-#endif
-
-#ifdef GMSL_CAMERA_5
- i2c@1 {
- status = "okay";
-
- camera@56 {
- compatible = GMSL_CAMERA_MODEL;
- reg = <0x56>, <0x66>;
-
- port {
- fakra_con5: endpoint {
- remote-endpoint = <&max9286_in5>;
- };
- };
- };
- };
-#endif
-
-#ifdef GMSL_CAMERA_6
- i2c@2 {
- status = "okay";
-
- camera@57 {
- compatible = GMSL_CAMERA_MODEL;
- reg = <0x57>, <0x67>;
-
- port {
- fakra_con6: endpoint {
- remote-endpoint = <&max9286_in6>;
- };
- };
- };
- };
-#endif
-
-#ifdef GMSL_CAMERA_7
- i2c@3 {
- status = "okay";
-
- camera@58 {
- compatible = GMSL_CAMERA_MODEL;
- reg = <0x58>, <0x68>;
-
- port {
- fakra_con7: endpoint {
- remote-endpoint = <&max9286_in7>;
- };
- };
- };
- };
-#endif
- };
-};
-#endif /* ifdef GMSL_1 */
pinctrl-names = "default";
status = "okay";
- cs2000: clk_multiplier@4f {
+ cs2000: clk-multiplier@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;
dma-names = "rx", "tx";
};
ssiu04: ssiu-4 {
- dmas = <&audma0 0x3F>, <&audma1 0x40>;
+ dmas = <&audma0 0x3f>, <&audma1 0x40>;
dma-names = "rx", "tx";
};
ssiu05: ssiu-5 {
dma-names = "rx", "tx";
};
ssiu06: ssiu-6 {
- dmas = <&audma0 0x4F>, <&audma1 0x50>;
+ dmas = <&audma0 0x4f>, <&audma1 0x50>;
dma-names = "rx", "tx";
};
ssiu07: ssiu-7 {
dma-names = "rx", "tx";
};
ssiu11: ssiu-9 {
- dmas = <&audma0 0x4B>, <&audma1 0x4C>;
+ dmas = <&audma0 0x4b>, <&audma1 0x4c>;
dma-names = "rx", "tx";
};
ssiu12: ssiu-10 {
dma-names = "rx", "tx";
};
ssiu13: ssiu-11 {
- dmas = <&audma0 0x59>, <&audma1 0x5A>;
+ dmas = <&audma0 0x59>, <&audma1 0x5a>;
dma-names = "rx", "tx";
};
ssiu14: ssiu-12 {
- dmas = <&audma0 0x5F>, <&audma1 0x60>;
+ dmas = <&audma0 0x5f>, <&audma1 0x60>;
dma-names = "rx", "tx";
};
ssiu15: ssiu-13 {
- dmas = <&audma0 0xC3>, <&audma1 0xC4>;
+ dmas = <&audma0 0xc3>, <&audma1 0xc4>;
dma-names = "rx", "tx";
};
ssiu16: ssiu-14 {
- dmas = <&audma0 0xC7>, <&audma1 0xC8>;
+ dmas = <&audma0 0xc7>, <&audma1 0xc8>;
dma-names = "rx", "tx";
};
ssiu17: ssiu-15 {
- dmas = <&audma0 0xCB>, <&audma1 0xCC>;
+ dmas = <&audma0 0xcb>, <&audma1 0xcc>;
dma-names = "rx", "tx";
};
ssiu20: ssiu-16 {
dma-names = "rx", "tx";
};
ssiu22: ssiu-18 {
- dmas = <&audma0 0x6B>, <&audma1 0x6C>;
+ dmas = <&audma0 0x6b>, <&audma1 0x6c>;
dma-names = "rx", "tx";
};
ssiu23: ssiu-19 {
- dmas = <&audma0 0x6D>, <&audma1 0x6E>;
+ dmas = <&audma0 0x6d>, <&audma1 0x6e>;
dma-names = "rx", "tx";
};
ssiu24: ssiu-20 {
- dmas = <&audma0 0xCF>, <&audma1 0xCE>;
+ dmas = <&audma0 0xcf>, <&audma1 0xce>;
dma-names = "rx", "tx";
};
ssiu25: ssiu-21 {
- dmas = <&audma0 0xEB>, <&audma1 0xEC>;
+ dmas = <&audma0 0xeb>, <&audma1 0xec>;
dma-names = "rx", "tx";
};
ssiu26: ssiu-22 {
- dmas = <&audma0 0xED>, <&audma1 0xEE>;
+ dmas = <&audma0 0xed>, <&audma1 0xee>;
dma-names = "rx", "tx";
};
ssiu27: ssiu-23 {
- dmas = <&audma0 0xEF>, <&audma1 0xF0>;
+ dmas = <&audma0 0xef>, <&audma1 0xf0>;
dma-names = "rx", "tx";
};
ssiu30: ssiu-24 {
dma-names = "rx", "tx";
};
ssiu35: ssiu-29 {
- dmas = <&audma0 0x29>, <&audma1 0x2A>;
+ dmas = <&audma0 0x29>, <&audma1 0x2a>;
dma-names = "rx", "tx";
};
ssiu36: ssiu-30 {
- dmas = <&audma0 0x2B>, <&audma1 0x2C>;
+ dmas = <&audma0 0x2b>, <&audma1 0x2c>;
dma-names = "rx", "tx";
};
ssiu37: ssiu-31 {
- dmas = <&audma0 0x2D>, <&audma1 0x2E>;
+ dmas = <&audma0 0x2d>, <&audma1 0x2e>;
dma-names = "rx", "tx";
};
ssiu40: ssiu-32 {
dma-names = "rx", "tx";
};
ssiu42: ssiu-34 {
- dmas = <&audma0 0x19>, <&audma1 0x1A>;
+ dmas = <&audma0 0x19>, <&audma1 0x1a>;
dma-names = "rx", "tx";
};
ssiu43: ssiu-35 {
- dmas = <&audma0 0x1B>, <&audma1 0x1C>;
+ dmas = <&audma0 0x1b>, <&audma1 0x1c>;
dma-names = "rx", "tx";
};
ssiu44: ssiu-36 {
- dmas = <&audma0 0x1D>, <&audma1 0x1E>;
+ dmas = <&audma0 0x1d>, <&audma1 0x1e>;
dma-names = "rx", "tx";
};
ssiu45: ssiu-37 {
- dmas = <&audma0 0x1F>, <&audma1 0x20>;
+ dmas = <&audma0 0x1f>, <&audma1 0x20>;
dma-names = "rx", "tx";
};
ssiu46: ssiu-38 {
dma-names = "rx", "tx";
};
ssiu91: ssiu-45 {
- dmas = <&audma0 0x7F>, <&audma1 0x80>;
+ dmas = <&audma0 0x7f>, <&audma1 0x80>;
dma-names = "rx", "tx";
};
ssiu92: ssiu-46 {
dma-names = "rx", "tx";
};
ssiu94: ssiu-48 {
- dmas = <&audma0 0xA3>, <&audma1 0xA4>;
+ dmas = <&audma0 0xa3>, <&audma1 0xa4>;
dma-names = "rx", "tx";
};
ssiu95: ssiu-49 {
- dmas = <&audma0 0xA5>, <&audma1 0xA6>;
+ dmas = <&audma0 0xa5>, <&audma1 0xa6>;
dma-names = "rx", "tx";
};
ssiu96: ssiu-50 {
- dmas = <&audma0 0xA7>, <&audma1 0xA8>;
+ dmas = <&audma0 0xa7>, <&audma1 0xa8>;
dma-names = "rx", "tx";
};
ssiu97: ssiu-51 {
- dmas = <&audma0 0xA9>, <&audma1 0xAA>;
+ dmas = <&audma0 0xa9>, <&audma1 0xaa>;
dma-names = "rx", "tx";
};
};
dma-names = "rx", "tx";
};
ssiu04: ssiu-4 {
- dmas = <&audma0 0x3F>, <&audma1 0x40>;
+ dmas = <&audma0 0x3f>, <&audma1 0x40>;
dma-names = "rx", "tx";
};
ssiu05: ssiu-5 {
dma-names = "rx", "tx";
};
ssiu06: ssiu-6 {
- dmas = <&audma0 0x4F>, <&audma1 0x50>;
+ dmas = <&audma0 0x4f>, <&audma1 0x50>;
dma-names = "rx", "tx";
};
ssiu07: ssiu-7 {
dma-names = "rx", "tx";
};
ssiu11: ssiu-9 {
- dmas = <&audma0 0x4B>, <&audma1 0x4C>;
+ dmas = <&audma0 0x4b>, <&audma1 0x4c>;
dma-names = "rx", "tx";
};
ssiu12: ssiu-10 {
dma-names = "rx", "tx";
};
ssiu13: ssiu-11 {
- dmas = <&audma0 0x59>, <&audma1 0x5A>;
+ dmas = <&audma0 0x59>, <&audma1 0x5a>;
dma-names = "rx", "tx";
};
ssiu14: ssiu-12 {
- dmas = <&audma0 0x5F>, <&audma1 0x60>;
+ dmas = <&audma0 0x5f>, <&audma1 0x60>;
dma-names = "rx", "tx";
};
ssiu15: ssiu-13 {
- dmas = <&audma0 0xC3>, <&audma1 0xC4>;
+ dmas = <&audma0 0xc3>, <&audma1 0xc4>;
dma-names = "rx", "tx";
};
ssiu16: ssiu-14 {
- dmas = <&audma0 0xC7>, <&audma1 0xC8>;
+ dmas = <&audma0 0xc7>, <&audma1 0xc8>;
dma-names = "rx", "tx";
};
ssiu17: ssiu-15 {
- dmas = <&audma0 0xCB>, <&audma1 0xCC>;
+ dmas = <&audma0 0xcb>, <&audma1 0xcc>;
dma-names = "rx", "tx";
};
ssiu20: ssiu-16 {
dma-names = "rx", "tx";
};
ssiu22: ssiu-18 {
- dmas = <&audma0 0x6B>, <&audma1 0x6C>;
+ dmas = <&audma0 0x6b>, <&audma1 0x6c>;
dma-names = "rx", "tx";
};
ssiu23: ssiu-19 {
- dmas = <&audma0 0x6D>, <&audma1 0x6E>;
+ dmas = <&audma0 0x6d>, <&audma1 0x6e>;
dma-names = "rx", "tx";
};
ssiu24: ssiu-20 {
- dmas = <&audma0 0xCF>, <&audma1 0xCE>;
+ dmas = <&audma0 0xcf>, <&audma1 0xce>;
dma-names = "rx", "tx";
};
ssiu25: ssiu-21 {
- dmas = <&audma0 0xEB>, <&audma1 0xEC>;
+ dmas = <&audma0 0xeb>, <&audma1 0xec>;
dma-names = "rx", "tx";
};
ssiu26: ssiu-22 {
- dmas = <&audma0 0xED>, <&audma1 0xEE>;
+ dmas = <&audma0 0xed>, <&audma1 0xee>;
dma-names = "rx", "tx";
};
ssiu27: ssiu-23 {
- dmas = <&audma0 0xEF>, <&audma1 0xF0>;
+ dmas = <&audma0 0xef>, <&audma1 0xf0>;
dma-names = "rx", "tx";
};
ssiu30: ssiu-24 {
dma-names = "rx", "tx";
};
ssiu35: ssiu-29 {
- dmas = <&audma0 0x29>, <&audma1 0x2A>;
+ dmas = <&audma0 0x29>, <&audma1 0x2a>;
dma-names = "rx", "tx";
};
ssiu36: ssiu-30 {
- dmas = <&audma0 0x2B>, <&audma1 0x2C>;
+ dmas = <&audma0 0x2b>, <&audma1 0x2c>;
dma-names = "rx", "tx";
};
ssiu37: ssiu-31 {
- dmas = <&audma0 0x2D>, <&audma1 0x2E>;
+ dmas = <&audma0 0x2d>, <&audma1 0x2e>;
dma-names = "rx", "tx";
};
ssiu40: ssiu-32 {
dma-names = "rx", "tx";
};
ssiu42: ssiu-34 {
- dmas = <&audma0 0x19>, <&audma1 0x1A>;
+ dmas = <&audma0 0x19>, <&audma1 0x1a>;
dma-names = "rx", "tx";
};
ssiu43: ssiu-35 {
- dmas = <&audma0 0x1B>, <&audma1 0x1C>;
+ dmas = <&audma0 0x1b>, <&audma1 0x1c>;
dma-names = "rx", "tx";
};
ssiu44: ssiu-36 {
- dmas = <&audma0 0x1D>, <&audma1 0x1E>;
+ dmas = <&audma0 0x1d>, <&audma1 0x1e>;
dma-names = "rx", "tx";
};
ssiu45: ssiu-37 {
- dmas = <&audma0 0x1F>, <&audma1 0x20>;
+ dmas = <&audma0 0x1f>, <&audma1 0x20>;
dma-names = "rx", "tx";
};
ssiu46: ssiu-38 {
dma-names = "rx", "tx";
};
ssiu91: ssiu-45 {
- dmas = <&audma0 0x7F>, <&audma1 0x80>;
+ dmas = <&audma0 0x7f>, <&audma1 0x80>;
dma-names = "rx", "tx";
};
ssiu92: ssiu-46 {
dma-names = "rx", "tx";
};
ssiu94: ssiu-48 {
- dmas = <&audma0 0xA3>, <&audma1 0xA4>;
+ dmas = <&audma0 0xa3>, <&audma1 0xa4>;
dma-names = "rx", "tx";
};
ssiu95: ssiu-49 {
- dmas = <&audma0 0xA5>, <&audma1 0xA6>;
+ dmas = <&audma0 0xa5>, <&audma1 0xa6>;
dma-names = "rx", "tx";
};
ssiu96: ssiu-50 {
- dmas = <&audma0 0xA7>, <&audma1 0xA8>;
+ dmas = <&audma0 0xa7>, <&audma1 0xa8>;
dma-names = "rx", "tx";
};
ssiu97: ssiu-51 {
- dmas = <&audma0 0xA9>, <&audma1 0xAA>;
+ dmas = <&audma0 0xa9>, <&audma1 0xaa>;
dma-names = "rx", "tx";
};
};
dma-names = "rx", "tx";
};
ssiu04: ssiu-4 {
- dmas = <&audma0 0x3F>, <&audma1 0x40>;
+ dmas = <&audma0 0x3f>, <&audma1 0x40>;
dma-names = "rx", "tx";
};
ssiu05: ssiu-5 {
dma-names = "rx", "tx";
};
ssiu06: ssiu-6 {
- dmas = <&audma0 0x4F>, <&audma1 0x50>;
+ dmas = <&audma0 0x4f>, <&audma1 0x50>;
dma-names = "rx", "tx";
};
ssiu07: ssiu-7 {
dma-names = "rx", "tx";
};
ssiu11: ssiu-9 {
- dmas = <&audma0 0x4B>, <&audma1 0x4C>;
+ dmas = <&audma0 0x4b>, <&audma1 0x4c>;
dma-names = "rx", "tx";
};
ssiu12: ssiu-10 {
dma-names = "rx", "tx";
};
ssiu13: ssiu-11 {
- dmas = <&audma0 0x59>, <&audma1 0x5A>;
+ dmas = <&audma0 0x59>, <&audma1 0x5a>;
dma-names = "rx", "tx";
};
ssiu14: ssiu-12 {
- dmas = <&audma0 0x5F>, <&audma1 0x60>;
+ dmas = <&audma0 0x5f>, <&audma1 0x60>;
dma-names = "rx", "tx";
};
ssiu15: ssiu-13 {
- dmas = <&audma0 0xC3>, <&audma1 0xC4>;
+ dmas = <&audma0 0xc3>, <&audma1 0xc4>;
dma-names = "rx", "tx";
};
ssiu16: ssiu-14 {
- dmas = <&audma0 0xC7>, <&audma1 0xC8>;
+ dmas = <&audma0 0xc7>, <&audma1 0xc8>;
dma-names = "rx", "tx";
};
ssiu17: ssiu-15 {
- dmas = <&audma0 0xCB>, <&audma1 0xCC>;
+ dmas = <&audma0 0xcb>, <&audma1 0xcc>;
dma-names = "rx", "tx";
};
ssiu20: ssiu-16 {
dma-names = "rx", "tx";
};
ssiu22: ssiu-18 {
- dmas = <&audma0 0x6B>, <&audma1 0x6C>;
+ dmas = <&audma0 0x6b>, <&audma1 0x6c>;
dma-names = "rx", "tx";
};
ssiu23: ssiu-19 {
- dmas = <&audma0 0x6D>, <&audma1 0x6E>;
+ dmas = <&audma0 0x6d>, <&audma1 0x6e>;
dma-names = "rx", "tx";
};
ssiu24: ssiu-20 {
- dmas = <&audma0 0xCF>, <&audma1 0xCE>;
+ dmas = <&audma0 0xcf>, <&audma1 0xce>;
dma-names = "rx", "tx";
};
ssiu25: ssiu-21 {
- dmas = <&audma0 0xEB>, <&audma1 0xEC>;
+ dmas = <&audma0 0xeb>, <&audma1 0xec>;
dma-names = "rx", "tx";
};
ssiu26: ssiu-22 {
- dmas = <&audma0 0xED>, <&audma1 0xEE>;
+ dmas = <&audma0 0xed>, <&audma1 0xee>;
dma-names = "rx", "tx";
};
ssiu27: ssiu-23 {
- dmas = <&audma0 0xEF>, <&audma1 0xF0>;
+ dmas = <&audma0 0xef>, <&audma1 0xf0>;
dma-names = "rx", "tx";
};
ssiu30: ssiu-24 {
dma-names = "rx", "tx";
};
ssiu35: ssiu-29 {
- dmas = <&audma0 0x29>, <&audma1 0x2A>;
+ dmas = <&audma0 0x29>, <&audma1 0x2a>;
dma-names = "rx", "tx";
};
ssiu36: ssiu-30 {
- dmas = <&audma0 0x2B>, <&audma1 0x2C>;
+ dmas = <&audma0 0x2b>, <&audma1 0x2c>;
dma-names = "rx", "tx";
};
ssiu37: ssiu-31 {
- dmas = <&audma0 0x2D>, <&audma1 0x2E>;
+ dmas = <&audma0 0x2d>, <&audma1 0x2e>;
dma-names = "rx", "tx";
};
ssiu40: ssiu-32 {
dma-names = "rx", "tx";
};
ssiu42: ssiu-34 {
- dmas = <&audma0 0x19>, <&audma1 0x1A>;
+ dmas = <&audma0 0x19>, <&audma1 0x1a>;
dma-names = "rx", "tx";
};
ssiu43: ssiu-35 {
- dmas = <&audma0 0x1B>, <&audma1 0x1C>;
+ dmas = <&audma0 0x1b>, <&audma1 0x1c>;
dma-names = "rx", "tx";
};
ssiu44: ssiu-36 {
- dmas = <&audma0 0x1D>, <&audma1 0x1E>;
+ dmas = <&audma0 0x1d>, <&audma1 0x1e>;
dma-names = "rx", "tx";
};
ssiu45: ssiu-37 {
- dmas = <&audma0 0x1F>, <&audma1 0x20>;
+ dmas = <&audma0 0x1f>, <&audma1 0x20>;
dma-names = "rx", "tx";
};
ssiu46: ssiu-38 {
dma-names = "rx", "tx";
};
ssiu91: ssiu-45 {
- dmas = <&audma0 0x7F>, <&audma1 0x80>;
+ dmas = <&audma0 0x7f>, <&audma1 0x80>;
dma-names = "rx", "tx";
};
ssiu92: ssiu-46 {
dma-names = "rx", "tx";
};
ssiu94: ssiu-48 {
- dmas = <&audma0 0xA3>, <&audma1 0xA4>;
+ dmas = <&audma0 0xa3>, <&audma1 0xa4>;
dma-names = "rx", "tx";
};
ssiu95: ssiu-49 {
- dmas = <&audma0 0xA5>, <&audma1 0xA6>;
+ dmas = <&audma0 0xa5>, <&audma1 0xa6>;
dma-names = "rx", "tx";
};
ssiu96: ssiu-50 {
- dmas = <&audma0 0xA7>, <&audma1 0xA8>;
+ dmas = <&audma0 0xa7>, <&audma1 0xa8>;
dma-names = "rx", "tx";
};
ssiu97: ssiu-51 {
- dmas = <&audma0 0xA9>, <&audma1 0xAA>;
+ dmas = <&audma0 0xa9>, <&audma1 0xaa>;
dma-names = "rx", "tx";
};
};
dma-names = "rx", "tx";
};
ssiu04: ssiu-4 {
- dmas = <&audma0 0x3F>, <&audma1 0x40>;
+ dmas = <&audma0 0x3f>, <&audma1 0x40>;
dma-names = "rx", "tx";
};
ssiu05: ssiu-5 {
dma-names = "rx", "tx";
};
ssiu06: ssiu-6 {
- dmas = <&audma0 0x4F>, <&audma1 0x50>;
+ dmas = <&audma0 0x4f>, <&audma1 0x50>;
dma-names = "rx", "tx";
};
ssiu07: ssiu-7 {
dma-names = "rx", "tx";
};
ssiu11: ssiu-9 {
- dmas = <&audma0 0x4B>, <&audma1 0x4C>;
+ dmas = <&audma0 0x4b>, <&audma1 0x4c>;
dma-names = "rx", "tx";
};
ssiu12: ssiu-10 {
dma-names = "rx", "tx";
};
ssiu13: ssiu-11 {
- dmas = <&audma0 0x59>, <&audma1 0x5A>;
+ dmas = <&audma0 0x59>, <&audma1 0x5a>;
dma-names = "rx", "tx";
};
ssiu14: ssiu-12 {
- dmas = <&audma0 0x5F>, <&audma1 0x60>;
+ dmas = <&audma0 0x5f>, <&audma1 0x60>;
dma-names = "rx", "tx";
};
ssiu15: ssiu-13 {
- dmas = <&audma0 0xC3>, <&audma1 0xC4>;
+ dmas = <&audma0 0xc3>, <&audma1 0xc4>;
dma-names = "rx", "tx";
};
ssiu16: ssiu-14 {
- dmas = <&audma0 0xC7>, <&audma1 0xC8>;
+ dmas = <&audma0 0xc7>, <&audma1 0xc8>;
dma-names = "rx", "tx";
};
ssiu17: ssiu-15 {
- dmas = <&audma0 0xCB>, <&audma1 0xCC>;
+ dmas = <&audma0 0xcb>, <&audma1 0xcc>;
dma-names = "rx", "tx";
};
ssiu20: ssiu-16 {
dma-names = "rx", "tx";
};
ssiu22: ssiu-18 {
- dmas = <&audma0 0x6B>, <&audma1 0x6C>;
+ dmas = <&audma0 0x6b>, <&audma1 0x6c>;
dma-names = "rx", "tx";
};
ssiu23: ssiu-19 {
- dmas = <&audma0 0x6D>, <&audma1 0x6E>;
+ dmas = <&audma0 0x6d>, <&audma1 0x6e>;
dma-names = "rx", "tx";
};
ssiu24: ssiu-20 {
- dmas = <&audma0 0xCF>, <&audma1 0xCE>;
+ dmas = <&audma0 0xcf>, <&audma1 0xce>;
dma-names = "rx", "tx";
};
ssiu25: ssiu-21 {
- dmas = <&audma0 0xEB>, <&audma1 0xEC>;
+ dmas = <&audma0 0xeb>, <&audma1 0xec>;
dma-names = "rx", "tx";
};
ssiu26: ssiu-22 {
- dmas = <&audma0 0xED>, <&audma1 0xEE>;
+ dmas = <&audma0 0xed>, <&audma1 0xee>;
dma-names = "rx", "tx";
};
ssiu27: ssiu-23 {
- dmas = <&audma0 0xEF>, <&audma1 0xF0>;
+ dmas = <&audma0 0xef>, <&audma1 0xf0>;
dma-names = "rx", "tx";
};
ssiu30: ssiu-24 {
dma-names = "rx", "tx";
};
ssiu35: ssiu-29 {
- dmas = <&audma0 0x29>, <&audma1 0x2A>;
+ dmas = <&audma0 0x29>, <&audma1 0x2a>;
dma-names = "rx", "tx";
};
ssiu36: ssiu-30 {
- dmas = <&audma0 0x2B>, <&audma1 0x2C>;
+ dmas = <&audma0 0x2b>, <&audma1 0x2c>;
dma-names = "rx", "tx";
};
ssiu37: ssiu-31 {
- dmas = <&audma0 0x2D>, <&audma1 0x2E>;
+ dmas = <&audma0 0x2d>, <&audma1 0x2e>;
dma-names = "rx", "tx";
};
ssiu40: ssiu-32 {
dma-names = "rx", "tx";
};
ssiu42: ssiu-34 {
- dmas = <&audma0 0x19>, <&audma1 0x1A>;
+ dmas = <&audma0 0x19>, <&audma1 0x1a>;
dma-names = "rx", "tx";
};
ssiu43: ssiu-35 {
- dmas = <&audma0 0x1B>, <&audma1 0x1C>;
+ dmas = <&audma0 0x1b>, <&audma1 0x1c>;
dma-names = "rx", "tx";
};
ssiu44: ssiu-36 {
- dmas = <&audma0 0x1D>, <&audma1 0x1E>;
+ dmas = <&audma0 0x1d>, <&audma1 0x1e>;
dma-names = "rx", "tx";
};
ssiu45: ssiu-37 {
- dmas = <&audma0 0x1F>, <&audma1 0x20>;
+ dmas = <&audma0 0x1f>, <&audma1 0x20>;
dma-names = "rx", "tx";
};
ssiu46: ssiu-38 {
dma-names = "rx", "tx";
};
ssiu91: ssiu-45 {
- dmas = <&audma0 0x7F>, <&audma1 0x80>;
+ dmas = <&audma0 0x7f>, <&audma1 0x80>;
dma-names = "rx", "tx";
};
ssiu92: ssiu-46 {
dma-names = "rx", "tx";
};
ssiu94: ssiu-48 {
- dmas = <&audma0 0xA3>, <&audma1 0xA4>;
+ dmas = <&audma0 0xa3>, <&audma1 0xa4>;
dma-names = "rx", "tx";
};
ssiu95: ssiu-49 {
- dmas = <&audma0 0xA5>, <&audma1 0xA6>;
+ dmas = <&audma0 0xa5>, <&audma1 0xa6>;
dma-names = "rx", "tx";
};
ssiu96: ssiu-50 {
- dmas = <&audma0 0xA7>, <&audma1 0xA8>;
+ dmas = <&audma0 0xa7>, <&audma1 0xa8>;
dma-names = "rx", "tx";
};
ssiu97: ssiu-51 {
- dmas = <&audma0 0xA9>, <&audma1 0xAA>;
+ dmas = <&audma0 0xa9>, <&audma1 0xaa>;
dma-names = "rx", "tx";
};
};
dma-names = "rx", "tx";
};
ssiu04: ssiu-4 {
- dmas = <&audma0 0x3F>, <&audma1 0x40>;
+ dmas = <&audma0 0x3f>, <&audma1 0x40>;
dma-names = "rx", "tx";
};
ssiu05: ssiu-5 {
dma-names = "rx", "tx";
};
ssiu06: ssiu-6 {
- dmas = <&audma0 0x4F>, <&audma1 0x50>;
+ dmas = <&audma0 0x4f>, <&audma1 0x50>;
dma-names = "rx", "tx";
};
ssiu07: ssiu-7 {
dma-names = "rx", "tx";
};
ssiu11: ssiu-9 {
- dmas = <&audma0 0x4B>, <&audma1 0x4C>;
+ dmas = <&audma0 0x4b>, <&audma1 0x4c>;
dma-names = "rx", "tx";
};
ssiu12: ssiu-10 {
dma-names = "rx", "tx";
};
ssiu13: ssiu-11 {
- dmas = <&audma0 0x59>, <&audma1 0x5A>;
+ dmas = <&audma0 0x59>, <&audma1 0x5a>;
dma-names = "rx", "tx";
};
ssiu14: ssiu-12 {
- dmas = <&audma0 0x5F>, <&audma1 0x60>;
+ dmas = <&audma0 0x5f>, <&audma1 0x60>;
dma-names = "rx", "tx";
};
ssiu15: ssiu-13 {
- dmas = <&audma0 0xC3>, <&audma1 0xC4>;
+ dmas = <&audma0 0xc3>, <&audma1 0xc4>;
dma-names = "rx", "tx";
};
ssiu16: ssiu-14 {
- dmas = <&audma0 0xC7>, <&audma1 0xC8>;
+ dmas = <&audma0 0xc7>, <&audma1 0xc8>;
dma-names = "rx", "tx";
};
ssiu17: ssiu-15 {
- dmas = <&audma0 0xCB>, <&audma1 0xCC>;
+ dmas = <&audma0 0xcb>, <&audma1 0xcc>;
dma-names = "rx", "tx";
};
ssiu20: ssiu-16 {
dma-names = "rx", "tx";
};
ssiu22: ssiu-18 {
- dmas = <&audma0 0x6B>, <&audma1 0x6C>;
+ dmas = <&audma0 0x6b>, <&audma1 0x6c>;
dma-names = "rx", "tx";
};
ssiu23: ssiu-19 {
- dmas = <&audma0 0x6D>, <&audma1 0x6E>;
+ dmas = <&audma0 0x6d>, <&audma1 0x6e>;
dma-names = "rx", "tx";
};
ssiu24: ssiu-20 {
- dmas = <&audma0 0xCF>, <&audma1 0xCE>;
+ dmas = <&audma0 0xcf>, <&audma1 0xce>;
dma-names = "rx", "tx";
};
ssiu25: ssiu-21 {
- dmas = <&audma0 0xEB>, <&audma1 0xEC>;
+ dmas = <&audma0 0xeb>, <&audma1 0xec>;
dma-names = "rx", "tx";
};
ssiu26: ssiu-22 {
- dmas = <&audma0 0xED>, <&audma1 0xEE>;
+ dmas = <&audma0 0xed>, <&audma1 0xee>;
dma-names = "rx", "tx";
};
ssiu27: ssiu-23 {
- dmas = <&audma0 0xEF>, <&audma1 0xF0>;
+ dmas = <&audma0 0xef>, <&audma1 0xf0>;
dma-names = "rx", "tx";
};
ssiu30: ssiu-24 {
dma-names = "rx", "tx";
};
ssiu35: ssiu-29 {
- dmas = <&audma0 0x29>, <&audma1 0x2A>;
+ dmas = <&audma0 0x29>, <&audma1 0x2a>;
dma-names = "rx", "tx";
};
ssiu36: ssiu-30 {
- dmas = <&audma0 0x2B>, <&audma1 0x2C>;
+ dmas = <&audma0 0x2b>, <&audma1 0x2c>;
dma-names = "rx", "tx";
};
ssiu37: ssiu-31 {
- dmas = <&audma0 0x2D>, <&audma1 0x2E>;
+ dmas = <&audma0 0x2d>, <&audma1 0x2e>;
dma-names = "rx", "tx";
};
ssiu40: ssiu-32 {
dma-names = "rx", "tx";
};
ssiu42: ssiu-34 {
- dmas = <&audma0 0x19>, <&audma1 0x1A>;
+ dmas = <&audma0 0x19>, <&audma1 0x1a>;
dma-names = "rx", "tx";
};
ssiu43: ssiu-35 {
- dmas = <&audma0 0x1B>, <&audma1 0x1C>;
+ dmas = <&audma0 0x1b>, <&audma1 0x1c>;
dma-names = "rx", "tx";
};
ssiu44: ssiu-36 {
- dmas = <&audma0 0x1D>, <&audma1 0x1E>;
+ dmas = <&audma0 0x1d>, <&audma1 0x1e>;
dma-names = "rx", "tx";
};
ssiu45: ssiu-37 {
- dmas = <&audma0 0x1F>, <&audma1 0x20>;
+ dmas = <&audma0 0x1f>, <&audma1 0x20>;
dma-names = "rx", "tx";
};
ssiu46: ssiu-38 {
dma-names = "rx", "tx";
};
ssiu91: ssiu-45 {
- dmas = <&audma0 0x7F>, <&audma1 0x80>;
+ dmas = <&audma0 0x7f>, <&audma1 0x80>;
dma-names = "rx", "tx";
};
ssiu92: ssiu-46 {
dma-names = "rx", "tx";
};
ssiu94: ssiu-48 {
- dmas = <&audma0 0xA3>, <&audma1 0xA4>;
+ dmas = <&audma0 0xa3>, <&audma1 0xa4>;
dma-names = "rx", "tx";
};
ssiu95: ssiu-49 {
- dmas = <&audma0 0xA5>, <&audma1 0xA6>;
+ dmas = <&audma0 0xa5>, <&audma1 0xa6>;
dma-names = "rx", "tx";
};
ssiu96: ssiu-50 {
- dmas = <&audma0 0xA7>, <&audma1 0xA8>;
+ dmas = <&audma0 0xa7>, <&audma1 0xa8>;
dma-names = "rx", "tx";
};
ssiu97: ssiu-51 {
- dmas = <&audma0 0xA9>, <&audma1 0xAA>;
+ dmas = <&audma0 0xa9>, <&audma1 0xaa>;
dma-names = "rx", "tx";
};
};
dma-names = "rx", "tx";
};
ssiu04: ssiu-4 {
- dmas = <&audma0 0x3F>, <&audma1 0x40>;
+ dmas = <&audma0 0x3f>, <&audma1 0x40>;
dma-names = "rx", "tx";
};
ssiu05: ssiu-5 {
dma-names = "rx", "tx";
};
ssiu06: ssiu-6 {
- dmas = <&audma0 0x4F>, <&audma1 0x50>;
+ dmas = <&audma0 0x4f>, <&audma1 0x50>;
dma-names = "rx", "tx";
};
ssiu07: ssiu-7 {
dma-names = "rx", "tx";
};
ssiu11: ssiu-9 {
- dmas = <&audma0 0x4B>, <&audma1 0x4C>;
+ dmas = <&audma0 0x4b>, <&audma1 0x4c>;
dma-names = "rx", "tx";
};
ssiu12: ssiu-10 {
dma-names = "rx", "tx";
};
ssiu13: ssiu-11 {
- dmas = <&audma0 0x59>, <&audma1 0x5A>;
+ dmas = <&audma0 0x59>, <&audma1 0x5a>;
dma-names = "rx", "tx";
};
ssiu14: ssiu-12 {
- dmas = <&audma0 0x5F>, <&audma1 0x60>;
+ dmas = <&audma0 0x5f>, <&audma1 0x60>;
dma-names = "rx", "tx";
};
ssiu15: ssiu-13 {
- dmas = <&audma0 0xC3>, <&audma1 0xC4>;
+ dmas = <&audma0 0xc3>, <&audma1 0xc4>;
dma-names = "rx", "tx";
};
ssiu16: ssiu-14 {
- dmas = <&audma0 0xC7>, <&audma1 0xC8>;
+ dmas = <&audma0 0xc7>, <&audma1 0xc8>;
dma-names = "rx", "tx";
};
ssiu17: ssiu-15 {
- dmas = <&audma0 0xCB>, <&audma1 0xCC>;
+ dmas = <&audma0 0xcb>, <&audma1 0xcc>;
dma-names = "rx", "tx";
};
ssiu20: ssiu-16 {
dma-names = "rx", "tx";
};
ssiu22: ssiu-18 {
- dmas = <&audma0 0x6B>, <&audma1 0x6C>;
+ dmas = <&audma0 0x6b>, <&audma1 0x6c>;
dma-names = "rx", "tx";
};
ssiu23: ssiu-19 {
- dmas = <&audma0 0x6D>, <&audma1 0x6E>;
+ dmas = <&audma0 0x6d>, <&audma1 0x6e>;
dma-names = "rx", "tx";
};
ssiu24: ssiu-20 {
- dmas = <&audma0 0xCF>, <&audma1 0xCE>;
+ dmas = <&audma0 0xcf>, <&audma1 0xce>;
dma-names = "rx", "tx";
};
ssiu25: ssiu-21 {
- dmas = <&audma0 0xEB>, <&audma1 0xEC>;
+ dmas = <&audma0 0xeb>, <&audma1 0xec>;
dma-names = "rx", "tx";
};
ssiu26: ssiu-22 {
- dmas = <&audma0 0xED>, <&audma1 0xEE>;
+ dmas = <&audma0 0xed>, <&audma1 0xee>;
dma-names = "rx", "tx";
};
ssiu27: ssiu-23 {
- dmas = <&audma0 0xEF>, <&audma1 0xF0>;
+ dmas = <&audma0 0xef>, <&audma1 0xf0>;
dma-names = "rx", "tx";
};
ssiu30: ssiu-24 {
dma-names = "rx", "tx";
};
ssiu35: ssiu-29 {
- dmas = <&audma0 0x29>, <&audma1 0x2A>;
+ dmas = <&audma0 0x29>, <&audma1 0x2a>;
dma-names = "rx", "tx";
};
ssiu36: ssiu-30 {
- dmas = <&audma0 0x2B>, <&audma1 0x2C>;
+ dmas = <&audma0 0x2b>, <&audma1 0x2c>;
dma-names = "rx", "tx";
};
ssiu37: ssiu-31 {
- dmas = <&audma0 0x2D>, <&audma1 0x2E>;
+ dmas = <&audma0 0x2d>, <&audma1 0x2e>;
dma-names = "rx", "tx";
};
ssiu40: ssiu-32 {
dma-names = "rx", "tx";
};
ssiu42: ssiu-34 {
- dmas = <&audma0 0x19>, <&audma1 0x1A>;
+ dmas = <&audma0 0x19>, <&audma1 0x1a>;
dma-names = "rx", "tx";
};
ssiu43: ssiu-35 {
- dmas = <&audma0 0x1B>, <&audma1 0x1C>;
+ dmas = <&audma0 0x1b>, <&audma1 0x1c>;
dma-names = "rx", "tx";
};
ssiu44: ssiu-36 {
- dmas = <&audma0 0x1D>, <&audma1 0x1E>;
+ dmas = <&audma0 0x1d>, <&audma1 0x1e>;
dma-names = "rx", "tx";
};
ssiu45: ssiu-37 {
- dmas = <&audma0 0x1F>, <&audma1 0x20>;
+ dmas = <&audma0 0x1f>, <&audma1 0x20>;
dma-names = "rx", "tx";
};
ssiu46: ssiu-38 {
dma-names = "rx", "tx";
};
ssiu91: ssiu-45 {
- dmas = <&audma0 0x7F>, <&audma1 0x80>;
+ dmas = <&audma0 0x7f>, <&audma1 0x80>;
dma-names = "rx", "tx";
};
ssiu92: ssiu-46 {
dma-names = "rx", "tx";
};
ssiu94: ssiu-48 {
- dmas = <&audma0 0xA3>, <&audma1 0xA4>;
+ dmas = <&audma0 0xa3>, <&audma1 0xa4>;
dma-names = "rx", "tx";
};
ssiu95: ssiu-49 {
- dmas = <&audma0 0xA5>, <&audma1 0xA6>;
+ dmas = <&audma0 0xa5>, <&audma1 0xa6>;
dma-names = "rx", "tx";
};
ssiu96: ssiu-50 {
- dmas = <&audma0 0xA7>, <&audma1 0xA8>;
+ dmas = <&audma0 0xa7>, <&audma1 0xa8>;
dma-names = "rx", "tx";
};
ssiu97: ssiu-51 {
- dmas = <&audma0 0xA9>, <&audma1 0xAA>;
+ dmas = <&audma0 0xa9>, <&audma1 0xaa>;
dma-names = "rx", "tx";
};
};
dma-names = "rx", "tx";
};
ssiu04: ssiu-4 {
- dmas = <&audma0 0x3F>, <&audma1 0x40>;
+ dmas = <&audma0 0x3f>, <&audma1 0x40>;
dma-names = "rx", "tx";
};
ssiu05: ssiu-5 {
dma-names = "rx", "tx";
};
ssiu06: ssiu-6 {
- dmas = <&audma0 0x4F>, <&audma1 0x50>;
+ dmas = <&audma0 0x4f>, <&audma1 0x50>;
dma-names = "rx", "tx";
};
ssiu07: ssiu-7 {
dma-names = "rx", "tx";
};
ssiu11: ssiu-9 {
- dmas = <&audma0 0x4B>, <&audma1 0x4C>;
+ dmas = <&audma0 0x4b>, <&audma1 0x4c>;
dma-names = "rx", "tx";
};
ssiu12: ssiu-10 {
dma-names = "rx", "tx";
};
ssiu13: ssiu-11 {
- dmas = <&audma0 0x59>, <&audma1 0x5A>;
+ dmas = <&audma0 0x59>, <&audma1 0x5a>;
dma-names = "rx", "tx";
};
ssiu14: ssiu-12 {
- dmas = <&audma0 0x5F>, <&audma1 0x60>;
+ dmas = <&audma0 0x5f>, <&audma1 0x60>;
dma-names = "rx", "tx";
};
ssiu15: ssiu-13 {
- dmas = <&audma0 0xC3>, <&audma1 0xC4>;
+ dmas = <&audma0 0xc3>, <&audma1 0xc4>;
dma-names = "rx", "tx";
};
ssiu16: ssiu-14 {
- dmas = <&audma0 0xC7>, <&audma1 0xC8>;
+ dmas = <&audma0 0xc7>, <&audma1 0xc8>;
dma-names = "rx", "tx";
};
ssiu17: ssiu-15 {
- dmas = <&audma0 0xCB>, <&audma1 0xCC>;
+ dmas = <&audma0 0xcb>, <&audma1 0xcc>;
dma-names = "rx", "tx";
};
ssiu20: ssiu-16 {
dma-names = "rx", "tx";
};
ssiu22: ssiu-18 {
- dmas = <&audma0 0x6B>, <&audma1 0x6C>;
+ dmas = <&audma0 0x6b>, <&audma1 0x6c>;
dma-names = "rx", "tx";
};
ssiu23: ssiu-19 {
- dmas = <&audma0 0x6D>, <&audma1 0x6E>;
+ dmas = <&audma0 0x6d>, <&audma1 0x6e>;
dma-names = "rx", "tx";
};
ssiu24: ssiu-20 {
- dmas = <&audma0 0xCF>, <&audma1 0xCE>;
+ dmas = <&audma0 0xcf>, <&audma1 0xce>;
dma-names = "rx", "tx";
};
ssiu25: ssiu-21 {
- dmas = <&audma0 0xEB>, <&audma1 0xEC>;
+ dmas = <&audma0 0xeb>, <&audma1 0xec>;
dma-names = "rx", "tx";
};
ssiu26: ssiu-22 {
- dmas = <&audma0 0xED>, <&audma1 0xEE>;
+ dmas = <&audma0 0xed>, <&audma1 0xee>;
dma-names = "rx", "tx";
};
ssiu27: ssiu-23 {
- dmas = <&audma0 0xEF>, <&audma1 0xF0>;
+ dmas = <&audma0 0xef>, <&audma1 0xf0>;
dma-names = "rx", "tx";
};
ssiu30: ssiu-24 {
dma-names = "rx", "tx";
};
ssiu35: ssiu-29 {
- dmas = <&audma0 0x29>, <&audma1 0x2A>;
+ dmas = <&audma0 0x29>, <&audma1 0x2a>;
dma-names = "rx", "tx";
};
ssiu36: ssiu-30 {
- dmas = <&audma0 0x2B>, <&audma1 0x2C>;
+ dmas = <&audma0 0x2b>, <&audma1 0x2c>;
dma-names = "rx", "tx";
};
ssiu37: ssiu-31 {
- dmas = <&audma0 0x2D>, <&audma1 0x2E>;
+ dmas = <&audma0 0x2d>, <&audma1 0x2e>;
dma-names = "rx", "tx";
};
ssiu40: ssiu-32 {
dma-names = "rx", "tx";
};
ssiu42: ssiu-34 {
- dmas = <&audma0 0x19>, <&audma1 0x1A>;
+ dmas = <&audma0 0x19>, <&audma1 0x1a>;
dma-names = "rx", "tx";
};
ssiu43: ssiu-35 {
- dmas = <&audma0 0x1B>, <&audma1 0x1C>;
+ dmas = <&audma0 0x1b>, <&audma1 0x1c>;
dma-names = "rx", "tx";
};
ssiu44: ssiu-36 {
- dmas = <&audma0 0x1D>, <&audma1 0x1E>;
+ dmas = <&audma0 0x1d>, <&audma1 0x1e>;
dma-names = "rx", "tx";
};
ssiu45: ssiu-37 {
- dmas = <&audma0 0x1F>, <&audma1 0x20>;
+ dmas = <&audma0 0x1f>, <&audma1 0x20>;
dma-names = "rx", "tx";
};
ssiu46: ssiu-38 {
dma-names = "rx", "tx";
};
ssiu91: ssiu-45 {
- dmas = <&audma0 0x7F>, <&audma1 0x80>;
+ dmas = <&audma0 0x7f>, <&audma1 0x80>;
dma-names = "rx", "tx";
};
ssiu92: ssiu-46 {
dma-names = "rx", "tx";
};
ssiu94: ssiu-48 {
- dmas = <&audma0 0xA3>, <&audma1 0xA4>;
+ dmas = <&audma0 0xa3>, <&audma1 0xa4>;
dma-names = "rx", "tx";
};
ssiu95: ssiu-49 {
- dmas = <&audma0 0xA5>, <&audma1 0xA6>;
+ dmas = <&audma0 0xa5>, <&audma1 0xa6>;
dma-names = "rx", "tx";
};
ssiu96: ssiu-50 {
- dmas = <&audma0 0xA7>, <&audma1 0xA8>;
+ dmas = <&audma0 0xa7>, <&audma1 0xa8>;
dma-names = "rx", "tx";
};
ssiu97: ssiu-51 {
- dmas = <&audma0 0xA9>, <&audma1 0xAA>;
+ dmas = <&audma0 0xa9>, <&audma1 0xaa>;
dma-names = "rx", "tx";
};
};
reg = <0x00040000 0x080000>;
read-only;
};
- cert_header_sa3@c0000 {
+ cert-header-sa3@c0000 {
reg = <0x000c0000 0x080000>;
read-only;
};
reg = <0x00140000 0x040000>;
read-only;
};
- cert_header_sa6@180000 {
+ cert-header-sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
reg = <0x00040000 0x080000>;
read-only;
};
- cert_header_sa3@c0000 {
+ cert-header-sa3@c0000 {
reg = <0x000c0000 0x080000>;
read-only;
};
reg = <0x00140000 0x040000>;
read-only;
};
- cert_header_sa6@180000 {
+ cert-header-sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
};
};
+ wwdt0: watchdog@ffc90000 {
+ compatible = "renesas,r8a77970-wwdt",
+ "renesas,rcar-gen3-wwdt";
+ reg = <0 0xffc90000 0 0x10>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A77970_CLK_R>,
+ <&cpg CPG_CORE R8A77970_CLK_CP>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 325>;
+ reset-names = "cnt";
+ status = "disabled";
+ };
+
+ wwdt1: watchdog@ffca0000 {
+ compatible = "renesas,r8a77970-wwdt",
+ "renesas,rcar-gen3-wwdt";
+ reg = <0 0xffca0000 0 0x10>;
+ interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A77970_CLK_R>,
+ <&cpg CPG_CORE R8A77970_CLK_CP>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 324>;
+ reset-names = "cnt";
+ status = "disabled";
+ };
+
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
reg = <0x00040000 0x080000>;
read-only;
};
- cert_header_sa3@c0000 {
+ cert-header-sa3@c0000 {
reg = <0x000c0000 0x080000>;
read-only;
};
reg = <0x00140000 0x040000>;
read-only;
};
- cert_header_sa6@180000 {
+ cert-header-sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
&scif_clk {
clock-frequency = <14745600>;
};
+
+/* Firmware should reserve it but sadly doesn't */
+&swdt {
+ status = "reserved";
+};
status = "disabled";
};
+ swdt: watchdog@e6030000 {
+ compatible = "renesas,r8a77980-wdt", "renesas,rcar-gen3-wdt";
+ reg = <0 0xe6030000 0 0x0c>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_CORE R8A77980_CLK_OSC>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a77980",
"renesas,rcar-gen3-gpio";
};
};
+ wwdt0: watchdog@ffc90000 {
+ compatible = "renesas,r8a77980-wwdt",
+ "renesas,rcar-gen3-wwdt";
+ reg = <0 0xffc90000 0 0x10>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A77980_CLK_R>,
+ <&cpg CPG_CORE R8A77980_CLK_CP>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 325>;
+ reset-names = "cnt";
+ status = "disabled";
+ };
+
+ wwdt1: watchdog@ffca0000 {
+ compatible = "renesas,r8a77980-wwdt",
+ "renesas,rcar-gen3-wwdt";
+ reg = <0 0xffca0000 0 0x10>;
+ interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A77980_CLK_R>,
+ <&cpg CPG_CORE R8A77980_CLK_CP>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 324>;
+ reset-names = "cnt";
+ status = "disabled";
+ };
+
+ wwdt2: watchdog@ffcb0000 {
+ compatible = "renesas,r8a77980-wwdt",
+ "renesas,rcar-gen3-wwdt";
+ reg = <0 0xffcb0000 0 0x10>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A77980_CLK_R>,
+ <&cpg CPG_CORE R8A77980_CLK_CP>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 321>;
+ reset-names = "cnt";
+ status = "disabled";
+ };
+
+ wwdt3: watchdog@ffcc0000 {
+ compatible = "renesas,r8a77980-wwdt",
+ "renesas,rcar-gen3-wwdt";
+ reg = <0 0xffcc0000 0 0x10>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A77980_CLK_R>,
+ <&cpg CPG_CORE R8A77980_CLK_CP>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 309>;
+ reset-names = "cnt";
+ status = "disabled";
+ };
+
+ wwdt4: watchdog@ffcf0000 {
+ compatible = "renesas,r8a77980-wwdt",
+ "renesas,rcar-gen3-wwdt";
+ reg = <0 0xffcf0000 0 0x10>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A77980_CLK_R>,
+ <&cpg CPG_CORE R8A77980_CLK_CP>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 403>;
+ reset-names = "cnt";
+ status = "disabled";
+ };
+
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
};
};
+ wwdt0: watchdog@ffc90000 {
+ compatible = "renesas,r8a779a0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffc90000 0 0x10>;
+ interrupts = <GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779A0_CLK_R>,
+ <&cpg CPG_CORE R8A779A0_CLK_CP>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 1200>, <&cpg 1318>;
+ reset-names = "cnt", "bus";
+ status = "disabled";
+ };
+
+ wwdt1: watchdog@ffca0000 {
+ compatible = "renesas,r8a779a0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffca0000 0 0x10>;
+ interrupts = <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779A0_CLK_R>,
+ <&cpg CPG_CORE R8A779A0_CLK_CP>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 1201>, <&cpg 1319>;
+ reset-names = "cnt", "bus";
+ status = "disabled";
+ };
+
+ wwdt2: watchdog@ffcb0000 {
+ compatible = "renesas,r8a779a0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffcb0000 0 0x10>;
+ interrupts = <GIC_SPI 484 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779A0_CLK_R>,
+ <&cpg CPG_CORE R8A779A0_CLK_CP>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 1202>, <&cpg 1320>;
+ reset-names = "cnt", "bus";
+ status = "disabled";
+ };
+
+ wwdt3: watchdog@ffcc0000 {
+ compatible = "renesas,r8a779a0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffcc0000 0 0x10>;
+ interrupts = <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779A0_CLK_R>,
+ <&cpg CPG_CORE R8A779A0_CLK_CP>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 1203>, <&cpg 1321>;
+ reset-names = "cnt", "bus";
+ status = "disabled";
+ };
+
+ wwdt4: watchdog@ffcf0000 {
+ compatible = "renesas,r8a779a0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffcf0000 0 0x10>;
+ interrupts = <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779A0_CLK_R>,
+ <&cpg CPG_CORE R8A779A0_CLK_CP>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 1204>, <&cpg 1322>;
+ reset-names = "cnt", "bus";
+ status = "disabled";
+ };
+
+ wwdt5: watchdog@ffef0000 {
+ compatible = "renesas,r8a779a0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffef0000 0 0x10>;
+ interrupts = <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779A0_CLK_R>,
+ <&cpg CPG_CORE R8A779A0_CLK_CP>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 1205>, <&cpg 1323>;
+ reset-names = "cnt", "bus";
+ status = "disabled";
+ };
+
+ wwdt6: watchdog@fff10000 {
+ compatible = "renesas,r8a779a0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xfff10000 0 0x10>;
+ interrupts = <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779A0_CLK_R>,
+ <&cpg CPG_CORE R8A779A0_CLK_CP>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 1206>, <&cpg 1324>;
+ reset-names = "cnt", "bus";
+ status = "disabled";
+ };
+
+ wwdt7: watchdog@fff20000 {
+ compatible = "renesas,r8a779a0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xfff20000 0 0x10>;
+ interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779A0_CLK_R>,
+ <&cpg CPG_CORE R8A779A0_CLK_CP>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 1207>, <&cpg 1325>;
+ reset-names = "cnt", "bus";
+ status = "disabled";
+ };
+
+ wwdt8: watchdog@fff30000 {
+ compatible = "renesas,r8a779a0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xfff30000 0 0x10>;
+ interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779A0_CLK_R>,
+ <&cpg CPG_CORE R8A779A0_CLK_CP>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 1208>, <&cpg 1326>;
+ reset-names = "cnt", "bus";
+ status = "disabled";
+ };
+
+ wwdt9: watchdog@fff40000 {
+ compatible = "renesas,r8a779a0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xfff40000 0 0x10>;
+ interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779A0_CLK_R>,
+ <&cpg CPG_CORE R8A779A0_CLK_CP>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 1209>, <&cpg 1327>;
+ reset-names = "cnt", "bus";
+ status = "disabled";
+ };
+
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
+ wwdt0: watchdog@ffc90000 {
+ compatible = "renesas,r8a779f0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffc90000 0 0x10>;
+ interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779F0_CLK_R>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 1200>, <&cpg 1318>;
+ reset-names = "cnt", "bus";
+ status = "disabled";
+ };
+
+ wwdt1: watchdog@ffca0000 {
+ compatible = "renesas,r8a779f0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffca0000 0 0x10>;
+ interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779F0_CLK_R>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 1201>, <&cpg 1319>;
+ reset-names = "cnt", "bus";
+ status = "disabled";
+ };
+
+ wwdt2: watchdog@ffcb0000 {
+ compatible = "renesas,r8a779f0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffcb0000 0 0x10>;
+ interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779F0_CLK_R>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 1202>, <&cpg 1320>;
+ reset-names = "cnt", "bus";
+ status = "disabled";
+ };
+
+ wwdt3: watchdog@ffcc0000 {
+ compatible = "renesas,r8a779f0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffcc0000 0 0x10>;
+ interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779F0_CLK_R>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 1203>, <&cpg 1321>;
+ reset-names = "cnt", "bus";
+ status = "disabled";
+ };
+
+ wwdt4: watchdog@ffcf0000 {
+ compatible = "renesas,r8a779f0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffcf0000 0 0x10>;
+ interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779F0_CLK_R>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 1204>, <&cpg 1322>;
+ reset-names = "cnt", "bus";
+ status = "disabled";
+ };
+
+ wwdt5: watchdog@ffef0000 {
+ compatible = "renesas,r8a779f0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffef0000 0 0x10>;
+ interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779F0_CLK_R>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 1205>, <&cpg 1323>;
+ reset-names = "cnt", "bus";
+ status = "disabled";
+ };
+
+ wwdt6: watchdog@fff10000 {
+ compatible = "renesas,r8a779f0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xfff10000 0 0x10>;
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779F0_CLK_R>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 1206>, <&cpg 1324>;
+ reset-names = "cnt", "bus";
+ status = "disabled";
+ };
+
+ wwdt7: watchdog@fff20000 {
+ compatible = "renesas,r8a779f0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xfff20000 0 0x10>;
+ interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779F0_CLK_R>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 1207>, <&cpg 1325>;
+ reset-names = "cnt", "bus";
+ status = "disabled";
+ };
+
+ wwdt8: watchdog@fff30000 {
+ compatible = "renesas,r8a779f0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xfff30000 0 0x10>;
+ interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779F0_CLK_R>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 1208>, <&cpg 1326>;
+ reset-names = "cnt", "bus";
+ status = "disabled";
+ };
+
+ wwdt9: watchdog@fff40000 {
+ compatible = "renesas,r8a779f0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xfff40000 0 0x10>;
+ interrupts = <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779F0_CLK_R>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 1209>, <&cpg 1327>;
+ reset-names = "cnt", "bus";
+ status = "disabled";
+ };
+
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
};
};
+ wwdt0: watchdog@ffc90000 {
+ compatible = "renesas,r8a779g0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffc90000 0 0x10>;
+ interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779G0_CLK_R>,
+ <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 1200>;
+ reset-names = "cnt";
+ status = "disabled";
+ };
+
+ wwdt1: watchdog@ffca0000 {
+ compatible = "renesas,r8a779g0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffca0000 0 0x10>;
+ interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779G0_CLK_R>,
+ <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 1201>;
+ reset-names = "cnt";
+ status = "disabled";
+ };
+
+ wwdt2: watchdog@ffcb0000 {
+ compatible = "renesas,r8a779g0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffcb0000 0 0x10>;
+ interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779G0_CLK_R>,
+ <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 1202>;
+ reset-names = "cnt";
+ status = "disabled";
+ };
+
+ wwdt3: watchdog@ffcc0000 {
+ compatible = "renesas,r8a779g0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffcc0000 0 0x10>;
+ interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779G0_CLK_R>,
+ <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 1203>;
+ reset-names = "cnt";
+ status = "disabled";
+ };
+
+ wwdt4: watchdog@ffcf0000 {
+ compatible = "renesas,r8a779g0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffcf0000 0 0x10>;
+ interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779G0_CLK_R>,
+ <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 1204>;
+ reset-names = "cnt";
+ status = "disabled";
+ };
+
+ wwdt5: watchdog@ffef0000 {
+ compatible = "renesas,r8a779g0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffef0000 0 0x10>;
+ interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779G0_CLK_R>,
+ <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 1205>;
+ reset-names = "cnt";
+ status = "disabled";
+ };
+
+ wwdt6: watchdog@fff10000 {
+ compatible = "renesas,r8a779g0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xfff10000 0 0x10>;
+ interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779G0_CLK_R>,
+ <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 1206>;
+ reset-names = "cnt";
+ status = "disabled";
+ };
+
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
reg = <0x6 0x00000000 0x1 0x00000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ tfa@40000000 {
+ reg = <0x0 0x40000000 0x0 0x8000000>;
+ no-map;
+ };
+ };
+
/* Page 27 / DSI to Display */
dp-con {
compatible = "dp-connector";
};
};
+ wwdt0: watchdog@ffc90000 {
+ compatible = "renesas,r8a779h0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffc90000 0 0x10>;
+ interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779H0_CLK_R>,
+ <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
+ resets = <&cpg 1200>;
+ reset-names = "cnt";
+ status = "disabled";
+ };
+
+ wwdt1: watchdog@ffca0000 {
+ compatible = "renesas,r8a779h0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffca0000 0 0x10>;
+ interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779H0_CLK_R>,
+ <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
+ resets = <&cpg 1201>;
+ reset-names = "cnt";
+ status = "disabled";
+ };
+
+ wwdt2: watchdog@ffcb0000 {
+ compatible = "renesas,r8a779h0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffcb0000 0 0x10>;
+ interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779H0_CLK_R>,
+ <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
+ resets = <&cpg 1202>;
+ reset-names = "cnt";
+ status = "disabled";
+ };
+
+ wwdt3: watchdog@ffcc0000 {
+ compatible = "renesas,r8a779h0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffcc0000 0 0x10>;
+ interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779H0_CLK_R>,
+ <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
+ resets = <&cpg 1203>;
+ reset-names = "cnt";
+ status = "disabled";
+ };
+
+ wwdt4: watchdog@ffcf0000 {
+ compatible = "renesas,r8a779h0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffcf0000 0 0x10>;
+ interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779H0_CLK_R>,
+ <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
+ resets = <&cpg 1204>;
+ reset-names = "cnt";
+ status = "disabled";
+ };
+
+ wwdt5: watchdog@ffef0000 {
+ compatible = "renesas,r8a779h0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xffef0000 0 0x10>;
+ interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779H0_CLK_R>,
+ <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
+ resets = <&cpg 1205>;
+ reset-names = "cnt";
+ status = "disabled";
+ };
+
+ wwdt6: watchdog@fff10000 {
+ compatible = "renesas,r8a779h0-wwdt",
+ "renesas,rcar-gen4-wwdt";
+ reg = <0 0xfff10000 0 0x10>;
+ interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pretimeout", "error";
+ clocks = <&cpg CPG_CORE R8A779H0_CLK_R>,
+ <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>;
+ clock-names = "cnt", "bus";
+ power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
+ resets = <&cpg 1206>;
+ reset-names = "cnt";
+ status = "disabled";
+ };
+
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Device Tree Source for the R-Car H3e (R8A779M0) SoC
- *
- * Copyright (C) 2021 Glider bv
- */
-
-#include "r8a77951.dtsi"
-
-/ {
- compatible = "renesas,r8a779m0", "renesas,r8a7795";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Device Tree Source for the R-Car M3e (R8A779M2) SoC
- *
- * Copyright (C) 2021 Glider bv
- */
-
-#include "r8a77961.dtsi"
-
-/ {
- compatible = "renesas,r8a779m2", "renesas,r8a77961";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Device Tree Source for the R-Car M3Ne (R8A779M4) SoC
- *
- * Copyright (C) 2021 Glider bv
- */
-
-#include "r8a77965.dtsi"
-
-/ {
- compatible = "renesas,r8a779m4", "renesas,r8a77965";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Device Tree Source for the R-Car E3e (R8A779M6) SoC
- *
- * Copyright (C) 2021 Glider bv
- */
-
-#include "r8a77990.dtsi"
-
-/ {
- compatible = "renesas,r8a779m6", "renesas,r8a77990";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Device Tree Source for the R-Car D3e (R8A779M7) SoC
- *
- * Copyright (C) 2021 Glider bv
- */
-
-#include "r8a77995.dtsi"
-
-/ {
- compatible = "renesas,r8a779m7", "renesas,r8a77995";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Device Tree Source for the R-Car H3Ne (R8A779M8) SoC
- *
- * Copyright (C) 2021 Glider bv
- */
-
-#include "r8a77951.dtsi"
-
-/ {
- compatible = "renesas,r8a779m8", "renesas,r8a7795";
-};
-
-&cluster0_opp {
- /delete-node/ opp-1600000000;
- /delete-node/ opp-1700000000;
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Device Tree Source for the R-Car H3Ne-1.7G (R8A779MB) SoC
- *
- * Copyright (C) 2022 Glider bv
- */
-
-#include "r8a77951.dtsi"
-
-/ {
- compatible = "renesas,r8a779mb", "renesas,r8a7795";
-};
compatible = "renesas,scif-r8a78000",
"renesas,rcar-gen5-scif", "renesas,scif";
reg = <0 0xc0700000 0 0x40>;
- interrupts = <GIC_SPI 4074 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_ESPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
compatible = "renesas,scif-r8a78000",
"renesas,rcar-gen5-scif", "renesas,scif";
reg = <0 0xc0704000 0 0x40>;
- interrupts = <GIC_SPI 4075 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_ESPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
compatible = "renesas,scif-r8a78000",
"renesas,rcar-gen5-scif", "renesas,scif";
reg = <0 0xc0708000 0 0x40>;
- interrupts = <GIC_SPI 4076 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_ESPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
compatible = "renesas,scif-r8a78000",
"renesas,rcar-gen5-scif", "renesas,scif";
reg = <0 0xc070c000 0 0x40>;
- interrupts = <GIC_SPI 4077 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_ESPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
compatible = "renesas,hscif-r8a78000",
"renesas,rcar-gen5-hscif", "renesas,hscif";
reg = <0 0xc0710000 0 0x60>;
- interrupts = <GIC_SPI 4078 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_ESPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
compatible = "renesas,hscif-r8a78000",
"renesas,rcar-gen5-hscif", "renesas,hscif";
reg = <0 0xc0714000 0 0x60>;
- interrupts = <GIC_SPI 4079 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_ESPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
compatible = "renesas,hscif-r8a78000",
"renesas,rcar-gen5-hscif", "renesas,hscif";
reg = <0 0xc0718000 0 0x60>;
- interrupts = <GIC_SPI 4080 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_ESPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
compatible = "renesas,hscif-r8a78000",
"renesas,rcar-gen5-hscif", "renesas,hscif";
reg = <0 0xc071c000 0 0x60>;
- interrupts = <GIC_SPI 4081 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_ESPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
status = "disabled";
wdt1: watchdog@12800c00 {
compatible = "renesas,r9a07g044-wdt",
"renesas,rzg2l-wdt";
- reg = <0 0x12800C00 0 0x400>;
+ reg = <0 0x12800c00 0 0x400>;
clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>,
<&cpg CPG_MOD R9A07G044_WDT1_CLK>;
clock-names = "pclk", "oscclk";
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the RZ/G2LC R9A07G044C1 SoC specific parts
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-
-/dts-v1/;
-#include "r9a07g044.dtsi"
-
-/ {
- compatible = "renesas,r9a07g044c1", "renesas,r9a07g044";
-
- cpus {
- /delete-node/ cpu-map;
- /delete-node/ cpu@100;
- };
-};
-
-&soc {
- /delete-node/ ssi@1004a800;
- /delete-node/ serial@1004c800;
- /delete-node/ adc@10059000;
- /delete-node/ ethernet@11c30000;
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the RZ/G2L R9A07G044L1 SoC specific parts
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-
-/dts-v1/;
-#include "r9a07g044.dtsi"
-
-/ {
- compatible = "renesas,r9a07g044l1", "renesas,r9a07g044";
-
- cpus {
- /delete-node/ cpu-map;
- /delete-node/ cpu@100;
- };
-};
wdt1: watchdog@12800c00 {
compatible = "renesas,r9a07g054-wdt",
"renesas,rzg2l-wdt";
- reg = <0 0x12800C00 0 0x400>;
+ reg = <0 0x12800c00 0 0x400>;
clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>,
<&cpg CPG_MOD R9A07G054_WDT1_CLK>;
clock-names = "pclk", "oscclk";
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the RZ/V2L R9A07G054L1 SoC specific parts
- *
- * Copyright (C) 2021 Renesas Electronics Corp.
- */
-
-/dts-v1/;
-#include "r9a07g054.dtsi"
-
-/ {
- compatible = "renesas,r9a07g054l1", "renesas,r9a07g054";
-
- cpus {
- /delete-node/ cpu-map;
- /delete-node/ cpu@100;
- };
-};
status = "disabled";
};
+ pcie: pcie@11e40000 {
+ compatible = "renesas,r9a08g045-pcie";
+ reg = <0 0x11e40000 0 0x10000>;
+ ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>;
+ /* Map all possible DRAM ranges (4 GB). */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>;
+ bus-range = <0x0 0xff>;
+ interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "serr", "serr_cor", "serr_nonfatal",
+ "serr_fatal", "axi_err", "inta",
+ "intb", "intc", "intd", "msi",
+ "link_bandwidth", "pm_pme", "dma",
+ "pcie_evt", "msg", "all";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */
+ <0 0 0 2 &pcie 0 0 0 1>, /* INTB */
+ <0 0 0 3 &pcie 0 0 0 2>, /* INTC */
+ <0 0 0 4 &pcie 0 0 0 3>; /* INTD */
+ clocks = <&cpg CPG_MOD R9A08G045_PCI_ACLK>,
+ <&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>;
+ clock-names = "aclk", "pm";
+ resets = <&cpg R9A08G045_PCI_ARESETN>,
+ <&cpg R9A08G045_PCI_RST_B>,
+ <&cpg R9A08G045_PCI_RST_GP_B>,
+ <&cpg R9A08G045_PCI_RST_PS_B>,
+ <&cpg R9A08G045_PCI_RST_RSM_B>,
+ <&cpg R9A08G045_PCI_RST_CFG_B>,
+ <&cpg R9A08G045_PCI_RST_LOAD_B>;
+ reset-names = "aresetn", "rst_b", "rst_gp_b", "rst_ps_b",
+ "rst_rsm_b", "rst_cfg_b", "rst_load_b";
+ power-domains = <&cpg>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ renesas,sysc = <&sysc>;
+ status = "disabled";
+
+ pcie_port0: pcie@0,0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ ranges;
+ device_type = "pci";
+ vendor-id = <0x1912>;
+ device-id = <0x0033>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ };
+ };
+
gic: interrupt-controller@12400000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
};
};
+ rsci0: serial@12800c00 {
+ compatible = "renesas,r9a09g047-rsci";
+ reg = <0 0x12800c00 0 0x400>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x5d>, <&cpg CPG_MOD 0x5e>,
+ <&cpg CPG_MOD 0x61>, <&cpg CPG_MOD 0x60>,
+ <&cpg CPG_MOD 0x5f>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x81>, <&cpg 0x82>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci1: serial@12801000 {
+ compatible = "renesas,r9a09g047-rsci";
+ reg = <0 0x12801000 0 0x400>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x62>, <&cpg CPG_MOD 0x63>,
+ <&cpg CPG_MOD 0x66>, <&cpg CPG_MOD 0x65>,
+ <&cpg CPG_MOD 0x64>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x83>, <&cpg 0x84>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci2: serial@12801400 {
+ compatible = "renesas,r9a09g047-rsci";
+ reg = <0 0x12801400 0 0x400>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x67>, <&cpg CPG_MOD 0x68>,
+ <&cpg CPG_MOD 0x6b>, <&cpg CPG_MOD 0x6a>,
+ <&cpg CPG_MOD 0x69>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x85>, <&cpg 0x86>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci3: serial@12801800 {
+ compatible = "renesas,r9a09g047-rsci";
+ reg = <0 0x12801800 0 0x400>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x6c>, <&cpg CPG_MOD 0x6d>,
+ <&cpg CPG_MOD 0x70>, <&cpg CPG_MOD 0x6f>,
+ <&cpg CPG_MOD 0x6e>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x87>, <&cpg 0x88>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci4: serial@12801c00 {
+ compatible = "renesas,r9a09g047-rsci";
+ reg = <0 0x12801c00 0 0x400>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x71>, <&cpg CPG_MOD 0x72>,
+ <&cpg CPG_MOD 0x75>, <&cpg CPG_MOD 0x74>,
+ <&cpg CPG_MOD 0x73>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x89>, <&cpg 0x8a>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci5: serial@12802000 {
+ compatible = "renesas,r9a09g047-rsci";
+ reg = <0 0x12802000 0 0x400>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x76>, <&cpg CPG_MOD 0x77>,
+ <&cpg CPG_MOD 0x7a>, <&cpg CPG_MOD 0x79>,
+ <&cpg CPG_MOD 0x78>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x8b>, <&cpg 0x8c>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci6: serial@12802400 {
+ compatible = "renesas,r9a09g047-rsci";
+ reg = <0 0x12802400 0 0x400>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x7b>, <&cpg CPG_MOD 0x7c>,
+ <&cpg CPG_MOD 0x7f>, <&cpg CPG_MOD 0x7e>,
+ <&cpg CPG_MOD 0x7d>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x8d>, <&cpg 0x8e>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci7: serial@12802800 {
+ compatible = "renesas,r9a09g047-rsci";
+ reg = <0 0x12802800 0 0x400>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x80>, <&cpg CPG_MOD 0x81>,
+ <&cpg CPG_MOD 0x84>, <&cpg CPG_MOD 0x83>,
+ <&cpg CPG_MOD 0x82>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x8f>, <&cpg 0x90>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci8: serial@12802c00 {
+ compatible = "renesas,r9a09g047-rsci";
+ reg = <0 0x12802c00 0 0x400>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x85>, <&cpg CPG_MOD 0x86>,
+ <&cpg CPG_MOD 0x89>, <&cpg CPG_MOD 0x88>,
+ <&cpg CPG_MOD 0x87>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x91>, <&cpg 0x92>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci9: serial@12803000 {
+ compatible = "renesas,r9a09g047-rsci";
+ reg = <0 0x12803000 0 0x400>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x8a>, <&cpg CPG_MOD 0x8b>,
+ <&cpg CPG_MOD 0x8e>, <&cpg CPG_MOD 0x8d>,
+ <&cpg CPG_MOD 0x8c>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x93>, <&cpg 0x94>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
wdt1: watchdog@14400000 {
compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt";
reg = <0 0x14400000 0 0x400>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
+ xhci: usb@15850000 {
+ compatible = "renesas,r9a09g047-xhci";
+ reg = <0 0x15850000 0 0x10000>;
+ interrupts = <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "all", "smi", "hse", "pme", "xhc";
+ clocks = <&cpg CPG_MOD 0xaf>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0xaa>;
+ phys = <&usb3_phy>, <&usb3_phy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ status = "disabled";
+ };
+
+ usb3_phy: usb-phy@15870000 {
+ compatible = "renesas,r9a09g047-usb3-phy";
+ reg = <0 0x15870000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0xb0>,
+ <&cpg CPG_CORE R9A09G047_USB3_0_CLKCORE>,
+ <&cpg CPG_CORE R9A09G047_USB3_0_REF_ALT_CLK_P>;
+ clock-names = "pclk", "core", "ref_alt_clk_p";
+ power-domains = <&cpg>;
+ resets = <&cpg 0xaa>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
sdhi0: mmc@15c00000 {
compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057";
reg = <0x0 0x15c00000 0 0x10000>;
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Device Tree Source for the RZ/G3E R9A09G047E37 SoC specific parts
- *
- * Copyright (C) 2024 Renesas Electronics Corp.
- */
-
-/dts-v1/;
-#include "r9a09g047.dtsi"
-
-/ {
- compatible = "renesas,r9a09g047e37", "renesas,r9a09g047";
-
- cpus {
- /delete-node/ cpu@200;
- /delete-node/ cpu@300;
- };
-};
/dts-v1/;
/* Switch selection settings */
-#define SW_LCD_EN 0
#define SW_GPIO8_CAN0_STB 0
#define SW_GPIO9_CAN1_STB 0
#define SW_LCD_EN 0
#define SW_PDM_EN 0
+#define SW_SER0_PMOD 1
+#define SW_SER2_EN 1
#define SW_SD0_DEV_SEL 0
#define SW_SDIO_M2E 0
compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm",
"renesas,r9a09g047e57", "renesas,r9a09g047";
+ aliases {
+ i2c0 = &i2c0;
+ serial0 = &rsci4;
+ serial1 = &rsci9;
+ serial2 = &rsci2;
+ serial3 = &scif0;
+ mmc1 = &sdhi1;
+ };
+
vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd {
compatible = "regulator-gpio";
regulator-name = "SD1_PVDD";
input-schmitt-enable;
};
+ rsci2_pins: rsci2 {
+ pinmux = <RZG3E_PORT_PINMUX(1, 0, 1)>, /* RXD2 */
+ <RZG3E_PORT_PINMUX(1, 1, 1)>, /* TXD2 */
+ <RZG3E_PORT_PINMUX(1, 2, 6)>, /* CTS2N */
+ <RZG3E_PORT_PINMUX(1, 3, 1)>; /* RTS2N */
+ bias-pull-up;
+ };
+
+ rsci4_pins: rsci4 {
+ pinmux = <RZG3E_PORT_PINMUX(7, 6, 5)>, /* RXD4 */
+ <RZG3E_PORT_PINMUX(7, 7, 5)>, /* TXD4 */
+ <RZG3E_PORT_PINMUX(8, 0, 6)>, /* CTS4N */
+ <RZG3E_PORT_PINMUX(8, 1, 5)>; /* RTS4N */
+ bias-pull-up;
+ };
+
+ rsci9_pins: rsci9 {
+ pinmux = <RZG3E_PORT_PINMUX(8, 2, 5)>, /* RXD9 */
+ <RZG3E_PORT_PINMUX(8, 3, 5)>; /* TXD9 */
+ bias-pull-up;
+ };
+
scif_pins: scif {
pins = "SCIF_TXD", "SCIF_RXD";
renesas,output-impedance = <1>;
<RZG3E_PORT_PINMUX(G, 5, 1)>; /* SD1DAT3 */
};
};
+
+ usb3_pins: usb3 {
+ pinmux = <RZG3E_PORT_PINMUX(4, 1, 12)>, /* USB30_VBUSEN */
+ <RZG3E_PORT_PINMUX(4, 0, 12)>; /* USB30_OVRCURN */
+ };
};
+#if SW_SER0_PMOD && SW_SER2_EN
+&rsci2 {
+ pinctrl-0 = <&rsci2_pins>;
+ pinctrl-names = "default";
+
+ uart-has-rtscts;
+
+ status = "okay";
+};
+#endif
+
+#if (!SW_LCD_EN) && (SW_SER0_PMOD)
+&rsci4 {
+ pinctrl-0 = <&rsci4_pins>;
+ pinctrl-names = "default";
+
+ uart-has-rtscts;
+
+ status = "okay";
+};
+#endif
+
+#if (!SW_LCD_EN)
+&rsci9 {
+ pinctrl-0 = <&rsci9_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+#endif
+
&scif0 {
pinctrl-0 = <&scif_pins>;
pinctrl-names = "default";
vmmc-supply = <®_3p3v>;
vqmmc-supply = <&vqmmc_sd1_pvdd>;
};
+
+&xhci {
+ pinctrl-0 = <&usb3_pins>;
+ pinctrl-names = "default";
+};
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK0>;
+ #cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK1>;
+ #cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK2>;
+ #cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK3>;
+ #cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};
#size-cells = <2>;
ranges;
+ icu: interrupt-controller@10400000 {
+ compatible = "renesas,r9a09g056-icu";
+ reg = <0 0x10400000 0 0x10000>;
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "nmi",
+ "port_irq0", "port_irq1", "port_irq2",
+ "port_irq3", "port_irq4", "port_irq5",
+ "port_irq6", "port_irq7", "port_irq8",
+ "port_irq9", "port_irq10", "port_irq11",
+ "port_irq12", "port_irq13", "port_irq14",
+ "port_irq15",
+ "tint0", "tint1", "tint2", "tint3",
+ "tint4", "tint5", "tint6", "tint7",
+ "tint8", "tint9", "tint10", "tint11",
+ "tint12", "tint13", "tint14", "tint15",
+ "tint16", "tint17", "tint18", "tint19",
+ "tint20", "tint21", "tint22", "tint23",
+ "tint24", "tint25", "tint26", "tint27",
+ "tint28", "tint29", "tint30", "tint31",
+ "int-ca55-0", "int-ca55-1",
+ "int-ca55-2", "int-ca55-3",
+ "icu-error-ca55",
+ "gpt-u0-gtciada", "gpt-u0-gtciadb",
+ "gpt-u1-gtciada", "gpt-u1-gtciadb";
+ clocks = <&cpg CPG_MOD 0x5>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0x36>;
+ };
+
pinctrl: pinctrl@10410000 {
compatible = "renesas,r9a09g056-pinctrl";
reg = <0 0x10410000 0 0x10000>;
clocks = <&cpg CPG_CORE R9A09G056_IOTOP_0_SHCLK>;
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&icu>;
gpio-ranges = <&pinctrl 0 0 96>;
power-domains = <&cpg>;
resets = <&cpg 0xa5>, <&cpg 0xa6>;
resets = <&cpg 0x30>;
};
+ tsu0: thermal@11000000 {
+ compatible = "renesas,r9a09g056-tsu", "renesas,r9a09g047-tsu";
+ reg = <0 0x11000000 0 0x1000>;
+ interrupts = <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "adi", "adcmpi";
+ clocks = <&cpg CPG_MOD 0x109>;
+ resets = <&cpg 0xf7>;
+ power-domains = <&cpg>;
+ #thermal-sensor-cells = <0>;
+ renesas,tsu-trim = <&sys 0x320>;
+ };
+
+ tsu1: thermal@14002000 {
+ compatible = "renesas,r9a09g056-tsu", "renesas,r9a09g047-tsu";
+ reg = <0 0x14002000 0 0x1000>;
+ interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "adi", "adcmpi";
+ clocks = <&cpg CPG_MOD 0x10a>;
+ resets = <&cpg 0xf8>;
+ power-domains = <&cpg>;
+ #thermal-sensor-cells = <0>;
+ renesas,tsu-trim = <&sys 0x330>;
+ };
+
xspi: spi@11030000 {
compatible = "renesas,r9a09g056-xspi", "renesas,r9a09g047-xspi";
reg = <0 0x11030000 0 0x10000>,
status = "disabled";
};
+ dmac0: dma-controller@11400000 {
+ compatible = "renesas,r9a09g056-dmac", "renesas,r9a09g057-dmac";
+ reg = <0 0x11400000 0 0x10000>;
+ interrupts = <GIC_SPI 499 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 94 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 0x0>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0x31>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 4>;
+ };
+
+ dmac1: dma-controller@14830000 {
+ compatible = "renesas,r9a09g056-dmac", "renesas,r9a09g057-dmac";
+ reg = <0 0x14830000 0 0x10000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 0x1>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0x32>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 0>;
+ };
+
+ dmac2: dma-controller@14840000 {
+ compatible = "renesas,r9a09g056-dmac", "renesas,r9a09g057-dmac";
+ reg = <0 0x14840000 0 0x10000>;
+ interrupts = <GIC_SPI 496 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 0x2>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0x33>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 1>;
+ };
+
+ dmac3: dma-controller@12000000 {
+ compatible = "renesas,r9a09g056-dmac", "renesas,r9a09g057-dmac";
+ reg = <0 0x12000000 0 0x10000>;
+ interrupts = <GIC_SPI 497 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 0x3>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0x34>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 2>;
+ };
+
+ dmac4: dma-controller@12010000 {
+ compatible = "renesas,r9a09g056-dmac", "renesas,r9a09g057-dmac";
+ reg = <0 0x12010000 0 0x10000>;
+ interrupts = <GIC_SPI 498 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 0x4>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0x35>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 3>;
+ };
+
ostm0: timer@11800000 {
compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
reg = <0x0 0x11800000 0x0 0x1000>;
status = "disabled";
};
+ canfd: can@12440000 {
+ compatible = "renesas,r9a09g056-canfd", "renesas,r9a09g047-canfd";
+ reg = <0 0x12440000 0 0x40000>;
+ interrupts = <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 698 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 705 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g_err", "g_recc",
+ "ch0_err", "ch0_rec", "ch0_trx",
+ "ch1_err", "ch1_rec", "ch1_trx",
+ "ch2_err", "ch2_rec", "ch2_trx",
+ "ch3_err", "ch3_rec", "ch3_trx",
+ "ch4_err", "ch4_rec", "ch4_trx",
+ "ch5_err", "ch5_rec", "ch5_trx";
+ clocks = <&cpg CPG_MOD 0x9c>, <&cpg CPG_MOD 0x9d>,
+ <&cpg CPG_MOD 0x9e>;
+ clock-names = "fck", "ram_clk", "can_clk";
+ assigned-clocks = <&cpg CPG_MOD 0x9e>;
+ assigned-clock-rates = <80000000>;
+ resets = <&cpg 0xa1>, <&cpg 0xa2>;
+ reset-names = "rstp_n", "rstc_n";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ channel0 {
+ status = "disabled";
+ };
+ channel1 {
+ status = "disabled";
+ };
+ channel2 {
+ status = "disabled";
+ };
+ channel3 {
+ status = "disabled";
+ };
+ channel4 {
+ status = "disabled";
+ };
+ channel5 {
+ status = "disabled";
+ };
+ };
+
+ rspi0: spi@12800000 {
+ compatible = "renesas,r9a09g056-rspi", "renesas,r9a09g057-rspi";
+ reg = <0x0 0x12800000 0x0 0x400>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 500 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 501 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "idle", "error", "end", "rx", "tx";
+ clocks = <&cpg CPG_MOD 0x54>,
+ <&cpg CPG_MOD 0x55>,
+ <&cpg CPG_MOD 0x56>;
+ clock-names = "pclk", "pclk_sfr", "tclk";
+ resets = <&cpg 0x7b>, <&cpg 0x7c>;
+ reset-names = "presetn", "tresetn";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ rspi1: spi@12800400 {
+ compatible = "renesas,r9a09g056-rspi", "renesas,r9a09g057-rspi";
+ reg = <0x0 0x12800400 0x0 0x400>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 502 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 503 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "idle", "error", "end", "rx", "tx";
+ clocks = <&cpg CPG_MOD 0x57>,
+ <&cpg CPG_MOD 0x58>,
+ <&cpg CPG_MOD 0x59>;
+ clock-names = "pclk", "pclk_sfr", "tclk";
+ resets = <&cpg 0x7d>, <&cpg 0x7e>;
+ reset-names = "presetn", "tresetn";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ rspi2: spi@12800800 {
+ compatible = "renesas,r9a09g056-rspi", "renesas,r9a09g057-rspi";
+ reg = <0x0 0x12800800 0x0 0x400>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 504 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 505 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "idle", "error", "end", "rx", "tx";
+ clocks = <&cpg CPG_MOD 0x5a>,
+ <&cpg CPG_MOD 0x5b>,
+ <&cpg CPG_MOD 0x5c>;
+ clock-names = "pclk", "pclk_sfr", "tclk";
+ resets = <&cpg 0x7f>, <&cpg 0x80>;
+ reset-names = "presetn", "tresetn";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ rsci0: serial@12800c00 {
+ compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci";
+ reg = <0 0x12800c00 0 0x400>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x5d>, <&cpg CPG_MOD 0x5e>,
+ <&cpg CPG_MOD 0x61>, <&cpg CPG_MOD 0x60>,
+ <&cpg CPG_MOD 0x5f>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x81>, <&cpg 0x82>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci1: serial@12801000 {
+ compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci";
+ reg = <0 0x12801000 0 0x400>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x62>, <&cpg CPG_MOD 0x63>,
+ <&cpg CPG_MOD 0x66>, <&cpg CPG_MOD 0x65>,
+ <&cpg CPG_MOD 0x64>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x83>, <&cpg 0x84>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci2: serial@12801400 {
+ compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci";
+ reg = <0 0x12801400 0 0x400>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x67>, <&cpg CPG_MOD 0x68>,
+ <&cpg CPG_MOD 0x6b>, <&cpg CPG_MOD 0x6a>,
+ <&cpg CPG_MOD 0x69>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x85>, <&cpg 0x86>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci3: serial@12801800 {
+ compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci";
+ reg = <0 0x12801800 0 0x400>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x6c>, <&cpg CPG_MOD 0x6d>,
+ <&cpg CPG_MOD 0x70>, <&cpg CPG_MOD 0x6f>,
+ <&cpg CPG_MOD 0x6e>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x87>, <&cpg 0x88>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci4: serial@12801c00 {
+ compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci";
+ reg = <0 0x12801c00 0 0x400>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x71>, <&cpg CPG_MOD 0x72>,
+ <&cpg CPG_MOD 0x75>, <&cpg CPG_MOD 0x74>,
+ <&cpg CPG_MOD 0x73>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x89>, <&cpg 0x8a>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci5: serial@12802000 {
+ compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci";
+ reg = <0 0x12802000 0 0x400>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x76>, <&cpg CPG_MOD 0x77>,
+ <&cpg CPG_MOD 0x7a>, <&cpg CPG_MOD 0x79>,
+ <&cpg CPG_MOD 0x78>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x8b>, <&cpg 0x8c>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci6: serial@12802400 {
+ compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci";
+ reg = <0 0x12802400 0 0x400>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x7b>, <&cpg CPG_MOD 0x7c>,
+ <&cpg CPG_MOD 0x7f>, <&cpg CPG_MOD 0x7e>,
+ <&cpg CPG_MOD 0x7d>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x8d>, <&cpg 0x8e>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci7: serial@12802800 {
+ compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci";
+ reg = <0 0x12802800 0 0x400>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x80>, <&cpg CPG_MOD 0x81>,
+ <&cpg CPG_MOD 0x84>, <&cpg CPG_MOD 0x83>,
+ <&cpg CPG_MOD 0x82>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x8f>, <&cpg 0x90>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci8: serial@12802c00 {
+ compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci";
+ reg = <0 0x12802c00 0 0x400>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x85>, <&cpg CPG_MOD 0x86>,
+ <&cpg CPG_MOD 0x89>, <&cpg CPG_MOD 0x88>,
+ <&cpg CPG_MOD 0x87>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x91>, <&cpg 0x92>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci9: serial@12803000 {
+ compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci";
+ reg = <0 0x12803000 0 0x400>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x8a>, <&cpg CPG_MOD 0x8b>,
+ <&cpg CPG_MOD 0x8e>, <&cpg CPG_MOD 0x8d>,
+ <&cpg CPG_MOD 0x8c>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x93>, <&cpg 0x94>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
i2c0: i2c@14400400 {
compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057";
reg = <0 0x14400400 0 0x400>;
status = "disabled";
};
+ xhci: usb@15850000 {
+ compatible = "renesas,r9a09g056-xhci", "renesas,r9a09g047-xhci";
+ reg = <0 0x15850000 0 0x10000>;
+ interrupts = <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "all", "smi", "hse", "pme", "xhc";
+ clocks = <&cpg CPG_MOD 0xaf>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0xaa>;
+ phys = <&usb3_phy>, <&usb3_phy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ status = "disabled";
+ };
+
+ usb3_phy: usb-phy@15870000 {
+ compatible = "renesas,r9a09g056-usb3-phy", "renesas,r9a09g047-usb3-phy";
+ reg = <0 0x15870000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0xb0>,
+ <&cpg CPG_CORE R9A09G056_USB3_0_CLKCORE>,
+ <&cpg CPG_CORE R9A09G056_USB3_0_REF_ALT_CLK_P>;
+ clock-names = "pclk", "core", "ref_alt_clk_p";
+ power-domains = <&cpg>;
+ resets = <&cpg 0xaa>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
sdhi0: mmc@15c00000 {
compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057";
reg = <0x0 0x15c00000 0 0x10000>;
};
};
};
+
+ dsi: dsi@16430000 {
+ compatible = "renesas,r9a09g056-mipi-dsi", "renesas,r9a09g057-mipi-dsi";
+ reg = <0 0x16430000 0 0x20000>;
+ interrupts = <GIC_SPI 874 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 876 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 877 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 878 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 879 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 880 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "seq0", "seq1", "vin1", "rcv",
+ "ferr", "ppi", "debug";
+ clocks = <&cpg CPG_MOD 0xec>, <&cpg CPG_MOD 0xe9>,
+ <&cpg CPG_MOD 0xe8>, <&cpg CPG_MOD 0xea>,
+ <&cpg CPG_MOD 0xeb>;
+ clock-names = "pllrefclk", "aclk", "pclk", "vclk", "lpclk";
+ resets = <&cpg 0xd8>, <&cpg 0xd7>;
+ reset-names = "arst", "prst";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <&du_out_dsi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ };
+ };
+ };
+ };
+
+ du: display@16460000 {
+ compatible = "renesas,r9a09g056-du", "renesas,r9a09g057-du";
+ reg = <0 0x16460000 0 0x10000>;
+ interrupts = <GIC_SPI 882 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xed>, <&cpg CPG_MOD 0xee>,
+ <&cpg CPG_MOD 0xef>;
+ clock-names = "aclk", "pclk", "vclk";
+ power-domains = <&cpg>;
+ resets = <&cpg 0xdc>;
+ renesas,vsps = <&vspd 0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_dsi: endpoint {
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+ };
+ };
+
+ fcpvd: fcp@16470000 {
+ compatible = "renesas,r9a09g056-fcpvd", "renesas,fcpv";
+ reg = <0 0x16470000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0xed>,
+ <&cpg CPG_MOD 0xee>,
+ <&cpg CPG_MOD 0xef>;
+ clock-names = "aclk", "pclk", "vclk";
+ power-domains = <&cpg>;
+ resets = <&cpg 0xdc>;
+ };
+
+ vspd: vsp@16480000 {
+ compatible = "renesas,r9a09g056-vsp2", "renesas,r9a07g044-vsp2";
+ reg = <0 0x16480000 0 0x10000>;
+ interrupts = <GIC_SPI 881 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xed>,
+ <&cpg CPG_MOD 0xee>,
+ <&cpg CPG_MOD 0xef>;
+ clock-names = "aclk", "pclk", "vclk";
+ power-domains = <&cpg>;
+ resets = <&cpg 0xdc>;
+ renesas,fcp = <&fcpvd>;
+ };
};
stmmac_axi_setup: stmmac-axi-config {
snps,blen = <16 8 4 0 0 0 0>;
};
+ thermal-zones {
+ sensor1_thermal: sensor1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&tsu0>;
+
+ trips {
+ sensor1_crit: sensor1-crit {
+ temperature = <120000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ sensor2_thermal: sensor2-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&tsu1>;
+
+ cooling-maps {
+ map0 {
+ trip = <&sensor2_target>;
+ cooling-device = <&cpu0 0 3>, <&cpu1 0 3>,
+ <&cpu2 0 3>, <&cpu3 0 3>;
+ contribution = <1024>;
+ };
+ };
+
+ trips {
+ sensor2_target: trip-point {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ sensor2_crit: sensor2-crit {
+ temperature = <120000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
#include "r9a09g056.dtsi"
/ {
stdout-path = "serial0:115200n8";
};
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "d";
+
+ port {
+ hdmi_con_out: endpoint {
+ remote-endpoint = <&adv7535_out>;
+ };
+ };
+ };
+
+ keys: keys {
+ compatible = "gpio-keys";
+
+ key-wakeup {
+ interrupts-extended = <&icu 0 IRQ_TYPE_EDGE_FALLING>;
+ linux,code = <KEY_WAKEUP>;
+ label = "NMI_SW";
+ debounce-interval = <20>;
+ wakeup-source;
+ };
+ };
+
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
#clock-cells = <0>;
clock-frequency = <32768>;
};
+
+ /* 12MHz oscillator for ADV7535 */
+ y1: y1-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12000000>;
+ };
};
&audio_extal_clk {
clock-frequency = <22579200>;
};
+&dsi {
+ status = "okay";
+
+ ports {
+ port@1 {
+ dsi_out: endpoint {
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&adv7535_in>;
+ };
+ };
+ };
+};
+
+&du {
+ status = "okay";
+};
+
&ehci0 {
dr_mode = "otg";
status = "okay";
pinctrl-names = "default";
clock-frequency = <400000>;
status = "okay";
+
+ adv7535: hdmi@3d {
+ compatible = "adi,adv7535";
+ reg = <0x3d>, <0x3f>, <0x3c>, <0x38>;
+ reg-names = "main", "edid", "cec", "packet";
+ clocks = <&y1>;
+ clock-names = "cec";
+ avdd-supply = <®_1p8v>;
+ dvdd-supply = <®_1p8v>;
+ pvdd-supply = <®_1p8v>;
+ a2vdd-supply = <®_1p8v>;
+ v3p3-supply = <®_3p3v>;
+ v1p2-supply = <®_1p8v>;
+ adi,dsi-lanes = <4>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7535_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7535_out: endpoint {
+ remote-endpoint = <&hdmi_con_out>;
+ };
+ };
+ };
+ };
};
&i2c6 {
};
};
+ usb3_pins: usb3 {
+ pinmux = <RZV2N_PORT_PINMUX(B, 0, 14)>, /* USB30_VBUSEN */
+ <RZV2N_PORT_PINMUX(B, 1, 14)>; /* USB30_OVRCURN */
+ };
+
xspi_pins: xspi0 {
ctrl {
pins = "XSPI0_RESET0N", "XSPI0_CS0N", "XSPI0_CKP";
status = "okay";
};
+&usb3_phy {
+ status = "okay";
+};
+
&wdt1 {
status = "okay";
};
+&xhci {
+ pinctrl-0 = <&usb3_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&xspi {
pinctrl-0 = <&xspi_pins>;
pinctrl-names = "default";
status = "disabled";
};
- wdt0: watchdog@11c00400 {
- compatible = "renesas,r9a09g057-wdt";
- reg = <0 0x11c00400 0 0x400>;
- clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>;
- clock-names = "pclk", "oscclk";
- resets = <&cpg 0x75>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
wdt1: watchdog@14400000 {
compatible = "renesas,r9a09g057-wdt";
reg = <0 0x14400000 0 0x400>;
status = "disabled";
};
- wdt2: watchdog@13000000 {
- compatible = "renesas,r9a09g057-wdt";
- reg = <0 0x13000000 0 0x400>;
- clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>;
- clock-names = "pclk", "oscclk";
- resets = <&cpg 0x77>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
- wdt3: watchdog@13000400 {
- compatible = "renesas,r9a09g057-wdt";
- reg = <0 0x13000400 0 0x400>;
- clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>;
- clock-names = "pclk", "oscclk";
- resets = <&cpg 0x78>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
rtc: rtc@11c00800 {
compatible = "renesas,r9a09g057-rtca3", "renesas,rz-rtca3";
reg = <0 0x11c00800 0 0x400>;
status = "disabled";
};
+ canfd: can@12440000 {
+ compatible = "renesas,r9a09g057-canfd", "renesas,r9a09g047-canfd";
+ reg = <0 0x12440000 0 0x40000>;
+ interrupts = <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 698 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 705 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g_err", "g_recc",
+ "ch0_err", "ch0_rec", "ch0_trx",
+ "ch1_err", "ch1_rec", "ch1_trx",
+ "ch2_err", "ch2_rec", "ch2_trx",
+ "ch3_err", "ch3_rec", "ch3_trx",
+ "ch4_err", "ch4_rec", "ch4_trx",
+ "ch5_err", "ch5_rec", "ch5_trx";
+ clocks = <&cpg CPG_MOD 0x9c>, <&cpg CPG_MOD 0x9d>,
+ <&cpg CPG_MOD 0x9e>;
+ clock-names = "fck", "ram_clk", "can_clk";
+ assigned-clocks = <&cpg CPG_MOD 0x9e>;
+ assigned-clock-rates = <80000000>;
+ resets = <&cpg 0xa1>, <&cpg 0xa2>;
+ reset-names = "rstp_n", "rstc_n";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ channel0 {
+ status = "disabled";
+ };
+ channel1 {
+ status = "disabled";
+ };
+ channel2 {
+ status = "disabled";
+ };
+ channel3 {
+ status = "disabled";
+ };
+ channel4 {
+ status = "disabled";
+ };
+ channel5 {
+ status = "disabled";
+ };
+ };
+
rspi0: spi@12800000 {
compatible = "renesas,r9a09g057-rspi";
reg = <0x0 0x12800000 0x0 0x400>;
status = "disabled";
};
+ rsci0: serial@12800c00 {
+ compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci";
+ reg = <0 0x12800c00 0 0x400>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x5d>, <&cpg CPG_MOD 0x5e>,
+ <&cpg CPG_MOD 0x61>, <&cpg CPG_MOD 0x60>,
+ <&cpg CPG_MOD 0x5f>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x81>, <&cpg 0x82>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci1: serial@12801000 {
+ compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci";
+ reg = <0 0x12801000 0 0x400>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x62>, <&cpg CPG_MOD 0x63>,
+ <&cpg CPG_MOD 0x66>, <&cpg CPG_MOD 0x65>,
+ <&cpg CPG_MOD 0x64>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x83>, <&cpg 0x84>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci2: serial@12801400 {
+ compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci";
+ reg = <0 0x12801400 0 0x400>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x67>, <&cpg CPG_MOD 0x68>,
+ <&cpg CPG_MOD 0x6b>, <&cpg CPG_MOD 0x6a>,
+ <&cpg CPG_MOD 0x69>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x85>, <&cpg 0x86>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci3: serial@12801800 {
+ compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci";
+ reg = <0 0x12801800 0 0x400>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x6c>, <&cpg CPG_MOD 0x6d>,
+ <&cpg CPG_MOD 0x70>, <&cpg CPG_MOD 0x6f>,
+ <&cpg CPG_MOD 0x6e>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x87>, <&cpg 0x88>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci4: serial@12801c00 {
+ compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci";
+ reg = <0 0x12801c00 0 0x400>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x71>, <&cpg CPG_MOD 0x72>,
+ <&cpg CPG_MOD 0x75>, <&cpg CPG_MOD 0x74>,
+ <&cpg CPG_MOD 0x73>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x89>, <&cpg 0x8a>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci5: serial@12802000 {
+ compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci";
+ reg = <0 0x12802000 0 0x400>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x76>, <&cpg CPG_MOD 0x77>,
+ <&cpg CPG_MOD 0x7a>, <&cpg CPG_MOD 0x79>,
+ <&cpg CPG_MOD 0x78>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x8b>, <&cpg 0x8c>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci6: serial@12802400 {
+ compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci";
+ reg = <0 0x12802400 0 0x400>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x7b>, <&cpg CPG_MOD 0x7c>,
+ <&cpg CPG_MOD 0x7f>, <&cpg CPG_MOD 0x7e>,
+ <&cpg CPG_MOD 0x7d>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x8d>, <&cpg 0x8e>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci7: serial@12802800 {
+ compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci";
+ reg = <0 0x12802800 0 0x400>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x80>, <&cpg CPG_MOD 0x81>,
+ <&cpg CPG_MOD 0x84>, <&cpg CPG_MOD 0x83>,
+ <&cpg CPG_MOD 0x82>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x8f>, <&cpg 0x90>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci8: serial@12802c00 {
+ compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci";
+ reg = <0 0x12802c00 0 0x400>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x85>, <&cpg CPG_MOD 0x86>,
+ <&cpg CPG_MOD 0x89>, <&cpg CPG_MOD 0x88>,
+ <&cpg CPG_MOD 0x87>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x91>, <&cpg 0x92>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
+ rsci9: serial@12803000 {
+ compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci";
+ reg = <0 0x12803000 0 0x400>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei",
+ "aed", "bfd";
+ clocks = <&cpg CPG_MOD 0x8a>, <&cpg CPG_MOD 0x8b>,
+ <&cpg CPG_MOD 0x8e>, <&cpg CPG_MOD 0x8d>,
+ <&cpg CPG_MOD 0x8c>;
+ clock-names = "pclk", "tclk", "tclk_div4",
+ "tclk_div16", "tclk_div64";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x93>, <&cpg 0x94>;
+ reset-names = "presetn", "tresetn";
+ status = "disabled";
+ };
+
i2c0: i2c@14400400 {
compatible = "renesas,riic-r9a09g057";
reg = <0 0x14400400 0 0x400>;
status = "disabled";
};
+ xhci0: usb@15850000 {
+ compatible = "renesas,r9a09g057-xhci", "renesas,r9a09g047-xhci";
+ reg = <0 0x15850000 0 0x10000>;
+ interrupts = <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "all", "smi", "hse", "pme", "xhc";
+ clocks = <&cpg CPG_MOD 0xaf>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0xaa>;
+ phys = <&usb3_phy0>, <&usb3_phy0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ status = "disabled";
+ };
+
+ xhci1: usb@15860000 {
+ compatible = "renesas,r9a09g057-xhci", "renesas,r9a09g047-xhci";
+ reg = <0 0x15860000 0 0x10000>;
+ interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "all", "smi", "hse", "pme", "xhc";
+ clocks = <&cpg CPG_MOD 0xb1>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0xab>;
+ phys = <&usb3_phy1>, <&usb3_phy1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ status = "disabled";
+ };
+
+ usb3_phy0: usb-phy@15870000 {
+ compatible = "renesas,r9a09g057-usb3-phy", "renesas,r9a09g047-usb3-phy";
+ reg = <0 0x15870000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0xb0>,
+ <&cpg CPG_CORE R9A09G057_USB3_0_CLKCORE>,
+ <&cpg CPG_CORE R9A09G057_USB3_0_REF_ALT_CLK_P>;
+ clock-names = "pclk", "core", "ref_alt_clk_p";
+ power-domains = <&cpg>;
+ resets = <&cpg 0xaa>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usb3_phy1: usb-phy@15880000 {
+ compatible = "renesas,r9a09g057-usb3-phy", "renesas,r9a09g047-usb3-phy";
+ reg = <0 0x15880000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0xb2>,
+ <&cpg CPG_CORE R9A09G057_USB3_1_CLKCORE>,
+ <&cpg CPG_CORE R9A09G057_USB3_1_REF_ALT_CLK_P>;
+ clock-names = "pclk", "core", "ref_alt_clk_p";
+ power-domains = <&cpg>;
+ resets = <&cpg 0xab>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
sdhi0: mmc@15c00000 {
compatible = "renesas,sdhi-r9a09g057";
reg = <0x0 0x15c00000 0 0x10000>;
};
};
};
+
+ dsi: dsi@16430000 {
+ compatible = "renesas,r9a09g057-mipi-dsi";
+ reg = <0 0x16430000 0 0x20000>;
+ interrupts = <GIC_SPI 874 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 876 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 877 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 878 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 879 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 880 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "seq0", "seq1", "vin1", "rcv",
+ "ferr", "ppi", "debug";
+ clocks = <&cpg CPG_MOD 0xec>, <&cpg CPG_MOD 0xe9>,
+ <&cpg CPG_MOD 0xe8>, <&cpg CPG_MOD 0xea>,
+ <&cpg CPG_MOD 0xeb>;
+ clock-names = "pllrefclk", "aclk", "pclk", "vclk", "lpclk";
+ resets = <&cpg 0xd8>, <&cpg 0xd7>;
+ reset-names = "arst", "prst";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <&du_out_dsi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ };
+ };
+ };
+ };
+
+ du: display@16460000 {
+ compatible = "renesas,r9a09g057-du";
+ reg = <0 0x16460000 0 0x10000>;
+ interrupts = <GIC_SPI 882 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xed>, <&cpg CPG_MOD 0xee>,
+ <&cpg CPG_MOD 0xef>;
+ clock-names = "aclk", "pclk", "vclk";
+ power-domains = <&cpg>;
+ resets = <&cpg 0xdc>;
+ renesas,vsps = <&vspd 0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_dsi: endpoint {
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+ };
+ };
+
+ fcpvd: fcp@16470000 {
+ compatible = "renesas,r9a09g057-fcpvd", "renesas,fcpv";
+ reg = <0 0x16470000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0xed>,
+ <&cpg CPG_MOD 0xee>,
+ <&cpg CPG_MOD 0xef>;
+ clock-names = "aclk", "pclk", "vclk";
+ power-domains = <&cpg>;
+ resets = <&cpg 0xdc>;
+ };
+
+ vspd: vsp@16480000 {
+ compatible = "renesas,r9a09g057-vsp2", "renesas,r9a07g044-vsp2";
+ reg = <0 0x16480000 0 0x10000>;
+ interrupts = <GIC_SPI 881 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xed>,
+ <&cpg CPG_MOD 0xee>,
+ <&cpg CPG_MOD 0xef>;
+ clock-names = "aclk", "pclk", "vclk";
+ power-domains = <&cpg>;
+ resets = <&cpg 0xdc>;
+ renesas,fcp = <&fcpvd>;
+ };
};
stmmac_axi_setup: stmmac-axi-config {
stdout-path = "serial0:115200n8";
};
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "d";
+
+ port {
+ hdmi_con_out: endpoint {
+ remote-endpoint = <&adv7535_out>;
+ };
+ };
+ };
+
keys: keys {
compatible = "gpio-keys";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x1 0xF8000000>;
+ reg = <0x0 0x48000000 0x1 0xf8000000>;
};
memory@240000000 {
#clock-cells = <0>;
clock-frequency = <32768>;
};
+
+ /* 12MHz crystal for ADV7535 */
+ y1: y1-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12000000>;
+ };
};
&audio_extal_clk {
clock-frequency = <22579200>;
};
+&dsi {
+ status = "okay";
+
+ ports {
+ port@1 {
+ dsi_out: endpoint {
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&adv7535_in>;
+ };
+ };
+ };
+};
+
+&du {
+ status = "okay";
+};
+
&ehci0 {
dr_mode = "otg";
status = "okay";
clock-frequency = <400000>;
status = "okay";
+
+ adv7535: hdmi@3d {
+ compatible = "adi,adv7535";
+ reg = <0x3d>, <0x3f>, <0x3c>, <0x38>;
+ reg-names = "main", "edid", "cec", "packet";
+ interrupt-parent = <&pinctrl>;
+ interrupts = <RZV2H_GPIO(7, 1) IRQ_TYPE_EDGE_FALLING>;
+ clocks = <&y1>;
+ clock-names = "cec";
+ avdd-supply = <®_1p8v>;
+ dvdd-supply = <®_1p8v>;
+ pvdd-supply = <®_1p8v>;
+ a2vdd-supply = <®_1p8v>;
+ v3p3-supply = <®_3p3v>;
+ v1p2-supply = <®_1p8v>;
+ adi,dsi-lanes = <4>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7535_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7535_out: endpoint {
+ remote-endpoint = <&hdmi_con_out>;
+ };
+ };
+ };
+ };
};
&i2c6 {
};
};
+ usb30_pins: usb30 {
+ pinmux = <RZV2H_PORT_PINMUX(B, 0, 14)>, /* USB30_VBUSEN */
+ <RZV2H_PORT_PINMUX(B, 1, 14)>; /* USB30_OVRCURN */
+ };
+
+ usb31_pins: usb31 {
+ pinmux = <RZV2H_PORT_PINMUX(6, 2, 14)>, /* USB31_VBUSEN */
+ <RZV2H_PORT_PINMUX(6, 3, 14)>; /* USB31_OVRCURN */
+ };
+
xspi_pins: xspi0 {
ctrl {
pins = "XSPI0_RESET0N", "XSPI0_CS0N", "XSPI0_CKP";
status = "okay";
};
+&usb3_phy0 {
+ status = "okay";
+};
+
+&usb3_phy1 {
+ status = "okay";
+};
+
&wdt1 {
status = "okay";
};
+&xhci0 {
+ pinctrl-0 = <&usb30_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&xhci1 {
+ pinctrl-0 = <&usb31_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&xspi {
pinctrl-0 = <&xspi_pins>;
pinctrl-names = "default";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x1 0xF8000000>;
+ reg = <0x0 0x48000000 0x1 0xf8000000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
};
reg_3p3v: regulator-3v3 {
pinmux = <RZV2H_PORT_PINMUX(A, 5, 15)>; /* SD0_CD */
};
};
+
+ xspi_pins: xspi0 {
+ ctrl {
+ pins = "XSPI0_RESET0N", "XSPI0_CS0N", "XSPI0_CKP";
+ output-enable;
+ };
+
+ io {
+ pins = "XSPI0_IO0", "XSPI0_IO1", "XSPI0_IO2", "XSPI0_IO3";
+ renesas,output-impedance = <3>;
+ };
+ };
};
&qextal_clk {
status = "okay";
};
+
+&xspi {
+ pinctrl-0 = <&xspi_pins>;
+ pinctrl-names = "default";
+ assigned-clocks = <&cpg CPG_CORE R9A09G057_SPI_CLK_SPI>;
+ assigned-clock-rates = <133333334>;
+ status = "okay";
+
+ flash@0 {
+ /* W25Q256JWPIM */
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ vcc-supply = <®_1p8v>;
+ m25p,fast-read;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
#size-cells = <2>;
interrupt-parent = <&gic>;
+ cluster0_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C0>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@100 {
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C1>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu@200 {
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C2>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu3: cpu@300 {
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C3>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cluster0_opp>;
};
L3_CA55: cache-controller-0 {
status = "disabled";
};
+ rspi0: spi@80007000 {
+ compatible = "renesas,r9a09g077-rspi";
+ reg = <0x0 0x80007000 0x0 0x400>;
+ interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 638 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 634 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 635 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "idle", "error", "end", "rx", "tx";
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>,
+ <&cpg CPG_MOD 104>;
+ clock-names = "pclk", "pclkspi";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ rspi1: spi@80007400 {
+ compatible = "renesas,r9a09g077-rspi";
+ reg = <0x0 0x80007400 0x0 0x400>;
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 643 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 639 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "idle", "error", "end", "rx", "tx";
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>,
+ <&cpg CPG_MOD 105>;
+ clock-names = "pclk", "pclkspi";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ rspi2: spi@80007800 {
+ compatible = "renesas,r9a09g077-rspi";
+ reg = <0x0 0x80007800 0x0 0x400>;
+ interrupts = <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 648 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 644 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 645 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "idle", "error", "end", "rx", "tx";
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>,
+ <&cpg CPG_MOD 106>;
+ clock-names = "pclk", "pclkspi";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ rspi3: spi@81007000 {
+ compatible = "renesas,r9a09g077-rspi";
+ reg = <0x0 0x81007000 0x0 0x400>;
+ interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 653 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 649 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "idle", "error", "end", "rx", "tx";
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>,
+ <&cpg CPG_MOD 602>;
+ clock-names = "pclk", "pclkspi";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ canfd: can@80040000 {
+ compatible = "renesas,r9a09g077-canfd";
+ reg = <0 0x80040000 0 0x20000>;
+ interrupts = <GIC_SPI 633 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 632 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g_err", "g_recc",
+ "ch0_err", "ch0_rec", "ch0_trx",
+ "ch1_err", "ch1_rec", "ch1_trx";
+ clocks = <&cpg CPG_MOD 310>,
+ <&cpg CPG_CORE R9A09G077_CLK_PCLKH>,
+ <&cpg CPG_CORE R9A09G077_PCLKCAN>;
+ clock-names = "fck", "ram_clk", "can_clk";
+ assigned-clocks = <&cpg CPG_CORE R9A09G077_PCLKCAN>;
+ assigned-clock-rates = <80000000>;
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ channel0 {
+ status = "disabled";
+ };
+ channel1 {
+ status = "disabled";
+ };
+ };
+
wdt0: watchdog@80082000 {
compatible = "renesas,r9a09g077-wdt";
reg = <0 0x80082000 0 0x400>,
status = "disabled";
};
+ tsu: thermal@80086000 {
+ compatible = "renesas,r9a09g077-tsu";
+ reg = <0 0x80086000 0 0x1000>;
+ interrupts = <GIC_SPI 713 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "adi", "adcmpi";
+ clocks = <&cpg CPG_MOD 307>;
+ power-domains = <&cpg>;
+ #thermal-sensor-cells = <0>;
+ };
+
i2c0: i2c@80088000 {
compatible = "renesas,riic-r9a09g077";
reg = <0 0x80088000 0 0x400>;
status = "disabled";
};
+ dmac0: dma-controller@800c0000 {
+ compatible = "renesas,r9a09g077-dmac";
+ reg = <0 0x800c0000 0 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKH>;
+ power-domains = <&cpg>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 0>;
+ };
+
+ dmac1: dma-controller@800c1000 {
+ compatible = "renesas,r9a09g077-dmac";
+ reg = <0 0x800c1000 0 0x1000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKH>;
+ power-domains = <&cpg>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 1>;
+ };
+
+ dmac2: dma-controller@800c2000 {
+ compatible = "renesas,r9a09g077-dmac";
+ reg = <0 0x800c2000 0 0x1000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKH>;
+ power-domains = <&cpg>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 2>;
+ };
+
gmac0: ethernet@80100000 {
compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20";
reg = <0 0x80100000 0 0x10000>;
cpg: clock-controller@80280000 {
compatible = "renesas,r9a09g077-cpg-mssr";
- reg = <0 0x80280000 0 0x1000>,
- <0 0x81280000 0 0x9000>;
+ reg = <0 0x80280000 0 0x10000>,
+ <0 0x81280000 0 0x10000>;
clocks = <&extal_clk>;
clock-names = "extal";
#clock-cells = <2>;
#power-domain-cells = <0>;
};
+ icu: interrupt-controller@802a0000 {
+ compatible = "renesas,r9a09g077-icu";
+ reg = <0 0x802a0000 0 0x10000>,
+ <0 0x812a0000 0 0x10000>;
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 7 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 9 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 14 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 16 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 408 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 409 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 412 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 413 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 415 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 416 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 417 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 418 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "intcpu0", "intcpu1", "intcpu2",
+ "intcpu3", "intcpu4", "intcpu5",
+ "intcpu6", "intcpu7", "intcpu8",
+ "intcpu9", "intcpu10", "intcpu11",
+ "intcpu12", "intcpu13", "intcpu14",
+ "intcpu15",
+ "irq0", "irq1", "irq2", "irq3",
+ "irq4", "irq5", "irq6", "irq7",
+ "irq8", "irq9", "irq10", "irq11",
+ "irq12", "irq13", "irq14", "irq15",
+ "sei",
+ "ca55-err0", "ca55-err1",
+ "cr520-err0", "cr520-err1",
+ "cr521-err0", "cr521-err1",
+ "peri-err0", "peri-err1",
+ "dsmif-err0", "dsmif-err1",
+ "encif-err0", "encif-err1";
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
+ power-domains = <&cpg>;
+ };
+
pinctrl: pinctrl@802c0000 {
compatible = "renesas,r9a09g077-pinctrl";
reg = <0 0x802c0000 0 0x10000>,
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 288>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&icu>;
power-domains = <&cpg>;
};
snps,blen = <16 8 4 0 0 0 0>;
};
+ thermal-zones {
+ cpu-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&tsu>;
+
+ cooling-maps {
+ map0 {
+ trip = <&target>;
+ cooling-device = <&cpu0 0 1>, <&cpu1 0 1>,
+ <&cpu2 0 1>, <&cpu3 0 1>;
+ contribution = <1024>;
+ };
+ };
+
+ trips {
+ target: trip-point {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ sensor_crit: sensor-crit {
+ temperature = <120000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
/dts-v1/;
+#include <dt-bindings/input/input.h>
+
#include "r9a09g077m44.dtsi"
/*
* P17_4 = SD1_CD; SW2[3] = ON
* P08_5 = SD1_PWEN; SW2[3] = ON
* P08_6 = SD1_IOVS; SW2[3] = ON; SW5[3] = OFF; SW5[4] = ON
+ * To enable proper operation in 1.8V modes, CN77 must have pins 2 and 3
+ * connected by the jumper. This connects SD1 power-supply control IC output
+ * back to VCC1833_7.
*/
#define SD1_MICRO_SD 1
model = "Renesas RZ/T2H EVK Board based on r9a09g077m44";
compatible = "renesas,rzt2h-evk", "renesas,r9a09g077m44", "renesas,r9a09g077";
+ keys {
+ compatible = "gpio-keys";
+
+#if (!SD1_MICRO_SD)
+ /* SW2-3: OFF */
+ key-1 {
+ interrupts-extended = <&pinctrl RZT2H_GPIO(8, 6) IRQ_TYPE_EDGE_FALLING>;
+ linux,code = <KEY_1>;
+ label = "SW9";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+#endif
+
+ key-2 {
+ interrupts-extended = <&pinctrl RZT2H_GPIO(0, 3) IRQ_TYPE_EDGE_FALLING>;
+ linux,code = <KEY_2>;
+ label = "SW10";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+
+ key-3 {
+ interrupts-extended = <&pinctrl RZT2H_GPIO(8, 7) IRQ_TYPE_EDGE_FALLING>;
+ linux,code = <KEY_3>;
+ label = "SW11";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ };
+
leds {
compatible = "gpio-leds";
};
};
+&adc2 {
+ status = "okay";
+
+ channel@0 {
+ reg = <0x0>;
+ };
+
+ channel@1 {
+ reg = <0x1>;
+ };
+
+ channel@2 {
+ reg = <0x2>;
+ };
+
+ channel@3 {
+ reg = <0x3>;
+ };
+
+ channel@4 {
+ reg = <0x4>;
+ };
+
+ channel@5 {
+ reg = <0x5>;
+ };
+};
+
+&canfd {
+ pinctrl-0 = <&can0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ channel0 {
+ status = "okay";
+ };
+};
+
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
};
&pinctrl {
+ /*
+ * CAN0 Pin Configuration:
+ *
+ * SW7[1] OFF; SW7[2] ON - Use P24_4 as CANTX0.
+ * SW7[3] OFF; SW7[4] ON - Use P24_3 as CANRX0.
+ */
+ can0_pins: can0-pins {
+ pinmux = <RZT2H_PORT_PINMUX(24, 3, 0x19)>, /* CANRX0 */
+ <RZT2H_PORT_PINMUX(24, 4, 0x19)>; /* CANTX0 */
+ };
+
/*
* GMAC2 Pin Configuration:
*
};
};
-&adc2 {
- status = "okay";
-
- channel@0 {
- reg = <0x0>;
- };
-
- channel@1 {
- reg = <0x1>;
- };
-
- channel@2 {
- reg = <0x2>;
- };
-
- channel@3 {
- reg = <0x3>;
- };
-
- channel@4 {
- reg = <0x4>;
- };
-
- channel@5 {
- reg = <0x5>;
- };
-};
#size-cells = <2>;
interrupt-parent = <&gic>;
+ cluster0_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C0>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@100 {
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C1>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu@200 {
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C2>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cluster0_opp>;
};
cpu3: cpu@300 {
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C3>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cluster0_opp>;
};
L3_CA55: cache-controller-0 {
status = "disabled";
};
+ rspi0: spi@80007000 {
+ compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi";
+ reg = <0x0 0x80007000 0x0 0x400>;
+ interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 638 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 634 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 635 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "idle", "error", "end", "rx", "tx";
+ clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>,
+ <&cpg CPG_MOD 104>;
+ clock-names = "pclk", "pclkspi";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ rspi1: spi@80007400 {
+ compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi";
+ reg = <0x0 0x80007400 0x0 0x400>;
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 643 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 639 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "idle", "error", "end", "rx", "tx";
+ clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>,
+ <&cpg CPG_MOD 105>;
+ clock-names = "pclk", "pclkspi";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ rspi2: spi@80007800 {
+ compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi";
+ reg = <0x0 0x80007800 0x0 0x400>;
+ interrupts = <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 648 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 644 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 645 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "idle", "error", "end", "rx", "tx";
+ clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>,
+ <&cpg CPG_MOD 106>;
+ clock-names = "pclk", "pclkspi";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ rspi3: spi@81007000 {
+ compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi";
+ reg = <0x0 0x81007000 0x0 0x400>;
+ interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 653 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 649 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "idle", "error", "end", "rx", "tx";
+ clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>,
+ <&cpg CPG_MOD 602>;
+ clock-names = "pclk", "pclkspi";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ canfd: can@80040000 {
+ compatible = "renesas,r9a09g087-canfd", "renesas,r9a09g077-canfd";
+ reg = <0 0x80040000 0 0x20000>;
+ interrupts = <GIC_SPI 633 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 632 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g_err", "g_recc",
+ "ch0_err", "ch0_rec", "ch0_trx",
+ "ch1_err", "ch1_rec", "ch1_trx";
+ clocks = <&cpg CPG_MOD 310>,
+ <&cpg CPG_CORE R9A09G087_CLK_PCLKH>,
+ <&cpg CPG_CORE R9A09G087_PCLKCAN>;
+ clock-names = "fck", "ram_clk", "can_clk";
+ assigned-clocks = <&cpg CPG_CORE R9A09G087_PCLKCAN>;
+ assigned-clock-rates = <80000000>;
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ channel0 {
+ status = "disabled";
+ };
+ channel1 {
+ status = "disabled";
+ };
+ };
+
wdt0: watchdog@80082000 {
compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt";
reg = <0 0x80082000 0 0x400>,
status = "disabled";
};
+ tsu: thermal@80086000 {
+ compatible = "renesas,r9a09g087-tsu", "renesas,r9a09g077-tsu";
+ reg = <0 0x80086000 0 0x1000>;
+ interrupts = <GIC_SPI 713 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "adi", "adcmpi";
+ clocks = <&cpg CPG_MOD 307>;
+ power-domains = <&cpg>;
+ #thermal-sensor-cells = <0>;
+ };
+
i2c0: i2c@80088000 {
compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077";
reg = <0 0x80088000 0 0x400>;
status = "disabled";
};
+ dmac0: dma-controller@800c0000 {
+ compatible = "renesas,r9a09g087-dmac", "renesas,r9a09g077-dmac";
+ reg = <0 0x800c0000 0 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKH>;
+ power-domains = <&cpg>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 0>;
+ };
+
+ dmac1: dma-controller@800c1000 {
+ compatible = "renesas,r9a09g087-dmac", "renesas,r9a09g077-dmac";
+ reg = <0 0x800c1000 0 0x1000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKH>;
+ power-domains = <&cpg>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 1>;
+ };
+
+ dmac2: dma-controller@800c2000 {
+ compatible = "renesas,r9a09g087-dmac", "renesas,r9a09g077-dmac";
+ reg = <0 0x800c2000 0 0x1000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKH>;
+ power-domains = <&cpg>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 2>;
+ };
+
gmac0: ethernet@80100000 {
compatible = "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth",
"snps,dwmac-5.20";
cpg: clock-controller@80280000 {
compatible = "renesas,r9a09g087-cpg-mssr";
- reg = <0 0x80280000 0 0x1000>,
- <0 0x81280000 0 0x9000>;
+ reg = <0 0x80280000 0 0x10000>,
+ <0 0x81280000 0 0x10000>;
clocks = <&extal_clk>;
clock-names = "extal";
#clock-cells = <2>;
#power-domain-cells = <0>;
};
+ icu: interrupt-controller@802a0000 {
+ compatible = "renesas,r9a09g087-icu", "renesas,r9a09g077-icu";
+ reg = <0 0x802a0000 0 0x10000>,
+ <0 0x812a0000 0 0x10000>;
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 7 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 9 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 14 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 16 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 408 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 409 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 412 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 413 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 415 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 416 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 417 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 418 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "intcpu0", "intcpu1", "intcpu2",
+ "intcpu3", "intcpu4", "intcpu5",
+ "intcpu6", "intcpu7", "intcpu8",
+ "intcpu9", "intcpu10", "intcpu11",
+ "intcpu12", "intcpu13", "intcpu14",
+ "intcpu15",
+ "irq0", "irq1", "irq2", "irq3",
+ "irq4", "irq5", "irq6", "irq7",
+ "irq8", "irq9", "irq10", "irq11",
+ "irq12", "irq13", "irq14", "irq15",
+ "sei",
+ "ca55-err0", "ca55-err1",
+ "cr520-err0", "cr520-err1",
+ "cr521-err0", "cr521-err1",
+ "peri-err0", "peri-err1",
+ "dsmif-err0", "dsmif-err1",
+ "encif-err0", "encif-err1";
+ clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
+ power-domains = <&cpg>;
+ };
+
pinctrl: pinctrl@802c0000 {
compatible = "renesas,r9a09g087-pinctrl";
reg = <0 0x802c0000 0 0x10000>,
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 280>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&icu>;
power-domains = <&cpg>;
};
snps,blen = <16 8 4 0 0 0 0>;
};
+ thermal-zones {
+ cpu-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&tsu>;
+
+ cooling-maps {
+ map0 {
+ trip = <&target>;
+ cooling-device = <&cpu0 0 1>, <&cpu1 0 1>,
+ <&cpu2 0 1>, <&cpu3 0 1>;
+ contribution = <1024>;
+ };
+ };
+
+ trips {
+ target: trip-point {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ sensor_crit: sensor-crit {
+ temperature = <120000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
/dts-v1/;
+#include <dt-bindings/input/input.h>
+
#include "r9a09g087m44.dtsi"
/*
#define SD0_EMMC 1
#define SD0_SD (!SD0_EMMC)
+/*
+ * To enable CANFD interface disable both eMMC and SD card on SDHI0 by
+ * setting SD0_EMMC and SD0_SD macros to 0 as pins P12_0 and P12_1
+ * will be used for CANFD interface.
+ */
+#define CANFD_ENABLE (!SD0_EMMC && !SD0_SD)
+
/*
* P17_4 = SD1_CD; DSW5[3] = ON; DSW19[1] = OFF; DSW19[2] = ON
* P08_6 = SD1_IOVS; DSW5[3] = ON
+ * To enable proper operation in 1.8V modes, JP21 must have pins 2 and 3
+ * connected by the jumper. This connects SD1 power-supply control IC output
+ * back to VCC1833_7.
*/
#define SD1_MICRO_SD 1
model = "Renesas RZ/N2H EVK Board based on r9a09g087m44";
compatible = "renesas,rzn2h-evk", "renesas,r9a09g087m44", "renesas,r9a09g087";
+ keys {
+ compatible = "gpio-keys";
+
+ key-1 {
+ interrupts-extended = <&pinctrl RZT2H_GPIO(18, 2) IRQ_TYPE_EDGE_FALLING>;
+ linux,code = <KEY_1>;
+ label = "SW2";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+
+ key-2 {
+ interrupts-extended = <&pinctrl RZT2H_GPIO(0, 4) IRQ_TYPE_EDGE_FALLING>;
+ linux,code = <KEY_2>;
+ label = "SW3";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+
+ key-3 {
+ interrupts-extended = <&pinctrl RZT2H_GPIO(18, 7) IRQ_TYPE_EDGE_FALLING>;
+ linux,code = <KEY_3>;
+ label = "SW4";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ };
+
leds {
compatible = "gpio-leds";
};
};
+&adc2 {
+ status = "okay";
+
+ channel@0 {
+ reg = <0x0>;
+ };
+
+ channel@1 {
+ reg = <0x1>;
+ };
+
+ channel@2 {
+ reg = <0x2>;
+ };
+
+ channel@3 {
+ reg = <0x3>;
+ };
+
+ channel@4 {
+ reg = <0x4>;
+ };
+
+ channel@5 {
+ reg = <0x5>;
+ };
+
+ channel@6 {
+ reg = <0x6>;
+ };
+
+ channel@7 {
+ reg = <0x7>;
+ };
+
+ channel@8 {
+ reg = <0x8>;
+ };
+
+ channel@9 {
+ reg = <0x9>;
+ };
+
+ channel@a {
+ reg = <0xa>;
+ };
+
+ channel@b {
+ reg = <0xb>;
+ };
+
+ channel@c {
+ reg = <0xc>;
+ };
+
+ channel@d {
+ reg = <0xd>;
+ };
+
+ channel@e {
+ reg = <0xe>;
+ };
+};
+
+#if CANFD_ENABLE
+&canfd {
+ pinctrl-0 = <&can1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ channel1 {
+ status = "okay";
+ };
+};
+#endif
+
#if I2C0
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
};
&pinctrl {
+ /*
+ * CAN1 Pin Configuration:
+ *
+ * DSW5[1] ON; DSW5[2] OFF - Use P12_0 and P12_1 for CAN1 interface.
+ */
+ can1_pins: can1-pins {
+ pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x19)>, /* CANRX1 */
+ <RZT2H_PORT_PINMUX(12, 1, 0x19)>; /* CANTX1 */
+ };
+
/*
* GMAC2 Pin Configuration:
*
};
};
-&adc2 {
- status = "okay";
-
- channel@0 {
- reg = <0x0>;
- };
-
- channel@1 {
- reg = <0x1>;
- };
-
- channel@2 {
- reg = <0x2>;
- };
-
- channel@3 {
- reg = <0x3>;
- };
-
- channel@4 {
- reg = <0x4>;
- };
-
- channel@5 {
- reg = <0x5>;
- };
-
- channel@6 {
- reg = <0x6>;
- };
-
- channel@7 {
- reg = <0x7>;
- };
-
- channel@8 {
- reg = <0x8>;
- };
-
- channel@9 {
- reg = <0x9>;
- };
-
- channel@a {
- reg = <0xa>;
- };
-
- channel@b {
- reg = <0xb>;
- };
-
- channel@c {
- reg = <0xc>;
- };
-
- channel@d {
- reg = <0xd>;
- };
-
- channel@e {
- reg = <0xe>;
- };
-};
* 0 - SMARC SDIO signal is connected to uSD1
* 1 - SMARC SDIO signal is connected to M.2 Key E connector
*
+ * Please set the switch position SW_OPT_MUX.4 on the carrier board and the
+ * corresponding macro SW_SER0_PMOD on the board DTS:
+ *
+ * SW_SER0_PMOD:
+ * 0 - SER0 signals connect to M.2 Key-E, SER2 signals are unconnected
+ * 1 - SER0 signals connect to PMOD, SER2 signals connect to M.2 Key-E
+ *
* Please set the switch position SW_GPIO_CAN_PMOD on the carrier board and the
* corresponding macro SW_GPIO8_CAN0_STB/SW_GPIO8_CAN0_STB on the board DTS:
*
stdout-path = "serial3:115200n8";
};
- aliases {
- i2c0 = &i2c0;
- serial3 = &scif0;
- mmc1 = &sdhi1;
- };
-
can_transceiver0: can-phy0 {
compatible = "ti,tcan1042";
#phy-cells = <0>;
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
* 0 - SD0 is connected to eMMC (default)
* 1 - SD0 is connected to uSD0 card
*
+ * Switch position SYS.4, Macro SW_SER2_EN:
+ * 0 - Select Module DSI connector(GPIO)
+ * 1 - Select SER2
+ *
* Switch position SYS.5, Macro SW_LCD_EN:
* 0 - Select Misc. Signals routing
* 1 - Select LCD
};
};
+&i3c {
+ pinctrl-0 = <&i3c_pins>;
+ pinctrl-names = "default";
+ i2c-scl-hz = <400000>;
+ i3c-scl-hz = <12500000>;
+ status = "okay";
+};
+
&mdio0 {
phy0: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
<RZG3E_PORT_PINMUX(3, 5, 1)>; /* SDA2 */
};
+ i3c_pins: i3c {
+ pinmux = <RZG3E_PORT_PINMUX(2, 0, 2)>, /* I3C0_SCL */
+ <RZG3E_PORT_PINMUX(2, 1, 2)>; /* I3C0_SDA */
+ drive-push-pull;
+ };
+
rtc_irq_pin: rtc-irq {
pins = "PS1";
bias-pull-up;
<100000000>;
renesas,settings = [
80 00 11 19 4c 42 dc 2f 06 7d 20 1a 5f 1e f2 27
- 00 40 00 00 00 00 00 00 06 0c 19 02 3f f0 90 86
+ 00 40 00 00 00 00 00 00 06 0c 19 02 3b f0 90 86
a0 80 30 30 9c
];
};
};
+&pcie_port0 {
+ clocks = <&versa3 5>;
+ clock-names = "ref";
+};
+
#if SW_CONFIG2 == SW_ON
/* SD0 slot */
&sdhi0 {
status = "okay";
};
+&pcie {
+ pinctrl-0 = <&pcie_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&phyrst {
status = "okay";
};
line-name = "key-3-gpio-irq";
};
+ pcie_pins: pcie {
+ pinmux = <RZG2L_PORT_PINMUX(13, 2, 2)>, /* PCIE_RST_OUT_B */
+ <RZG2L_PORT_PINMUX(13, 3, 2)>; /* PCIE_CLKREQ_B */
+ };
+
scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(6, 3, 1)>, /* RXD */
<RZG2L_PORT_PINMUX(6, 4, 1)>; /* TXD */
regulator-max-microvolt = <3300000>;
gpios-states = <0>;
states = <3300000 0>, <1800000 1>;
+ regulator-ramp-delay = <60>;
};
#endif
#endif
};
+/*
+ * ADC0 AN000 can be connected to a potentiometer on the board or
+ * exposed on ADC header.
+ *
+ * T2H:
+ * SW17[1] = ON, SW17[2] = OFF - Potentiometer
+ * SW17[1] = OFF, SW17[2] = ON - CN41 header
+ * N2H:
+ * DSW6[1] = OFF, DSW6[2] = ON - Potentiometer
+ * DSW6[1] = ON, DSW6[2] = OFF - CN3 header
+ */
+&adc0 {
+ status = "okay";
+
+ channel@0 {
+ reg = <0x0>;
+ };
+
+ channel@1 {
+ reg = <0x1>;
+ };
+
+ channel@2 {
+ reg = <0x2>;
+ };
+
+ channel@3 {
+ reg = <0x3>;
+ };
+};
+
+/*
+ * ADC1 AN100 can be exposed on ADC header or on mikroBUS connector.
+ *
+ * T2H:
+ * SW18[1] = ON, SW18[2] = OFF - CN42 header
+ * SW18[1] = OFF, SW18[2] = ON - mikroBUS
+ * N2H:
+ * DSW6[3] = ON, DSW6[4] = OFF - CN4 header
+ * DSW6[3] = OFF, DSW6[4] = ON - mikroBUS
+ *
+ * ADC1 AN101 can be exposed on ADC header or on Grove2 connector.
+ *
+ * T2H:
+ * SW18[3] = ON, SW18[4] = OFF - CN42 header
+ * SW18[3] = OFF, SW18[4] = ON - Grove2
+ * N2H:
+ * DSW6[5] = ON, DSW6[6] = OFF - CN4 header
+ * DSW6[5] = OFF, DSW6[6] = ON - Grove2
+ *
+ * ADC1 AN102 can be exposed on ADC header or on Grove2 connector.
+ *
+ * T2H:
+ * SW18[5] = ON, SW18[6] = OFF - CN42 header
+ * SW18[5] = OFF, SW18[6] = ON - Grove2
+ * N2H:
+ * DSW6[7] = ON, DSW6[8] = OFF - CN4 header
+ * DSW6[7] = OFF, DSW6[8] = ON - Grove2
+ */
+&adc1 {
+ status = "okay";
+
+ channel@0 {
+ reg = <0x0>;
+ };
+
+ channel@1 {
+ reg = <0x1>;
+ };
+
+ channel@2 {
+ reg = <0x2>;
+ };
+
+ channel@3 {
+ reg = <0x3>;
+ };
+};
+
&ehci {
dr_mode = "otg";
status = "okay";
ctrl-pins {
pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
<RZT2H_PORT_PINMUX(12, 1, 0x29)>, /* SD0_CMD */
- <RZT2H_PORT_PINMUX(22, 5, 0x29)>, /* SD0_CD */
- <RZT2H_PORT_PINMUX(22, 6, 0x29)>; /* SD0_WP */
+ <RZT2H_PORT_PINMUX(22, 5, 0x29)>; /* SD0_CD */
};
};
pinctrl-names = "default", "state_uhs";
vmmc-supply = <®_3p3v>;
vqmmc-supply = <&vqmmc_sdhi0>;
+ wp-gpios = <&pinctrl RZT2H_GPIO(22, 6) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
timeout-sec = <60>;
};
-/*
- * ADC0 AN000 can be connected to a potentiometer on the board or
- * exposed on ADC header.
- *
- * T2H:
- * SW17[1] = ON, SW17[2] = OFF - Potentiometer
- * SW17[1] = OFF, SW17[2] = ON - CN41 header
- * N2H:
- * DSW6[1] = OFF, DSW6[2] = ON - Potentiometer
- * DSW6[1] = ON, DSW6[2] = OFF - CN3 header
- */
-&adc0 {
- status = "okay";
-
- channel@0 {
- reg = <0x0>;
- };
-
- channel@1 {
- reg = <0x1>;
- };
-
- channel@2 {
- reg = <0x2>;
- };
-
- channel@3 {
- reg = <0x3>;
- };
-};
-
-/*
- * ADC1 AN100 can be exposed on ADC header or on mikroBUS connector.
- *
- * T2H:
- * SW18[1] = ON, SW18[2] = OFF - CN42 header
- * SW18[1] = OFF, SW18[2] = ON - mikroBUS
- * N2H:
- * DSW6[3] = ON, DSW6[4] = OFF - CN4 header
- * DSW6[3] = OFF, DSW6[4] = ON - mikroBUS
- *
- * ADC1 AN101 can be exposed on ADC header or on Grove2 connector.
- *
- * T2H:
- * SW18[3] = ON, SW18[4] = OFF - CN42 header
- * SW18[3] = OFF, SW18[4] = ON - Grove2
- * N2H:
- * DSW6[5] = ON, DSW6[6] = OFF - CN4 header
- * DSW6[5] = OFF, DSW6[6] = ON - Grove2
- *
- * ADC1 AN102 can be exposed on ADC header or on Grove2 connector.
- *
- * T2H:
- * SW18[5] = ON, SW18[6] = OFF - CN42 header
- * SW18[5] = OFF, SW18[6] = ON - Grove2
- * N2H:
- * DSW6[7] = ON, DSW6[8] = OFF - CN4 header
- * DSW6[7] = OFF, DSW6[8] = ON - Grove2
- */
-&adc1 {
- status = "okay";
-
- channel@0 {
- reg = <0x0>;
- };
-
- channel@1 {
- reg = <0x1>;
- };
-
- channel@2 {
- reg = <0x2>;
- };
-
- channel@3 {
- reg = <0x3>;
- };
-};
regulator-max-microvolt = <3300000>;
gpios-states = <0>;
states = <3300000 0>, <1800000 1>;
+ regulator-ramp-delay = <60>;
};
};
};
};
- cs2000: clk_multiplier@4f {
+ cs2000: clk-multiplier@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;
reg = <0x00040000 0x140000>;
read-only;
};
- cert_header_sa6@180000 {
+ cert-header-sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
reg = <0x00040000 0x140000>;
read-only;
};
- cert_header_sa6@180000 {
+ cert-header-sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2025 Cherry Embedded Solutions GmbH
+ *
+ * DEVKIT ADDON CAM-TS-A01
+ * https://embedded.cherry.de/product/development-kit/
+ *
+ * DT-overlay for the camera / DSI demo appliance for Haikou boards.
+ * In the flavour for use with a Lion system-on-module.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/rk3368-cru.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+&{/} {
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ power-supply = <&dc_12v>;
+ pwms = <&pwm1 0 25000 0>;
+ };
+
+ cam_afvdd_2v8: regulator-cam-afvdd-2v8 {
+ compatible = "regulator-fixed";
+ gpio = <&pca9670 2 GPIO_ACTIVE_LOW>;
+ regulator-max-microvolt = <2800000>;
+ regulator-min-microvolt = <2800000>;
+ regulator-name = "cam-afvdd-2v8";
+ vin-supply = <&vcc2v8_video>;
+ };
+
+ cam_avdd_2v8: regulator-cam-avdd-2v8 {
+ compatible = "regulator-fixed";
+ gpio = <&pca9670 4 GPIO_ACTIVE_LOW>;
+ regulator-max-microvolt = <2800000>;
+ regulator-min-microvolt = <2800000>;
+ regulator-name = "cam-avdd-2v8";
+ vin-supply = <&vcc2v8_video>;
+ };
+
+ cam_dovdd_1v8: regulator-cam-dovdd-1v8 {
+ compatible = "regulator-fixed";
+ gpio = <&pca9670 3 GPIO_ACTIVE_LOW>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "cam-dovdd-1v8";
+ vin-supply = <&vcc1v8_video>;
+ };
+
+ cam_dvdd_1v2: regulator-cam-dvdd-1v2 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&pca9670 5 GPIO_ACTIVE_HIGH>;
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microvolt = <1200000>;
+ regulator-name = "cam-dvdd-1v2";
+ vin-supply = <&vcc3v3_baseboard>;
+ };
+
+ vcc1v8_video: regulator-vcc1v8-video {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "vcc1v8-video";
+ vin-supply = <&vcc3v3_baseboard>;
+ };
+
+ vcc2v8_video: regulator-vcc2v8-video {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <2800000>;
+ regulator-min-microvolt = <2800000>;
+ regulator-name = "vcc2v8-video";
+ vin-supply = <&vcc3v3_baseboard>;
+ };
+
+ video-adapter-leds {
+ compatible = "gpio-leds";
+
+ video-adapter-led {
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&pca9670 7 GPIO_ACTIVE_HIGH>;
+ label = "video-adapter-led";
+ linux,default-trigger = "none";
+ };
+ };
+};
+
+&dphy {
+ status = "okay";
+};
+
+&i2c_gp2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* OV5675, GT911, DW9714 are limited to 400KHz */
+ clock-frequency = <400000>;
+
+ touchscreen@14 {
+ compatible = "goodix,gt911";
+ reg = <0x14>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PB5 IRQ_TYPE_LEVEL_LOW>;
+ irq-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&touch_int>;
+ pinctrl-names = "default";
+ reset-gpios = <&pca9670 1 GPIO_ACTIVE_HIGH>;
+ AVDD28-supply = <&vcc2v8_video>;
+ VDDIO-supply = <&vcc3v3_baseboard>;
+ };
+
+ pca9670: gpio@27 {
+ compatible = "nxp,pca9670";
+ reg = <0x27>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-0 = <&pca9670_resetn>;
+ pinctrl-names = "default";
+ reset-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&mipi_dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ panel@0 {
+ compatible = "leadtek,ltk050h3148w";
+ reg = <0>;
+ backlight = <&backlight>;
+ iovcc-supply = <&vcc1v8_video>;
+ reset-gpios = <&pca9670 0 GPIO_ACTIVE_LOW>;
+ vci-supply = <&vcc2v8_video>;
+
+ port {
+ mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+ };
+ };
+ };
+};
+
+&mipi_out {
+ mipi_out_panel: endpoint {
+ remote-endpoint = <&mipi_in_panel>;
+ };
+};
+
+&pinctrl {
+ pca9670 {
+ pca9670_resetn: pca9670-resetn {
+ rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ touch {
+ touch_int: touch-int {
+ rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
stdout-path = "serial0:115200n8";
};
- i2cmux2 {
- i2c@0 {
- eeprom: eeprom@50 {
- compatible = "atmel,24c01";
- pagesize = <8>;
- reg = <0x50>;
- };
- };
- };
-
leds {
pinctrl-0 = <&module_led_pins>, <&sd_card_led_pin>;
};
};
+&display_subsystem {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&i2c_lvds_blc {
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c01";
+ pagesize = <8>;
+ reg = <0x50>;
+ };
+};
+
+&pwm1 {
+ status = "okay";
+};
+
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
status = "disabled";
};
+&vop {
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&haikou_pin_hog>;
assigned-clocks = <&cru SCLK_MAC>;
assigned-clock-parents = <&ext_gmac>;
clock_in_out = "input";
+ phy-handle = <&vsc8531_2>;
phy-supply = <&vcc33_io>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
- snps,reset-gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
tx_delay = <0x10>;
rx_delay = <0x10>;
status = "okay";
};
+&hdmi {
+ avdd-0v9-supply = <&vdd10_video>;
+ avdd-1v8-supply = <&vcc18_video>;
+};
+
&i2c0 {
status = "okay";
status = "okay";
};
+&mdio {
+ vsc8531_2: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&phy_rst>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <50000>;
+ reset-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
+ };
+};
+
&pinctrl {
+ ethernet {
+ phy_rst: phy-rst {
+ rockchip,pins = <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
leds {
module_led_pins: module-led-pins {
rockchip,pins =
"mac_clk_rx", "mac_clk_tx",
"clk_mac_ref", "clk_mac_refout",
"aclk_mac", "pclk_mac";
+ resets = <&cru SRST_MAC>;
+ reset-names = "stmmaceth";
status = "disabled";
+
+ mdio: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
usb_host0_ehci: usb@ff500000 {
reg = <0>;
remote-endpoint = <&dsi_in_vop>;
};
+
+ vop_out_hdmi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&hdmi_in_vop>;
+ };
};
};
status = "disabled";
};
+ hdmi: hdmi@ff980000 {
+ compatible = "rockchip,rk3368-dw-hdmi";
+ reg = <0x0 0xff980000 0x0 0x20000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
+ clock-names = "iahb", "isfr", "cec";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_i2c_xfer>;
+ power-domains = <&power RK3368_PD_VIO>;
+ reg-io-width = <4>;
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ reg = <0>;
+
+ hdmi_in_vop: endpoint {
+ remote-endpoint = <&vop_out_hdmi>;
+ };
+ };
+
+ hdmi_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
hevc_mmu: iommu@ff9a0440 {
compatible = "rockchip,iommu";
reg = <0x0 0xff9a0440 0x0 0x40>,
};
};
+ hdmi {
+ hdmi_i2c_xfer: hdmi-i2c-xfer {
+ rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>,
+ <3 RK_PD3 1 &pcfg_pull_none>;
+ };
+ };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
status = "okay";
};
-&hdmi_sound {
- status = "okay";
-};
-
&i2c0 {
clock-frequency = <400000>;
i2c-scl-falling-time-ns = <4>;
};
};
- wifi {
- wifi_host_wake_l: wifi-host-wake-l {
- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
wireless-bluetooth {
bt_wake_pin: bt-wake-pin {
rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
- #address-cells = <1>;
- #size-cells = <0>;
status = "okay";
-
- brcmf: wifi@1 {
- compatible = "brcm,bcm4329-fmac";
- reg = <1>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host-wake";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_host_wake_l>;
- };
};
&sdhci {
status = "okay";
wcam: camera@1a {
- compatible = "sony,imx258";
+ compatible = "sony,imx258-pdaf";
reg = <0x1a>;
clocks = <&cru SCLK_CIF_OUT>; /* MIPI_MCLK0, derived from CIF_CLKO */
lens-focus = <&wcam_lens>;
touchscreen-size-x = <720>;
touchscreen-size-y = <1440>;
};
+
+ light-sensor@48 {
+ compatible = "sensortek,stk3311";
+ reg = <0x48>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <RK_PD3 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&light_int_l>;
+ proximity-near-level = <300>;
+ };
};
&i2c4 {
reg = <0x68>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PC6 IRQ_TYPE_LEVEL_LOW>;
+ vdd-supply = <&vcc_1v8>;
vddio-supply = <&vcc_1v8>;
+
+ mount-matrix =
+ "1", "0", "0",
+ "0", "-1", "0",
+ "0", "0", "-1";
+ };
+};
+
+&i2c4 {
+ af8133j: compass@1c {
+ compatible = "voltafield,af8133j";
+ reg = <0x1c>;
+ avdd-supply = <&vcc_3v0>;
+ dvdd-supply = <&vcc_1v8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&compass_rst_l>;
+ reset-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>;
+
+ mount-matrix =
+ "0", "1", "0",
+ "-1", "0", "0",
+ "0", "0", "1";
};
};
};
};
+ compass {
+ compass_rst_l: compass-rst-l {
+ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
leds {
red_led_pin: red-led-pin {
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+ stk3311 {
+ light_int_l: light-int-l {
+ rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_input_pull_up>;
+ };
+ };
+
wifi {
wifi_host_wake_l: wifi-host-wake-l {
rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
reg = <0x11>;
clocks = <&cru SCLK_I2S_8CH_OUT>;
#sound-dai-cells = <0>;
+ AVDD-supply = <&vcca3v0_codec>;
+ DVDD-supply = <&vcca1v8_codec>;
+ HPVDD-supply = <&vcca3v0_codec>;
+ PVDD-supply = <&vcca1v8_codec>;
};
};
vcca3v0_codec: LDO_REG5 {
regulator-name = "vcca3v0_codec";
- regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-off-in-suspend;
};
};
+
+ eeprom@50 {
+ compatible = "belling,bl24c04a", "atmel,24c04";
+ reg = <0x50>;
+ pagesize = <16>;
+ read-only;
+ vcc-supply = <&vcc_3v0_s0>;
+ };
};
&i2c3 {
#include "rk3399-t.dtsi"
#include "rk3399-rock-pi-4.dtsi"
+/delete-node/ &eeprom;
+
/ {
model = "Radxa ROCK 4SE";
compatible = "radxa,rock-4se", "rockchip,rk3399";
};
};
+&i2c0 {
+ eeprom@50 {
+ compatible = "belling,bl24c16a", "atmel,24c16";
+ reg = <0x50>;
+ pagesize = <16>;
+ read-only;
+ vcc-supply = <&vcc_3v0>;
+ };
+};
+
&sdio0 {
status = "okay";
regulator-off-in-suspend;
};
};
+
+ eeprom: eeprom@50 {
+ compatible = "belling,bl24c04a", "atmel,24c04";
+ reg = <0x50>;
+ pagesize = <16>;
+ read-only;
+ vcc-supply = <&vcc_3v0>;
+ };
};
&i2c1 {
};
};
};
+
+&uart0 {
+ bluetooth {
+ compatible = "brcm,bcm4345c5";
+ max-speed = <1500000>;
+ };
+};
};
};
};
+
+&uart0 {
+ bluetooth {
+ compatible = "brcm,bcm4345c5";
+ max-speed = <1500000>;
+ };
+};
};
};
+&combphy {
+ status = "okay";
+};
+
&cpu0 {
cpu-supply = <&vdd_arm>;
};
};
};
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie20_perstn>;
+ reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
&pinctrl {
bluetooth {
bt_reg_on_h: bt-reg-on-h {
};
};
+ pcie {
+ pcie20_perstn: pcie20-perstn {
+ rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
rtc {
rtc_int_l: rtc-int-l {
rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
+
+ ebc_pmic: pmic@68 {
+ compatible = "ti,tps65185";
+ reg = <0x68>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <RK_PA6 IRQ_TYPE_LEVEL_LOW>;
+ enable-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&ebc_pmic_pins>;
+ pinctrl-names = "default";
+ pwr-good-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
+ vcom-ctrl-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vcc_bat>;
+ wakeup-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
+
+ regulators {
+ v3p3: v3p3 {
+ regulator-name = "v3p3";
+ /* Keep it always on because IRQ is pulled up against this line */
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vcom: vcom {
+ regulator-name = "vcom";
+ };
+
+ vposneg: vposneg {
+ regulator-name = "vposneg";
+ regulator-min-microvolt = <15000000>;
+ regulator-max-microvolt = <15000000>;
+ };
+ };
+ };
};
&i2c5 {
};
};
+ ebc-pmic {
+ ebc_pmic_pins: ebc-pmic-pins {
+ rockchip,pins = /* wakeup */
+ <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
+ /* int */
+ <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
+ /* pwr_good */
+ <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>,
+ /* pwrup */
+ <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>,
+ /* vcom_ctrl */
+ <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
led {
led_pin: led-pin {
rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2024 Heiko Stuebner <heiko@sntech.de>
+ */
+
+/dts-v1/;
+
+#include "rk3566.dtsi"
+#include "rk3568-qnap-tsx33.dtsi"
+
+/ {
+ model = "Qnap TS-133-2G NAS System 1-Bay";
+ compatible = "qnap,ts133", "rockchip,rk3566";
+
+ aliases {
+ ethernet0 = &gmac1;
+ };
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+ assigned-clock-rates = <0>, <125000000>;
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy0>;
+ phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_tx_bus2
+ &gmac1m1_rx_bus2
+ &gmac1m1_rgmii_clk
+ &gmac1m1_rgmii_bus>;
+ status = "okay";
+};
+
+&mcu {
+ compatible = "qnap,ts133-mcu";
+};
+
+&mdio1 {
+ rgmii_phy0: ethernet-phy@3 {
+ /* Motorcomm YT8521 phy */
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x3>;
+ pinctrl-0 = <ð_phy0_reset_pin>;
+ pinctrl-names = "default";
+ reset-assert-us = <10000>;
+ reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pinctrl {
+ gmac1 {
+ eth_phy0_reset_pin: eth-phy0-reset-pin {
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+/* connected to usb_host1_xhci */
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_otg>;
+ status = "okay";
+};
+
+/* USB3 port on backside */
+&usb_host1_xhci {
+ dr_mode = "host";
+ status = "okay";
+};
compatible = "belling,bl24c16a", "atmel,24c16";
reg = <0x50>;
pagesize = <16>;
+ read-only;
vcc-supply = <&vcca1v8_pmu>;
};
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+ model = "Anbernic RG DS";
+ chassis-type = "handset";
+ compatible = "anbernic,rg-ds", "rockchip,rk3568";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc0;
+ mmc2 = &sdmmc2;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ adc_keys_home: adc-keys-home {
+ compatible = "adc-keys";
+ io-channel-names = "buttons";
+ io-channels = <&saradc 0>;
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <60>;
+
+ button-home {
+ label = "HOME";
+ linux,code = <BTN_MODE>;
+ press-threshold-microvolt = <1750>;
+ };
+ };
+
+ adc_keys_play: adc-keys-play {
+ compatible = "adc-keys";
+ io-channel-names = "buttons";
+ io-channels = <&saradc 2>;
+ keyup-threshold-microvolt = <1300000>;
+ poll-interval = <60>;
+
+ button-play {
+ label = "PLAY";
+ linux,code = <KEY_PLAYPAUSE>;
+ press-threshold-microvolt = <1750>;
+ };
+ };
+
+ adc_mux: adc-mux {
+ compatible = "io-channel-mux";
+ channels = "left_x", "right_x", "left_y", "right_y";
+ #io-channel-cells = <1>;
+ io-channels = <&saradc 3>;
+ io-channel-names = "parent";
+ mux-controls = <&gpio_mux>;
+ settle-time-us = <100>;
+ };
+
+ adc-joystick {
+ compatible = "adc-joystick";
+ #address-cells = <1>;
+ io-channels = <&adc_mux 0>,
+ <&adc_mux 1>,
+ <&adc_mux 2>,
+ <&adc_mux 3>;
+ pinctrl-0 = <&joy_mux_en>;
+ pinctrl-names = "default";
+ poll-interval = <60>;
+ #size-cells = <0>;
+
+ axis@0 {
+ reg = <0>;
+ abs-flat = <32>;
+ abs-fuzz = <32>;
+ abs-range = <1023 15>;
+ linux,code = <ABS_X>;
+ };
+
+ axis@1 {
+ reg = <1>;
+ abs-flat = <32>;
+ abs-fuzz = <32>;
+ abs-range = <15 1023>;
+ linux,code = <ABS_RY>;
+ };
+
+ axis@2 {
+ reg = <2>;
+ abs-flat = <32>;
+ abs-fuzz = <32>;
+ abs-range = <15 1023>;
+ linux,code = <ABS_Y>;
+ };
+
+ axis@3 {
+ reg = <3>;
+ abs-flat = <32>;
+ abs-fuzz = <32>;
+ abs-range = <15 1023>;
+ linux,code = <ABS_RX>;
+ };
+ };
+
+ backlight0: backlight0 {
+ compatible = "pwm-backlight";
+ enable-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
+ pwms = <&pwm12 0 25000 0>;
+ };
+
+ backlight1: backlight1 {
+ compatible = "pwm-backlight";
+ enable-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
+ pwms = <&pwm13 0 25000 0>;
+ };
+
+ /*
+ * Values taken from BSP device-tree except for
+ * "charge-full-design-microamp-hours" which was set
+ * incorrectly at 2500000 (based on markings on the battery it
+ * should be 4000000), "factory-internal-resistance-micro-ohms"
+ * which was set at 8 but based on context should likely be 80000.
+ *
+ * "constant-charge-current-max-microamp" is set at 10 AMPs
+ * which is likely incorrect but I cannot validate; furthermore
+ * the onboard charger of the rk817 cannot charge past 3.5A
+ * anyway.
+ */
+ battery: battery {
+ compatible = "simple-battery";
+ charge-full-design-microamp-hours = <4000000>;
+ charge-term-current-microamp = <300000>;
+ constant-charge-current-max-microamp = <10000000>;
+ constant-charge-voltage-max-microvolt = <4350000>;
+ factory-internal-resistance-micro-ohms = <80000>;
+ precharge-current-microamp = <180000>;
+ precharge-upper-limit-microvolt = <3600000>;
+ voltage-max-design-microvolt = <4350000>;
+ voltage-min-design-microvolt = <3000000>;
+
+ /*
+ * BSP device-tree missing value for 5 percent, so I
+ * picked a value between 10 and 0.
+ */
+ ocv-capacity-celsius = <20>;
+ ocv-capacity-table-0 = <4338000 100>, <4251000 95>,
+ <4191000 90>, <4136000 85>,
+ <4083000 80>, <4039000 75>,
+ <3978000 70>, <3947000 65>,
+ <3908000 60>, <3861000 55>,
+ <3826000 50>, <3786000 45>,
+ <3772000 40>, <3761000 35>,
+ <3749000 30>, <3731000 25>,
+ <3707000 20>, <3677000 15>,
+ <3663000 10>, <3446000 5>,
+ <3400000 0>;
+ };
+
+ gpio_keys_control: gpio-keys-control {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&gamepad_keys_l>;
+ pinctrl-names = "default";
+
+ button-a {
+ gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ label = "EAST";
+ linux,code = <BTN_EAST>;
+ };
+
+ button-b {
+ gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+ label = "SOUTH";
+ linux,code = <BTN_SOUTH>;
+ };
+
+ button-down {
+ gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_LOW>;
+ label = "DPAD-DOWN";
+ linux,code = <BTN_DPAD_DOWN>;
+ };
+
+ button-l1 {
+ gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>;
+ label = "TL";
+ linux,code = <BTN_TL>;
+ };
+
+ button-l2 {
+ gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
+ label = "TL2";
+ linux,code = <BTN_TL2>;
+ };
+
+ button-left {
+ gpios = <&gpio2 RK_PD7 GPIO_ACTIVE_LOW>;
+ label = "DPAD-LEFT";
+ linux,code = <BTN_DPAD_LEFT>;
+ };
+
+ button-menu {
+ gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
+ label = "HOME";
+ linux,code = <KEY_HOME>;
+ };
+
+ button-right {
+ gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_LOW>;
+ label = "DPAD-RIGHT";
+ linux,code = <BTN_DPAD_RIGHT>;
+ };
+
+ button-r1 {
+ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "T2";
+ linux,code = <BTN_TR>;
+ };
+
+ button-r2 {
+ gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
+ label = "TR2";
+ linux,code = <BTN_TR2>;
+ };
+
+ button-select {
+ gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
+ label = "SELECT";
+ linux,code = <BTN_SELECT>;
+ };
+
+ button-start {
+ gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>;
+ label = "START";
+ linux,code = <BTN_START>;
+ };
+
+ button-thumbl {
+ gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>;
+ label = "THUMBL";
+ linux,code = <BTN_THUMBL>;
+ };
+
+ button-thumbr {
+ gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+ label = "THUMBR";
+ linux,code = <BTN_THUMBR>;
+ };
+
+ button-up {
+ gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>;
+ label = "DPAD-UP";
+ linux,code = <BTN_DPAD_UP>;
+ };
+
+ button-x {
+ gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
+ label = "NORTH";
+ linux,code = <BTN_NORTH>;
+ };
+
+ button-y {
+ gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+ label = "WEST";
+ linux,code = <BTN_WEST>;
+ };
+ };
+
+ gpio_keys_hall: gpio-keys-hall {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&hall_int_l>;
+ pinctrl-names = "default";
+
+ lid-switch {
+ gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
+ label = "LID";
+ linux,code = <SW_LID>;
+ linux,input-type = <EV_SW>;
+ wakeup-event-action = <EV_ACT_DEASSERTED>;
+ wakeup-source;
+ };
+ };
+
+ gpio_keys_volume: gpio-keys-volume {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-0 = <&vol_keys_l>;
+ pinctrl-names = "default";
+
+ vol-down-key {
+ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
+ label = "VOLUMEDOWN";
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+
+ vol-up-key {
+ gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
+ label = "VOLUMEUP";
+ linux,code = <KEY_VOLUMEUP>;
+ };
+ };
+
+ gpio_mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+ mux-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>,
+ <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&joy_mux_config>;
+ pinctrl-names = "default";
+ };
+
+ leds: pwm-leds {
+ compatible = "pwm-leds";
+
+ green_led: led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ function = LED_FUNCTION_POWER;
+ max-brightness = <255>;
+ pwms = <&pwm5 0 25000 0>;
+ };
+
+ amber_led: led-1 {
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_CHARGING;
+ max-brightness = <255>;
+ pwms = <&pwm6 0 25000 0>;
+ };
+
+ red_led: led-2 {
+ color = <LED_COLOR_ID_RED>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ max-brightness = <255>;
+ pwms = <&pwm7 0 25000 0>;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clock-names = "ext_clock";
+ clocks = <&rk817 1>;
+ pinctrl-0 = <&wifi_enable_h>;
+ pinctrl-names = "default";
+ post-power-on-delay-ms = <200>;
+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ pinctrl-0 = <&hp_det>;
+ pinctrl-names = "default";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,hp-det-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,name = "rk817_ext";
+ simple-audio-card,pin-switches = "Internal Speakers";
+ simple-audio-card,routing =
+ "MICL", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR",
+ "Internal Speakers", "HPOL",
+ "Internal Speakers", "HPOR";
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Headphone", "Headphones",
+ "Speaker", "Internal Speakers";
+
+ simple-audio-card,codec {
+ sound-dai = <&rk817>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_8ch>;
+ };
+ };
+
+ vdd_lcd0: regulator-vdd-lcd0 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&vdd_lcd0_h>;
+ pinctrl-names = "default";
+ regulator-name = "vdd_lcd0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_lcd0: regulator-vccio-lcd0 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&vccio_lcd0_h>;
+ pinctrl-names = "default";
+ regulator-name = "vccio_lcd0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_lcd1: regulator-vdd-lcd1 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&vdd_lcd1_h>;
+ pinctrl-names = "default";
+ regulator-name = "vdd_lcd1";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_lcd1: regulator-vccio-lcd1 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&vccio_lcd1_h>;
+ pinctrl-names = "default";
+ regulator-name = "vccio_lcd1";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: regulator-vcc3v3-sd {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&sdmmc_pwren_l>;
+ pinctrl-names = "default";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc3v3_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vccio_sd>;
+ };
+
+ vcc_sys: regulator-vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3800000>;
+ regulator-max-microvolt = <3800000>;
+ regulator-name = "vcc_sys";
+ };
+
+ vibrator: pwm-vibrator {
+ compatible = "pwm-vibrator";
+ pwm-names = "enable";
+ pwms = <&pwm14 0 100000 0>;
+ vcc-supply = <&vcc_sys>;
+ };
+
+ vcc_wifi: regulator-vcc-wifi {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&vcc_wifi_h>;
+ pinctrl-names = "default";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_wifi";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cru {
+ assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
+ <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
+ assigned-clock-rates = <32768>, <1200000000>,
+ <200000000>, <292500000>;
+};
+
+&dsi0 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ dsi0_in: port@0 {
+ reg = <0>;
+ dsi0_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_dsi0>;
+ };
+ };
+
+ dsi0_out: port@1 {
+ reg = <1>;
+ mipi_out_panel0: endpoint {
+ remote-endpoint = <&mipi_in_panel0>;
+ };
+ };
+ };
+
+ panel0: panel@0 {
+ compatible = "anbernic,rg-ds-display-bottom", "jadard,jd9365da-h3";
+ reg = <0>;
+ backlight = <&backlight0>;
+ pinctrl-0 = <&lcd0_rst>;
+ pinctrl-names = "default";
+ reset-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&vdd_lcd0>;
+ vccio-supply = <&vccio_lcd0>;
+
+ port {
+ mipi_in_panel0: endpoint {
+ remote-endpoint = <&mipi_out_panel0>;
+ };
+ };
+ };
+};
+
+&dsi1 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ dsi1_in: port@0 {
+ reg = <0>;
+ dsi1_in_vp1: endpoint {
+ remote-endpoint = <&vp1_out_dsi1>;
+ };
+ };
+
+ dsi1_out: port@1 {
+ reg = <1>;
+ mipi_out_panel1: endpoint {
+ remote-endpoint = <&mipi_in_panel1>;
+ };
+ };
+ };
+
+ panel1: panel@0 {
+ compatible = "anbernic,rg-ds-display-top", "jadard,jd9365da-h3";
+ reg = <0>;
+ backlight = <&backlight1>;
+ pinctrl-0 = <&lcd1_rst>;
+ pinctrl-names = "default";
+ reset-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&vdd_lcd1>;
+ vccio-supply = <&vccio_lcd1>;
+
+ port {
+ mipi_in_panel1: endpoint {
+ remote-endpoint = <&mipi_out_panel1>;
+ };
+ };
+ };
+};
+
+&dsi_dphy0 {
+ status = "okay";
+};
+
+&dsi_dphy1 {
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ rk817: pmic@20 {
+ compatible = "rockchip,rk817";
+ reg = <0x20>;
+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+ #clock-cells = <1>;
+ clock-names = "mclk";
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+ clocks = <&cru I2S1_MCLKOUT_TX>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&i2s1m0_mclk &pmic_int_l>;
+ pinctrl-names = "default";
+ #sound-dai-cells = <0>;
+ system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc_sys>;
+ vcc9-supply = <&dcdc_boost>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-max-microvolt = <1350000>;
+ regulator-min-microvolt = <900000>;
+ regulator-name = "vdd_logic";
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-max-microvolt = <1350000>;
+ regulator-min-microvolt = <825000>;
+ regulator-name = "vdd_gpu";
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc_ddr";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_3v3: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "vcc_3v3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "vcca1v8_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <900000>;
+ regulator-min-microvolt = <900000>;
+ regulator-name = "vdda_0v9";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <900000>;
+ regulator-min-microvolt = <900000>;
+ regulator-name = "vdda0v9_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "vccio_acodec";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "vccio_sd";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "vcc3v3_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_1v8: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "vcc_1v8";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc1v8_dvp: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "vcc1v8_dvp";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc2v8_dvp: LDO_REG9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <2800000>;
+ regulator-min-microvolt = <2800000>;
+ regulator-name = "vcc2v8_dvp";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ dcdc_boost: BOOST {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <5400000>;
+ regulator-min-microvolt = <4700000>;
+ regulator-name = "boost";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ otg_switch: OTG_SWITCH {
+ regulator-name = "otg_switch";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+
+ rk817_charger: charger {
+ monitored-battery = <&battery>;
+ rockchip,resistor-sense-micro-ohms = <10000>;
+ rockchip,sleep-enter-current-microamp = <150000>;
+ rockchip,sleep-filter-current-microamp = <100000>;
+ };
+ };
+
+ vdd_cpu: regulator@40 {
+ compatible = "silergy,syr827";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1390000>;
+ regulator-min-microvolt = <712500>;
+ regulator-name = "vdd_cpu";
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc_sys>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ /*
+ * Currently the rk817_charger and the cw2015 don't work together.
+ * Disable the cw2015 for now because it performs the same function
+ * as the rk817_charger for battery monitoring.
+ */
+ cw2015: battery@62 {
+ compatible = "cellwise,cw2015";
+ reg = <0x62>;
+ cellwise,battery-profile = /bits/ 8
+ < 0x17 0x67 0x81 0x6F 0x69 0x65 0x63 0x54
+ 0x75 0x50 0x57 0x56 0x4E 0x4F 0x44 0x35
+ 0x2C 0x24 0x1E 0x1B 0x24 0x32 0x41 0x4D
+ 0x1C 0x57 0x0B 0x85 0x34 0x54 0x59 0x6D
+ 0x85 0x81 0x81 0x84 0x3C 0x1B 0x6C 0x6C
+ 0x0B 0x41 0x1C 0x4D 0x80 0x95 0xA0 0x14
+ 0x38 0x7E 0x98 0xA3 0x80 0x89 0x97 0xCB
+ 0x2F 0x00 0x64 0xA5 0xB5 0xC1 0x46 0xAE>;
+ cellwise,monitor-interval-ms = <5000>;
+ monitored-battery = <&battery>;
+ power-supplies = <&rk817_charger>;
+ status = "disabled";
+ };
+};
+
+&i2c2 {
+ clock-frequency = <200000>;
+ pinctrl-0 = <&i2c2m1_xfer>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /* awinic,aw87391 at 0x58 */
+ /* awinic,aw87391 at 0x5b */
+ /* invensense,icm42607p at 0x68 */
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c3m1_xfer>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ touch1: touchscreen@14 {
+ compatible = "goodix,gt911";
+ reg = <0x14>;
+ AVDD28-supply = <&vcc2v8_dvp>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PC0 IRQ_TYPE_LEVEL_LOW>;
+ irq-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
+ panel = <&panel1>;
+ reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+ touchscreen-size-x = <640>;
+ touchscreen-size-y = <480>;
+ touchscreen-inverted-x;
+ touchscreen-inverted-y;
+ pinctrl-0 = <&touch1_rst &touch1_irq>;
+ pinctrl-names = "default";
+ VDDIO-supply = <&vcc3v3_pmu>;
+ };
+};
+
+&i2c5 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c5m0_xfer>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ touch0: touchscreen@14 {
+ compatible = "goodix,gt911";
+ reg = <0x14>;
+ AVDD28-supply = <&vcc2v8_dvp>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB6 IRQ_TYPE_LEVEL_LOW>;
+ irq-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+ panel = <&panel0>;
+ reset-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
+ touchscreen-size-x = <640>;
+ touchscreen-size-y = <480>;
+ pinctrl-0 = <&touch0_rst &touch0_irq>;
+ pinctrl-names = "default";
+ VDDIO-supply = <&vcc3v3_pmu>;
+ };
+
+ /* Unused iSmartWare SW2001 encryption device at 0x3c */
+};
+
+&i2s1_8ch {
+ pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>;
+ pinctrl-names = "default";
+ rockchip,trcm-sync-tx-only;
+ status = "okay";
+};
+
+&pinctrl {
+ gpio-keys {
+ vol_keys_l: vol-keys_l {
+ rockchip,pins =
+ <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ gamepad_keys_l: gamepad-keys-l {
+ rockchip,pins =
+ <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ gpio-lcd {
+ lcd0_rst: lcd0-rst {
+ rockchip,pins =
+ <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ lcd1_rst: lcd1-rst {
+ rockchip,pins =
+ <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ hall-sensor {
+ hall_int_l: hal-int-l {
+ rockchip,pins =
+ <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ hp-detect {
+ hp_det: hp-det {
+ rockchip,pins =
+ <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ joy-mux {
+ joy_mux_en: joy-mux-en {
+ rockchip,pins =
+ <3 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>;
+ };
+
+ joy_mux_config: joy-mux-config {
+ rockchip,pins =
+ <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
+ <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins =
+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins =
+ <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_pwren_l: sdmmc-pwren-l {
+ rockchip,pins =
+ <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ touch {
+ touch0_rst: touch0-rst {
+ rockchip,pins =
+ <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ touch0_irq: touch0-irq {
+ rockchip,pins =
+ <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ touch1_rst: touch1-rst {
+ rockchip,pins =
+ <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ touch1_irq: touch1-irq {
+ rockchip,pins =
+ <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ vcc-lcd {
+ vdd_lcd0_h: vdd-lcd0-h {
+ rockchip,pins =
+ <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vccio_lcd0_h: vccio-lcd0-h {
+ rockchip,pins =
+ <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vdd_lcd1_h: vdd-lcd1-h {
+ rockchip,pins =
+ <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vccio_lcd1_h: vccio-lcd1-h {
+ rockchip,pins =
+ <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ vcc-wifi {
+ vcc_wifi_h: vcc-wifi-h {
+ rockchip,pins =
+ <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wifi-irq {
+ wifi_host_wake_irq: wifi-host-wake-irq {
+ rockchip,pins =
+ <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ status = "okay";
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_3v3>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_3v3>;
+};
+
+&pwm5 {
+ pinctrl-0 = <&pwm5_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pwm6 {
+ pinctrl-0 = <&pwm6_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pwm7 {
+ pinctrl-0 = <&pwm7_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pwm12 {
+ pinctrl-0 = <&pwm12m1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pwm13 {
+ pinctrl-0 = <&pwm13m1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pwm14 {
+ pinctrl-0 = <&pwm14m0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ no-sd;
+ no-sdio;
+ non-removable;
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ pinctrl-names = "default";
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&sdmmc2 {
+ #address-cells = <1>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ max-frequency = <100000000>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_clk &sdmmc2m0_cmd>;
+ pinctrl-names = "default";
+ sd-uhs-sdr104;
+ #size-cells = <0>;
+ vmmc-supply = <&vcc_wifi>;
+ status = "okay";
+
+ sdio_wifi: wifi@1 {
+ reg = <1>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "host-wake";
+ pinctrl-0 = <&wifi_host_wake_irq>;
+ pinctrl-names = "default";
+ };
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <0>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn &uart1m1_rtsn>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt";
+ device-wake-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+ host-wake-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* No DMA for a debug serial console. */
+&uart2 {
+ /delete-property/ dmas;
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ dr_mode = "peripheral";
+ phy-names = "usb2-phy";
+ phys = <&usb2phy0_otg>;
+ maximum-speed = "high-speed";
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&cru PLL_VPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 {
+ reg = <ROCKCHIP_VOP2_EP_MIPI0>;
+ remote-endpoint = <&dsi0_in_vp0>;
+ };
+};
+
+&vp1 {
+ vp1_out_dsi1: endpoint@ROCKCHIP_VOP2_EP_MIPI1 {
+ reg = <ROCKCHIP_VOP2_EP_MIPI1>;
+ remote-endpoint = <&dsi1_in_vp1>;
+ };
+};
/dts-v1/;
+#include "rk3568.dtsi"
#include "rk3568-qnap-tsx33.dtsi"
/ {
};
};
-/* connected to sata2 */
-&combphy2 {
+/* Connected to usb_host0_xhci */
+&combphy0 {
status = "okay";
};
};
};
+&keys {
+ pinctrl-names = "default";
+ pinctrl-0 = <©_button_pin>, <&reset_button_pin>;
+
+ key-copy {
+ label = "copy";
+ gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_COPY>;
+ };
+};
+
&leds {
led-1 {
color = <LED_COLOR_ID_GREEN>;
};
};
-&sata2 {
+&sata1 {
status = "okay";
};
/dts-v1/;
+#include "rk3568.dtsi"
#include "rk3568-qnap-tsx33.dtsi"
/ {
};
};
-/* connected to sata2 */
-&combphy2 {
+/* Connected to usb_host0_xhci */
+&combphy0 {
status = "okay";
};
};
};
+&keys {
+ pinctrl-names = "default";
+ pinctrl-0 = <©_button_pin>, <&reset_button_pin>;
+
+ key-copy {
+ label = "copy";
+ gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_COPY>;
+ };
+};
+
&leds {
led-1 {
color = <LED_COLOR_ID_GREEN>;
};
};
-&sata2 {
+&sata1 {
status = "okay";
};
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
-#include "rk3568.dtsi"
/ {
aliases {
stdout-path = "serial2:115200n8";
};
- keys {
+ keys: keys {
compatible = "gpio-keys";
- pinctrl-0 = <©_button_pin>, <&reset_button_pin>;
+ pinctrl-0 = <&reset_button_pin>;
pinctrl-names = "default";
- key-copy {
- label = "copy";
- gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_COPY>;
- };
-
key-reset {
label = "reset";
gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>;
};
};
-/* connected to usb_host0_xhci */
-&combphy0 {
+/* Connected USB3 on TS133 / SATA1 on all the others */
+&combphy1 {
status = "okay";
};
-/* connected to sata1 */
-&combphy1 {
+/* Connected to SATA2 */
+&combphy2 {
status = "okay";
};
status = "okay";
};
-&sata1 {
+&sata2 {
status = "okay";
};
};
};
- vcc_3v3: SWITCH_REG1 {
+ gpio_vref: vcc_3v3: SWITCH_REG1 {
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
};
};
};
+
+ eeprom@50 {
+ compatible = "belling,bl24c16a", "atmel,24c16";
+ reg = <0x50>;
+ pagesize = <16>;
+ read-only;
+ vcc-supply = <&gpio_vref>;
+ };
};
&pinctrl {
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2025 Radxa Computer (Shenzhen) Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3568-radxa-cm3j.dtsi"
+
+/ {
+ model = "Radxa CM3J on RPi CM4 IO Board";
+ compatible = "radxa,cm3j-rpi-cm4", "radxa,cm3j", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 = &gmac1;
+ mmc1 = &sdmmc0;
+ rtc0 = &pcf85063;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ leds-1 {
+ compatible = "gpio-leds";
+
+ led-1 {
+ color = <LED_COLOR_ID_RED>;
+ default-state = "on";
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&npwr_led>;
+ };
+
+ led-2 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pi_nled_activity>;
+ };
+ };
+
+ dc12v: regulator-12v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "dc12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ dc3v3_pcie: regulator-3v3-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "dc3v3_pcie";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc12v>;
+ };
+
+ gpio_vref: regulator-3v3-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gpio_vref";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc3v3>;
+ };
+
+ dc5v: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "dc5v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc12v>;
+ };
+};
+
+&combphy0 {
+ status = "okay";
+};
+
+&combphy2 {
+ status = "okay";
+};
+
+&gmac1 {
+ status = "okay";
+};
+
+&gpio0 {
+ nextrst-hog {
+ gpio-hog;
+ /*
+ * GPIO_ACTIVE_LOW + output-low here means that the pin is set
+ * to high, because output-low decides the value pre-inversion.
+ */
+ gpios = <RK_PC0 GPIO_ACTIVE_LOW>;
+ line-name = "nEXTRST";
+ output-low;
+ };
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2c0 {
+ emc2301: fan-controller@2f {
+ compatible = "microchip,emc2301", "microchip,emc2305";
+ reg = <0x2f>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pwm-cells = <3>;
+
+ fan@0 {
+ reg = <0x0>;
+ pwms = <&emc2301 26000 0 1>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ pcf85063: rtc@51 {
+ compatible = "nxp,pcf85063a";
+ reg = <0x51>;
+ wakeup-source;
+ };
+};
+
+&i2s0_8ch {
+ status = "okay";
+};
+
+&pinctrl {
+ leds {
+ npwr_led: npwr-led {
+ rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pi_nled_activity: pi-nled-activity {
+ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pcie2x1 {
+ vpcie3v3-supply = <&dc3v3_pcie>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ broken-cd;
+ disable-wp;
+ no-mmc;
+ no-sdio;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
+ vmmc-supply = <&dc3v3>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2025 Radxa Computer (Shenzhen) Co., Ltd.
+ */
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+ aliases {
+ mmc0 = &sdhci;
+ mmc2 = &sdmmc2;
+ };
+
+ gmac1_clkin: clock-125m {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
+ leds-0 {
+ compatible = "gpio-leds";
+
+ led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio0_b4_led>;
+ };
+ };
+
+ vcc3v3_sys: regulator-3v3-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc5v>;
+ };
+
+ vcc_3v3_1: regulator-3v3-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_1";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_reg_on_h_gpio3_d4>;
+ reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
+ clock_in_out = "input";
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii-id";
+ phy-supply = <&vcc_3v3_1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_clkinout
+ &gmac1m1_rx_bus2
+ &gmac1m1_tx_bus2
+ &gmac1m1_rgmii_clk
+ &gmac1m1_rgmii_bus>;
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ avdd-0v9-supply = <&vdda0v9_image>;
+ avdd-1v8-supply = <&vcca1v8_image>;
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ #clock-cells = <1>;
+ clock-output-names = "rk809-clkout1", "rk809-clkout2";
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ system-power-controller;
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ wakeup-source;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ dc1v8: vccio_flash: vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ dc3v3: vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+
+ vdd_cpu: regulator@40 {
+ compatible = "silergy,syr827";
+ reg = <0x40>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1390000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&dc5v>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "belling,bl24c16a", "atmel,24c16";
+ reg = <0x50>;
+ pagesize = <16>;
+ read-only;
+ vcc-supply = <&gpio_vref>;
+ };
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-id001c.c916";
+ reg = <0x0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1_rstn_gpio3_b0>; // GPIO4_C3
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pinctrl {
+ bluetooth {
+ bt_reg_on_h_gpio4_b2: bt-reg-on-h-gpio4-b2 {
+ rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_host_h_gpio4_b4: bt-wake-host-h-gpio4-b4 {
+ rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ host_wake_bt_h_gpio4_b5: host-wake-bt-h-gpio4-b5 {
+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ ethernet {
+ gmac1_rstn_gpio3_b0: gmac1-rstn-gpio3-b0 {
+ rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ gpio0_b4_led: gpio0-b4-led {
+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ pcie20_clkreqnm2: pcie20_clkreqnm2 {
+ rockchip,pins = <1 RK_PB0 4 &pcfg_pull_none>;
+ };
+
+ pcie_nrst: pcie-nrst {
+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ wifi {
+ wifi_reg_on_h_gpio3_d4: wifi-reg-on-h-gpio3-d4 {
+ rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pcie2x1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie20_clkreqnm2 &pcie_nrst>;
+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+ supports-clkreq;
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc_3v3>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio2-supply = <&vccio_flash>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ no-sd;
+ no-sdio;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vccio_flash>;
+ status = "okay";
+};
+
+&sdmmc2 {
+ #address-cells = <1>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ max-frequency = <200000000>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ no-mmc;
+ no-sd;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_clk &sdmmc2m0_cmd>;
+ sd-uhs-sdr104;
+ #size-cells = <0>;
+ status = "okay";
+
+ wifi@1 {
+ compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac";
+ reg = <1>;
+ };
+};
+
+&sfc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <104000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ vcc-supply = <&vccio_flash>;
+ };
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart8 {
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4345c5";
+ clocks = <&rk809 1>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
+ max-speed = <1500000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_reg_on_h_gpio4_b2
+ &bt_wake_host_h_gpio4_b4
+ &host_wake_bt_h_gpio4_b5>;
+ shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
+ vbat-supply = <&vcc_3v3_1>;
+ vddio-supply = <&vcc_1v8>;
+ };
+};
+
+&usb_host0_xhci {
+ extcon = <&usb2phy0>;
+ maximum-speed = "high-speed";
+ phys = <&usb2phy0_otg>;
+ phy-names = "usb2-phy";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};
};
};
};
+
+ eeprom@50 {
+ compatible = "belling,bl24c16a", "atmel,24c16";
+ reg = <0x50>;
+ pagesize = <16>;
+ read-only;
+ vcc-supply = <&vcc3v3_pmu>;
+ };
};
&i2c3 {
};
};
};
+
+ eeprom@50 {
+ compatible = "belling,bl24c16a", "atmel,24c16";
+ reg = <0x50>;
+ pagesize = <16>;
+ read-only;
+ vcc-supply = <&vcc3v3_sys>;
+ };
};
&i2c5 {
<0x0 0xf2000000 0x0 0x00100000>;
ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
<0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>,
- <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>;
+ <0x03000000 0x3 0x40000000 0x3 0x40000000 0x0 0x40000000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE30X1_POWERUP>;
reset-names = "pipe";
<0x0 0xf0000000 0x0 0x00100000>;
ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
<0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>,
- <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>;
+ <0x03000000 0x3 0x80000000 0x3 0x80000000 0x0 0x40000000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE30X2_POWERUP>;
reset-names = "pipe";
power-domains = <&power RK3568_PD_PIPE>;
ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
<0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
- <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
+ <0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;
resets = <&cru SRST_PCIE20_POWERUP>;
reset-names = "pipe";
#address-cells = <3>;
vin-supply = <&vcc_5v0_sys>;
};
- vcc_3v3_rtc_s5: regulator-vcc-3v3-rtc-s5 {
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3_rtc_s5";
- regulator-boot-on;
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_5v0_sys>;
- };
-
vcc_3v3_s0: regulator-vcc-3v3-s0 {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_s0";
};
headphone {
- hp_det: hp-det {
- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+ hp_det_l: hp-det-l {
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
status = "okay";
};
+&saradc {
+ vref-supply = <&vcca_1v8_s0>;
+ status = "okay";
+};
+
&sdhci {
bus-width = <8>;
full-pwr-cycle-in-suspend;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * DT-overlay to enable the onboard PCIe x1 slot, which shares pins and the PHY
+ * with the USB3 host port.
+ * To use the PCIe slot, apply this overlay and flip the Dial_Switch_1 right
+ * next to the PCIe slot to low state (labeled "ON - PCIe1"). USB3 host port
+ * will be unusable (not even in 2.0 mode)
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/pinctrl/rockchip.h>
+
+&pcie1 {
+ pinctrl-0 = <&pcie1m0_pins &pcie1_rst>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pinctrl {
+ pcie1 {
+ pcie1_rst: pcie1-rst {
+ rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&usb_drd1_dwc3 {
+ status = "disabled";
+};
vin-supply = <&vcc_3v3_s3>;
};
+ vcc3v3_sd: regulator-vcc-3v3-sd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_pwren>;
+ regulator-name = "vcc3v3_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_s0>;
+ };
+
vcc_ufs_s0: regulator-vcc-ufs-s0 {
compatible = "regulator-fixed";
regulator-name = "vcc_ufs_s0";
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_1v8_s3>;
};
+
+ sound {
+ compatible = "simple-audio-card";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_det>;
+ simple-audio-card,name = "On-board Analog ES8388";
+ simple-audio-card,aux-devs = <&hp_power>, <&spk_power>;
+ simple-audio-card,bitclock-master = <&masterdai>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <&masterdai>;
+ simple-audio-card,hp-det-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,routing =
+ "Headphone Power INL", "LOUT1",
+ "Headphone Power INR", "ROUT1",
+ "Speaker Power INL", "LOUT2",
+ "Speaker Power INR", "ROUT2",
+ "Headphones", "Headphone Power OUTL",
+ "Headphones", "Headphone Power OUTR",
+ "Speaker", "Speaker Power OUTL",
+ "Speaker", "Speaker Power OUTR",
+ "LINPUT1", "Main Mic",
+ "LINPUT2", "Main Mic",
+ "RINPUT1", "Headset Mic",
+ "RINPUT2", "Headset Mic";
+ simple-audio-card,widgets =
+ "Microphone", "Main Mic",
+ "Microphone", "Headset Mic",
+ "Headphone", "Headphones",
+ "Speaker", "Speaker";
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai1>;
+ };
+
+ masterdai: simple-audio-card,codec {
+ sound-dai = <&es8388>;
+ system-clock-frequency = <12288000>;
+ };
+ };
+
+ hp_power: headphone-amplifier {
+ compatible = "simple-audio-amplifier";
+ enable-gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_ctl>;
+ sound-name-prefix = "Headphone Power";
+ };
+
+ spk_power: speaker-amplifier {
+ compatible = "simple-audio-amplifier";
+ enable-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spk_ctl>;
+ sound-name-prefix = "Speaker Power";
+ VCC-supply = <&vcc5v0_device>;
+ };
};
&cpu_l0 {
};
};
+&hdmi_sound {
+ status = "okay";
+};
+
&hdptxphy {
status = "okay";
};
};
};
+&i2c3 {
+ status = "okay";
+
+ es8388: audio-codec@10 {
+ compatible = "everest,es8388", "everest,es8328";
+ reg = <0x10>;
+ AVDD-supply = <&vcca_3v3_s0>;
+ DVDD-supply = <&vcc_1v8_s0>;
+ HPVDD-supply = <&vcca_3v3_s0>;
+ PVDD-supply = <&vcc_1v8_s0>;
+ assigned-clocks = <&cru CLK_SAI1_MCLKOUT_TO_IO>;
+ assigned-clock-rates = <12288000>;
+ clocks = <&cru CLK_SAI1_MCLKOUT_TO_IO>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sai1m0_mclk>;
+ #sound-dai-cells = <0>;
+ };
+};
+
&mdio0 {
rgmii_phy0: ethernet-phy@1 {
compatible = "ethernet-phy-id001c.c916";
};
&pinctrl {
+ audio {
+ hp_det: hp-det {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ hp_ctl: hp-ctl {
+ rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ spk_ctl: spk-ctl {
+ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
bluetooth {
bt_reg_on: bt-reg-on {
rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
+ sdmmc {
+ sdmmc_pwren: sdmmc-pwren {
+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
usb {
usb_host_pwren: usb-host-pwren {
rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+&sai1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sai1m0_lrck
+ &sai1m0_sclk
+ &sai1m0_sdi0
+ &sai1m0_sdo0>;
+ status = "okay";
+};
+
+&sai6 {
+ status = "okay";
+};
+
&sdhci {
bus-width = <8>;
full-pwr-cycle-in-suspend;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <200000000>;
no-sdio;
no-mmc;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd>;
vqmmc-supply = <&vccio_sd_s0>;
status = "okay";
};
};
};
+&hdmi_sound {
+ status = "okay";
+};
+
&hdptxphy {
status = "okay";
};
status = "okay";
};
+&sai6 {
+ status = "okay";
+};
+
&saradc {
vref-supply = <&vcca_1v8_s0>;
status = "okay";
regulator-name = "vcc12v_dcin";
};
+ vcc1v2_ufs_vccq: regulator-vcc1v2-ufs-vccq {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc1v2_ufs_vccq";
+ vin-supply = <&vcc5v0_sys_s5>;
+ };
+
+ vcc1v8_ufs_vccq2: regulator-vcc1v8-ufs-vccq2 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_ufs_vccq2";
+ vin-supply = <&vcc_1v8_s3>;
+ };
+
vcc3v3_m2_keym: regulator-vcc3v3-m2-keym {
compatible = "regulator-fixed";
enable-active-high;
simple-audio-card,format = "i2s";
simple-audio-card,hp-det-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_LOW>;
simple-audio-card,mclk-fs = <256>;
- simple-audio-card,name = "realtek,rt5616-codec";
+ simple-audio-card,name = "Onboard Analog RT5616";
simple-audio-card,routing =
"Headphones", "HPOL",
};
};
+&hdmi_sound {
+ status = "okay";
+};
+
&hdptxphy {
status = "okay";
};
status = "okay";
};
+&sai6 {
+ status = "okay";
+};
+
&saradc {
vref-supply = <&vcca_1v8_s0>;
status = "okay";
status = "okay";
};
+&ufshc {
+ vcc-supply = <&vcc_3v3_s3>;
+ vccq-supply = <&vcc1v2_ufs_vccq>;
+ vccq2-supply = <&vcc1v8_ufs_vccq2>;
+ vdd-hba-supply = <&vdda_1v2_s0>;
+ status = "okay";
+};
+
&usbdp_phy {
status = "okay";
};
regulator-name = "vcc_3v3_s0";
vin-supply = <&vcc_3v3_s3>;
};
+
+ vcc3v3_sd: regulator-vcc-3v3-sd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_pwren>;
+ regulator-name = "vcc3v3_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_s0>;
+ };
};
&combphy0_ps {
};
};
+ sdmmc {
+ sdmmc_pwren: sdmmc-pwren {
+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
usb {
usb_otg0_pwren_h: usb-otg0-pwren-h {
rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
disable-wp;
no-mmc;
no-sdio;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3_s3>;
+ vmmc-supply = <&vcc3v3_sd>;
vqmmc-supply = <&vccio_sd_s0>;
status = "okay";
};
/* ufs_rstn */
<4 RK_PD0 1 &pcfg_pull_none>;
};
+
+ /omit-if-no-ref/
+ ufs_rstgpio: ufs-rstgpio {
+ rockchip,pins =
+ /* ufs_rstn */
+ <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
};
ufs_testdata0 {
};
};
+&i2c6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6m3_xfer>;
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "belling,bl24c16f", "atmel,24c16";
+ reg = <0x50>;
+ pagesize = <16>;
+ read-only;
+ vcc-supply = <&vcc_3v3_s3>;
+ };
+};
+
&mdio0 {
rgmii_phy0: ethernet-phy@1 {
compatible = "ethernet-phy-id001c.c916";
"aclk_dbi", "pclk",
"aux";
device_type = "pci";
+ dma-coherent;
interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
"aclk_dbi", "pclk",
"aux";
device_type = "pci";
+ dma-coherent;
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
status = "disabled";
};
+ vdec: video-codec@27b00000 {
+ compatible = "rockchip,rk3576-vdec";
+ reg = <0x0 0x27b00100 0x0 0x500>,
+ <0x0 0x27b00000 0x0 0x100>,
+ <0x0 0x27b00600 0x0 0x100>;
+ reg-names = "function", "link", "cache";
+ interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC>,
+ <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_CORE>,
+ <&cru CLK_RKVDEC_HEVC_CA>;
+ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+ assigned-clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru CLK_RKVDEC_CORE>,
+ <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_HEVC_CA>;
+ assigned-clock-rates = <600000000>, <600000000>,
+ <500000000>, <1000000000>;
+ iommus = <&vdec_mmu>;
+ power-domains = <&power RK3576_PD_VDEC>;
+ resets = <&cru SRST_A_RKVDEC_BIU>, <&cru SRST_H_RKVDEC_BIU>,
+ <&cru SRST_H_RKVDEC>, <&cru SRST_RKVDEC_CORE>,
+ <&cru SRST_RKVDEC_HEVC_CA>;
+ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+ sram = <&rkvdec_sram>;
+ };
+
+ vdec_mmu: iommu@27b00800 {
+ compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0x27b00800 0x0 0x40>, <0x0 0x27b00900 0x0 0x40>;
+ interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_RKVDEC_CORE>, <&cru HCLK_RKVDEC>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3576_PD_VDEC>;
+ rockchip,disable-mmu-reset;
+ #iommu-cells = <0>;
+ };
+
vop: vop@27d00000 {
compatible = "rockchip,rk3576-vop";
reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>;
clock-names = "stmmaceth", "clk_mac_ref",
"pclk_mac", "aclk_mac",
"ptp_ref";
+ dma-coherent;
interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
clock-names = "stmmaceth", "clk_mac_ref",
"pclk_mac", "aclk_mac",
"ptp_ref";
+ dma-coherent;
interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
assigned-clock-parents = <&cru CLK_REF_MPHY_26M>;
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&power RK3576_PD_USB>;
- pinctrl-0 = <&ufs_refclk>;
+ pinctrl-0 = <&ufs_refclk &ufs_rstgpio>;
pinctrl-names = "default";
resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>,
<&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>;
/* start address and size should be 4k align */
rkvdec_sram: rkvdec-sram@0 {
reg = <0x0 0x78000>;
+ pool;
};
};
#iommu-cells = <0>;
};
+ vdec0: video-codec@fdc38000 {
+ compatible = "rockchip,rk3588-vdec";
+ reg = <0x0 0xfdc38100 0x0 0x500>,
+ <0x0 0xfdc38000 0x0 0x100>,
+ <0x0 0xfdc38600 0x0 0x100>;
+ reg-names = "function", "link", "cache";
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>,
+ <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>;
+ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+ assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>,
+ <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>;
+ assigned-clock-rates = <800000000>, <600000000>,
+ <600000000>, <1000000000>;
+ iommus = <&vdec0_mmu>;
+ power-domains = <&power RK3588_PD_RKVDEC0>;
+ resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CA>,
+ <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>;
+ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+ sram = <&vdec0_sram>;
+ };
+
+ vdec0_mmu: iommu@fdc38700 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_RKVDEC0>;
+ #iommu-cells = <0>;
+ };
+
+ vdec1: video-codec@fdc40000 {
+ compatible = "rockchip,rk3588-vdec";
+ reg = <0x0 0xfdc40100 0x0 0x500>,
+ <0x0 0xfdc40000 0x0 0x100>,
+ <0x0 0xfdc40600 0x0 0x100>;
+ reg-names = "function", "link", "cache";
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>,
+ <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>;
+ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+ assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>,
+ <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>;
+ assigned-clock-rates = <800000000>, <600000000>,
+ <600000000>, <1000000000>;
+ iommus = <&vdec1_mmu>;
+ power-domains = <&power RK3588_PD_RKVDEC1>;
+ resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CA>,
+ <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>;
+ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+ sram = <&vdec1_sram>;
+ };
+
+ vdec1_mmu: iommu@fdc40700 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdc40700 0x0 0x40>, <0x0 0xfdc40740 0x0 0x40>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_RKVDEC1>;
+ #iommu-cells = <0>;
+ };
+
av1d: video-codec@fdc70000 {
compatible = "rockchip,rk3588-av1-vpu";
reg = <0x0 0xfdc70000 0x0 0x800>;
power-domains = <&power RK3588_PD_PCIE>;
ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
<0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
- <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
+ <0x03000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>;
reg = <0xa 0x40c00000 0x0 0x00400000>,
<0x0 0xfe180000 0x0 0x00010000>,
<0x0 0xf3000000 0x0 0x00100000>;
power-domains = <&power RK3588_PD_PCIE>;
ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
<0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
- <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
+ <0x03000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>;
reg = <0xa 0x41000000 0x0 0x00400000>,
<0x0 0xfe190000 0x0 0x00010000>,
<0x0 0xf4000000 0x0 0x00100000>;
ranges = <0x0 0x0 0xff001000 0xef000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ vdec0_sram: codec-sram@0 {
+ reg = <0x0 0x78000>;
+ pool;
+ };
+
+ vdec1_sram: codec-sram@78000 {
+ reg = <0x78000 0x77000>;
+ pool;
+ };
};
pinctrl: pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&pcie2_0_rst>, <&pcie2_0_wake>, <&pcie2_0_clkreq>, <&wifi_host_wake_irq>;
reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+ supports-clkreq;
vpcie3v3-supply = <&vcc3v3_wlan>;
status = "okay";
&pcie2x1l1 {
reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&pcie2_1_rst>, <&rtl8111_isolate>;
+ pinctrl-0 = <&pcie2_1_rst>, <&rtl8111_isolate>, <&pcie30x1m1_1_clkreqn>;
+ supports-clkreq;
status = "okay";
};
&pcie3x4 {
pinctrl-names = "default";
- pinctrl-0 = <&pcie3_reset>;
+ pinctrl-0 = <&pcie3_reset>, <&pcie30x4m1_clkreqn>;
+ supports-clkreq;
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie30>;
status = "okay";
power-domains = <&power RK3588_PD_PCIE>;
ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
<0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
- <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
+ <0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
reg = <0xa 0x40000000 0x0 0x00400000>,
<0x0 0xfe150000 0x0 0x00010000>,
<0x0 0xf0000000 0x0 0x00100000>;
power-domains = <&power RK3588_PD_PCIE>;
ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
<0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
- <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
+ <0x03000000 0x9 0x40000000 0x9 0x40000000 0x0 0x40000000>;
reg = <0xa 0x40400000 0x0 0x00400000>,
<0x0 0xfe160000 0x0 0x00010000>,
<0x0 0xf1000000 0x0 0x00100000>;
power-domains = <&power RK3588_PD_PCIE>;
ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
<0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
- <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
+ <0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
reg = <0xa 0x40800000 0x0 0x00400000>,
<0x0 0xfe170000 0x0 0x00010000>,
<0x0 0xf2000000 0x0 0x00100000>;
};
};
+ hdmi1-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi1_con_in: endpoint {
+ remote-endpoint = <&hdmi1_out_con>;
+ };
+ };
+ };
+
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>;
};
};
+&hdmi1 {
+ status = "okay";
+};
+
+&hdmi1_in {
+ hdmi1_in_vp1: endpoint {
+ remote-endpoint = <&vp1_out_hdmi1>;
+ };
+};
+
+&hdmi1_out {
+ hdmi1_out_con: endpoint {
+ remote-endpoint = <&hdmi1_con_in>;
+ };
+};
+
&hdmi_receiver_cma {
status = "okay";
};
status = "okay";
};
+&hdptxphy1 {
+ status = "okay";
+};
+
/* Connected to MIPI-DSI0 */
&i2c5 {
pinctrl-names = "default";
remote-endpoint = <&hdmi0_in_vp0>;
};
};
+
+&vp1 {
+ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI1>;
+ remote-endpoint = <&hdmi1_in_vp1>;
+ };
+};
reg = <0x42>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_npu_s0";
- regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
domain-supply = <&vdd_gpu_s0>;
};
+&pd_npu {
+ domain-supply = <&vdd_npu_s0>;
+};
+
&pinctrl {
gpio-leds {
led_sys_pin: led-sys-pin {
};
};
+&rknn_core_0 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_core_1 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_core_2 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_mmu_0 {
+ status = "okay";
+};
+
+&rknn_mmu_1 {
+ status = "okay";
+};
+
+&rknn_mmu_2 {
+ status = "okay";
+};
+
&saradc {
vref-supply = <&avcc_1v8_s0>;
status = "okay";
reg = <0x42>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_npu_s0";
- regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
domain-supply = <&vdd_gpu_s0>;
};
+&pd_npu {
+ domain-supply = <&vdd_npu_s0>;
+};
+
&pinctrl {
emmc {
emmc_reset: emmc-reset {
};
};
+&rknn_core_0 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_core_1 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_core_2 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_mmu_0 {
+ status = "okay";
+};
+
+&rknn_mmu_1 {
+ status = "okay";
+};
+
+&rknn_mmu_2 {
+ status = "okay";
+};
+
&saradc {
vref-supply = <&vcc_1v8_s0>;
status = "okay";
reg = <0x42>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_npu_s0";
- regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
domain-supply = <&vdd_gpu_s0>;
};
+&pd_npu {
+ domain-supply = <&vdd_npu_s0>;
+};
+
&pinctrl {
gpio-leds {
sys_led_pin: sys-led-pin {
status = "okay";
};
+&rknn_core_0 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_core_1 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_core_2 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_mmu_0 {
+ status = "okay";
+};
+
+&rknn_mmu_1 {
+ status = "okay";
+};
+
+&rknn_mmu_2 {
+ status = "okay";
+};
+
+
&saradc {
vref-supply = <&avcc_1v8_s0>;
status = "okay";
reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
};
+ spdif_dit: spdif-dit {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+ };
+
+ spdif_sound: spdif-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "SPDIF";
+
+ simple-audio-card,cpu {
+ sound-dai = <&spdif_tx1>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&spdif_dit>;
+ };
+ };
+
typec_vin: regulator-typec-vin {
compatible = "regulator-fixed";
enable-active-high;
};
};
+&spdif_tx1 {
+ pinctrl-0 = <&spdif1m2_tx>;
+ status = "okay";
+};
+
&spi2 {
status = "okay";
assigned-clocks = <&cru CLK_SPI2>;
};
};
+&i2c1 {
+ eeprom@50 {
+ compatible = "belling,bl24c16a", "atmel,24c16";
+ reg = <0x50>;
+ pagesize = <16>;
+ read-only;
+ vcc-supply = <&vcc_3v3_s3>;
+ };
+};
+
&pcie30phy {
data-lanes = <1 1 2 2>;
};
status = "okay";
};
+&i2c1 {
+ eeprom@50 {
+ compatible = "belling,bl24c16a", "atmel,24c16";
+ reg = <0x50>;
+ pagesize = <16>;
+ read-only;
+ vcc-supply = <&vcc_3v3_s3>;
+ };
+};
+
&pcie2x1l1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie2_1_rst>;
reg = <0x42>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_npu_s0";
- regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
domain-supply = <&vdd_gpu_s0>;
};
+&pd_npu {
+ domain-supply = <&vdd_npu_s0>;
+};
+
&pinctrl {
emmc {
emmc_reset: emmc-reset {
pinctrl-names = "default";
};
+&rknn_core_0 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_core_1 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_core_2 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_mmu_0 {
+ status = "okay";
+};
+
+&rknn_mmu_1 {
+ status = "okay";
+};
+
+&rknn_mmu_2 {
+ status = "okay";
+};
+
&saradc {
vref-supply = <&vcc_1v8_s0>;
status = "okay";
reg = <0x42>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_npu_s0";
- regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
domain-supply = <&vdd_gpu_s0>;
};
+&pd_npu {
+ domain-supply = <&vdd_npu_s0>;
+};
+
&pinctrl {
fan {
fan_int: fan-int {
status = "okay";
};
+&rknn_core_0 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_core_1 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_core_2 {
+ npu-supply = <&vdd_npu_s0>;
+ sram-supply = <&vdd_npu_s0>;
+ status = "okay";
+};
+
+&rknn_mmu_0 {
+ status = "okay";
+};
+
+&rknn_mmu_1 {
+ status = "okay";
+};
+
+&rknn_mmu_2 {
+ status = "okay";
+};
+
&sdhci {
bus-width = <8>;
no-sdio;
sound-name-prefix = "Headphones Amplifier";
};
+ hdmi0-con {
+ compatible = "hdmi-connector";
+ ddc-en-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&hdmi0_en>;
+ pinctrl-names = "default";
+ type = "d";
+
+ port {
+ hdmi0_con_in: endpoint {
+ remote-endpoint = <&hdmi0_out_con>;
+ };
+ };
+ };
+
pwm_fan: pwm-fan {
compatible = "pwm-fan";
#cooling-cells = <2>;
status = "okay";
};
+&hdmi0 {
+ no-hpd;
+ pinctrl-0 = <&hdmim0_tx0_cec>, <&hdmim0_tx0_scl>,
+ <&hdmim0_tx0_sda>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&hdmi0_in {
+ hdmi0_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi0>;
+ };
+};
+
+&hdmi0_out {
+ hdmi0_out_con: endpoint {
+ remote-endpoint = <&hdmi0_con_in>;
+ };
+};
+
+&hdmi0_sound {
+ status = "okay";
+};
+
+&hdptxphy0 {
+ status = "okay";
+};
+
&i2c0 {
pinctrl-0 = <&i2c0m2_xfer>;
pinctrl-names = "default";
status = "okay";
};
+&i2s5_8ch {
+ status = "okay";
+};
+
&mipidcphy0 {
status = "okay";
};
};
};
+ hdmi {
+ hdmi0_en: hdmi0-en {
+ rockchip,pins =
+ <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins =
status = "okay";
};
+&vp0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi0_in_vp0>;
+ };
+};
+
&vp3 {
#address-cells = <1>;
#size-cells = <0>;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+
+#include "rk3588s-orangepi-cm5.dtsi"
+
+/ {
+ model = "Xunlong Orange Pi CM5 Base";
+ compatible = "xunlong,orangepi-cm5-base", "xunlong,orangepi-cm5", "rockchip,rk3588s";
+
+ aliases {
+ ethernet0 = &gmac1;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&key1_pin>;
+
+ button {
+ debounce-interval = <50>;
+ gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>;
+ label = "USERKEY";
+ linux,code = <BTN_MISC>;
+ wakeup-source;
+ };
+ };
+
+ hdmi0-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi0_con_in: endpoint {
+ remote-endpoint = <&hdmi0_out_con>;
+ };
+ };
+ };
+
+ pwm-leds {
+ compatible = "pwm-leds";
+
+ led-1 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_STATUS;
+ linux,default-trigger = "heartbeat";
+ max-brightness = <255>;
+ pwms = <&pwm2 0 25000 0>;
+ };
+
+ led-2 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WAN;
+ max-brightness = <255>;
+ pwms = <&pwm4 0 25000 PWM_POLARITY_INVERTED>;
+ };
+
+ led-3 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <0>;
+ max-brightness = <255>;
+ pwms = <&pwm5 0 25000 PWM_POLARITY_INVERTED>;
+ };
+
+ led-4 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <1>;
+ max-brightness = <255>;
+ pwms = <&pwm6 0 25000 0>;
+ };
+ };
+
+ vbus_5v0: regulator-vbus-5v0 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vbus_5v0_en_pin>;
+ regulator-name = "vbus_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc_3v3: regulator-vcc-3v3 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc_3v3_en_pin>;
+ regulator-name = "vcc_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <50000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_sys: regulator-vcc-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&gmac1 {
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy>;
+ phy-mode = "rgmii-id";
+ phy-supply = <&vcc_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1_miim
+ &gmac1_rx_bus2
+ &gmac1_tx_bus2
+ &gmac1_rgmii_clk
+ &gmac1_rgmii_bus>;
+ status = "okay";
+};
+
+&hdmi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
+ &hdmim0_tx0_scl &hdmim0_tx0_sda
+ &hdmi_frl_pin>;
+ status = "okay";
+};
+
+&hdmi0_in {
+ hdmi0_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi0>;
+ };
+};
+
+&hdmi0_out {
+ hdmi0_out_con: endpoint {
+ remote-endpoint = <&hdmi0_con_in>;
+ };
+};
+
+&hdmi0_sound {
+ status = "okay";
+};
+
+&hdptxphy0 {
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1m2_xfer>;
+ status = "okay";
+
+ rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtc_int_pin>;
+ wakeup-source;
+ };
+};
+
+&i2s5_8ch {
+ status = "okay";
+};
+
+&mdio1 {
+ rgmii_phy: ethernet-phy@1 {
+ /* YT8531C */
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_phy_pin>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pcie2x1l1 {
+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&pcie2x1l2 {
+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&pinctrl {
+ camera {
+ cam1_reset_pin: cam1-reset-pin {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ cam2_reset_pin: cam2-reset-pin {
+ rockchip,pins = <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ cam3_reset_pin: cam3-reset-pin {
+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ cam4_reset_pin: cam4-reset-pin {
+ rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ ethernet {
+ rgmii_phy_pin: rgmii-phy-pin {
+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ gpio-key {
+ key1_pin: key1-pin {
+ rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ hdmi {
+ hdmi_frl_pin: hdmi-frl-pin {
+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ power {
+ vcc_3v3_en_pin: vcc-3v3-en-pin {
+ rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ rtc {
+ rtc_int_pin: rtc-int-pin {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vbus_5v0_en_pin: vbus-5v0-en-pin {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&pwm5 {
+ pinctrl-0 = <&pwm5m1_pins>;
+ status = "okay";
+};
+
+&pwm6 {
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <150000000>;
+ no-mmc;
+ no-sdio;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ phy-supply = <&vbus_5v0>;
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ phy-supply = <&vbus_5v0>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbdp_phy0 {
+ status = "okay";
+};
+
+&vop {
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi0_in_vp0>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/clock/rockchip,rk3588-cru.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "rk3588s.dtsi"
+#include "rk8xx.h"
+
+/ {
+ aliases {
+ mmc0 = &sdhci;
+ };
+
+ /* Can't be verified due to missing schematics for the CM5. */
+ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu_s0>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ vdd_npu_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_npu_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&pd_gpu {
+ domain-supply = <&vdd_gpu_s0>;
+};
+
+&sdhci {
+ bus-width = <8>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ max-frequency = <200000000>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ status = "okay";
+};
+
+&spi2 {
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <1>;
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+ status = "okay";
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ reg = <0x0>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ spi-max-frequency = <1000000>;
+ system-power-controller;
+ rockchip,reset-mode = <RK806_RESET>;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: dcdc-reg1 {
+ regulator-name = "vdd_gpu_s0";
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <400>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: dcdc-reg2 {
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: dcdc-reg3 {
+ regulator-name = "vdd_log_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: dcdc-reg4 {
+ regulator-name = "vdd_vdenc_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-name = "vdd_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-name = "vdd2_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1100000>;
+ regulator-min-microvolt = <1100000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-name = "vdd_2v0_pldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-name = "vcc_3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-name = "vddq_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg10 {
+ regulator-name = "vcc_1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avcc_1v8_s0: pldo-reg1 {
+ regulator-name = "avcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg2 {
+ regulator-name = "vcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avdd_1v2_s0: pldo-reg3 {
+ regulator-name = "avdd_1v2_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s0: pldo-reg4 {
+ regulator-name = "vcc_3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-name = "vccio_sd_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-name = "pldo6_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-name = "vdd_0v75_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_ddr_pll_s0: nldo-reg2 {
+ regulator-name = "vdd_ddr_pll_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ avdd_0v75_s0: nldo-reg3 {
+ regulator-name = "avdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: nldo-reg4 {
+ regulator-name = "vdd_0v85_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: nldo-reg5 {
+ regulator-name = "vdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&tsadc {
+ /*
+ * The TSADC_SHUT pin is exposed to carrier boards as a signal named
+ * PMIC_RESET_L, meant to be driven externally. Reference carrier
+ * boards connect it to a reset button that pulls the signal to GND
+ * through a 100Ω resistor. This is too weak to overcome even the
+ * minimum drive strength of the TSADC_SHUT pin when driven in
+ * push-pull mode. Configure it as a GPIO, reset will be generated
+ * through the CRU.
+ */
+ pinctrl-0 = <&tsadc_gpio_func>;
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2025 Joseph Kogut <joseph.kogut@gmail.com>
+ */
+
+/*
+ * CM5 IO board data sheet
+ * https://dl.radxa.com/cm5/v2200/radxa_cm5_io_v2200_schematic.pdf
+ */
+
+/dts-v1/;
+#include "rk3588s.dtsi"
+#include "rk3588s-radxa-cm5.dtsi"
+
+/ {
+ model = "Radxa Compute Module 5 (CM5) IO Board";
+ compatible = "radxa,cm5-io", "radxa,cm5", "rockchip,rk3588s";
+
+ aliases {
+ ethernet0 = &gmac1;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi0_out_con>;
+ };
+ };
+ };
+
+ vcc12v_dcin: regulator-12v0-vcc-dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_host";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_sys: regulator-5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vbus5v0_typec: vbus5v0-typec {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus5v0_typec";
+ gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vbus5v0_typec_en>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_pcie: regulator-3v3-vcc-pcie {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie2x1l0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <50000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc_3v3_s0: pldo-reg4 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&gmac1 {
+ status = "okay";
+};
+
+&hdmi0 {
+ status = "okay";
+};
+
+&hdmi0_in {
+ hdmi0_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi0>;
+ };
+};
+
+&hdmi0_out {
+ hdmi0_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&hdmi0_sound {
+ status = "okay";
+};
+
+&hdptxphy0 {
+ status = "okay";
+};
+
+&i2c6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6m3_xfer>;
+ status = "okay";
+
+ fusb302: usb-typec@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbc0_int>;
+ vbus-supply = <&vbus5v0_typec>;
+
+ connector {
+ compatible = "usb-c-connector";
+ data-role = "dual";
+ label = "USB-C";
+ power-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
+ op-sink-microwatt = <1000000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ usbc0_orientation_switch: endpoint {
+ remote-endpoint = <&usbdp_phy0_orientation_switch>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ usbc0_role_switch: endpoint {
+ remote-endpoint = <&usb_host0_xhci_role_switch>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ usbc0_dp_altmode_mux: endpoint {
+ remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&i2s5_8ch {
+ status = "okay";
+};
+
+&pcie2x1l2 {
+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
+&pinctrl {
+ fusb302 {
+ vbus5v0_typec_en: vbus5v0-typec-en {
+ rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usbc0_int: usbc0-int {
+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ no-sdio;
+ sd-uhs-sdr104;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy3_host {
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ dr_mode = "otg";
+ usb-role-switch;
+ status = "okay";
+
+ port {
+ usb_host0_xhci_role_switch: endpoint {
+ remote-endpoint = <&usbc0_role_switch>;
+ };
+ };
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usb_host2_xhci {
+ status = "okay";
+};
+
+&usbdp_phy0 {
+ mode-switch;
+ orientation-switch;
+ sbu1-dc-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
+ sbu2-dc-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbdp_phy0_orientation_switch: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&usbc0_orientation_switch>;
+ };
+
+ usbdp_phy0_dp_altmode_mux: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&usbc0_dp_altmode_mux>;
+ };
+ };
+};
+
+&vop {
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi0_in_vp0>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2025 Joseph Kogut <joseph.kogut@gmail.com>
+ */
+
+/*
+ * CM5 data sheet
+ * https://dl.radxa.com/cm5/v2210/radxa_cm5_v2210_schematic.pdf
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include <dt-bindings/usb/pd.h>
+
+/ {
+ compatible = "radxa,cm5", "rockchip,rk3588s";
+
+ aliases {
+ mmc0 = &sdhci;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_sys: led-0 {
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "on";
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gmac1 {
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii-id";
+ phy-supply = <&vcc_3v3_s0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1_miim
+ &gmac1_tx_bus2
+ &gmac1_rx_bus2
+ &gmac1_rgmii_clk
+ &gmac1_rgmii_bus
+ &gmac1_clkinout>;
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu_s0>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&mdio1 {
+ rgmii_phy1: phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ };
+};
+
+&pd_gpu {
+ domain-supply = <&vdd_gpu_s0>;
+};
+
+&sdhci {
+ bus-width = <8>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ max-frequency = <200000000>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ mmc-hs200-1_8v;
+ status = "okay";
+};
+
+&spi2 {
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+ status = "okay";
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ reg = <0x0>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ spi-max-frequency = <1000000>;
+ system-power-controller;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vdd2_ddr_s3>;
+ vcc14-supply = <&vdd2_ddr_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: dcdc-reg1 {
+ regulator-name = "vdd_gpu_s0";
+ regulator-boot-on;
+ regulator-enable-ramp-delay = <400>;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: dcdc-reg2 {
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-name = "vdd2_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-name = "vdd_2v0_pldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-name = "vcc_3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+ };
+ };
+};
compatible = "belling,bl24c16a", "atmel,24c16";
reg = <0x50>;
pagesize = <16>;
+ read-only;
vcc-supply = <&vcc_3v3_pmu>;
};
};
compatible = "belling,bl24c16a", "atmel,24c16";
reg = <0x50>;
pagesize = <16>;
+ read-only;
vcc-supply = <&vcc_3v3_pmu>;
};
};
idle-states {
entry-method = "psci";
- CORE_PD: core_pd {
+ CORE_PD: cpu-pd {
compatible = "arm,idle-state";
entry-latency-us = <1000>;
exit-latency-us = <700>;
arm,psci-suspend-param = <0x00010002>;
};
- CLUSTER_PD: cluster_pd {
+ CLUSTER_PD: cluster-pd {
compatible = "arm,idle-state";
entry-latency-us = <1000>;
exit-latency-us = <1000>;
reg = <0 0x10003000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
- out-ports {
+
+ in-ports {
port {
etb_in: endpoint {
remote-endpoint =
idle-states {
entry-method = "psci";
- CORE_PD: core-pd {
+ CORE_PD: cpu-pd {
compatible = "arm,idle-state";
entry-latency-us = <4000>;
exit-latency-us = <4000>;
};
};
- ap-ahb {
+ ahb {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
#size-cells = <2>;
ranges;
- ap-apb {
+ apb {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
#clock-cells = <1>;
};
- ap-apb@70000000 {
+ apb@70000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
- ap-ahb {
+ ahb {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
};
};
- aon {
+ aon-bus {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
};
};
- agcp {
+ agcp-bus {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/ {
-};
<&hpdma 52 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 23>;
+ power-domains = <&cluster_pd>;
status = "disabled";
};
<&hpdma 54 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 24>;
+ power-domains = <&cluster_pd>;
status = "disabled";
};
<&hpdma 28 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 41>;
+ power-domains = <&cluster_pd>;
+ i2c-analog-filter;
status = "disabled";
};
<&hpdma 31 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 42>;
+ power-domains = <&cluster_pd>;
+ i2c-analog-filter;
status = "disabled";
};
<&hpdma 46 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 47>;
+ power-domains = <&cluster_pd>;
+ i2c-analog-filter;
status = "disabled";
};
<&hpdma 50 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 22>;
+ power-domains = <&cluster_pd>;
status = "disabled";
};
<&hpdma 56 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 25>;
+ power-domains = <&cluster_pd>;
status = "disabled";
};
<&hpdma 58 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 26>;
+ power-domains = <&cluster_pd>;
status = "disabled";
};
<&hpdma 169 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 48>;
+ power-domains = <&cluster_pd>;
+ i2c-analog-filter;
status = "disabled";
};
<&rcc CK_KER_CSIPHY>;
clock-names = "pclk", "txesc", "csi2phy";
access-controllers = <&rifsc 86>;
+ power-domains = <&cluster_pd>;
status = "disabled";
};
clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>;
clock-names = "kclk", "mclk";
access-controllers = <&rifsc 87>;
+ power-domains = <&cluster_pd>;
status = "disabled";
};
#address-cells = <1>;
#size-cells = <1>;
- part_number_otp@24 {
+ part-number-otp@24 {
reg = <0x24 0x4>;
};
- package_otp@1e8 {
+ package-otp@1e8 {
reg = <0x1e8 0x1>;
bits = <0 3>;
};
gpio-leds {
compatible = "gpio-leds";
- led-blue {
+ led_blue: led-blue {
function = LED_FUNCTION_HEARTBEAT;
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioh 5 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-orange {
+ color = <LED_COLOR_ID_ORANGE>;
+ gpios = <&gpioh 6 GPIO_ACTIVE_HIGH>;
+ };
};
memory@80000000 {
reg = <0x0 0x80000000 0x0 0x80000000>;
};
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ boot-led = <&led_blue>;
+ };
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
phy1_eth1: ethernet-phy@1 {
compatible = "ethernet-phy-id001c.c916";
reg = <1>;
- reset-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/ {
-};
<&hpdma 52 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 23>;
+ power-domains = <&CLUSTER_PD>;
status = "disabled";
};
<&hpdma 54 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 24>;
+ power-domains = <&CLUSTER_PD>;
status = "disabled";
};
<&hpdma 28 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 41>;
+ power-domains = <&CLUSTER_PD>;
+ i2c-analog-filter;
status = "disabled";
};
<&hpdma 31 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 42>;
+ power-domains = <&CLUSTER_PD>;
+ i2c-analog-filter;
status = "disabled";
};
<&hpdma 34 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 43>;
+ power-domains = <&CLUSTER_PD>;
+ i2c-analog-filter;
status = "disabled";
};
<&hpdma 37 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 44>;
+ power-domains = <&CLUSTER_PD>;
+ i2c-analog-filter;
status = "disabled";
};
<&hpdma 40 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 45>;
+ power-domains = <&CLUSTER_PD>;
+ i2c-analog-filter;
status = "disabled";
};
<&hpdma 43 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 46>;
+ power-domains = <&CLUSTER_PD>;
+ i2c-analog-filter;
status = "disabled";
};
<&hpdma 46 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 47>;
+ power-domains = <&CLUSTER_PD>;
+ i2c-analog-filter;
status = "disabled";
};
<&hpdma 50 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 22>;
+ power-domains = <&CLUSTER_PD>;
status = "disabled";
};
<&hpdma 56 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 25>;
+ power-domains = <&CLUSTER_PD>;
status = "disabled";
};
<&hpdma 58 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 26>;
+ power-domains = <&CLUSTER_PD>;
status = "disabled";
};
<&hpdma 60 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 27>;
+ power-domains = <&CLUSTER_PD>;
status = "disabled";
};
<&hpdma 62 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 28>;
+ power-domains = <&CLUSTER_PD>;
status = "disabled";
};
<&hpdma 172 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 29>;
+ power-domains = <&CLUSTER_PD>;
status = "disabled";
};
<&hpdma 169 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 48>;
+ power-domains = <&CLUSTER_PD>;
+ i2c-analog-filter;
status = "disabled";
};
<&rcc CK_KER_CSIPHY>;
clock-names = "pclk", "txesc", "csi2phy";
access-controllers = <&rifsc 86>;
+ power-domains = <&CLUSTER_PD>;
status = "disabled";
};
clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>;
clock-names = "kclk", "mclk";
access-controllers = <&rifsc 87>;
+ power-domains = <&CLUSTER_PD>;
status = "disabled";
};
#address-cells = <1>;
#size-cells = <1>;
- part_number_otp@24 {
+ part-number-otp@24 {
reg = <0x24 0x4>;
};
- package_otp@1e8 {
+ package-otp@1e8 {
reg = <0x1e8 0x1>;
bits = <0 3>;
};
gpio-leds {
compatible = "gpio-leds";
- led-blue {
+ led_blue: led-blue {
function = LED_FUNCTION_HEARTBEAT;
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpioh 5 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-orange {
+ color = <LED_COLOR_ID_ORANGE>;
+ gpios = <&gpioh 6 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ lpddr_channel: sdram-channel-0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "jedec,lpddr4-channel";
+ io-width = <32>;
};
memory@80000000 {
reg = <0x0 0x80000000 0x1 0x0>;
};
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ boot-led = <&led_blue>;
+ };
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
phy1_eth1: ethernet-phy@1 {
compatible = "ethernet-phy-id001c.c916";
reg = <1>;
- reset-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
};
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/regulator/st,stm32mp25-regulator.h>
#include "stm32mp257.dtsi"
#include "stm32mp25xf.dtsi"
};
};
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ led_blue: led-blue {
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&gpioj 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpiod 8 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-orange {
+ color = <LED_COLOR_ID_ORANGE>;
+ gpios = <&gpioj 6 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ ddr_channel: sdram-channel-0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "jedec,ddr4-channel";
+ io-width = <32>;
+ };
+
imx335_2v9: regulator-2v9 {
compatible = "regulator-fixed";
regulator-name = "imx335-avdd";
reg = <0x0 0x80000000 0x1 0x0>;
};
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ boot-led = <&led_blue>;
+ };
+ };
+
panel_lvds: display {
compatible = "edt,etml0700z9ndha", "panel-lvds";
enable-gpios = <&gpiog 15 GPIO_ACTIVE_HIGH>;
phy1_eth1: ethernet-phy@4 {
compatible = "ethernet-phy-id001c.c916";
reg = <4>;
- reset-gpios = <&gpioj 9 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpioj 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-/ {
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
- */
-
-&pinctrl {
- st,package = <STM32MP_PKG_AL>;
-
- gpioa: gpio@44240000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@44250000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@44260000 {
- status = "okay";
- ngpios = <14>;
- gpio-ranges = <&pinctrl 0 32 14>;
- };
-
- gpiod: gpio@44270000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@44280000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@44290000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@442a0000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@442b0000 {
- status = "okay";
- ngpios = <12>;
- gpio-ranges = <&pinctrl 2 114 12>;
- };
-
- gpioi: gpio@442c0000 {
- status = "okay";
- ngpios = <12>;
- gpio-ranges = <&pinctrl 0 128 12>;
- };
-};
-
-&pinctrl_z {
- gpioz: gpio@46200000 {
- status = "okay";
- ngpios = <10>;
- gpio-ranges = <&pinctrl_z 0 400 10>;
- };
-};
bootph-all;
};
+&cpsw_mac_syscon {
+ bootph-all;
+};
+
&cpsw3g_mdio {
pinctrl-names = "default";
pinctrl-0 = <&main_mdio1_pins_default>;
};
};
+&phy_gmii_sel {
+ bootph-all;
+};
+
&sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
bootph-all;
};
+&cpsw_mac_syscon {
+ bootph-all;
+};
+
&cpsw3g_mdio {
pinctrl-names = "default";
pinctrl-0 = <&main_mdio1_pins_default>;
};
};
+&phy_gmii_sel {
+ bootph-all;
+};
+
&sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
pinctrl-0 = <&ospi0_pins_default>;
status = "okay";
- flash@0{
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
clocks = <&k3_clks 204 2>;
power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>;
};
+
+ hsm: remoteproc@43c00000 {
+ compatible = "ti,hsm-m4fss";
+ /* contiguous regions but instantiated separately in HW */
+ reg = <0x00 0x43c00000 0x00 0x20000>,
+ <0x00 0x43c20000 0x00 0x10000>,
+ <0x00 0x43c30000 0x00 0x10000>;
+ reg-names = "sram0_0", "sram0_1", "sram1";
+ resets = <&k3_reset 225 1>;
+ firmware-name = "am62p-hsm-m4f-fw";
+ bootph-pre-ram;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <225>;
+ ti,sci-proc-ids = <0x80 0xff>;
+ /* reserved for early-stage bootloader */
+ status = "reserved";
+ };
};
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "+V3.3_SD";
- startup-delay-us = <2000>;
+ startup-delay-us = <20000>;
};
reg_sd1_vqmmc: regulator-sdhci1-vqmmc {
pinctrl-single,pins = <
AM62PX_IOPAD(0x0120, PIN_INPUT, 0) /* (K24) MMC2_CMD */ /* SODIMM 160, WiFi_SDIO_CMD */
AM62PX_IOPAD(0x0118, PIN_OUTPUT, 0) /* (K21) MMC2_CLK */ /* SODIMM 156, WiFi_SDIO_CLK */
- AM62PX_IOPAD(0x011C, PIN_INPUT, 0) /* () MMC2_CLKLB */
+ AM62PX_IOPAD(0x011c, PIN_INPUT, 0) /* () MMC2_CLKLB */
AM62PX_IOPAD(0x0114, PIN_INPUT, 0) /* (K23) MMC2_DAT0 */ /* SODIMM 162, WiFi_SDIO_DATA0 */
AM62PX_IOPAD(0x0110, PIN_INPUT, 0) /* (K22) MMC2_DAT1 */ /* SODIMM 164, WiFi_SDIO_DATA1 */
AM62PX_IOPAD(0x010c, PIN_INPUT, 0) /* (L20) MMC2_DAT2 */ /* SODIMM 166, WiFi_SDIO_DATA2 */
<0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
+ <0x00 0x43c00000 0x00 0x43c00000 0x00 0x00040000>, /* HSM SRAM ranges */
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
<0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */
pinctrl-single,pins = <
AM62PX_IOPAD(0x0120, PIN_INPUT, 0) /* (K24) MMC2_CMD */
AM62PX_IOPAD(0x0118, PIN_OUTPUT, 0) /* (K21) MMC2_CLK */
- AM62PX_IOPAD(0x011C, PIN_INPUT, 0) /* () MMC2_CLKLB */
+ AM62PX_IOPAD(0x011c, PIN_INPUT, 0) /* () MMC2_CLKLB */
AM62PX_IOPAD(0x0114, PIN_INPUT, 0) /* (K23) MMC2_DAT0 */
AM62PX_IOPAD(0x0110, PIN_INPUT_PULLUP, 0) /* (K22) MMC2_DAT1 */
AM62PX_IOPAD(0x010c, PIN_INPUT_PULLUP, 0) /* (L20) MMC2_DAT2 */
status = "okay";
};
-&main_i2c0{
+&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_mmc1>;
disable-wp;
bootph-all;
- status="okay";
+ status = "okay";
};
&ti_csi2rx0 {
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01840000 0x00 0xC0000>, /* GICR */
+ <0x00 0x01840000 0x00 0xc0000>, /* GICR */
<0x01 0x00000000 0x00 0x2000>, /* GICC */
<0x01 0x00010000 0x00 0x1000>, /* GICH */
<0x01 0x00020000 0x00 0x2000>; /* GICV */
power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
- dmas = <&main_pktdma 0xC500 15>,
- <&main_pktdma 0xC501 15>,
- <&main_pktdma 0xC502 15>,
- <&main_pktdma 0xC503 15>,
- <&main_pktdma 0xC504 15>,
- <&main_pktdma 0xC505 15>,
- <&main_pktdma 0xC506 15>,
- <&main_pktdma 0xC507 15>,
+ dmas = <&main_pktdma 0xc500 15>,
+ <&main_pktdma 0xc501 15>,
+ <&main_pktdma 0xc502 15>,
+ <&main_pktdma 0xc503 15>,
+ <&main_pktdma 0xc504 15>,
+ <&main_pktdma 0xc505 15>,
+ <&main_pktdma 0xc506 15>,
+ <&main_pktdma 0xc507 15>,
<&main_pktdma 0x4500 15>;
dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
"tx7", "rx";
pinctrl-single,pins = <
AM64X_IOPAD(0x0200, PIN_INPUT, 0) /* (P2) PRG0_MDIO0_MDIO */
AM64X_IOPAD(0x0204, PIN_OUTPUT, 0) /* (P3) PRG0_MDIO0_MDC */
- AM64X_IOPAD(0x01A8, PIN_OUTPUT, 7) /* (V1) PRG0_PRU0_GPO18.GPIO1_18 */
- AM64X_IOPAD(0x01AC, PIN_OUTPUT, 7) /* (W1) PRG0_PRU0_GPO19.GPIO1_19 */
+ AM64X_IOPAD(0x01a8, PIN_OUTPUT, 7) /* (V1) PRG0_PRU0_GPO18.GPIO1_18 */
+ AM64X_IOPAD(0x01ac, PIN_OUTPUT, 7) /* (W1) PRG0_PRU0_GPO19.GPIO1_19 */
>;
};
main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
- AM64X_IOPAD(0x024C, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
+ AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
>;
main_spi1_pins_default: main-spi1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0224, PIN_INPUT, 0) /* (C14) SPI1_CLK */
- AM64X_IOPAD(0x021C, PIN_OUTPUT, 0) /* (B14) SPI1_CS0 */
+ AM64X_IOPAD(0x021c, PIN_OUTPUT, 0) /* (B14) SPI1_CS0 */
AM64X_IOPAD(0x0228, PIN_OUTPUT, 0) /* (B15) SPI1_D0 */
- AM64X_IOPAD(0x022C, PIN_INPUT, 0) /* (A15) SPI1_D1 */
+ AM64X_IOPAD(0x022c, PIN_INPUT, 0) /* (A15) SPI1_D1 */
>;
};
d2_uart0_ctsn: d2-uart0-ctsn-pins {
pinctrl-single,pins = <
/* (P1) MCU_UART0_CTSn */
- AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4)
+ AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 4)
>;
};
d2_gpio: d2-gpio-pins {
pinctrl-single,pins = <
/* (P5) WKUP_GPIO0_31 */
- AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7)
+ AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 7)
>;
};
d2_gpio_pullup: d2-gpio-pullup-pins {
pinctrl-single,pins = <
/* (P5) WKUP_GPIO0_31 */
- AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7)
+ AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 7)
>;
};
d2_gpio_pulldown: d2-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (P5) WKUP_GPIO0_31 */
- AM65X_WKUP_IOPAD(0x004C, PIN_INPUT_PULLDOWN, 7)
+ AM65X_WKUP_IOPAD(0x004c, PIN_INPUT_PULLDOWN, 7)
>;
};
a2_gpio: a2-gpio-pins {
pinctrl-single,pins = <
/* (L5) WKUP_GPIO0_43 */
- AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7)
+ AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 7)
>;
};
a2_gpio_pullup: a2-gpio-pullup-pins {
pinctrl-single,pins = <
/* (L5) WKUP_GPIO0_43 */
- AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7)
+ AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 7)
>;
};
a2_gpio_pulldown: a2-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (L5) WKUP_GPIO0_43 */
- AM65X_WKUP_IOPAD(0x007C, PIN_INPUT_PULLDOWN, 7)
+ AM65X_WKUP_IOPAD(0x007c, PIN_INPUT_PULLDOWN, 7)
>;
};
a3_gpio: a3-gpio-pins {
pinctrl-single,pins = <
/* (M5) WKUP_GPIO0_39 */
- AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7)
+ AM65X_WKUP_IOPAD(0x006c, PIN_INPUT, 7)
>;
};
a3_gpio_pullup: a3-gpio-pullup-pins {
pinctrl-single,pins = <
/* (M5) WKUP_GPIO0_39 */
- AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7)
+ AM65X_WKUP_IOPAD(0x006c, PIN_INPUT, 7)
>;
};
a3_gpio_pulldown: a3-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (M5) WKUP_GPIO0_39 */
- AM65X_WKUP_IOPAD(0x006C, PIN_INPUT_PULLDOWN, 7)
+ AM65X_WKUP_IOPAD(0x006c, PIN_INPUT_PULLDOWN, 7)
>;
};
a5_gpio: a5-gpio-pins {
pinctrl-single,pins = <
/* (N5) WKUP_GPIO0_35 */
- AM65X_WKUP_IOPAD(0x005C, PIN_INPUT, 7)
+ AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 7)
>;
};
a5_gpio_pullup: a5-gpio-pullup-pins {
pinctrl-single,pins = <
/* (N5) WKUP_GPIO0_35 */
- AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLUP, 7)
+ AM65X_WKUP_IOPAD(0x005c, PIN_INPUT_PULLUP, 7)
>;
};
a5_gpio_pulldown: a5-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (N5) WKUP_GPIO0_35 */
- AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLDOWN, 7)
+ AM65X_WKUP_IOPAD(0x005c, PIN_INPUT_PULLDOWN, 7)
>;
};
d5_ehrpwm1_a: d5-ehrpwm1-a-pins {
pinctrl-single,pins = <
/* (AF17) EHRPWM1_A */
- AM65X_IOPAD(0x008C, PIN_OUTPUT, 5)
+ AM65X_IOPAD(0x008c, PIN_OUTPUT, 5)
>;
};
d5_gpio: d5-gpio-pins {
pinctrl-single,pins = <
/* (AF17) GPIO0_35 */
- AM65X_IOPAD(0x008C, PIN_INPUT, 7)
+ AM65X_IOPAD(0x008c, PIN_INPUT, 7)
>;
};
d5_gpio_pullup: d5-gpio-pullup-pins {
pinctrl-single,pins = <
/* (AF17) GPIO0_35 */
- AM65X_IOPAD(0x008C, PIN_INPUT_PULLUP, 7)
+ AM65X_IOPAD(0x008c, PIN_INPUT_PULLUP, 7)
>;
};
d5_gpio_pulldown: d5-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (AF17) GPIO0_35 */
- AM65X_IOPAD(0x008C, PIN_INPUT_PULLDOWN, 7)
+ AM65X_IOPAD(0x008c, PIN_INPUT_PULLDOWN, 7)
>;
};
d7_ehrpwm3_a: d7-ehrpwm3-a-pins {
pinctrl-single,pins = <
/* (AH15) EHRPWM3_A */
- AM65X_IOPAD(0x00AC, PIN_OUTPUT, 5)
+ AM65X_IOPAD(0x00ac, PIN_OUTPUT, 5)
>;
};
d7_gpio: d7-gpio-pins {
pinctrl-single,pins = <
/* (AH15) GPIO0_43 */
- AM65X_IOPAD(0x00AC, PIN_INPUT, 7)
+ AM65X_IOPAD(0x00ac, PIN_INPUT, 7)
>;
};
d7_gpio_pullup: d7-gpio-pullup-pins {
pinctrl-single,pins = <
/* (AH15) GPIO0_43 */
- AM65X_IOPAD(0x00AC, PIN_INPUT_PULLUP, 7)
+ AM65X_IOPAD(0x00ac, PIN_INPUT_PULLUP, 7)
>;
};
d7_gpio_pulldown: d7-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (AH15) GPIO0_43 */
- AM65X_IOPAD(0x00AC, PIN_INPUT_PULLDOWN, 7)
+ AM65X_IOPAD(0x00ac, PIN_INPUT_PULLDOWN, 7)
>;
};
d8_ehrpwm4_a: d8-ehrpwm4-a-pins {
pinctrl-single,pins = <
/* (AG15) EHRPWM4_A */
- AM65X_IOPAD(0x00C0, PIN_OUTPUT, 5)
+ AM65X_IOPAD(0x00c0, PIN_OUTPUT, 5)
>;
};
d8_gpio: d8-gpio-pins {
pinctrl-single,pins = <
/* (AG15) GPIO0_48 */
- AM65X_IOPAD(0x00C0, PIN_INPUT, 7)
+ AM65X_IOPAD(0x00c0, PIN_INPUT, 7)
>;
};
d8_gpio_pullup: d8-gpio-pullup-pins {
pinctrl-single,pins = <
/* (AG15) GPIO0_48 */
- AM65X_IOPAD(0x00C0, PIN_INPUT_PULLUP, 7)
+ AM65X_IOPAD(0x00c0, PIN_INPUT_PULLUP, 7)
>;
};
d8_gpio_pulldown: d8-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (AG15) GPIO0_48 */
- AM65X_IOPAD(0x00C0, PIN_INPUT_PULLDOWN, 7)
+ AM65X_IOPAD(0x00c0, PIN_INPUT_PULLDOWN, 7)
>;
};
d9_ehrpwm5_a: d9-ehrpwm5-a-pins {
pinctrl-single,pins = <
/* (AD15) EHRPWM5_A */
- AM65X_IOPAD(0x00CC, PIN_OUTPUT, 5)
+ AM65X_IOPAD(0x00cc, PIN_OUTPUT, 5)
>;
};
d9_gpio: d9-gpio-pins {
pinctrl-single,pins = <
/* (AD15) GPIO0_51 */
- AM65X_IOPAD(0x00CC, PIN_INPUT, 7)
+ AM65X_IOPAD(0x00cc, PIN_INPUT, 7)
>;
};
d9_gpio_pullup: d9-gpio-pullup-pins {
pinctrl-single,pins = <
/* (AD15) GPIO0_51 */
- AM65X_IOPAD(0x00CC, PIN_INPUT_PULLUP, 7)
+ AM65X_IOPAD(0x00cc, PIN_INPUT_PULLUP, 7)
>;
};
d9_gpio_pulldown: d9-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (AD15) GPIO0_51 */
- AM65X_IOPAD(0x00CC, PIN_INPUT_PULLDOWN, 7)
+ AM65X_IOPAD(0x00cc, PIN_INPUT_PULLDOWN, 7)
>;
};
};
minipcie_pins_default: minipcie-default-pins {
pinctrl-single,pins = <
/* (P2) MCU_OSPI1_DQS.WKUP_GPIO0_27 */
- AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7)
+ AM65X_WKUP_IOPAD(0x003c, PIN_OUTPUT, 7)
>;
};
};
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
- <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
+ <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07fd0000>;
ti,syscon-pcie-id = <&scm_conf 0x210>;
ti,syscon-pcie-mode = <&scm_conf 0x4060>;
bus-range = <0x0 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>,
- <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
+ <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07fd0000>;
ti,syscon-pcie-id = <&scm_conf 0x210>;
ti,syscon-pcie-mode = <&scm_conf 0x4070>;
bus-range = <0x0 0xff>;
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */
AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */
- AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */
+ AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */
AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */
>;
bootph-all;
linux,cma {
compatible = "shared-dma-pool";
reusable;
- size = <0x10000000>;
- alignment = <0x2000>;
+ size = <0x00 0x10000000>;
linux,cma-default;
};
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_3p3_s0>;
regulator-boot-on;
+ enable-active-high;
enable-gpios = <&main_gpio0 7 GPIO_ACTIVE_HIGH>;
gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>;
states = <3300000 0x0>,
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
+ J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
- J721S2_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
+ J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
- J721S2_WKUP_IOPAD(0x00C, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
+ J721S2_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
mcu_mcan1_pins_default: mcu-mcan1-default-pins {
pinctrl-single,pins = <
- J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
+ J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/
>;
};
mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */
- J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */
+ J721S2_WKUP_IOPAD(0x05c, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */
J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */
J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */
J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/
- J721S2_WKUP_IOPAD(0x0B8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */
+ J721S2_WKUP_IOPAD(0x0b8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */
J721S2_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */
- J721S2_WKUP_IOPAD(0x11C, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */
+ J721S2_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */
J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */
>;
};
pinctrl-0 = <&pinctrl_main_spi2>,
<&pinctrl_main_spi2_cs0>,
<&pinctrl_gpio_05>;
- cs-gpios = <0>, <&wkup_gpio0 29 GPIO_ACTIVE_LOW>;
+ cs-gpios = <&main_gpio0 39 GPIO_ACTIVE_LOW>,
+ <&wkup_gpio0 29 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@1 {
try-power-role = "sink";
self-powered;
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
- sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
- op-sink-microwatt = <1000000>;
+ sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>;
+ op-sink-microwatt = <0>;
ports {
#address-cells = <1>;
try-power-role = "sink";
self-powered;
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
- sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
- op-sink-microwatt = <1000000>;
+ sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>;
+ op-sink-microwatt = <0>;
ports {
#address-cells = <1>;
/* Aquila SPI_2 CS */
pinctrl_main_spi0_cs0: main-spi0-cs0-default-pins {
pinctrl-single,pins = <
- J784S4_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (AM37) SPI0_CS0 */ /* AQUILA D16 */
+ J784S4_IOPAD(0x0cc, PIN_OUTPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */ /* AQUILA D16 */
>;
};
/* Aquila SPI_1 CS */
pinctrl_main_spi2_cs0: main-spi2-cs0-default-pins {
pinctrl-single,pins = <
- J784S4_IOPAD(0x09c, PIN_OUTPUT, 10) /* (AF35) MCASP0_AXR11.SPI2_CS1 */ /* AQUILA D9 */
+ J784S4_IOPAD(0x09c, PIN_OUTPUT, 7) /* (AF35) MCASP0_AXR11.GPIO0_39 */ /* AQUILA D9 */
>;
};
&main_spi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_main_spi0>, <&pinctrl_main_spi0_cs0>;
+ cs-gpios = <&main_gpio0 51 GPIO_ACTIVE_LOW>;
status = "disabled";
};
&main_spi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_main_spi2>, <&pinctrl_main_spi2_cs0>;
+ cs-gpios = <&main_gpio0 39 GPIO_ACTIVE_LOW>;
status = "disabled";
};
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
pinctrl-single,pins = <
- J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */
+ J784S4_IOPAD(0x0c4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */
>;
};
rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
pinctrl-single,pins = <
- J784S4_IOPAD(0x0BC, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */
- J784S4_IOPAD(0x06C, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */
- J784S4_IOPAD(0x0B4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */
- J784S4_IOPAD(0x0C0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */
- J784S4_IOPAD(0x00C, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */
- J784S4_IOPAD(0x0B8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */
+ J784S4_IOPAD(0x0bc, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */
+ J784S4_IOPAD(0x06c, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */
+ J784S4_IOPAD(0x0b4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */
+ J784S4_IOPAD(0x0c0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */
+ J784S4_IOPAD(0x00c, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */
+ J784S4_IOPAD(0x0b8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */
J784S4_IOPAD(0x090, PIN_INPUT, 7) /* (AC35) MCASP0_AXR8.GPIO0_36 */
- J784S4_IOPAD(0x0A8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */
- J784S4_IOPAD(0x0A4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */
+ J784S4_IOPAD(0x0a8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */
+ J784S4_IOPAD(0x0a4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */
J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */
- J784S4_IOPAD(0x0CC, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */
- J784S4_IOPAD(0x08C, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */
+ J784S4_IOPAD(0x0cc, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */
+ J784S4_IOPAD(0x08c, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */
J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */
J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */
>;
main_mcan7_pins_default: main-mcan7-default-pins {
pinctrl-single,pins = <
- J784S4_IOPAD(0x0A0, PIN_INPUT, 0) /* (AD34) MCAN7_RX */
- J784S4_IOPAD(0x09C, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */
+ J784S4_IOPAD(0x0a0, PIN_INPUT, 0) /* (AD34) MCAN7_RX */
+ J784S4_IOPAD(0x09c, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */
>;
};
reg = <0x0 0x40f04200 0x0 0x28>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x0000000F>;
+ pinctrl-single,function-mask = <0x0000000f>;
status = "reserved";
};
reg = <0x0 0x40f04280 0x0 0x28>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x0000000F>;
+ pinctrl-single,function-mask = <0x0000000f>;
status = "reserved";
};
rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
pinctrl-single,pins = <
- J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */
+ J721E_IOPAD(0x01c, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */
J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */
- J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
- J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */
+ J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
+ J721E_IOPAD(0x02c, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */
J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
- J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
- J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
+ J721E_IOPAD(0x1b0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
+ J721E_IOPAD(0x1a0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */
- J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */
- J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */
+ J721E_IOPAD(0x1d0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */
+ J721E_IOPAD(0x11c, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */
J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */
J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */
J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */
J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */
- J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
- J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */
+ J721E_IOPAD(0x19c, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
+ J721E_IOPAD(0x1b4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */
J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
- J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */
+ J721E_IOPAD(0x00c, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */
J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */
J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */
- J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */
+ J721E_IOPAD(0x17c, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */
J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */
- J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */
+ J721E_IOPAD(0x18c, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */
>;
};
reg = <0x000>;
device_type = "cpu";
enable-method = "psci";
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
reg = <0x001>;
device_type = "cpu";
enable-method = "psci";
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
wkup_pmx1: pinctrl@4301c038 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
- reg = <0x00 0x4301c038 0x00 0x02C>;
+ reg = <0x00 0x4301c038 0x00 0x02c>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
/* reserved for MCU_R5F0_1 */
status = "reserved";
};
+
+ hsm: remoteproc@43c00000 {
+ compatible = "ti,hsm-m4fss";
+ /* contiguous regions but instantiated separately in HW */
+ reg = <0x00 0x43c00000 0x00 0x20000>,
+ <0x00 0x43c20000 0x00 0x10000>,
+ <0x00 0x43c30000 0x00 0x10000>;
+ reg-names = "sram0_0", "sram0_1", "sram1";
+ resets = <&k3_reset 304 1>;
+ firmware-name = "j721s2-hsm-m4f-fw";
+ bootph-pre-ram;
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <304>;
+ ti,sci-proc-ids = <0x80 0xff>;
+ /* reserved for early-stage bootloader */
+ status = "reserved";
+ };
};
mcu_mcan1_pins_default: mcu-mcan1-default-pins {
pinctrl-single,pins = <
J722S_MCU_IOPAD(0x040, PIN_INPUT, 0) /* (B1) MCU_MCAN1_RX */
- J722S_MCU_IOPAD(0x03C, PIN_OUTPUT, 0) /*(C1) MCU_MCAN1_TX */
+ J722S_MCU_IOPAD(0x03c, PIN_OUTPUT, 0) /*(C1) MCU_MCAN1_TX */
>;
};
firmware-name = "j722s-wkup-r5f0_0-fw";
};
+/* MAIN domain overrides */
+&hsm {
+ firmware-name = "j722s-hsm-m4f-fw";
+};
+
&main_conf {
serdes_ln_ctrl: mux-controller@4080 {
compatible = "reg-mux";
<0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */
<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
<0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
- <0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */
+ <0x00 0x301c0000 0x00 0x301c0000 0x00 0x00001000>, /* DPHY-TX */
<0x00 0x30101000 0x00 0x30101000 0x00 0x00080100>, /* CSI window */
<0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
<0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
<0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core window */
<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
+ <0x00 0x43c00000 0x00 0x43c00000 0x00 0x00040000>, /* HSM SRAM ranges */
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
<0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */
&mcu_r5fss0_core1 {
firmware-name = "j742s2-mcu-r5f0_1-fw";
};
+
+&hsm {
+ firmware-name = "j742s2-hsm-m4f-fw";
+};
J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */
J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */
J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */
- J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */
+ J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */
J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */
J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */
- J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */
+ J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */
>;
};
};
assigned-clock-parents = <&k3_clks 351 4>;
};
- watchdog4: watchdog@2240000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x2240000 0x00 0x100>;
- clocks = <&k3_clks 352 0>;
- power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 352 0>;
- assigned-clock-parents = <&k3_clks 352 4>;
- };
-
- watchdog5: watchdog@2250000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x2250000 0x00 0x100>;
- clocks = <&k3_clks 353 0>;
- power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 353 0>;
- assigned-clock-parents = <&k3_clks 353 4>;
- };
-
- watchdog6: watchdog@2260000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x2260000 0x00 0x100>;
- clocks = <&k3_clks 354 0>;
- power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 354 0>;
- assigned-clock-parents = <&k3_clks 354 4>;
- };
-
- watchdog7: watchdog@2270000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x2270000 0x00 0x100>;
- clocks = <&k3_clks 355 0>;
- power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 355 0>;
- assigned-clock-parents = <&k3_clks 355 4>;
- };
-
/*
* The following RTI instances are coupled with MCU R5Fs, c7x and
* GPU so keeping them reserved as these will be used by their
/* reserved for MCU_R5F0_1 */
status = "reserved";
};
+
+ hsm: remoteproc@43c00000 {
+ compatible = "ti,hsm-m4fss";
+ /* contiguous regions but instantiated separately in HW */
+ reg = <0x00 0x43c00000 0x00 0x20000>,
+ <0x00 0x43c20000 0x00 0x10000>,
+ <0x00 0x43c30000 0x00 0x10000>;
+ reg-names = "sram0_0", "sram0_1", "sram1";
+ resets = <&k3_reset 371 1>;
+ firmware-name = "j784s4-hsm-m4f-fw";
+ bootph-pre-ram;
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <371>;
+ ti,sci-proc-ids = <0x80 0xff>;
+ /* reserved for early-stage bootloader */
+ status = "reserved";
+ };
};
*/
&cbass_main {
- c71_3: dsp@67800000 {
- compatible = "ti,j721s2-c71-dsp";
- reg = <0x00 0x67800000 0x00 0x00080000>,
- <0x00 0x67e00000 0x00 0x0000c000>;
- reg-names = "l2sram", "l1dram";
- resets = <&k3_reset 40 1>;
- firmware-name = "j784s4-c71_3-fw";
- ti,sci = <&sms>;
- ti,sci-dev-id = <40>;
- ti,sci-proc-ids = <0x33 0xff>;
- status = "disabled";
+ watchdog4: watchdog@2240000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2240000 0x00 0x100>;
+ clocks = <&k3_clks 352 0>;
+ power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 352 0>;
+ assigned-clock-parents = <&k3_clks 352 4>;
+ };
+
+ watchdog5: watchdog@2250000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2250000 0x00 0x100>;
+ clocks = <&k3_clks 353 0>;
+ power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 353 0>;
+ assigned-clock-parents = <&k3_clks 353 4>;
+ };
+
+ watchdog6: watchdog@2260000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2260000 0x00 0x100>;
+ clocks = <&k3_clks 354 0>;
+ power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 354 0>;
+ assigned-clock-parents = <&k3_clks 354 4>;
+ };
+
+ watchdog7: watchdog@2270000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2270000 0x00 0x100>;
+ clocks = <&k3_clks 355 0>;
+ power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 355 0>;
+ assigned-clock-parents = <&k3_clks 355 4>;
};
pcie2_rc: pcie@2920000 {
status = "disabled";
};
};
+
+ c71_3: dsp@67800000 {
+ compatible = "ti,j721s2-c71-dsp";
+ reg = <0x00 0x67800000 0x00 0x00080000>,
+ <0x00 0x67e00000 0x00 0x0000c000>;
+ reg-names = "l2sram", "l1dram";
+ resets = <&k3_reset 40 1>;
+ firmware-name = "j784s4-c71_3-fw";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <40>;
+ ti,sci-proc-ids = <0x33 0xff>;
+ status = "disabled";
+ };
};
&scm_conf {
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
- mdio0 {
+ mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
- mdio0 {
+ mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
&spi0 {
status = "okay";
- mmc-slot@0 {
+ mmc@0 {
compatible = "mmc-spi-slot";
reg = <0>;
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
<0 0x24006000 0 0x2000>;
};
- pmux: pmux@24190000 {
+ pmux: pinctrl@24190000 {
compatible = "toshiba,tmpv7708-pinctrl";
reg = <0 0x24190000 0 0x10000>;
};
status = "disabled";
};
- wdt: wdt@28330000 {
+ wdt: watchdog@28330000 {
compatible = "toshiba,visconti-wdt";
reg = <0 0x28330000 0 0x1000>;
clocks = <&pismu TMPV770X_CLK_WDTCLK>;
bias-pull-up;
};
- pwm_mux: pwm_mux {
+ pwm_mux: pwm-pins {
function = "pwm";
};
};
spi0: spi@f1960000 {
- compatible = "cdns,spi-r1p6";
+ compatible = "xlnx,versal-net-spi-r1p6", "cdns,spi-r1p6";
status = "disabled";
interrupts = <0 23 4>;
reg = <0 0xf1960000 0 0x1000>;
};
spi1: spi@f1970000 {
- compatible = "cdns,spi-r1p6";
+ compatible = "xlnx,versal-net-spi-r1p6", "cdns,spi-r1p6";
status = "disabled";
interrupts = <0 24 4>;
reg = <0 0xf1970000 0 0x1000>;
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <33333333>;
+ clock-frequency = <33333000>;
clock-output-names = "pss_ref_clk";
};
ethernet0 = "/axi/ethernet@ff0c0000"; /* &gem1 */
};
- ina260-u3 {
- compatible = "iio-hwmon";
- io-channels = <&u3 0>, <&u3 1>, <&u3 2>;
- };
-
clk_26: clock2 { /* u17 - USB */
compatible = "fixed-clock";
#clock-cells = <0>;
u3: ina260@40 { /* u3 */
compatible = "ti,ina260";
- #io-channel-cells = <1>;
label = "ina260-u14";
reg = <0x40>;
};
slg7xl45106: gpio@11 { /* u13 - reset logic */
compatible = "dlg,slg7xl45106";
reg = <0x11>;
- label = "resetchip";
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "USB0_PHY_RESET_B", "",
ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */
};
- ina260-u14 {
- compatible = "iio-hwmon";
- io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
- };
-
clk_27: clock0 { /* u86 - DP */
compatible = "fixed-clock";
#clock-cells = <0>;
u14: ina260@40 { /* u14 */
compatible = "ti,ina260";
- #io-channel-cells = <1>;
label = "ina260-u14";
reg = <0x40>;
};
slg7xl45106: gpio@11 { /* u19 - reset logic */
compatible = "dlg,slg7xl45106";
reg = <0x11>;
- label = "resetchip";
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B",
ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */
};
- ina260-u14 {
- compatible = "iio-hwmon";
- io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
- };
-
clk_125: clock0 { /* u87 - GEM0/1 */
compatible = "fixed-clock";
#clock-cells = <0>;
u14: ina260@40 { /* u14 */
compatible = "ti,ina260";
- #io-channel-cells = <1>;
label = "ina260-u14";
reg = <0x40>;
};
slg7xl45106: gpio@11 { /* u19 - reset logic */
compatible = "dlg,slg7xl45106";
reg = <0x11>;
- label = "resetchip";
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B",
ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */
};
- ina260-u14 {
- compatible = "iio-hwmon";
- io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
- };
-
si5332_0: si5332-0 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
u14: ina260@40 { /* u14 */
compatible = "ti,ina260";
- #io-channel-cells = <1>;
label = "ina260-u14";
reg = <0x40>;
};
ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */
};
- ina260-u14 {
- compatible = "iio-hwmon";
- io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
- };
-
si5332_0: si5332-0 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
u14: ina260@40 { /* u14 */
compatible = "ti,ina260";
- #io-channel-cells = <1>;
label = "ina260-u14";
reg = <0x40>;
};
cpu_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
- opp00 {
- opp-hz = /bits/ 64 <1199999988>;
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <500000>;
};
- opp01 {
- opp-hz = /bits/ 64 <599999994>;
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <500000>;
};
- opp02 {
- opp-hz = /bits/ 64 <399999996>;
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <500000>;
};
- opp03 {
- opp-hz = /bits/ 64 <299999997>;
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <500000>;
};
};
firmware {
- optee: optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
-
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
#power-domain-cells = <1>;
};
spi0: spi@ff040000 {
- compatible = "cdns,spi-r1p6";
+ compatible = "xlnx,zynqmp-spi-r1p6", "cdns,spi-r1p6";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
};
spi1: spi@ff050000 {
- compatible = "cdns,spi-r1p6";
+ compatible = "xlnx,zynqmp-spi-r1p6", "cdns,spi-r1p6";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
};
};
+&apbdma0 {
+ status = "okay";
+};
+
+&nand {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nand@0 {
+ reg = <0>;
+ label = "ls2k0500-nand";
+ nand-use-soft-ecc-engine;
+ nand-ecc-algo = "bch";
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ };
+};
+
&apbdma3 {
status = "okay";
};
clock-names = "ref_100m";
};
- dma-controller@1fe10c00 {
+ apbdma0: dma-controller@1fe10c00 {
compatible = "loongson,ls2k0500-apbdma", "loongson,ls2k1000-apbdma";
reg = <0 0x1fe10c00 0 0x8>;
interrupt-parent = <&eiointc>;
interrupts = <3>;
};
+ nand: nand-controller@1ff58000 {
+ compatible = "loongson,ls2k0500-nand-controller";
+ reg = <0 0x1ff58000 0 0x24>,
+ <0 0x1ff58040 0 0x4>;
+ reg-names = "nand", "nand-dma";
+ dmas = <&apbdma0 0>;
+ dma-names = "rxtx";
+ status = "disabled";
+ };
+
pwm@1ff5c000 {
compatible = "loongson,ls2k0500-pwm", "loongson,ls7a-pwm";
reg = <0x0 0x1ff5c000 0x0 0x10>;
};
};
+&apbdma0 {
+ status = "okay";
+};
+
+&nand {
+ status = "okay";
+
+ pinctrl-0 = <&nand_pins_default>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nand@0 {
+ reg = <0>;
+ label = "ls2k1000-nand";
+ nand-use-soft-ecc-engine;
+ nand-ecc-algo = "bch";
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ };
+};
+
&apbdma1 {
status = "okay";
};
#thermal-sensor-cells = <1>;
};
- dma-controller@1fe00c00 {
+ apbdma0: dma-controller@1fe00c00 {
compatible = "loongson,ls2k1000-apbdma";
reg = <0x0 0x1fe00c00 0x0 0x8>;
interrupt-parent = <&liointc1>;
status = "disabled";
};
+ nand: nand-controller@1fe26000 {
+ compatible = "loongson,ls2k1000-nand-controller";
+ reg = <0 0x1fe26000 0 0x24>,
+ <0 0x1fe26040 0 0x4>,
+ <0 0x1fe00438 0 0x8>;
+ reg-names = "nand", "nand-dma", "dma-config";
+ dmas = <&apbdma0 0>;
+ dma-names = "rxtx";
+ status = "disabled";
+ };
+
pmc: power-management@1fe27000 {
compatible = "loongson,ls2k1000-pmc", "loongson,ls2k0500-pmc", "syscon";
reg = <0x0 0x1fe27000 0x0 0x58>;
<13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_lpi";
interrupt-parent = <&pic>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
<15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_lpi";
interrupt-parent = <&pic>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ leds0: leds {
+ compatible = "gpio-leds";
+
+ led-heartbeat {
+ gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_HEARTBEAT;
+ linux,default-trigger = "heartbeat";
+ label = "heartbeat";
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x02000000>;
+ };
+
+ /* 8 Green LEDs */
+ gpio0: gpio@91000000 {
+ compatible = "opencores,gpio";
+ reg = <0x91000000 0x1>, <0x91000001 0x1>;
+ reg-names = "dat", "dirout";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ /* 4 DIP Switches */
+ gpio1: gpio@92000000 {
+ compatible = "opencores,gpio";
+ reg = <0x92000000 0x1>, <0x92000001 0x1>;
+ reg-names = "dat", "dirout";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/dts-v1/;
+
+#include "simple-smp.dtsi"
+#include "de0-nano-common.dtsi"
+
+/ {
+ model = "Terasic DE0 Nano - Multicore";
+};
+
+&cpu0 {
+ clock-frequency = <50000000>;
+};
+
+&cpu1 {
+ clock-frequency = <50000000>;
+};
+
+&serial0 {
+ clock-frequency = <50000000>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "de0-nano-common.dtsi"
+
+/ {
+ model = "Terasic DE0 Nano";
+ compatible = "opencores,or1ksim";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&pic>;
+
+ aliases {
+ uart0 = &serial0;
+ };
+
+ chosen {
+ stdout-path = "uart0:115200";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "opencores,or1200-rtlsvn481";
+ reg = <0>;
+ clock-frequency = <50000000>;
+ };
+ };
+
+ /*
+ * OR1K PIC is built into CPU and accessed via special purpose
+ * registers. It is not addressable and, hence, has no 'reg'
+ * property.
+ */
+ pic: pic {
+ compatible = "opencores,or1k-pic";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ serial0: serial@90000000 {
+ compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
+ reg = <0x90000000 0x100>;
+ interrupts = <2>;
+ clock-frequency = <50000000>;
+ };
+};
+
+&gpio1 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "simple-smp.dtsi"
+
+/ {
+ model = "Simple SMP Board";
+};
+
+&cpu0 {
+ clock-frequency = <20000000>;
+};
+
+&cpu1 {
+ clock-frequency = <20000000>;
+};
+
+&enet0 {
+ status = "okay";
+};
+
+&serial0 {
+ clock-frequency = <20000000>;
+};
-/dts-v1/;
/ {
compatible = "opencores,or1ksim";
#address-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+
+ cpu0: cpu@0 {
compatible = "opencores,or1200-rtlsvn481";
reg = <0>;
- clock-frequency = <20000000>;
};
- cpu@1 {
+
+ cpu1: cpu@1 {
compatible = "opencores,or1200-rtlsvn481";
reg = <1>;
- clock-frequency = <20000000>;
};
};
compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
reg = <0x90000000 0x100>;
interrupts = <2>;
- clock-frequency = <20000000>;
};
enet0: ethoc@92000000 {
reg = <0x92000000 0x800>;
interrupts = <4>;
big-endian;
+ status = "disabled";
};
};
};
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x8000000>; // 128MB at 0
};
+++ /dev/null
-/* T4240 Interlaken LAC Portal device tree stub with 24 portals.
- *
- * Copyright 2012 Freescale Semiconductor Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Freescale Semiconductor nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- *
- * ALTERNATIVELY, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") as published by the Free Software
- * Foundation, either version 2 of that License or (at your option) any
- * later version.
- *
- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#address-cells = <0x1>;
-#size-cells = <0x1>;
-compatible = "fsl,interlaken-lac-portals";
-
-lportal0: lac-portal@0 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0x0 0x1000>;
-};
-
-lportal1: lac-portal@1000 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0x1000 0x1000>;
-};
-
-lportal2: lac-portal@2000 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0x2000 0x1000>;
-};
-
-lportal3: lac-portal@3000 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0x3000 0x1000>;
-};
-
-lportal4: lac-portal@4000 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0x4000 0x1000>;
-};
-
-lportal5: lac-portal@5000 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0x5000 0x1000>;
-};
-
-lportal6: lac-portal@6000 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0x6000 0x1000>;
-};
-
-lportal7: lac-portal@7000 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0x7000 0x1000>;
-};
-
-lportal8: lac-portal@8000 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0x8000 0x1000>;
-};
-
-lportal9: lac-portal@9000 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0x9000 0x1000>;
-};
-
-lportal10: lac-portal@A000 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0xA000 0x1000>;
-};
-
-lportal11: lac-portal@B000 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0xB000 0x1000>;
-};
-
-lportal12: lac-portal@C000 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0xC000 0x1000>;
-};
-
-lportal13: lac-portal@D000 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0xD000 0x1000>;
-};
-
-lportal14: lac-portal@E000 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0xE000 0x1000>;
-};
-
-lportal15: lac-portal@F000 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0xF000 0x1000>;
-};
-
-lportal16: lac-portal@10000 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0x10000 0x1000>;
-};
-
-lportal17: lac-portal@11000 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0x11000 0x1000>;
-};
-
-lportal18: lac-portal@1200 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0x12000 0x1000>;
-};
-
-lportal19: lac-portal@13000 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0x13000 0x1000>;
-};
-
-lportal20: lac-portal@14000 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0x14000 0x1000>;
-};
-
-lportal21: lac-portal@15000 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0x15000 0x1000>;
-};
-
-lportal22: lac-portal@16000 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0x16000 0x1000>;
-};
-
-lportal23: lac-portal@17000 {
- compatible = "fsl,interlaken-lac-portal-v1.0";
- reg = <0x17000 0x1000>;
-};
+++ /dev/null
-/*
- * T4 Interlaken Look-aside Controller (LAC) device tree stub
- *
- * Copyright 2012 Freescale Semiconductor Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Freescale Semiconductor nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- *
- * ALTERNATIVELY, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") as published by the Free Software
- * Foundation, either version 2 of that License or (at your option) any
- * later version.
- *
- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-lac: lac@229000 {
- compatible = "fsl,interlaken-lac";
- reg = <0x229000 0x1000>;
- interrupts = <16 2 1 18>;
-};
-
-lac-hv@228000 {
- compatible = "fsl,interlaken-lac-hv";
- reg = <0x228000 0x1000>;
- fsl,non-hv-node = <&lac>;
-};
+++ /dev/null
-/*
- * PQ3 MPIC Message (Group B) device tree stub [ controller @ offset 0x42400 ]
- *
- * Copyright 2012 Freescale Semiconductor Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Freescale Semiconductor nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- *
- * ALTERNATIVELY, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") as published by the Free Software
- * Foundation, either version 2 of that License or (at your option) any
- * later version.
- *
- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-message@42400 {
- compatible = "fsl,mpic-v3.1-msgr";
- reg = <0x42400 0x200>;
- interrupts = <
- 0xb4 2 0 0
- 0xb5 2 0 0
- 0xb6 2 0 0
- 0xb7 2 0 0>;
-};
+++ /dev/null
-/*
- * QorIQ FMan v3 1g port #1 device tree stub [ controller @ offset 0x400000 ]
- *
- * Copyright 2012 - 2015 Freescale Semiconductor Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Freescale Semiconductor nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- *
- * ALTERNATIVELY, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") as published by the Free Software
- * Foundation, either version 2 of that License or (at your option) any
- * later version.
- *
- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-fman@400000 {
- fman0_rx_0x09: port@89000 {
- cell-index = <0x9>;
- compatible = "fsl,fman-v3-port-rx";
- reg = <0x89000 0x1000>;
- fsl,fman-10g-port;
- fsl,fman-best-effort-port;
- };
-
- fman0_tx_0x29: port@a9000 {
- cell-index = <0x29>;
- compatible = "fsl,fman-v3-port-tx";
- reg = <0xa9000 0x1000>;
- fsl,fman-10g-port;
- fsl,fman-best-effort-port;
- };
-
- ethernet@e2000 {
- cell-index = <1>;
- compatible = "fsl,fman-memac";
- reg = <0xe2000 0x1000>;
- fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
- ptp-timer = <&ptp_timer0>;
- pcsphy-handle = <&pcsphy1>, <&qsgmiia_pcs1>;
- pcs-handle-names = "sgmii", "qsgmii";
- };
-
- mdio@e1000 {
- qsgmiia_pcs1: ethernet-pcs@1 {
- compatible = "fsl,lynx-pcs";
- reg = <1>;
- };
- };
-
- mdio@e3000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
- reg = <0xe3000 0x1000>;
- fsl,erratum-a011043; /* must ignore read errors */
-
- pcsphy1: ethernet-phy@0 {
- reg = <0x0>;
- };
- };
-};
};
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>; // 128MB at 0
};
};
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>; // 128MB at 0
};
*/
/dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "MPC8313ERDB";
};
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>; // 128MB at 0
};
#size-cells = <1>;
compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus";
reg = <0xe0005000 0x1000>;
- interrupts = <77 0x8>;
+ interrupts = <77 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
// CS0 and CS1 are swapped when
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
- interrupts = <14 0x8>;
+ interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
dfsrr;
rtc@68 {
compatible = "fsl,sec2.2", "fsl,sec2.1",
"fsl,sec2.0";
reg = <0x30000 0x10000>;
- interrupts = <11 0x8>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
fsl,num-channels = <1>;
fsl,channel-fifo-len = <24>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
- interrupts = <15 0x8>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
dfsrr;
};
cell-index = <0>;
compatible = "fsl,spi";
reg = <0x7000 0x1000>;
- interrupts = <16 0x8>;
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
mode = "cpu";
};
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&ipic>;
- interrupts = <38 0x8>;
+ interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
phy_type = "utmi_wide";
sleep = <&pmc 0x00300000>;
};
ptp_clock@24E00 {
compatible = "fsl,etsec-ptp";
reg = <0x24E00 0xB0>;
- interrupts = <12 0x8 13 0x8>;
+ interrupts = <12 IRQ_TYPE_LEVEL_LOW>,
+ <13 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = < &ipic >;
fsl,tclk-period = <10>;
fsl,tmr-prsc = <100>;
compatible = "gianfar";
reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <37 0x8 36 0x8 35 0x8>;
+ interrupts = <37 IRQ_TYPE_LEVEL_LOW>,
+ <36 IRQ_TYPE_LEVEL_LOW>,
+ <35 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
tbi-handle = < &tbi0 >;
/* Vitesse 7385 isn't on the MDIO bus */
reg = <0x520 0x20>;
phy4: ethernet-phy@4 {
interrupt-parent = <&ipic>;
- interrupts = <20 0x8>;
+ interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
reg = <0x4>;
};
tbi0: tbi-phy@11 {
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <34 0x8 33 0x8 32 0x8>;
+ interrupts = <34 IRQ_TYPE_LEVEL_LOW>,
+ <33 IRQ_TYPE_LEVEL_LOW>,
+ <32 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
tbi-handle = < &tbi1 >;
phy-handle = < &phy4 >;
compatible = "fsl,ns16550", "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
- interrupts = <9 0x8>;
+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
};
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
- interrupts = <10 0x8>;
+ interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
};
/* IPIC
- * interrupts cell = <intr #, sense>
- * sense values match linux IORESOURCE_IRQ_* defines:
- * sense == 8: Level, low assertion
- * sense == 2: Edge, high-to-low change
+ * interrupts cell = <intr #, type>
*/
ipic: pic@700 {
interrupt-controller;
pmc: power@b00 {
compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
reg = <0xb00 0x100 0xa00 0x100>;
- interrupts = <80 8>;
+ interrupts = <80 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
fsl,mpc8313-wakeup-timer = <>m1>;
gtm1: timer@500 {
compatible = "fsl,mpc8313-gtm", "fsl,gtm";
reg = <0x500 0x100>;
- interrupts = <90 8 78 8 84 8 72 8>;
+ interrupts = <90 IRQ_TYPE_LEVEL_LOW>,
+ <78 IRQ_TYPE_LEVEL_LOW>,
+ <84 IRQ_TYPE_LEVEL_LOW>,
+ <72 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
};
timer@600 {
compatible = "fsl,mpc8313-gtm", "fsl,gtm";
reg = <0x600 0x100>;
- interrupts = <91 8 79 8 85 8 73 8>;
+ interrupts = <91 IRQ_TYPE_LEVEL_LOW>,
+ <79 IRQ_TYPE_LEVEL_LOW>,
+ <85 IRQ_TYPE_LEVEL_LOW>,
+ <73 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
};
};
0x7800 0x0 0x0 0x3 &ipic 17 0x8
0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
interrupt-parent = <&ipic>;
- interrupts = <66 0x8>;
+ interrupts = <66 IRQ_TYPE_LEVEL_LOW>;
bus-range = <0x0 0x0>;
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
reg = <0xe00082a8 4>;
ranges = <0 0xe0008100 0x1a8>;
interrupt-parent = <&ipic>;
- interrupts = <71 8>;
+ interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
dma-channel@0 {
compatible = "fsl,mpc8313-dma-channel",
"fsl,elo-dma-channel";
reg = <0 0x28>;
interrupt-parent = <&ipic>;
- interrupts = <71 8>;
+ interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
cell-index = <0>;
};
"fsl,elo-dma-channel";
reg = <0x80 0x28>;
interrupt-parent = <&ipic>;
- interrupts = <71 8>;
+ interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
cell-index = <1>;
};
"fsl,elo-dma-channel";
reg = <0x100 0x28>;
interrupt-parent = <&ipic>;
- interrupts = <71 8>;
+ interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
cell-index = <2>;
};
"fsl,elo-dma-channel";
reg = <0x180 0x28>;
interrupt-parent = <&ipic>;
- interrupts = <71 8>;
+ interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
cell-index = <3>;
};
};
};
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>; // 128MB at 0
};
#size-cells = <1>;
compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
reg = <0xe0005000 0x1000>;
- interrupts = <77 0x8>;
+ interrupts = <77 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
// CS0 and CS1 are swapped when
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
- interrupts = <14 0x8>;
+ interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
dfsrr;
rtc@68 {
cell-index = <0>;
compatible = "fsl,spi";
reg = <0x7000 0x1000>;
- interrupts = <16 0x8>;
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
+ #address-cells = <1>;
+ #size-cells = <0>;
mode = "cpu";
};
reg = <0x82a8 4>;
ranges = <0 0x8100 0x1a8>;
interrupt-parent = <&ipic>;
- interrupts = <71 8>;
+ interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0 0x80>;
cell-index = <0>;
interrupt-parent = <&ipic>;
- interrupts = <71 8>;
+ interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
};
dma-channel@80 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&ipic>;
- interrupts = <71 8>;
+ interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
};
dma-channel@100 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&ipic>;
- interrupts = <71 8>;
+ interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
};
dma-channel@180 {
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
reg = <0x180 0x28>;
cell-index = <3>;
interrupt-parent = <&ipic>;
- interrupts = <71 8>;
+ interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
};
};
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&ipic>;
- interrupts = <38 0x8>;
+ interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
phy_type = "utmi";
};
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <32 0x8 33 0x8 34 0x8>;
+ interrupts = <32 IRQ_TYPE_LEVEL_LOW>,
+ <33 IRQ_TYPE_LEVEL_LOW>,
+ <34 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
tbi-handle = <&tbi0>;
phy-handle = < &phy0 >;
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <35 0x8 36 0x8 37 0x8>;
+ interrupts = <35 IRQ_TYPE_LEVEL_LOW>,
+ <36 IRQ_TYPE_LEVEL_LOW>,
+ <37 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
tbi-handle = <&tbi1>;
phy-handle = < &phy1 >;
compatible = "fsl,ns16550", "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <133333333>;
- interrupts = <9 0x8>;
+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
};
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <133333333>;
- interrupts = <10 0x8>;
+ interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
};
"fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
"fsl,sec2.0";
reg = <0x30000 0x10000>;
- interrupts = <11 0x8>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
reg = <0x18000 0x1000>;
cell-index = <1>;
- interrupts = <44 0x8>;
+ interrupts = <44 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
};
compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
reg = <0x19000 0x1000>;
cell-index = <2>;
- interrupts = <45 0x8>;
+ interrupts = <45 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
};
gtm1: timer@500 {
compatible = "fsl,mpc8315-gtm", "fsl,gtm";
reg = <0x500 0x100>;
- interrupts = <90 8 78 8 84 8 72 8>;
+ interrupts = <90 IRQ_TYPE_LEVEL_LOW>,
+ <78 IRQ_TYPE_LEVEL_LOW>,
+ <84 IRQ_TYPE_LEVEL_LOW>,
+ <72 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
clock-frequency = <133333333>;
};
timer@600 {
compatible = "fsl,mpc8315-gtm", "fsl,gtm";
reg = <0x600 0x100>;
- interrupts = <91 8 79 8 85 8 73 8>;
+ interrupts = <91 IRQ_TYPE_LEVEL_LOW>,
+ <79 IRQ_TYPE_LEVEL_LOW>,
+ <85 IRQ_TYPE_LEVEL_LOW>,
+ <73 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
clock-frequency = <133333333>;
};
/* IPIC
- * interrupts cell = <intr #, sense>
- * sense values match linux IORESOURCE_IRQ_* defines:
- * sense == 8: Level, low assertion
- * sense == 2: Edge, high-to-low change
+ * interrupts cell = <intr #, type>
*/
ipic: interrupt-controller@700 {
interrupt-controller;
compatible = "fsl,ipic-msi";
reg = <0x7c0 0x40>;
msi-available-ranges = <0 0x100>;
- interrupts = <0x43 0x8
- 0x4 0x8
- 0x51 0x8
- 0x52 0x8
- 0x56 0x8
- 0x57 0x8
- 0x58 0x8
- 0x59 0x8>;
+ interrupts = <0x43 IRQ_TYPE_LEVEL_LOW
+ 0x4 IRQ_TYPE_LEVEL_LOW
+ 0x51 IRQ_TYPE_LEVEL_LOW
+ 0x52 IRQ_TYPE_LEVEL_LOW
+ 0x56 IRQ_TYPE_LEVEL_LOW
+ 0x57 IRQ_TYPE_LEVEL_LOW
+ 0x58 IRQ_TYPE_LEVEL_LOW
+ 0x59 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = < &ipic >;
};
compatible = "fsl,mpc8315-pmc", "fsl,mpc8313-pmc",
"fsl,mpc8349-pmc";
reg = <0xb00 0x100 0xa00 0x100>;
- interrupts = <80 8>;
+ interrupts = <80 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
fsl,mpc8313-wakeup-timer = <>m1>;
};
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0E -mini PCI */
- 0x7000 0x0 0x0 0x1 &ipic 18 0x8
- 0x7000 0x0 0x0 0x2 &ipic 18 0x8
- 0x7000 0x0 0x0 0x3 &ipic 18 0x8
- 0x7000 0x0 0x0 0x4 &ipic 18 0x8
+ 0x7000 0x0 0x0 0x1 &ipic 18 IRQ_TYPE_LEVEL_LOW
+ 0x7000 0x0 0x0 0x2 &ipic 18 IRQ_TYPE_LEVEL_LOW
+ 0x7000 0x0 0x0 0x3 &ipic 18 IRQ_TYPE_LEVEL_LOW
+ 0x7000 0x0 0x0 0x4 &ipic 18 IRQ_TYPE_LEVEL_LOW
/* IDSEL 0x0F -mini PCI */
- 0x7800 0x0 0x0 0x1 &ipic 17 0x8
- 0x7800 0x0 0x0 0x2 &ipic 17 0x8
- 0x7800 0x0 0x0 0x3 &ipic 17 0x8
- 0x7800 0x0 0x0 0x4 &ipic 17 0x8
+ 0x7800 0x0 0x0 0x1 &ipic 17 IRQ_TYPE_LEVEL_LOW
+ 0x7800 0x0 0x0 0x2 &ipic 17 IRQ_TYPE_LEVEL_LOW
+ 0x7800 0x0 0x0 0x3 &ipic 17 IRQ_TYPE_LEVEL_LOW
+ 0x7800 0x0 0x0 0x4 &ipic 17 IRQ_TYPE_LEVEL_LOW
/* IDSEL 0x10 - PCI slot */
- 0x8000 0x0 0x0 0x1 &ipic 48 0x8
- 0x8000 0x0 0x0 0x2 &ipic 17 0x8
- 0x8000 0x0 0x0 0x3 &ipic 48 0x8
- 0x8000 0x0 0x0 0x4 &ipic 17 0x8>;
+ 0x8000 0x0 0x0 0x1 &ipic 48 IRQ_TYPE_LEVEL_LOW
+ 0x8000 0x0 0x0 0x2 &ipic 17 IRQ_TYPE_LEVEL_LOW
+ 0x8000 0x0 0x0 0x3 &ipic 48 IRQ_TYPE_LEVEL_LOW
+ 0x8000 0x0 0x0 0x4 &ipic 17 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
- interrupts = <66 0x8>;
+ interrupts = <66 IRQ_TYPE_LEVEL_LOW>;
bus-range = <0x0 0x0>;
ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
0x42000000 0 0x80000000 0x80000000 0 0x10000000
0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
bus-range = <0 255>;
interrupt-map-mask = <0xf800 0 0 7>;
- interrupt-map = <0 0 0 1 &ipic 1 8
- 0 0 0 2 &ipic 1 8
- 0 0 0 3 &ipic 1 8
- 0 0 0 4 &ipic 1 8>;
+ interrupt-map = <0 0 0 1 &ipic 1 IRQ_TYPE_LEVEL_LOW
+ 0 0 0 2 &ipic 1 IRQ_TYPE_LEVEL_LOW
+ 0 0 0 3 &ipic 1 IRQ_TYPE_LEVEL_LOW
+ 0 0 0 4 &ipic 1 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <0>;
pcie@0 {
0x01000000 0 0x00000000 0xd1000000 0 0x00800000>;
bus-range = <0 255>;
interrupt-map-mask = <0xf800 0 0 7>;
- interrupt-map = <0 0 0 1 &ipic 2 8
- 0 0 0 2 &ipic 2 8
- 0 0 0 3 &ipic 2 8
- 0 0 0 4 &ipic 2 8>;
+ interrupt-map = <0 0 0 1 &ipic 2 IRQ_TYPE_LEVEL_LOW
+ 0 0 0 2 &ipic 2 IRQ_TYPE_LEVEL_LOW
+ 0 0 0 3 &ipic 2 IRQ_TYPE_LEVEL_LOW
+ 0 0 0 4 &ipic 2 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <0>;
pcie@0 {
leds {
compatible = "gpio-leds";
- pwr {
+ led-pwr {
gpios = <&mcu_pio 0 0>;
default-state = "on";
};
- hdd {
+ led-hdd {
gpios = <&mcu_pio 1 0>;
linux,default-trigger = "disk-activity";
};
};
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x04000000>;
};
};
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x10000000>;
};
};
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x10000000>;
};
};
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x10000000>; // 256MB at 0
};
};
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; // 512MB at 0
};
};
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x10000000>; // 256MB at 0
};
};
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x10000000>; // 256MB at 0
};
status = "okay";
};
+&ledc {
+ pinctrl-0 = <&ledc_pc0_pin>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ multi-led@0 {
+ reg = <0x0>;
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_STATUS;
+ };
+};
+
&mmc1 {
bus-width = <4>;
mmc-pwrseq = <&wifi_pwrseq>;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
/dts-v1/;
};
};
+&ledc {
+ pinctrl-0 = <&ledc_pc0_pin>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ multi-led@0 {
+ reg = <0x0>;
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_STATUS;
+ };
+};
+
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
function = "i2c2";
};
+ /omit-if-no-ref/
+ ledc_pc0_pin: ledc-pc0-pin {
+ pins = "PC0";
+ function = "ledc";
+ };
+
/omit-if-no-ref/
uart0_pb8_pins: uart0-pb8-pins {
pins = "PB8", "PB9";
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
+#include <dt-bindings/thermal/thermal.h>
+
#define SOC_PERIPHERAL_IRQ(nr) (nr + 16)
#include "sunxi-d1s-t113.dtsi"
<0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
};
+
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths>;
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-crit {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
};
#reset-cells = <1>;
};
+ ledc: led-controller@2008000 {
+ compatible = "allwinner,sun20i-d1-ledc",
+ "allwinner,sun50i-a100-ledc";
+ reg = <0x2008000 0x400>;
+ interrupts = <SOC_PERIPHERAL_IRQ(20) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_LEDC>;
+ dmas = <&dma 42>;
+ dma-names = "tx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
gpadc: adc@2009000 {
compatible = "allwinner,sun20i-d1-gpadc";
reg = <0x2009000 0x400>;
#io-channel-cells = <1>;
};
+ ths: thermal-sensor@2009400 {
+ compatible = "allwinner,sun20i-d1-ths";
+ reg = <0x2009400 0x400>;
+ interrupts = <SOC_PERIPHERAL_IRQ(58) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_THS>;
+ clock-names = "bus";
+ resets = <&ccu RST_BUS_THS>;
+ nvmem-cells = <&ths_calibration>;
+ nvmem-cell-names = "calibration";
+ #thermal-sensor-cells = <0>;
+ };
+
dmic: dmic@2031000 {
compatible = "allwinner,sun20i-d1-dmic",
"allwinner,sun50i-h6-dmic";
reg = <0x3006000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ ths_calibration: thermal-sensor-calibration@14 {
+ reg = <0x14 0x8>;
+ };
};
crypto: crypto@3040000 {
mmu-type = "riscv,sv39";
reg = <0>;
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbc",
- "zbkc", "zbs", "zicntr", "zicsr", "zifencei",
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b",
+ "zba", "zbb", "zbc", "zbkc", "zbs",
+ "zicntr", "zicsr", "zifencei",
"zihintpause", "zihpm";
cpu0_intc: interrupt-controller {
#dma-cells = <1>;
};
- clkcfg: clkcfg@20002000 {
- compatible = "microchip,mpfs-clkcfg";
- reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
- clocks = <&refclk>;
- #clock-cells = <1>;
+ mss_top_sysreg: syscon@20002000 {
+ compatible = "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd";
+ reg = <0x0 0x20002000 0x0 0x1000>;
#reset-cells = <1>;
};
+ sysreg_scb: syscon@20003000 {
+ compatible = "microchip,mpfs-sysreg-scb", "syscon";
+ reg = <0x0 0x20003000 0x0 0x1000>;
+ };
+
ccc_se: clock-controller@38010000 {
compatible = "microchip,mpfs-ccc";
reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>,
clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>;
interrupt-parent = <&plic>;
interrupts = <56>;
+ resets = <&mss_top_sysreg CLK_CAN0>;
status = "disabled";
};
clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>;
interrupt-parent = <&plic>;
interrupts = <57>;
+ resets = <&mss_top_sysreg CLK_CAN1>;
status = "disabled";
};
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
- resets = <&clkcfg CLK_MAC0>;
+ resets = <&mss_top_sysreg CLK_MAC0>;
status = "disabled";
};
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
- resets = <&clkcfg CLK_MAC1>;
+ resets = <&mss_top_sysreg CLK_MAC1>;
status = "disabled";
};
status = "disabled";
};
- mbox: mailbox@37020000 {
+ control_scb: syscon@37020000 {
+ compatible = "microchip,mpfs-control-scb", "syscon";
+ reg = <0x0 0x37020000 0x0 0x100>;
+ };
+
+ mbox: mailbox@37020800 {
compatible = "microchip,mpfs-mailbox";
- reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>,
- <0x0 0x37020800 0x0 0x100>;
+ reg = <0x0 0x37020800 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <96>;
#mbox-cells = <1>;
clocks = <&scbclk>;
status = "disabled";
};
+
+ clkcfg: clkcfg@3e001000 {
+ compatible = "microchip,mpfs-clkcfg";
+ reg = <0x0 0x3e001000 0x0 0x1000>;
+ clocks = <&refclk>;
+ #clock-cells = <1>;
+ };
};
};
#include <arm64/renesas/r9a07g043.dtsi>
/ {
+ interrupt-parent = <&plic>;
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
&soc {
dma-noncoherent;
- interrupt-parent = <&plic>;
irqc: interrupt-controller@110a0000 {
compatible = "renesas,r9a07g043f-irqc";
clocks = <&clk CLK_AXI4_USB>, <&clk CLK_APB_USB>;
clock-names = "otg", "utmi";
g-np-tx-fifo-size = <32>;
- g-rx-fifo-size = <536>;
- g-tx-fifo-size = <768 512 512 384 128 128>;
+ g-rx-fifo-size = <1536>;
+ g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
interrupts = <SOC_PERIPHERAL_IRQ(14) IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbphy>;
phy-names = "usb2-phy";
cache-unified;
};
};
+
+ soc {
+ intc: interrupt-controller@7090000000 {
+ compatible = "sophgo,sg2042-plic", "thead,c900-plic";
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
+ interrupt-controller;
+ interrupts-extended =
+ <&cpu0_intc 11>, <&cpu0_intc 9>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>,
+ <&cpu2_intc 11>, <&cpu2_intc 9>,
+ <&cpu3_intc 11>, <&cpu3_intc 9>,
+ <&cpu4_intc 11>, <&cpu4_intc 9>,
+ <&cpu5_intc 11>, <&cpu5_intc 9>,
+ <&cpu6_intc 11>, <&cpu6_intc 9>,
+ <&cpu7_intc 11>, <&cpu7_intc 9>,
+ <&cpu8_intc 11>, <&cpu8_intc 9>,
+ <&cpu9_intc 11>, <&cpu9_intc 9>,
+ <&cpu10_intc 11>, <&cpu10_intc 9>,
+ <&cpu11_intc 11>, <&cpu11_intc 9>,
+ <&cpu12_intc 11>, <&cpu12_intc 9>,
+ <&cpu13_intc 11>, <&cpu13_intc 9>,
+ <&cpu14_intc 11>, <&cpu14_intc 9>,
+ <&cpu15_intc 11>, <&cpu15_intc 9>,
+ <&cpu16_intc 11>, <&cpu16_intc 9>,
+ <&cpu17_intc 11>, <&cpu17_intc 9>,
+ <&cpu18_intc 11>, <&cpu18_intc 9>,
+ <&cpu19_intc 11>, <&cpu19_intc 9>,
+ <&cpu20_intc 11>, <&cpu20_intc 9>,
+ <&cpu21_intc 11>, <&cpu21_intc 9>,
+ <&cpu22_intc 11>, <&cpu22_intc 9>,
+ <&cpu23_intc 11>, <&cpu23_intc 9>,
+ <&cpu24_intc 11>, <&cpu24_intc 9>,
+ <&cpu25_intc 11>, <&cpu25_intc 9>,
+ <&cpu26_intc 11>, <&cpu26_intc 9>,
+ <&cpu27_intc 11>, <&cpu27_intc 9>,
+ <&cpu28_intc 11>, <&cpu28_intc 9>,
+ <&cpu29_intc 11>, <&cpu29_intc 9>,
+ <&cpu30_intc 11>, <&cpu30_intc 9>,
+ <&cpu31_intc 11>, <&cpu31_intc 9>,
+ <&cpu32_intc 11>, <&cpu32_intc 9>,
+ <&cpu33_intc 11>, <&cpu33_intc 9>,
+ <&cpu34_intc 11>, <&cpu34_intc 9>,
+ <&cpu35_intc 11>, <&cpu35_intc 9>,
+ <&cpu36_intc 11>, <&cpu36_intc 9>,
+ <&cpu37_intc 11>, <&cpu37_intc 9>,
+ <&cpu38_intc 11>, <&cpu38_intc 9>,
+ <&cpu39_intc 11>, <&cpu39_intc 9>,
+ <&cpu40_intc 11>, <&cpu40_intc 9>,
+ <&cpu41_intc 11>, <&cpu41_intc 9>,
+ <&cpu42_intc 11>, <&cpu42_intc 9>,
+ <&cpu43_intc 11>, <&cpu43_intc 9>,
+ <&cpu44_intc 11>, <&cpu44_intc 9>,
+ <&cpu45_intc 11>, <&cpu45_intc 9>,
+ <&cpu46_intc 11>, <&cpu46_intc 9>,
+ <&cpu47_intc 11>, <&cpu47_intc 9>,
+ <&cpu48_intc 11>, <&cpu48_intc 9>,
+ <&cpu49_intc 11>, <&cpu49_intc 9>,
+ <&cpu50_intc 11>, <&cpu50_intc 9>,
+ <&cpu51_intc 11>, <&cpu51_intc 9>,
+ <&cpu52_intc 11>, <&cpu52_intc 9>,
+ <&cpu53_intc 11>, <&cpu53_intc 9>,
+ <&cpu54_intc 11>, <&cpu54_intc 9>,
+ <&cpu55_intc 11>, <&cpu55_intc 9>,
+ <&cpu56_intc 11>, <&cpu56_intc 9>,
+ <&cpu57_intc 11>, <&cpu57_intc 9>,
+ <&cpu58_intc 11>, <&cpu58_intc 9>,
+ <&cpu59_intc 11>, <&cpu59_intc 9>,
+ <&cpu60_intc 11>, <&cpu60_intc 9>,
+ <&cpu61_intc 11>, <&cpu61_intc 9>,
+ <&cpu62_intc 11>, <&cpu62_intc 9>,
+ <&cpu63_intc 11>, <&cpu63_intc 9>;
+ riscv,ndev = <224>;
+ };
+
+ clint_mswi: interrupt-controller@7094000000 {
+ compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
+ reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
+ interrupts-extended = <&cpu0_intc 3>,
+ <&cpu1_intc 3>,
+ <&cpu2_intc 3>,
+ <&cpu3_intc 3>,
+ <&cpu4_intc 3>,
+ <&cpu5_intc 3>,
+ <&cpu6_intc 3>,
+ <&cpu7_intc 3>,
+ <&cpu8_intc 3>,
+ <&cpu9_intc 3>,
+ <&cpu10_intc 3>,
+ <&cpu11_intc 3>,
+ <&cpu12_intc 3>,
+ <&cpu13_intc 3>,
+ <&cpu14_intc 3>,
+ <&cpu15_intc 3>,
+ <&cpu16_intc 3>,
+ <&cpu17_intc 3>,
+ <&cpu18_intc 3>,
+ <&cpu19_intc 3>,
+ <&cpu20_intc 3>,
+ <&cpu21_intc 3>,
+ <&cpu22_intc 3>,
+ <&cpu23_intc 3>,
+ <&cpu24_intc 3>,
+ <&cpu25_intc 3>,
+ <&cpu26_intc 3>,
+ <&cpu27_intc 3>,
+ <&cpu28_intc 3>,
+ <&cpu29_intc 3>,
+ <&cpu30_intc 3>,
+ <&cpu31_intc 3>,
+ <&cpu32_intc 3>,
+ <&cpu33_intc 3>,
+ <&cpu34_intc 3>,
+ <&cpu35_intc 3>,
+ <&cpu36_intc 3>,
+ <&cpu37_intc 3>,
+ <&cpu38_intc 3>,
+ <&cpu39_intc 3>,
+ <&cpu40_intc 3>,
+ <&cpu41_intc 3>,
+ <&cpu42_intc 3>,
+ <&cpu43_intc 3>,
+ <&cpu44_intc 3>,
+ <&cpu45_intc 3>,
+ <&cpu46_intc 3>,
+ <&cpu47_intc 3>,
+ <&cpu48_intc 3>,
+ <&cpu49_intc 3>,
+ <&cpu50_intc 3>,
+ <&cpu51_intc 3>,
+ <&cpu52_intc 3>,
+ <&cpu53_intc 3>,
+ <&cpu54_intc 3>,
+ <&cpu55_intc 3>,
+ <&cpu56_intc 3>,
+ <&cpu57_intc 3>,
+ <&cpu58_intc 3>,
+ <&cpu59_intc 3>,
+ <&cpu60_intc 3>,
+ <&cpu61_intc 3>,
+ <&cpu62_intc 3>,
+ <&cpu63_intc 3>;
+ };
+
+ clint_mtimer0: timer@70ac004000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac004000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu0_intc 7>,
+ <&cpu1_intc 7>,
+ <&cpu2_intc 7>,
+ <&cpu3_intc 7>;
+ };
+
+ clint_mtimer1: timer@70ac014000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac014000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu4_intc 7>,
+ <&cpu5_intc 7>,
+ <&cpu6_intc 7>,
+ <&cpu7_intc 7>;
+ };
+
+ clint_mtimer2: timer@70ac024000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac024000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu8_intc 7>,
+ <&cpu9_intc 7>,
+ <&cpu10_intc 7>,
+ <&cpu11_intc 7>;
+ };
+
+ clint_mtimer3: timer@70ac034000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac034000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu12_intc 7>,
+ <&cpu13_intc 7>,
+ <&cpu14_intc 7>,
+ <&cpu15_intc 7>;
+ };
+
+ clint_mtimer4: timer@70ac044000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac044000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu16_intc 7>,
+ <&cpu17_intc 7>,
+ <&cpu18_intc 7>,
+ <&cpu19_intc 7>;
+ };
+
+ clint_mtimer5: timer@70ac054000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac054000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu20_intc 7>,
+ <&cpu21_intc 7>,
+ <&cpu22_intc 7>,
+ <&cpu23_intc 7>;
+ };
+
+ clint_mtimer6: timer@70ac064000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac064000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu24_intc 7>,
+ <&cpu25_intc 7>,
+ <&cpu26_intc 7>,
+ <&cpu27_intc 7>;
+ };
+
+ clint_mtimer7: timer@70ac074000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac074000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu28_intc 7>,
+ <&cpu29_intc 7>,
+ <&cpu30_intc 7>,
+ <&cpu31_intc 7>;
+ };
+
+ clint_mtimer8: timer@70ac084000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac084000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu32_intc 7>,
+ <&cpu33_intc 7>,
+ <&cpu34_intc 7>,
+ <&cpu35_intc 7>;
+ };
+
+ clint_mtimer9: timer@70ac094000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac094000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu36_intc 7>,
+ <&cpu37_intc 7>,
+ <&cpu38_intc 7>,
+ <&cpu39_intc 7>;
+ };
+
+ clint_mtimer10: timer@70ac0a4000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu40_intc 7>,
+ <&cpu41_intc 7>,
+ <&cpu42_intc 7>,
+ <&cpu43_intc 7>;
+ };
+
+ clint_mtimer11: timer@70ac0b4000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu44_intc 7>,
+ <&cpu45_intc 7>,
+ <&cpu46_intc 7>,
+ <&cpu47_intc 7>;
+ };
+
+ clint_mtimer12: timer@70ac0c4000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu48_intc 7>,
+ <&cpu49_intc 7>,
+ <&cpu50_intc 7>,
+ <&cpu51_intc 7>;
+ };
+
+ clint_mtimer13: timer@70ac0d4000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu52_intc 7>,
+ <&cpu53_intc 7>,
+ <&cpu54_intc 7>,
+ <&cpu55_intc 7>;
+ };
+
+ clint_mtimer14: timer@70ac0e4000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu56_intc 7>,
+ <&cpu57_intc 7>,
+ <&cpu58_intc 7>,
+ <&cpu59_intc 7>;
+ };
+
+ clint_mtimer15: timer@70ac0f4000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu60_intc 7>,
+ <&cpu61_intc 7>,
+ <&cpu62_intc 7>,
+ <&cpu63_intc 7>;
+ };
+ };
};
status = "okay";
};
+&i2c0 {
+ pinctrl-0 = <&i2c0_cfg>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ rtc: rtc@68 {
+ compatible = "dallas,ds1307";
+ reg = <0x68>;
+ };
+};
+
&i2c1 {
pinctrl-0 = <&i2c1_cfg>;
pinctrl-names = "default";
};
};
+ i2c0_cfg: i2c0-cfg {
+ i2c0-pins {
+ pinmux = <PINMUX(PIN_IIC0_SDA, 0)>,
+ <PINMUX(PIN_IIC0_SCL, 0)>;
+ bias-pull-up;
+ drive-strength-microamp = <26800>;
+ input-schmitt-enable;
+ };
+ };
+
i2c1_cfg: i2c1-cfg {
i2c1-pins {
pinmux = <PINMUX(PIN_IIC1_SDA, 0)>,
#clock-cells = <1>;
};
- pcie_rc0: pcie@7060000000 {
- compatible = "sophgo,sg2042-pcie-host";
- device_type = "pci";
- reg = <0x70 0x60000000 0x0 0x00800000>,
- <0x40 0x00000000 0x0 0x00001000>;
- reg-names = "reg", "cfg";
- linux,pci-domain = <0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>,
- <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>,
- <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>,
- <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
- <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
- bus-range = <0x0 0xff>;
- vendor-id = <0x1f1c>;
- device-id = <0x2042>;
- cdns,no-bar-match-nbits = <48>;
- msi-parent = <&msi>;
- status = "disabled";
- };
-
- pcie_rc1: pcie@7060800000 {
- compatible = "sophgo,sg2042-pcie-host";
- device_type = "pci";
- reg = <0x70 0x60800000 0x0 0x00800000>,
- <0x44 0x00000000 0x0 0x00001000>;
- reg-names = "reg", "cfg";
- linux,pci-domain = <1>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>,
- <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>,
- <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>,
- <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>,
- <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>;
- bus-range = <0x0 0xff>;
- vendor-id = <0x1f1c>;
- device-id = <0x2042>;
- cdns,no-bar-match-nbits = <48>;
- msi-parent = <&msi>;
- status = "disabled";
- };
-
- pcie_rc2: pcie@7062000000 {
- compatible = "sophgo,sg2042-pcie-host";
- device_type = "pci";
- reg = <0x70 0x62000000 0x0 0x00800000>,
- <0x48 0x00000000 0x0 0x00001000>;
- reg-names = "reg", "cfg";
- linux,pci-domain = <2>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>,
- <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>,
- <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>,
- <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>,
- <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>;
- bus-range = <0x0 0xff>;
- vendor-id = <0x1f1c>;
- device-id = <0x2042>;
- cdns,no-bar-match-nbits = <48>;
- msi-parent = <&msi>;
- status = "disabled";
- };
-
- pcie_rc3: pcie@7062800000 {
- compatible = "sophgo,sg2042-pcie-host";
- device_type = "pci";
- reg = <0x70 0x62800000 0x0 0x00800000>,
- <0x4c 0x00000000 0x0 0x00001000>;
- reg-names = "reg", "cfg";
- linux,pci-domain = <3>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>,
- <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>,
- <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>,
- <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>,
- <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>;
- bus-range = <0x0 0xff>;
- vendor-id = <0x1f1c>;
- device-id = <0x2042>;
- cdns,no-bar-match-nbits = <48>;
- msi-parent = <&msi>;
- status = "disabled";
- };
-
- clint_mswi: interrupt-controller@7094000000 {
- compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
- reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
- interrupts-extended = <&cpu0_intc 3>,
- <&cpu1_intc 3>,
- <&cpu2_intc 3>,
- <&cpu3_intc 3>,
- <&cpu4_intc 3>,
- <&cpu5_intc 3>,
- <&cpu6_intc 3>,
- <&cpu7_intc 3>,
- <&cpu8_intc 3>,
- <&cpu9_intc 3>,
- <&cpu10_intc 3>,
- <&cpu11_intc 3>,
- <&cpu12_intc 3>,
- <&cpu13_intc 3>,
- <&cpu14_intc 3>,
- <&cpu15_intc 3>,
- <&cpu16_intc 3>,
- <&cpu17_intc 3>,
- <&cpu18_intc 3>,
- <&cpu19_intc 3>,
- <&cpu20_intc 3>,
- <&cpu21_intc 3>,
- <&cpu22_intc 3>,
- <&cpu23_intc 3>,
- <&cpu24_intc 3>,
- <&cpu25_intc 3>,
- <&cpu26_intc 3>,
- <&cpu27_intc 3>,
- <&cpu28_intc 3>,
- <&cpu29_intc 3>,
- <&cpu30_intc 3>,
- <&cpu31_intc 3>,
- <&cpu32_intc 3>,
- <&cpu33_intc 3>,
- <&cpu34_intc 3>,
- <&cpu35_intc 3>,
- <&cpu36_intc 3>,
- <&cpu37_intc 3>,
- <&cpu38_intc 3>,
- <&cpu39_intc 3>,
- <&cpu40_intc 3>,
- <&cpu41_intc 3>,
- <&cpu42_intc 3>,
- <&cpu43_intc 3>,
- <&cpu44_intc 3>,
- <&cpu45_intc 3>,
- <&cpu46_intc 3>,
- <&cpu47_intc 3>,
- <&cpu48_intc 3>,
- <&cpu49_intc 3>,
- <&cpu50_intc 3>,
- <&cpu51_intc 3>,
- <&cpu52_intc 3>,
- <&cpu53_intc 3>,
- <&cpu54_intc 3>,
- <&cpu55_intc 3>,
- <&cpu56_intc 3>,
- <&cpu57_intc 3>,
- <&cpu58_intc 3>,
- <&cpu59_intc 3>,
- <&cpu60_intc 3>,
- <&cpu61_intc 3>,
- <&cpu62_intc 3>,
- <&cpu63_intc 3>;
- };
-
- clint_mtimer0: timer@70ac004000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac004000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu0_intc 7>,
- <&cpu1_intc 7>,
- <&cpu2_intc 7>,
- <&cpu3_intc 7>;
- };
-
- clint_mtimer1: timer@70ac014000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac014000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu4_intc 7>,
- <&cpu5_intc 7>,
- <&cpu6_intc 7>,
- <&cpu7_intc 7>;
- };
-
- clint_mtimer2: timer@70ac024000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac024000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu8_intc 7>,
- <&cpu9_intc 7>,
- <&cpu10_intc 7>,
- <&cpu11_intc 7>;
- };
-
- clint_mtimer3: timer@70ac034000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac034000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu12_intc 7>,
- <&cpu13_intc 7>,
- <&cpu14_intc 7>,
- <&cpu15_intc 7>;
- };
-
- clint_mtimer4: timer@70ac044000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac044000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu16_intc 7>,
- <&cpu17_intc 7>,
- <&cpu18_intc 7>,
- <&cpu19_intc 7>;
- };
-
- clint_mtimer5: timer@70ac054000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac054000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu20_intc 7>,
- <&cpu21_intc 7>,
- <&cpu22_intc 7>,
- <&cpu23_intc 7>;
- };
-
- clint_mtimer6: timer@70ac064000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac064000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu24_intc 7>,
- <&cpu25_intc 7>,
- <&cpu26_intc 7>,
- <&cpu27_intc 7>;
- };
-
- clint_mtimer7: timer@70ac074000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac074000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu28_intc 7>,
- <&cpu29_intc 7>,
- <&cpu30_intc 7>,
- <&cpu31_intc 7>;
- };
-
- clint_mtimer8: timer@70ac084000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac084000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu32_intc 7>,
- <&cpu33_intc 7>,
- <&cpu34_intc 7>,
- <&cpu35_intc 7>;
- };
-
- clint_mtimer9: timer@70ac094000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac094000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu36_intc 7>,
- <&cpu37_intc 7>,
- <&cpu38_intc 7>,
- <&cpu39_intc 7>;
- };
-
- clint_mtimer10: timer@70ac0a4000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu40_intc 7>,
- <&cpu41_intc 7>,
- <&cpu42_intc 7>,
- <&cpu43_intc 7>;
- };
-
- clint_mtimer11: timer@70ac0b4000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu44_intc 7>,
- <&cpu45_intc 7>,
- <&cpu46_intc 7>,
- <&cpu47_intc 7>;
- };
-
- clint_mtimer12: timer@70ac0c4000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu48_intc 7>,
- <&cpu49_intc 7>,
- <&cpu50_intc 7>,
- <&cpu51_intc 7>;
- };
-
- clint_mtimer13: timer@70ac0d4000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu52_intc 7>,
- <&cpu53_intc 7>,
- <&cpu54_intc 7>,
- <&cpu55_intc 7>;
- };
-
- clint_mtimer14: timer@70ac0e4000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu56_intc 7>,
- <&cpu57_intc 7>,
- <&cpu58_intc 7>,
- <&cpu59_intc 7>;
- };
-
- clint_mtimer15: timer@70ac0f4000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu60_intc 7>,
- <&cpu61_intc 7>,
- <&cpu62_intc 7>,
- <&cpu63_intc 7>;
- };
-
- intc: interrupt-controller@7090000000 {
- compatible = "sophgo,sg2042-plic", "thead,c900-plic";
- #address-cells = <0>;
- #interrupt-cells = <2>;
- reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
- interrupt-controller;
- interrupts-extended =
- <&cpu0_intc 11>, <&cpu0_intc 9>,
- <&cpu1_intc 11>, <&cpu1_intc 9>,
- <&cpu2_intc 11>, <&cpu2_intc 9>,
- <&cpu3_intc 11>, <&cpu3_intc 9>,
- <&cpu4_intc 11>, <&cpu4_intc 9>,
- <&cpu5_intc 11>, <&cpu5_intc 9>,
- <&cpu6_intc 11>, <&cpu6_intc 9>,
- <&cpu7_intc 11>, <&cpu7_intc 9>,
- <&cpu8_intc 11>, <&cpu8_intc 9>,
- <&cpu9_intc 11>, <&cpu9_intc 9>,
- <&cpu10_intc 11>, <&cpu10_intc 9>,
- <&cpu11_intc 11>, <&cpu11_intc 9>,
- <&cpu12_intc 11>, <&cpu12_intc 9>,
- <&cpu13_intc 11>, <&cpu13_intc 9>,
- <&cpu14_intc 11>, <&cpu14_intc 9>,
- <&cpu15_intc 11>, <&cpu15_intc 9>,
- <&cpu16_intc 11>, <&cpu16_intc 9>,
- <&cpu17_intc 11>, <&cpu17_intc 9>,
- <&cpu18_intc 11>, <&cpu18_intc 9>,
- <&cpu19_intc 11>, <&cpu19_intc 9>,
- <&cpu20_intc 11>, <&cpu20_intc 9>,
- <&cpu21_intc 11>, <&cpu21_intc 9>,
- <&cpu22_intc 11>, <&cpu22_intc 9>,
- <&cpu23_intc 11>, <&cpu23_intc 9>,
- <&cpu24_intc 11>, <&cpu24_intc 9>,
- <&cpu25_intc 11>, <&cpu25_intc 9>,
- <&cpu26_intc 11>, <&cpu26_intc 9>,
- <&cpu27_intc 11>, <&cpu27_intc 9>,
- <&cpu28_intc 11>, <&cpu28_intc 9>,
- <&cpu29_intc 11>, <&cpu29_intc 9>,
- <&cpu30_intc 11>, <&cpu30_intc 9>,
- <&cpu31_intc 11>, <&cpu31_intc 9>,
- <&cpu32_intc 11>, <&cpu32_intc 9>,
- <&cpu33_intc 11>, <&cpu33_intc 9>,
- <&cpu34_intc 11>, <&cpu34_intc 9>,
- <&cpu35_intc 11>, <&cpu35_intc 9>,
- <&cpu36_intc 11>, <&cpu36_intc 9>,
- <&cpu37_intc 11>, <&cpu37_intc 9>,
- <&cpu38_intc 11>, <&cpu38_intc 9>,
- <&cpu39_intc 11>, <&cpu39_intc 9>,
- <&cpu40_intc 11>, <&cpu40_intc 9>,
- <&cpu41_intc 11>, <&cpu41_intc 9>,
- <&cpu42_intc 11>, <&cpu42_intc 9>,
- <&cpu43_intc 11>, <&cpu43_intc 9>,
- <&cpu44_intc 11>, <&cpu44_intc 9>,
- <&cpu45_intc 11>, <&cpu45_intc 9>,
- <&cpu46_intc 11>, <&cpu46_intc 9>,
- <&cpu47_intc 11>, <&cpu47_intc 9>,
- <&cpu48_intc 11>, <&cpu48_intc 9>,
- <&cpu49_intc 11>, <&cpu49_intc 9>,
- <&cpu50_intc 11>, <&cpu50_intc 9>,
- <&cpu51_intc 11>, <&cpu51_intc 9>,
- <&cpu52_intc 11>, <&cpu52_intc 9>,
- <&cpu53_intc 11>, <&cpu53_intc 9>,
- <&cpu54_intc 11>, <&cpu54_intc 9>,
- <&cpu55_intc 11>, <&cpu55_intc 9>,
- <&cpu56_intc 11>, <&cpu56_intc 9>,
- <&cpu57_intc 11>, <&cpu57_intc 9>,
- <&cpu58_intc 11>, <&cpu58_intc 9>,
- <&cpu59_intc 11>, <&cpu59_intc 9>,
- <&cpu60_intc 11>, <&cpu60_intc 9>,
- <&cpu61_intc 11>, <&cpu61_intc 9>,
- <&cpu62_intc 11>, <&cpu62_intc 9>,
- <&cpu63_intc 11>, <&cpu63_intc 9>;
- riscv,ndev = <224>;
- };
-
rstgen: reset-controller@7030013000 {
compatible = "sophgo,sg2042-reset";
reg = <0x00000070 0x30013000 0x00000000 0x0000000c>;
"timer";
status = "disabled";
};
+
+ pcie_rc0: pcie@7060000000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x60000000 0x0 0x00800000>,
+ <0x40 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>,
+ <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>,
+ <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>,
+ <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
+
+ pcie_rc1: pcie@7060800000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x60800000 0x0 0x00800000>,
+ <0x44 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>,
+ <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>,
+ <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>,
+ <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
+
+ pcie_rc2: pcie@7062000000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x62000000 0x0 0x00800000>,
+ <0x48 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>,
+ <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>,
+ <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>,
+ <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>,
+ <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
+
+ pcie_rc3: pcie@7062800000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x62800000 0x0 0x00800000>,
+ <0x4c 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>,
+ <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>,
+ <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>,
+ <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
};
};
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache0>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache0>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache0>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache0>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache1>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache1>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache1>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache1>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache2>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache2>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache2>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache2>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache3>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache3>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache3>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache3>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache4>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache4>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache4>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache4>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache5>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache5>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache5>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache5>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache6>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache6>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache6>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache6>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache7>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache7>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache7>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache7>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache8>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache8>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache8>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache8>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache9>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache9>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache9>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache9>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache10>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache10>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache10>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache10>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache11>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache11>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache11>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache11>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache12>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache12>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache12>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache12>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache13>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache13>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache13>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache13>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache14>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache14>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache14>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache14>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache15>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache15>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache15>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache15>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
};
};
+ pcie_vcc_3v3: pcie-vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "PCIE_VCC3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
reg_dc_in: dc-in-12v {
compatible = "regulator-fixed";
regulator-name = "dc_in_12v";
regulator-always-on;
vin-supply = <®_dc_in>;
};
+
+ usb3-vbus-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "USB30_VBUS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ usb3_hub_5v: usb3-hub-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "USB30_HUB";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&combo_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_3_cfg>;
+ status = "okay";
};
&emmc {
};
};
+&pcie1_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_3_cfg>;
+ status = "okay";
+};
+
+&pcie1_port {
+ phys = <&pcie1_phy>;
+};
+
+&pcie1 {
+ vpcie3v3-supply = <&pcie_vcc_3v3>;
+ status = "okay";
+};
+
+&pcie2_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_4_cfg>;
+ status = "okay";
+};
+
+&pcie2_port {
+ phys = <&pcie2_phy>;
+};
+
+&pcie2 {
+ vpcie3v3-supply = <&pcie_vcc_3v3>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_2_cfg>;
status = "okay";
};
+
+&usbphy2 {
+ status = "okay";
+};
+
+&usb_dwc3 {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ hub_2_0: hub@1 {
+ compatible = "usb2109,2817";
+ reg = <0x1>;
+ vdd-supply = <&usb3_hub_5v>;
+ peer-hub = <&hub_3_0>;
+ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
+ };
+
+ hub_3_0: hub@2 {
+ compatible = "usb2109,817";
+ reg = <0x2>;
+ vdd-supply = <&usb3_hub_5v>;
+ peer-hub = <&hub_2_0>;
+ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
+ };
+};
chosen {
stdout-path = "serial0";
};
+
+ reg_dc_in: dc-in-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_in_12v";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vcc_4v: vcc-4v {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_4v";
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <4000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ vin-supply = <®_dc_in>;
+ };
};
ð0 {
status = "okay";
};
+&i2c8 {
+ pinctrl-0 = <&i2c8_cfg>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ pmic@41 {
+ compatible = "spacemit,p1";
+ reg = <0x41>;
+ interrupts = <64>;
+ vin-supply = <®_vcc_4v>;
+
+ regulators {
+ buck1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck3_1v8: buck3 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck4 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck5 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck6 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ aldo1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ };
+
+ aldo2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ aldo3 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ aldo4 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ dldo1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ };
+
+ dldo2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ dldo3 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ dldo4 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-always-on;
+ };
+
+ dldo5 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ dldo6 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-always-on;
+ };
+
+ dldo7 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+ };
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_2_cfg>;
rgmii0: phy@1 {
reg = <0x1>;
+ motorcomm,auto-sleep-disabled;
};
};
};
rgmii1: phy@1 {
reg = <0x1>;
+ motorcomm,auto-sleep-disabled;
};
};
};
rgmii0: phy@1 {
reg = <0x1>;
+ motorcomm,auto-sleep-disabled;
};
};
};
rgmii1: phy@1 {
reg = <0x1>;
+ motorcomm,auto-sleep-disabled;
};
};
};
};
};
+ pcie0_3_cfg: pcie0-3-cfg {
+ pcie0-3-pins {
+ pinmux = <K1_PADCONF(54, 3)>, /* PERST# */
+ <K1_PADCONF(55, 3)>, /* WAKE# */
+ <K1_PADCONF(53, 3)>; /* CLKREQ# */
+
+ bias-pull-up = <0>;
+ drive-strength = <21>;
+ };
+ };
+
+ pcie1_3_cfg: pcie1-3-cfg {
+ pcie1-3-pins {
+ pinmux = <K1_PADCONF(59, 4)>, /* PERST# */
+ <K1_PADCONF(60, 4)>, /* WAKE# */
+ <K1_PADCONF(61, 4)>; /* CLKREQ# */
+
+ bias-pull-up = <0>;
+ drive-strength = <21>;
+ };
+ };
+
+ pcie2_4_cfg: pcie2-4-cfg {
+ pcie2-4-pins {
+ pinmux = <K1_PADCONF(62, 4)>, /* PERST# */
+ <K1_PADCONF(112, 3)>, /* WAKE# */
+ <K1_PADCONF(117, 4)>; /* CLKREQ# */
+
+ bias-pull-up = <0>;
+ drive-strength = <21>;
+ };
+ };
+
pwm14_1_cfg: pwm14-1-cfg {
pwm14-1-pins {
pinmux = <K1_PADCONF(44, 4)>;
*/
#include <dt-bindings/clock/spacemit,k1-syscon.h>
+#include <dt-bindings/phy/phy.h>
/dts-v1/;
/ {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <0>;
- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <1>;
- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <2>;
- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <3>;
- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <4>;
- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <5>;
- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <6>;
- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <7>;
- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
<&syscon_apbc CLK_TWSI0_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
+ resets = <&syscon_apbc RESET_TWSI0>;
interrupts = <36>;
status = "disabled";
};
<&syscon_apbc CLK_TWSI1_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
+ resets = <&syscon_apbc RESET_TWSI1>;
interrupts = <37>;
status = "disabled";
};
<&syscon_apbc CLK_TWSI2_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
+ resets = <&syscon_apbc RESET_TWSI2>;
interrupts = <38>;
status = "disabled";
};
<&syscon_apbc CLK_TWSI4_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
+ resets = <&syscon_apbc RESET_TWSI4>;
interrupts = <40>;
status = "disabled";
};
<&syscon_apbc CLK_TWSI5_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
+ resets = <&syscon_apbc RESET_TWSI5>;
interrupts = <41>;
status = "disabled";
};
+ usbphy2: phy@c0a30000 {
+ compatible = "spacemit,k1-usb2-phy";
+ reg = <0x0 0xc0a30000 0x0 0x200>;
+ clocks = <&syscon_apmu CLK_USB30>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ combo_phy: phy@c0b10000 {
+ compatible = "spacemit,k1-combo-phy";
+ reg = <0x0 0xc0b10000 0x0 0x1000>;
+ clocks = <&vctcxo_24m>,
+ <&syscon_apmu CLK_PCIE0_DBI>,
+ <&syscon_apmu CLK_PCIE0_MASTER>,
+ <&syscon_apmu CLK_PCIE0_SLAVE>;
+ clock-names = "refclk",
+ "dbi",
+ "mstr",
+ "slv";
+ resets = <&syscon_apmu RESET_PCIE0_GLOBAL>,
+ <&syscon_apmu RESET_PCIE0_DBI>,
+ <&syscon_apmu RESET_PCIE0_MASTER>,
+ <&syscon_apmu RESET_PCIE0_SLAVE>;
+ reset-names = "phy",
+ "dbi",
+ "mstr",
+ "slv";
+ #phy-cells = <1>;
+ spacemit,apmu = <&syscon_apmu>;
+ status = "disabled";
+ };
+
+ pcie1_phy: phy@c0c10000 {
+ compatible = "spacemit,k1-pcie-phy";
+ reg = <0x0 0xc0c10000 0x0 0x1000>;
+ clocks = <&vctcxo_24m>;
+ clock-names = "refclk";
+ resets = <&syscon_apmu RESET_PCIE1_GLOBAL>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ pcie2_phy: phy@c0d10000 {
+ compatible = "spacemit,k1-pcie-phy";
+ reg = <0x0 0xc0d10000 0x0 0x1000>;
+ clocks = <&vctcxo_24m>;
+ clock-names = "refclk";
+ resets = <&syscon_apmu RESET_PCIE2_GLOBAL>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
syscon_apbc: system-controller@d4015000 {
compatible = "spacemit,k1-syscon-apbc";
reg = <0x0 0xd4015000 0x0 0x1000>;
<&syscon_apbc CLK_TWSI6_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
+ resets = <&syscon_apbc RESET_TWSI6>;
interrupts = <70>;
status = "disabled";
};
<&syscon_apbc CLK_TWSI7_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
+ resets = <&syscon_apbc RESET_TWSI7>;
interrupts = <18>;
status = "disabled";
};
<&syscon_apbc CLK_TWSI8_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
+ resets = <&syscon_apbc RESET_TWSI8>;
interrupts = <19>;
status = "disabled";
};
pinctrl: pinctrl@d401e000 {
compatible = "spacemit,k1-pinctrl";
- reg = <0x0 0xd401e000 0x0 0x400>;
+ reg = <0x0 0xd401e000 0x0 0x1000>;
clocks = <&syscon_apbc CLK_AIB>,
<&syscon_apbc CLK_AIB_BUS>;
clock-names = "func", "bus";
+ spacemit,apbc = <&syscon_apbc>;
};
pwm8: pwm@d4020000 {
#size-cells = <2>;
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
<0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>;
+ pcie0: pcie@ca000000 {
+ device_type = "pci";
+ compatible = "spacemit,k1-pcie";
+ reg = <0x0 0xca000000 0x0 0x00001000>,
+ <0x0 0xca300000 0x0 0x0001ff24>,
+ <0x0 0x8f000000 0x0 0x00002000>,
+ <0x0 0xc0b20000 0x0 0x00001000>;
+ reg-names = "dbi",
+ "atu",
+ "config",
+ "link";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>,
+ <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x0f000000>;
+ interrupts = <141>;
+ interrupt-names = "msi";
+ clocks = <&syscon_apmu CLK_PCIE0_DBI>,
+ <&syscon_apmu CLK_PCIE0_MASTER>,
+ <&syscon_apmu CLK_PCIE0_SLAVE>;
+ clock-names = "dbi",
+ "mstr",
+ "slv";
+ resets = <&syscon_apmu RESET_PCIE0_DBI>,
+ <&syscon_apmu RESET_PCIE0_MASTER>,
+ <&syscon_apmu RESET_PCIE0_SLAVE>;
+ reset-names = "dbi",
+ "mstr",
+ "slv";
+ spacemit,apmu = <&syscon_apmu 0x03cc>;
+ status = "disabled";
+
+ pcie0_port: pcie@0 {
+ device_type = "pci";
+ compatible = "pciclass,0604";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+
+ pcie1: pcie@ca400000 {
+ device_type = "pci";
+ compatible = "spacemit,k1-pcie";
+ reg = <0x0 0xca400000 0x0 0x00001000>,
+ <0x0 0xca700000 0x0 0x0001ff24>,
+ <0x0 0x9f000000 0x0 0x00002000>,
+ <0x0 0xc0c20000 0x0 0x00001000>;
+ reg-names = "dbi",
+ "atu",
+ "config",
+ "link";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>,
+ <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x0f000000>;
+ interrupts = <142>;
+ interrupt-names = "msi";
+ clocks = <&syscon_apmu CLK_PCIE1_DBI>,
+ <&syscon_apmu CLK_PCIE1_MASTER>,
+ <&syscon_apmu CLK_PCIE1_SLAVE>;
+ clock-names = "dbi",
+ "mstr",
+ "slv";
+ resets = <&syscon_apmu RESET_PCIE1_DBI>,
+ <&syscon_apmu RESET_PCIE1_MASTER>,
+ <&syscon_apmu RESET_PCIE1_SLAVE>;
+ reset-names = "dbi",
+ "mstr",
+ "slv";
+ spacemit,apmu = <&syscon_apmu 0x3d4>;
+ status = "disabled";
+
+ pcie1_port: pcie@0 {
+ device_type = "pci";
+ compatible = "pciclass,0604";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+
+ pcie2: pcie@ca800000 {
+ device_type = "pci";
+ compatible = "spacemit,k1-pcie";
+ reg = <0x0 0xca800000 0x0 0x00001000>,
+ <0x0 0xcab00000 0x0 0x0001ff24>,
+ <0x0 0xb7000000 0x0 0x00002000>,
+ <0x0 0xc0d20000 0x0 0x00001000>;
+ reg-names = "dbi",
+ "atu",
+ "config",
+ "link";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>,
+ <0x42000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000>,
+ <0x02000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x07000000>;
+ interrupts = <143>;
+ interrupt-names = "msi";
+ clocks = <&syscon_apmu CLK_PCIE2_DBI>,
+ <&syscon_apmu CLK_PCIE2_MASTER>,
+ <&syscon_apmu CLK_PCIE2_SLAVE>;
+ clock-names = "dbi",
+ "mstr",
+ "slv";
+ resets = <&syscon_apmu RESET_PCIE2_DBI>,
+ <&syscon_apmu RESET_PCIE2_MASTER>,
+ <&syscon_apmu RESET_PCIE2_SLAVE>;
+ reset-names = "dbi",
+ "mstr",
+ "slv";
+ spacemit,apmu = <&syscon_apmu 0x3dc>;
+ status = "disabled";
+
+ pcie2_port: pcie@0 {
+ device_type = "pci";
+ compatible = "pciclass,0604";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
};
storage-bus {
#size-cells = <2>;
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
+ usb_dwc3: usb@c0a00000 {
+ compatible = "spacemit,k1-dwc3";
+ reg = <0x0 0xc0a00000 0x0 0x10000>;
+ clocks = <&syscon_apmu CLK_USB30>;
+ clock-names = "usbdrd30";
+ interrupts = <125>;
+ phys = <&usbphy2>, <&combo_phy PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi";
+ resets = <&syscon_apmu RESET_USB30_AHB>,
+ <&syscon_apmu RESET_USB30_VCC>,
+ <&syscon_apmu RESET_USB30_PHY>;
+ reset-names = "ahb", "vcc", "phy";
+ reset-delay = <2>;
+ snps,hsphy_interface = "utmi";
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,dis_rxdet_inp3_quirk;
+ status = "disabled";
+ };
+
emmc: mmc@d4281000 {
compatible = "spacemit,k1-sdhci";
reg = <0x0 0xd4281000 0x0 0x200>;
clocks = <&syscon_apmu CLK_SDH_AXI>,
<&syscon_apmu CLK_SDH2>;
clock-names = "core", "io";
+ resets = <&syscon_apmu RESET_SDH_AXI>,
+ <&syscon_apmu RESET_SDH2>;
+ reset-names = "axi", "sdh";
interrupts = <101>;
status = "disabled";
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd
+ * Copyright (c) 2026 Guodong Xu <guodong@riscstar.com>
+ */
+
+#include "k3.dtsi"
+
+/ {
+ model = "SpacemiT K3 Pico-ITX";
+ compatible = "spacemit,k3-pico-itx", "spacemit,k3";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ memory@100000000 {
+ device_type = "memory";
+ reg = <0x1 0x00000000 0x4 0x00000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd
+ * Copyright (c) 2026 Guodong Xu <guodong@riscstar.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "SpacemiT K3";
+ compatible = "spacemit,k3";
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <24000000>;
+
+ cpu_0: cpu@0 {
+ compatible = "spacemit,x100", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "sha", "shcounterenw", "shgatpa", "shtvala",
+ "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+ "smstateen", "ssaia", "ssccptr", "sscofpmf",
+ "sscounterenw", "ssnpm", "ssstateen", "sstc",
+ "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt", "za64rs",
+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+ "ziccamoa", "ziccif", "zicclsm", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintntl",
+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <256>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache0>;
+ mmu-type = "riscv,sv39";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu_1: cpu@1 {
+ compatible = "spacemit,x100", "riscv";
+ device_type = "cpu";
+ reg = <1>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "sha", "shcounterenw", "shgatpa", "shtvala",
+ "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+ "smstateen", "ssaia", "ssccptr", "sscofpmf",
+ "sscounterenw", "ssnpm", "ssstateen", "sstc",
+ "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt", "za64rs",
+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+ "ziccamoa", "ziccif", "zicclsm", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintntl",
+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <256>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache0>;
+ mmu-type = "riscv,sv39";
+
+ cpu1_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu_2: cpu@2 {
+ compatible = "spacemit,x100", "riscv";
+ device_type = "cpu";
+ reg = <2>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "sha", "shcounterenw", "shgatpa", "shtvala",
+ "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+ "smstateen", "ssaia", "ssccptr", "sscofpmf",
+ "sscounterenw", "ssnpm", "ssstateen", "sstc",
+ "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt", "za64rs",
+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+ "ziccamoa", "ziccif", "zicclsm", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintntl",
+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <256>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache0>;
+ mmu-type = "riscv,sv39";
+
+ cpu2_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu_3: cpu@3 {
+ compatible = "spacemit,x100", "riscv";
+ device_type = "cpu";
+ reg = <3>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "sha", "shcounterenw", "shgatpa", "shtvala",
+ "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+ "smstateen", "ssaia", "ssccptr", "sscofpmf",
+ "sscounterenw", "ssnpm", "ssstateen", "sstc",
+ "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt", "za64rs",
+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+ "ziccamoa", "ziccif", "zicclsm", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintntl",
+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <256>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache0>;
+ mmu-type = "riscv,sv39";
+
+ cpu3_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu_4: cpu@4 {
+ compatible = "spacemit,x100", "riscv";
+ device_type = "cpu";
+ reg = <4>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "sha", "shcounterenw", "shgatpa", "shtvala",
+ "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+ "smstateen", "ssaia", "ssccptr", "sscofpmf",
+ "sscounterenw", "ssnpm", "ssstateen", "sstc",
+ "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt", "za64rs",
+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+ "ziccamoa", "ziccif", "zicclsm", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintntl",
+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <256>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache1>;
+ mmu-type = "riscv,sv39";
+
+ cpu4_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu_5: cpu@5 {
+ compatible = "spacemit,x100", "riscv";
+ device_type = "cpu";
+ reg = <5>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "sha", "shcounterenw", "shgatpa", "shtvala",
+ "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+ "smstateen", "ssaia", "ssccptr", "sscofpmf",
+ "sscounterenw", "ssnpm", "ssstateen", "sstc",
+ "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt", "za64rs",
+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+ "ziccamoa", "ziccif", "zicclsm", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintntl",
+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <256>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache1>;
+ mmu-type = "riscv,sv39";
+
+ cpu5_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu_6: cpu@6 {
+ compatible = "spacemit,x100", "riscv";
+ device_type = "cpu";
+ reg = <6>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "sha", "shcounterenw", "shgatpa", "shtvala",
+ "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+ "smstateen", "ssaia", "ssccptr", "sscofpmf",
+ "sscounterenw", "ssnpm", "ssstateen", "sstc",
+ "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt", "za64rs",
+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+ "ziccamoa", "ziccif", "zicclsm", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintntl",
+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <256>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache1>;
+ mmu-type = "riscv,sv39";
+
+ cpu6_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu_7: cpu@7 {
+ compatible = "spacemit,x100", "riscv";
+ device_type = "cpu";
+ reg = <7>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "sha", "shcounterenw", "shgatpa", "shtvala",
+ "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+ "smstateen", "ssaia", "ssccptr", "sscofpmf",
+ "sscounterenw", "ssnpm", "ssstateen", "sstc",
+ "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt", "za64rs",
+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+ "ziccamoa", "ziccif", "zicclsm", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintntl",
+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <256>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache1>;
+ mmu-type = "riscv,sv39";
+
+ cpu7_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ l2_cache0: cache-controller-0 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <4194304>;
+ cache-sets = <4096>;
+ cache-unified;
+ };
+
+ l2_cache1: cache-controller-1 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <4194304>;
+ cache-sets = <4096>;
+ cache-unified;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu_0>;
+ };
+ core1 {
+ cpu = <&cpu_1>;
+ };
+ core2 {
+ cpu = <&cpu_2>;
+ };
+ core3 {
+ cpu = <&cpu_3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu_4>;
+ };
+ core1 {
+ cpu = <&cpu_5>;
+ };
+ core2 {
+ cpu = <&cpu_6>;
+ };
+ core3 {
+ cpu = <&cpu_7>;
+ };
+ };
+ };
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&saplic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-noncoherent;
+ ranges;
+
+ uart0: serial@d4017000 {
+ compatible = "spacemit,k3-uart", "intel,xscale-uart";
+ reg = <0x0 0xd4017000 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <14700000>;
+ interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart2: serial@d4017100 {
+ compatible = "spacemit,k3-uart", "intel,xscale-uart";
+ reg = <0x0 0xd4017100 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <14700000>;
+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart3: serial@d4017200 {
+ compatible = "spacemit,k3-uart", "intel,xscale-uart";
+ reg = <0x0 0xd4017200 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <14700000>;
+ interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart4: serial@d4017300 {
+ compatible = "spacemit,k3-uart", "intel,xscale-uart";
+ reg = <0x0 0xd4017300 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <14700000>;
+ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart5: serial@d4017400 {
+ compatible = "spacemit,k3-uart", "intel,xscale-uart";
+ reg = <0x0 0xd4017400 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <14700000>;
+ interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart6: serial@d4017500 {
+ compatible = "spacemit,k3-uart", "intel,xscale-uart";
+ reg = <0x0 0xd4017500 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <14700000>;
+ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart7: serial@d4017600 {
+ compatible = "spacemit,k3-uart", "intel,xscale-uart";
+ reg = <0x0 0xd4017600 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <14700000>;
+ interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart8: serial@d4017700 {
+ compatible = "spacemit,k3-uart", "intel,xscale-uart";
+ reg = <0x0 0xd4017700 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <14700000>;
+ interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart9: serial@d4017800 {
+ compatible = "spacemit,k3-uart", "intel,xscale-uart";
+ reg = <0x0 0xd4017800 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <14700000>;
+ interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart10: serial@d401f000 {
+ compatible = "spacemit,k3-uart", "intel,xscale-uart";
+ reg = <0x0 0xd401f000 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <14700000>;
+ interrupts = <281 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ simsic: interrupt-controller@e0400000 {
+ compatible = "spacemit,k3-imsics", "riscv,imsics";
+ reg = <0x0 0xe0400000 0x0 0x200000>;
+ #interrupt-cells = <0>;
+ #msi-cells = <0>;
+ interrupt-controller;
+ interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>,
+ <&cpu2_intc 9>, <&cpu3_intc 9>,
+ <&cpu4_intc 9>, <&cpu5_intc 9>,
+ <&cpu6_intc 9>, <&cpu7_intc 9>;
+ msi-controller;
+ riscv,guest-index-bits = <6>;
+ riscv,hart-index-bits = <4>;
+ riscv,num-guest-ids = <511>;
+ riscv,num-ids = <511>;
+ };
+
+ saplic: interrupt-controller@e0804000 {
+ compatible = "spacemit,k3-aplic", "riscv,aplic";
+ reg = <0x0 0xe0804000 0x0 0x4000>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ msi-parent = <&simsic>;
+ riscv,num-sources = <512>;
+ };
+
+ clint: timer@e081c000 {
+ compatible = "spacemit,k3-clint", "sifive,clint0";
+ reg = <0x0 0xe081c000 0x0 0x4000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>,
+ <&cpu2_intc 3>, <&cpu2_intc 7>,
+ <&cpu3_intc 3>, <&cpu3_intc 7>,
+ <&cpu4_intc 3>, <&cpu4_intc 7>,
+ <&cpu5_intc 3>, <&cpu5_intc 7>,
+ <&cpu6_intc 3>, <&cpu6_intc 7>,
+ <&cpu7_intc 3>, <&cpu7_intc 7>;
+ };
+
+ mimsic: interrupt-controller@f1000000 {
+ compatible = "spacemit,k3-imsics", "riscv,imsics";
+ reg = <0x0 0xf1000000 0x0 0x10000>;
+ #interrupt-cells = <0>;
+ #msi-cells = <0>;
+ interrupt-controller;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>,
+ <&cpu2_intc 11>, <&cpu3_intc 11>,
+ <&cpu4_intc 11>, <&cpu5_intc 11>,
+ <&cpu6_intc 11>, <&cpu7_intc 11>;
+ msi-controller;
+ riscv,guest-index-bits = <6>;
+ riscv,hart-index-bits = <4>;
+ riscv,num-guest-ids = <511>;
+ riscv,num-ids = <511>;
+ status = "reserved";
+ };
+
+ maplic: interrupt-controller@f1800000 {
+ compatible = "spacemit,k3-aplic", "riscv,aplic";
+ reg = <0x0 0xf1800000 0x0 0x4000>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ msi-parent = <&mimsic>;
+ riscv,children = <&saplic>;
+ riscv,delegation = <&saplic 1 512>;
+ riscv,num-sources = <512>;
+ status = "reserved";
+ };
+ };
+};
/ {
model = "StarFive VisionFive 2 Lite eMMC";
- compatible = "starfive,visionfive-2-lite-emmc", "starfive,jh7110s";
+ compatible = "starfive,visionfive-2-lite-emmc", "starfive,jh7110s", "starfive,jh7110";
};
&mmc0 {
/ {
model = "StarFive VisionFive 2 Lite";
- compatible = "starfive,visionfive-2-lite", "starfive,jh7110s";
+ compatible = "starfive,visionfive-2-lite", "starfive,jh7110s", "starfive,jh7110";
};
&mmc0 {
projects / thirdparty / u-boot.git / commitdiff
