]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
perf/x86/core: Do not set bit width for unavailable counters
authorSandipan Das <sandipan.das@amd.com>
Sat, 6 Dec 2025 00:16:46 +0000 (16:16 -0800)
committerPeter Zijlstra <peterz@infradead.org>
Wed, 17 Dec 2025 12:31:06 +0000 (13:31 +0100)
Not all x86 processors have fixed counters. It may also be the case that
a processor has only fixed counters and no general-purpose counters. Set
the bit widths corresponding to each counter type only if such counters
are available.

Fixes: b3d9468a8bd2 ("perf, x86: Expose perf capability to other modules")
Signed-off-by: Sandipan Das <sandipan.das@amd.com>
Co-developed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Mingwei Zhang <mizhang@google.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: Xudong Hao <xudong.hao@intel.com>
Link: https://patch.msgid.link/20251206001720.468579-11-seanjc@google.com
arch/x86/events/core.c

index 3ad5c658e28660d1e98530d322106527820da564..3f7838810cc5d13d51e281f9793e10c0832c0cdc 100644 (file)
@@ -3105,8 +3105,8 @@ void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
        cap->version            = x86_pmu.version;
        cap->num_counters_gp    = x86_pmu_num_counters(NULL);
        cap->num_counters_fixed = x86_pmu_num_counters_fixed(NULL);
-       cap->bit_width_gp       = x86_pmu.cntval_bits;
-       cap->bit_width_fixed    = x86_pmu.cntval_bits;
+       cap->bit_width_gp       = cap->num_counters_gp ? x86_pmu.cntval_bits : 0;
+       cap->bit_width_fixed    = cap->num_counters_fixed ? x86_pmu.cntval_bits : 0;
        cap->events_mask        = (unsigned int)x86_pmu.events_maskl;
        cap->events_mask_len    = x86_pmu.events_mask_len;
        cap->pebs_ept           = x86_pmu.pebs_ept;