net/mlx5: Add missing masks and QoS bit masks for scheduling elements

[ Upstream commit 452ef7f86036392005940de54228d42ca0044192 ]

Add the missing masks for supported element types and Transmit
Scheduling Arbiter (TSAR) types in scheduling elements.

Also, add the corresponding bit masks for these types in the QoS
capabilities of a NIC scheduler.

Fixes: 214baf22870c ("net/mlx5e: Support HTB offload")
Signed-off-by: Carolina Jubran <cjubran@nvidia.com>
Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index e42d6d2d8ecbd767d45111f652af1fb4c8bd2eb5..d974c235ad8ee1a873714c3b9e01ad20108ac14d 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -891,7 +891,8 @@ struct mlx5_ifc_qos_cap_bits {
 
        u8         max_tsar_bw_share[0x20];
 
-       u8         reserved_at_100[0x20];
+       u8         nic_element_type[0x10];
+       u8         nic_tsar_type[0x10];
 
        u8         reserved_at_120[0x3];
        u8         log_meter_aso_granularity[0x5];
@@ -3521,6 +3522,7 @@ enum {
        ELEMENT_TYPE_CAP_MASK_VPORT             = 1 << 1,
        ELEMENT_TYPE_CAP_MASK_VPORT_TC          = 1 << 2,
        ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC     = 1 << 3,
+       ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP       = 1 << 4,
 };
 
 struct mlx5_ifc_scheduling_context_bits {
@@ -4187,6 +4189,12 @@ enum {
        TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
 };
 
+enum {
+       TSAR_TYPE_CAP_MASK_DWRR         = 1 << 0,
+       TSAR_TYPE_CAP_MASK_ROUND_ROBIN  = 1 << 1,
+       TSAR_TYPE_CAP_MASK_ETS          = 1 << 2,
+};
+
 struct mlx5_ifc_tsar_element_bits {
        u8         reserved_at_0[0x8];
        u8         tsar_type[0x8];