spi: qcom-geni: Add trace events for Qualcomm GENI SPI driver

Add tracepoints to the Qualcomm GENI (Generic Interface) SPI driver.
These trace events enable runtime debugging and performance analysis
of SPI operations.

The trace events capture SPI clock configuration, setup parameters,
transfer details, interrupt status.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
Link: https://patch.msgid.link/20260518-add-tracepoints-for-qcom-geni-spi-v3-2-7928f6810a79@oss.qualcomm.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
index d5fb0edc8e0c8b24f24f21ffa9afcdaee2350af0..a04cdc1e5ad4d71f3826c8e2857d18d2f5222806 100644 (file)
--- a/drivers/spi/spi-geni-qcom.c
+++ b/drivers/spi/spi-geni-qcom.c
@@ -1,6 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0
 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
 
+#define CREATE_TRACE_POINTS
+#include <trace/events/qcom_geni_spi.h>
+
 #include <linux/clk.h>
 #include <linux/dmaengine.h>
 #include <linux/dma-mapping.h>
@@ -332,6 +335,9 @@ static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas,
        writel(clk_sel, se->base + SE_GENI_CLK_SEL);
        writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
 
+       trace_geni_spi_clk_cfg(mas->dev, clk_hz, mas->cur_sclk_hz, idx, div,
+                              mas->cur_bits_per_word);
+
        /* Set BW quota for CPU as driver supports FIFO mode only. */
        se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz);
        ret = geni_icc_set_bw(se);
@@ -366,6 +372,9 @@ static int setup_fifo_params(struct spi_device *spi_slv,
        if ((mode_changed & SPI_CS_HIGH) || (cs_changed && (spi_slv->mode & SPI_CS_HIGH)))
                writel((spi_slv->mode & SPI_CS_HIGH) ? BIT(chipselect) : 0, se->base + SE_SPI_DEMUX_OUTPUT_INV);
 
+       trace_geni_spi_setup_params(mas->dev, chipselect, spi_slv->mode,
+                                   mode_changed, cs_changed);
+
        return 0;
 }
 
@@ -861,6 +870,8 @@ static int setup_se_xfer(struct spi_transfer *xfer,
        spin_lock_irq(&mas->lock);
        geni_se_setup_m_cmd(se, m_cmd, m_params);
 
+       trace_geni_spi_transfer(mas->dev, len, m_cmd);
+
        if (mas->cur_xfer_mode == GENI_SE_DMA) {
                if (m_cmd & SPI_RX_ONLY)
                        geni_se_rx_init_dma(se, sg_dma_address(xfer->rx_sg.sgl),
@@ -915,6 +926,8 @@ static irqreturn_t geni_spi_isr(int irq, void *data)
        if (!m_irq && !dma_tx_status && !dma_rx_status)
                return IRQ_NONE;
 
+       trace_geni_spi_irq(mas->dev, m_irq, dma_tx_status, dma_rx_status);
+
        if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |
                     M_RX_FIFO_RD_ERR_EN | M_RX_FIFO_WR_ERR_EN |
                     M_TX_FIFO_RD_ERR_EN | M_TX_FIFO_WR_ERR_EN))