arm64/sysreg: Drop ICH_HFGRTR_EL2.ICC_HAPR_EL1 and make RES1

The GICv5 architecture is dropping the ICC_HAPR_EL1 and ICV_HAPR_EL1
system registers. These registers were never added to the sysregs, but
the traps for them were.

Drop the trap bit from the ICH_HFGRTR_EL2 and make it Res1 as per the
upcoming GICv5 spec change. Additionally, update the EL2 setup code to
not attempt to set that bit.

Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Link: https://patch.msgid.link/20260128175919.3828384-4-sascha.bischoff@arm.com
Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index cacd20df1786e2241ea95206d1abef56c2d472f3..07c12f4a69b412f89479ae3d9ec832027f8eb3e3 100644 (file)
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -225,7 +225,6 @@
                     ICH_HFGRTR_EL2_ICC_ICSR_EL1                | \
                     ICH_HFGRTR_EL2_ICC_PCR_EL1                 | \
                     ICH_HFGRTR_EL2_ICC_HPPIR_EL1               | \
-                    ICH_HFGRTR_EL2_ICC_HAPR_EL1                | \
                     ICH_HFGRTR_EL2_ICC_CR0_EL1                 | \
                     ICH_HFGRTR_EL2_ICC_IDRn_EL1                | \
                     ICH_HFGRTR_EL2_ICC_APR_EL1)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 8921b51866d64c71c8b7585cf0da6012a6b04236..dab5bfe8c968617ef199b4e41129096bb5e102d5 100644 (file)
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -4579,7 +4579,7 @@ Field     7       ICC_IAFFIDR_EL1
 Field  6       ICC_ICSR_EL1
 Field  5       ICC_PCR_EL1
 Field  4       ICC_HPPIR_EL1
-Field  3       ICC_HAPR_EL1
+Res1   3
 Field  2       ICC_CR0_EL1
 Field  1       ICC_IDRn_EL1
 Field  0       ICC_APR_EL1