arm64: dts: freescale: imx8mm-var-som: Update FEC support with MaxLinear PHY

Update the FEC Ethernet controller on the i.MX8MM VAR-SOM to match the
latest SOM hardware revision using the integrated MaxLinear MXL86110 PHY.

Add the PHY VDDIO supply regulator, adjust reset timings and add a
pinctrl sleep state for low-power operation.

The PHY LED signals originate on the SOM, but the actual LEDs are part
of the carrier implementation (RJ45 connector). Move the LED
configuration to the Symphony carrier device tree, matching the
evaluation board LED wiring.

Wake-on-LAN via magic packet is not supported at the VAR-SOM level and
is therefore not enabled in the SOM device tree nor in the official
evaluation carrier board configuration (symphony).
Designs requiring WoL support may enable it in their own carrier-specific
device trees if properly integrated at the hardware level.

Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts
index 819707e6f3bf3506733bbed9bcde4fd42220c4a6..9f4e004f0a37584b36c3d7609390864f608046d2 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts
@@ -5,6 +5,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/leds/common.h>
 #include "imx8mm-var-som.dtsi"
 
 / {
@@ -71,7 +72,24 @@
 };
 
 &ethphy {
-       reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>;
+       leds {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               led@0 {
+                       reg = <0>;
+                       color = <LED_COLOR_ID_YELLOW>;
+                       function = LED_FUNCTION_LAN;
+                       linux,default-trigger = "netdev";
+               };
+
+               led@1 {
+                       reg = <1>;
+                       color = <LED_COLOR_ID_GREEN>;
+                       function = LED_FUNCTION_LAN;
+                       linux,default-trigger = "netdev";
+               };
+       };
 };
 
 &i2c2 {

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi
index da3c7332ec34ff309ee1a7a29e90bfd4e6852fba..24924ee1e8c7bad96d3a5e4cd15d6b4e0840efc3 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi
@@ -24,6 +24,13 @@
                gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
                enable-active-high;
        };
+
+       reg_phy_vddio: regulator-phy-vddio {
+               compatible = "regulator-fixed";
+               regulator-name = "vddio-1v8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+       };
 };
 
 &A53_0 {
@@ -99,12 +106,17 @@
 };
 
 &fec1 {
-       pinctrl-names = "default";
+       pinctrl-names = "default", "sleep";
        pinctrl-0 = <&pinctrl_fec1>;
+       pinctrl-1 = <&pinctrl_fec1_sleep>;
+       /*
+        * The required RGMII TX and RX 2ns delays are implemented directly
+        * in hardware via passive delay elements on the SOM PCB.
+        * No delay configuration is needed in software via PHY driver.
+        */
        phy-mode = "rgmii";
        phy-handle = <&ethphy>;
        phy-supply = <&reg_eth_phy>;
-       fsl,magic-packet;
        status = "okay";
 
        mdio {
@@ -116,7 +128,8 @@
                        reg = <4>;
                        reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
                        reset-assert-us = <10000>;
-                       reset-deassert-us = <10000>;
+                       reset-deassert-us = <100000>;
+                       vddio-supply = <&reg_phy_vddio>;
                };
        };
 };
@@ -366,6 +379,26 @@
                >;
        };
 
+       pinctrl_fec1_sleep: fec1sleepgrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16                0x120
+                       MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17               0x120
+                       MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18                0x120
+                       MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19                0x120
+                       MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20                0x120
+                       MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21                0x120
+                       MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29                0x120
+                       MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28                0x120
+                       MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27                0x120
+                       MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26                0x120
+                       MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23                0x120
+                       MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25                0x120
+                       MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24             0x120
+                       MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22             0x120
+                       MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9               0x100
+               >;
+       };
+
        pinctrl_i2c1: i2c1grp {
                fsl,pins = <
                        MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL                  0x400001c3