RISC-V: prefetch: const offset needs to have 5 bits zero, not 4

Spotted this by chance as I saw a similar fixup in comment.
From comments, I think this is needed, but I've not hit any issues due
to this.

gcc/ChangeLog:

	* config/riscv/predicates.md (prefetch_operand): mack 5 bits.

Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
(cherry picked from commit b960201091fcab631a34a8c8d5b30e9f297dfbe5)

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index c20d82c551631ed1be82669a6420856c1c771259..715ac96203203505571add03a2c3ef1d2eba627d 100644 (file)
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -33,11 +33,11 @@
 (define_predicate "prefetch_operand"
   (ior (match_operand 0 "register_operand")
        (and (match_test "const_arith_operand (op, VOIDmode)")
-           (match_test "(INTVAL (op) & 0xf) == 0"))
+           (match_test "(INTVAL (op) & 0x1f) == 0"))
        (and (match_code "plus")
            (match_test "register_operand (XEXP (op, 0), word_mode)")
            (match_test "const_arith_operand (XEXP (op, 1), VOIDmode)")
-           (match_test "(INTVAL (XEXP (op, 1)) & 0xf) == 0"))))
+           (match_test "(INTVAL (XEXP (op, 1)) & 0x1f) == 0"))))
 
 (define_predicate "lui_operand"
   (and (match_code "const_int")