misc: amd-sbi: Add revision support for AMD Venice platform

The AMD Venice platform uses revision 0x31 and a two-byte register
address size. Add the revision to the CPUID and MCAMSR protocol
functions to ensure correct protocol identification.

Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com>
Signed-off-by: Akshay Gupta <Akshay.Gupta@amd.com>
Link: https://patch.msgid.link/20260318112711.2757467-1-Akshay.Gupta@amd.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/misc/amd-sbi/rmi-core.c b/drivers/misc/amd-sbi/rmi-core.c
index 6979bfd7da6477de276ade019d9153a8e0a6e380..d4238ebad3c6c844d06bef376043fa78e5cce7d4 100644 (file)
--- a/drivers/misc/amd-sbi/rmi-core.c
+++ b/drivers/misc/amd-sbi/rmi-core.c
@@ -214,6 +214,7 @@ static int rmi_cpuid_read(struct sbrmi_data *data,
                        goto exit_unlock;
                break;
        case 0x21:
+       case 0x31:
                ret = rmi_cpuid_input_ext(data, msg, thread);
                if (ret)
                        goto exit_unlock;
@@ -327,6 +328,7 @@ static int rmi_mca_msr_read(struct sbrmi_data *data,
                        goto exit_unlock;
                break;
        case 0x21:
+       case 0x31:
                ret = rmi_mcamsr_input_ext(data, msg, thread);
                if (ret)
                        goto exit_unlock;