ASoC: fsl_xcvr: Add sample rate constraint

Platforms like i.MX93/91 only have one audio PLL. Some sample rates are
not supported. If the PLL source is used for 8kHz series rates, then
11kHz series rates can't be supported. Use fsl_asoc_constrain_rates()
to constrain rates according to PLL sources. This constraint is merely
applicable to playback cases on SPDIF only platforms.

Signed-off-by: Chancel Liu <chancel.liu@nxp.com>
Link: https://patch.msgid.link/20241126115440.3929061-4-chancel.liu@nxp.com
Acked-by: Shengjiu Wang <shengjiu.wang@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/sound/soc/fsl/fsl_xcvr.c b/sound/soc/fsl/fsl_xcvr.c
index 8150f877e1ae934789bbcfea9d69840cc9da7bc3..051add7930221404cfac3fa863f13c8187b1553a 100644 (file)
--- a/sound/soc/fsl/fsl_xcvr.c
+++ b/sound/soc/fsl/fsl_xcvr.c
@@ -19,6 +19,7 @@
 #include "imx-pcm.h"
 
 #define FSL_XCVR_CAPDS_SIZE    256
+#define SPDIF_NUM_RATES                7
 
 enum fsl_xcvr_pll_verison {
        PLL_MX8MP,
@@ -57,6 +58,8 @@ struct fsl_xcvr {
        u8 cap_ds[FSL_XCVR_CAPDS_SIZE];
        struct work_struct work_rst;
        spinlock_t lock; /* Protect hw_reset and trigger */
+       struct snd_pcm_hw_constraint_list spdif_constr_rates;
+       u32 spdif_constr_rates_list[SPDIF_NUM_RATES];
 };
 
 static const struct fsl_xcvr_pll_conf {
@@ -640,8 +643,12 @@ static int fsl_xcvr_startup(struct snd_pcm_substream *substream,
        switch (xcvr->mode) {
        case FSL_XCVR_MODE_SPDIF:
        case FSL_XCVR_MODE_ARC:
-               ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr,
-                                     &fsl_xcvr_spdif_rates_constr);
+               if (xcvr->soc_data->spdif_only && tx)
+                       ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr,
+                                             &xcvr->spdif_constr_rates);
+               else
+                       ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr,
+                                             &fsl_xcvr_spdif_rates_constr);
                break;
        case FSL_XCVR_MODE_EARC:
                ret = fsl_xcvr_constr(substream, &fsl_xcvr_earc_channels_constr,
@@ -1546,6 +1553,15 @@ static int fsl_xcvr_probe(struct platform_device *pdev)
        fsl_asoc_get_pll_clocks(dev, &xcvr->pll8k_clk,
                                &xcvr->pll11k_clk);
 
+       if (xcvr->soc_data->spdif_only) {
+               if (!(xcvr->pll8k_clk || xcvr->pll11k_clk))
+                       xcvr->pll8k_clk = xcvr->phy_clk;
+               fsl_asoc_constrain_rates(&xcvr->spdif_constr_rates,
+                                        &fsl_xcvr_spdif_rates_constr,
+                                        xcvr->pll8k_clk, xcvr->pll11k_clk, NULL,
+                                        xcvr->spdif_constr_rates_list);
+       }
+
        xcvr->ram_addr = devm_platform_ioremap_resource_byname(pdev, "ram");
        if (IS_ERR(xcvr->ram_addr))
                return PTR_ERR(xcvr->ram_addr);