cadence_qspi: Update the delays for flash reset

Updating the delays for flash reset in the mini u-boot case.
These experimental delay values by looking at different flash device
vendors datasheets.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3fd0641a164a4d628fdf28a94771829f3bf9cb0c.1764181308.git.michal.simek@amd.com

diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c
index 0efbbf56a5e310bb1a404da92da6a527e6229249..e3ddf127e5a83571344b8d29e37b7c6e0c266398 100644 (file)
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -178,15 +178,15 @@ int cadence_qspi_flash_reset(struct udevice *dev)
 
        /* Disable Tri-state */
        writel((readl(BANK0_TRI) & ~BIT(FLASH_RESET_GPIO)), BANK0_TRI);
-       udelay(1);
+       udelay(5);
 
        /* Set value 0 to pin */
        writel((readl(BANK0_OUTPUT) & ~BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT);
-       udelay(10);
+       udelay(150);
 
        /* Set value 1 to pin */
        writel((readl(BANK0_OUTPUT) | BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT);
-       udelay(10);
+       udelay(1200);
 
        return 0;
 }